drivers/i2c/busses/i2c-octeon.c

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
   4  *
   5  * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
   6  *
   7  * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/i2c.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24
  25 #include <asm/octeon/octeon.h>
  26
  27 #define DRV_NAME "i2c-octeon"
  28
  29 /* Register offsets */
  30 #define SW_TWSI                 0x00
  31 #define TWSI_INT                0x10
  32
  33 /* Controller command patterns */
  34 #define SW_TWSI_V               BIT_ULL(63)     /* Valid bit */
  35 #define SW_TWSI_R               BIT_ULL(56)     /* Result or read bit */
  36
  37 /* Controller opcode word (bits 60:57) */
  38 #define SW_TWSI_OP_SHIFT        57
  39 #define SW_TWSI_OP_TWSI_CLK     (4ULL << SW_TWSI_OP_SHIFT)
  40 #define SW_TWSI_OP_EOP          (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
  41
  42 /* Controller extended opcode word (bits 34:32) */
  43 #define SW_TWSI_EOP_SHIFT       32
  44 #define SW_TWSI_EOP_TWSI_DATA   (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
  45 #define SW_TWSI_EOP_TWSI_CTL    (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
  46 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
  47 #define SW_TWSI_EOP_TWSI_STAT   (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
  48 #define SW_TWSI_EOP_TWSI_RST    (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
  49
  50 /* Controller command and status bits */
  51 #define TWSI_CTL_CE             0x80
  52 #define TWSI_CTL_ENAB           0x40    /* Bus enable */
  53 #define TWSI_CTL_STA            0x20    /* Master-mode start, HW clears when done */
  54 #define TWSI_CTL_STP            0x10    /* Master-mode stop, HW clears when done */
  55 #define TWSI_CTL_IFLG           0x08    /* HW event, SW writes 0 to ACK */
  56 #define TWSI_CTL_AAK            0x04    /* Assert ACK */
  57
  58 /* Some status values */
  59 #define STAT_START              0x08
  60 #define STAT_RSTART             0x10
  61 #define STAT_TXADDR_ACK         0x18
  62 #define STAT_TXDATA_ACK         0x28
  63 #define STAT_RXADDR_ACK         0x40
  64 #define STAT_RXDATA_ACK         0x50
  65 #define STAT_IDLE               0xF8
  66
  67 /* TWSI_INT values */
  68 #define TWSI_INT_CORE_EN        BIT_ULL(6)
  69 #define TWSI_INT_SDA_OVR        BIT_ULL(8)
  70 #define TWSI_INT_SCL_OVR        BIT_ULL(9)
  71
  72 struct octeon_i2c {
  73         wait_queue_head_t queue;
  74         struct i2c_adapter adap;
  75         int irq;
  76         u32 twsi_freq;
  77         int sys_freq;
  78         void __iomem *twsi_base;
  79         struct device *dev;
  80 };
  81
  82 /**
  83  * octeon_i2c_write_sw - write an I2C core register
  84  * @i2c: The struct octeon_i2c
  85  * @eop_reg: Register selector
  86  * @data: Value to be written
  87  *
  88  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
  89  */
  90 static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
  91 {
  92         u64 tmp;
  93
  94         __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
  95         do {
  96                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
  97         } while ((tmp & SW_TWSI_V) != 0);
  98 }
  99
 100 /**
 101  * octeon_i2c_read_sw - read lower bits of an I2C core register
 102  * @i2c: The struct octeon_i2c
 103  * @eop_reg: Register selector
 104  *
 105  * Returns the data.
 106  *
 107  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 108  */
 109 static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
 110 {
 111         u64 tmp;
 112
 113         __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
 114         do {
 115                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
 116         } while ((tmp & SW_TWSI_V) != 0);
 117
 118         return tmp & 0xFF;
 119 }
 120
 121 /**
 122  * octeon_i2c_write_int - write the TWSI_INT register
 123  * @i2c: The struct octeon_i2c
 124  * @data: Value to be written
 125  */
 126 static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
 127 {
 128         __raw_writeq(data, i2c->twsi_base + TWSI_INT);
 129         __raw_readq(i2c->twsi_base + TWSI_INT);
 130 }
 131
 132 /**
 133  * octeon_i2c_int_enable - enable the CORE interrupt
 134  * @i2c: The struct octeon_i2c
 135  *
 136  * The interrupt will be asserted when there is non-STAT_IDLE state in
 137  * the SW_TWSI_EOP_TWSI_STAT register.
 138  */
 139 static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
 140 {
 141         octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
 142 }
 143
 144 /* disable the CORE interrupt */
 145 static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
 146 {
 147         /* clear TS/ST/IFLG events */
 148         octeon_i2c_write_int(i2c, 0);
 149 }
 150
 151 /**
 152  * octeon_i2c_unblock - unblock the bus
 153  * @i2c: The struct octeon_i2c
 154  *
 155  * If there was a reset while a device was driving 0 to bus, bus is blocked.
 156  * We toggle it free manually by some clock cycles and send a stop.
 157  */
 158 static void octeon_i2c_unblock(struct octeon_i2c *i2c)
 159 {
 160         int i;
 161
 162         dev_dbg(i2c->dev, "%s\n", __func__);
 163
 164         for (i = 0; i < 9; i++) {
 165                 octeon_i2c_write_int(i2c, 0);
 166                 udelay(5);
 167                 octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
 168                 udelay(5);
 169         }
 170         /* hand-crank a STOP */
 171         octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
 172         udelay(5);
 173         octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
 174         udelay(5);
 175         octeon_i2c_write_int(i2c, 0);
 176 }
 177
 178 /* interrupt service routine */
 179 static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
 180 {
 181         struct octeon_i2c *i2c = dev_id;
 182
 183         octeon_i2c_int_disable(i2c);
 184         wake_up(&i2c->queue);
 185
 186         return IRQ_HANDLED;
 187 }
 188
 189
 190 static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
 191 {
 192         return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
 193 }
 194
 195 /**
 196  * octeon_i2c_wait - wait for the IFLG to be set
 197  * @i2c: The struct octeon_i2c
 198  *
 199  * Returns 0 on success, otherwise a negative errno.
 200  */
 201 static int octeon_i2c_wait(struct octeon_i2c *i2c)
 202 {
 203         long time_left;
 204
 205         octeon_i2c_int_enable(i2c);
 206         time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
 207                                        i2c->adap.timeout);
 208         octeon_i2c_int_disable(i2c);
 209         if (!time_left) {
 210                 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
 211                 return -ETIMEDOUT;
 212         }
 213
 214         return 0;
 215 }
 216
 217 /**
 218  * octeon_i2c_start - send START to the bus
 219  * @i2c: The struct octeon_i2c
 220  *
 221  * Returns 0 on success, otherwise a negative errno.
 222  */
 223 static int octeon_i2c_start(struct octeon_i2c *i2c)
 224 {
 225         int result;
 226         u8 data;
 227
 228         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 229                             TWSI_CTL_ENAB | TWSI_CTL_STA);
 230
 231         result = octeon_i2c_wait(i2c);
 232         if (result) {
 233                 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
 234                         /*
 235                          * Controller refused to send start flag May
 236                          * be a client is holding SDA low - let's try
 237                          * to free it.
 238                          */
 239                         octeon_i2c_unblock(i2c);
 240                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 241                                             TWSI_CTL_ENAB | TWSI_CTL_STA);
 242                         result = octeon_i2c_wait(i2c);
 243                 }
 244                 if (result)
 245                         return result;
 246         }
 247
 248         data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 249         if ((data != STAT_START) && (data != STAT_RSTART)) {
 250                 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
 251                 return -EIO;
 252         }
 253
 254         return 0;
 255 }
 256
 257 /* send STOP to the bus */
 258 static void octeon_i2c_stop(struct octeon_i2c *i2c)
 259 {
 260         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 261                             TWSI_CTL_ENAB | TWSI_CTL_STP);
 262 }
 263
 264 /**
 265  * octeon_i2c_write - send data to the bus via low-level controller
 266  * @i2c: The struct octeon_i2c
 267  * @target: Target address
 268  * @data: Pointer to the data to be sent
 269  * @length: Length of the data
 270  *
 271  * The address is sent over the bus, then the data.
 272  *
 273  * Returns 0 on success, otherwise a negative errno.
 274  */
 275 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
 276                             const u8 *data, int length)
 277 {
 278         int i, result;
 279         u8 tmp;
 280
 281         result = octeon_i2c_start(i2c);
 282         if (result)
 283                 return result;
 284
 285         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
 286         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 287
 288         result = octeon_i2c_wait(i2c);
 289         if (result)
 290                 return result;
 291
 292         for (i = 0; i < length; i++) {
 293                 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 294
 295                 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
 296                         dev_err(i2c->dev,
 297                                 "%s: bad status before write (0x%x)\n",
 298                                 __func__, tmp);
 299                         return -EIO;
 300                 }
 301
 302                 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
 303                 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 304
 305                 result = octeon_i2c_wait(i2c);
 306                 if (result)
 307                         return result;
 308         }
 309
 310         return 0;
 311 }
 312
 313 /**
 314  * octeon_i2c_read - receive data from the bus via low-level controller
 315  * @i2c: The struct octeon_i2c
 316  * @target: Target address
 317  * @data: Pointer to the location to store the data
 318  * @rlength: Length of the data
 319  * @recv_len: flag for length byte
 320  *
 321  * The address is sent over the bus, then the data is read.
 322  *
 323  * Returns 0 on success, otherwise a negative errno.
 324  */
 325 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
 326                            u8 *data, u16 *rlength, bool recv_len)
 327 {
 328         int i, result, length = *rlength;
 329         u8 tmp;
 330
 331         if (length < 1)
 332                 return -EINVAL;
 333
 334         result = octeon_i2c_start(i2c);
 335         if (result)
 336                 return result;
 337
 338         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
 339         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 340
 341         result = octeon_i2c_wait(i2c);
 342         if (result)
 343                 return result;
 344
 345         for (i = 0; i < length; i++) {
 346                 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 347
 348                 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
 349                         dev_err(i2c->dev,
 350                                 "%s: bad status before read (0x%x)\n",
 351                                 __func__, tmp);
 352                         return -EIO;
 353                 }
 354
 355                 if (i + 1 < length)
 356                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 357                                             TWSI_CTL_ENAB | TWSI_CTL_AAK);
 358                 else
 359                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 360                                             TWSI_CTL_ENAB);
 361
 362                 result = octeon_i2c_wait(i2c);
 363                 if (result)
 364                         return result;
 365
 366                 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
 367                 if (recv_len && i == 0) {
 368                         if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
 369                                 dev_err(i2c->dev,
 370                                         "%s: read len > I2C_SMBUS_BLOCK_MAX %d\n",
 371                                         __func__, data[i]);
 372                                 return -EPROTO;
 373                         }
 374                         length += data[i];
 375                 }
 376         }
 377         *rlength = length;
 378         return 0;
 379 }
 380
 381 /**
 382  * octeon_i2c_xfer - The driver's master_xfer function
 383  * @adap: Pointer to the i2c_adapter structure
 384  * @msgs: Pointer to the messages to be processed
 385  * @num: Length of the MSGS array
 386  *
 387  * Returns the number of messages processed, or a negative errno on failure.
 388  */
 389 static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 390                            int num)
 391 {
 392         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 393         int i, ret = 0;
 394
 395         for (i = 0; ret == 0 && i < num; i++) {
 396                 struct i2c_msg *pmsg = &msgs[i];
 397
 398                 dev_dbg(i2c->dev,
 399                         "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
 400                          pmsg->flags & I2C_M_RD ? "read" : "write",
 401                          pmsg->len, pmsg->addr, i + 1, num);
 402                 if (pmsg->flags & I2C_M_RD)
 403                         ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
 404                                               &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
 405                 else
 406                         ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
 407                                                pmsg->len);
 408         }
 409         octeon_i2c_stop(i2c);
 410
 411         return (ret != 0) ? ret : num;
 412 }
 413
 414 static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
 415 {
 416         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 417                I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
 418 }
 419
 420 static const struct i2c_algorithm octeon_i2c_algo = {
 421         .master_xfer = octeon_i2c_xfer,
 422         .functionality = octeon_i2c_functionality,
 423 };
 424
 425 static struct i2c_adapter octeon_i2c_ops = {
 426         .owner = THIS_MODULE,
 427         .name = "OCTEON adapter",
 428         .algo = &octeon_i2c_algo,
 429 };
 430
 431 /* calculate and set clock divisors */
 432 static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
 433 {
 434         int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
 435         int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
 436
 437         for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
 438                 /*
 439                  * An mdiv value of less than 2 seems to not work well
 440                  * with ds1337 RTCs, so we constrain it to larger values.
 441                  */
 442                 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
 443                         /*
 444                          * For given ndiv and mdiv values check the
 445                          * two closest thp values.
 446                          */
 447                         tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
 448                         tclk *= (1 << ndiv_idx);
 449                         thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
 450
 451                         for (inc = 0; inc <= 1; inc++) {
 452                                 thp_idx = thp_base + inc;
 453                                 if (thp_idx < 5 || thp_idx > 0xff)
 454                                         continue;
 455
 456                                 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
 457                                 foscl = foscl / (1 << ndiv_idx);
 458                                 foscl = foscl / (mdiv_idx + 1) / 10;
 459                                 diff = abs(foscl - i2c->twsi_freq);
 460                                 if (diff < delta_hz) {
 461                                         delta_hz = diff;
 462                                         thp = thp_idx;
 463                                         mdiv = mdiv_idx;
 464                                         ndiv = ndiv_idx;
 465                                 }
 466                         }
 467                 }
 468         }
 469         octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
 470         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
 471 }
 472
 473 static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
 474 {
 475         u8 status;
 476         int tries;
 477
 478         /* disable high level controller, enable bus access */
 479         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 480
 481         /* reset controller */
 482         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
 483
 484         for (tries = 10; tries; tries--) {
 485                 udelay(1);
 486                 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 487                 if (status == STAT_IDLE)
 488                         return 0;
 489         }
 490         dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
 491         return -EIO;
 492 }
 493
 494 static int octeon_i2c_probe(struct platform_device *pdev)
 495 {
 496         struct device_node *node = pdev->dev.of_node;
 497         struct resource *res_mem;
 498         struct octeon_i2c *i2c;
 499         int irq, result = 0;
 500
 501         /* All adaptors have an irq.  */
 502         irq = platform_get_irq(pdev, 0);
 503         if (irq < 0)
 504                 return irq;
 505
 506         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 507         if (!i2c) {
 508                 result = -ENOMEM;
 509                 goto out;
 510         }
 511         i2c->dev = &pdev->dev;
 512
 513         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 514         i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
 515         if (IS_ERR(i2c->twsi_base)) {
 516                 result = PTR_ERR(i2c->twsi_base);
 517                 goto out;
 518         }
 519
 520         /*
 521          * "clock-rate" is a legacy binding, the official binding is
 522          * "clock-frequency".  Try the official one first and then
 523          * fall back if it doesn't exist.
 524          */
 525         if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
 526             of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
 527                 dev_err(i2c->dev,
 528                         "no I2C 'clock-rate' or 'clock-frequency' property\n");
 529                 result = -ENXIO;
 530                 goto out;
 531         }
 532
 533         i2c->sys_freq = octeon_get_io_clock_rate();
 534
 535         init_waitqueue_head(&i2c->queue);
 536
 537         i2c->irq = irq;
 538
 539         result = devm_request_irq(&pdev->dev, i2c->irq,
 540                                   octeon_i2c_isr, 0, DRV_NAME, i2c);
 541         if (result < 0) {
 542                 dev_err(i2c->dev, "failed to attach interrupt\n");
 543                 goto out;
 544         }
 545
 546         result = octeon_i2c_init_lowlevel(i2c);
 547         if (result) {
 548                 dev_err(i2c->dev, "init low level failed\n");
 549                 goto  out;
 550         }
 551
 552         octeon_i2c_set_clock(i2c);
 553
 554         i2c->adap = octeon_i2c_ops;
 555         i2c->adap.timeout = msecs_to_jiffies(2);
 556         i2c->adap.retries = 5;
 557         i2c->adap.dev.parent = &pdev->dev;
 558         i2c->adap.dev.of_node = node;
 559         i2c_set_adapdata(&i2c->adap, i2c);
 560         platform_set_drvdata(pdev, i2c);
 561
 562         result = i2c_add_adapter(&i2c->adap);
 563         if (result < 0) {
 564                 dev_err(i2c->dev, "failed to add adapter\n");
 565                 goto out;
 566         }
 567         dev_info(i2c->dev, "probed\n");
 568         return 0;
 569
 570 out:
 571         return result;
 572 };
 573
 574 static int octeon_i2c_remove(struct platform_device *pdev)
 575 {
 576         struct octeon_i2c *i2c = platform_get_drvdata(pdev);
 577
 578         i2c_del_adapter(&i2c->adap);
 579         return 0;
 580 };
 581
 582 static const struct of_device_id octeon_i2c_match[] = {
 583         { .compatible = "cavium,octeon-3860-twsi", },
 584         {},
 585 };
 586 MODULE_DEVICE_TABLE(of, octeon_i2c_match);
 587
 588 static struct platform_driver octeon_i2c_driver = {
 589         .probe          = octeon_i2c_probe,
 590         .remove         = octeon_i2c_remove,
 591         .driver         = {
 592                 .name   = DRV_NAME,
 593                 .of_match_table = octeon_i2c_match,
 594         },
 595 };
 596
 597 module_platform_driver(octeon_i2c_driver);
 598
 599 MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
 600 MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
 601 MODULE_LICENSE("GPL");