drivers/i2c/busses/i2c-mpc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This is a combined i2c adapter and algorithm driver for the
   4  * MPC107/Tsi107 PowerPC northbridge and processors that include
   5  * the same I2C unit (8240, 8245, 85xx).
   6  *
   7  * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
   8  * Copyright (C) 2021 Allied Telesis Labs
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/sched/signal.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/property.h>
  18 #include <linux/slab.h>
  19
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/fsl_devices.h>
  24 #include <linux/i2c.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27
  28 #include <asm/mpc52xx.h>
  29 #include <asm/mpc85xx.h>
  30 #include <sysdev/fsl_soc.h>
  31
  32 #define DRV_NAME "mpc-i2c"
  33
  34 #define MPC_I2C_CLOCK_LEGACY   0
  35 #define MPC_I2C_CLOCK_PRESERVE (~0U)
  36
  37 #define MPC_I2C_FDR   0x04
  38 #define MPC_I2C_CR    0x08
  39 #define MPC_I2C_SR    0x0c
  40 #define MPC_I2C_DR    0x10
  41 #define MPC_I2C_DFSRR 0x14
  42
  43 #define CCR_MEN  0x80
  44 #define CCR_MIEN 0x40
  45 #define CCR_MSTA 0x20
  46 #define CCR_MTX  0x10
  47 #define CCR_TXAK 0x08
  48 #define CCR_RSTA 0x04
  49 #define CCR_RSVD 0x02
  50
  51 #define CSR_MCF  0x80
  52 #define CSR_MAAS 0x40
  53 #define CSR_MBB  0x20
  54 #define CSR_MAL  0x10
  55 #define CSR_SRW  0x04
  56 #define CSR_MIF  0x02
  57 #define CSR_RXAK 0x01
  58
  59 enum mpc_i2c_action {
  60         MPC_I2C_ACTION_START = 1,
  61         MPC_I2C_ACTION_RESTART,
  62         MPC_I2C_ACTION_READ_BEGIN,
  63         MPC_I2C_ACTION_READ_BYTE,
  64         MPC_I2C_ACTION_WRITE,
  65         MPC_I2C_ACTION_STOP,
  66
  67         __MPC_I2C_ACTION_CNT
  68 };
  69
  70 static const char * const action_str[] = {
  71         "invalid",
  72         "start",
  73         "restart",
  74         "read begin",
  75         "read",
  76         "write",
  77         "stop",
  78 };
  79
  80 static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT);
  81
  82 struct mpc_i2c {
  83         struct device *dev;
  84         void __iomem *base;
  85         u32 interrupt;
  86         wait_queue_head_t waitq;
  87         spinlock_t lock;
  88         struct i2c_adapter adap;
  89         int irq;
  90         u32 real_clk;
  91         u8 fdr, dfsrr;
  92         struct clk *clk_per;
  93         u32 cntl_bits;
  94         enum mpc_i2c_action action;
  95         struct i2c_msg *msgs;
  96         int num_msgs;
  97         int curr_msg;
  98         u32 byte_posn;
  99         u32 block;
 100         int rc;
 101         int expect_rxack;
 102         bool has_errata_A004447;
 103 };
 104
 105 struct mpc_i2c_divider {
 106         u16 divider;
 107         u16 fdr;        /* including dfsrr */
 108 };
 109
 110 struct mpc_i2c_data {
 111         void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
 112 };
 113
 114 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
 115 {
 116         writeb(x, i2c->base + MPC_I2C_CR);
 117 }
 118
 119 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
 120  * the bus, because it wants to send ACK.
 121  * Following sequence of enabling/disabling and sending start/stop generates
 122  * the 9 pulses, so it's all OK.
 123  */
 124 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 125 {
 126         int k;
 127         u32 delay_val = 1000000 / i2c->real_clk + 1;
 128
 129         if (delay_val < 2)
 130                 delay_val = 2;
 131
 132         for (k = 9; k; k--) {
 133                 writeccr(i2c, 0);
 134                 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
 135                 readb(i2c->base + MPC_I2C_DR);
 136                 writeccr(i2c, CCR_MEN);
 137                 udelay(delay_val << 1);
 138         }
 139 }
 140
 141 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
 142 {
 143         void __iomem *addr = i2c->base + MPC_I2C_SR;
 144         u8 val;
 145
 146         return readb_poll_timeout(addr, val, val & mask, 0, 100);
 147 }
 148
 149 /*
 150  * Workaround for Erratum A004447. From the P2040CE Rev Q
 151  *
 152  * 1.  Set up the frequency divider and sampling rate.
 153  * 2.  I2CCR - a0h
 154  * 3.  Poll for I2CSR[MBB] to get set.
 155  * 4.  If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
 156  *     step 5. If MAL is not set, then go to step 13.
 157  * 5.  I2CCR - 00h
 158  * 6.  I2CCR - 22h
 159  * 7.  I2CCR - a2h
 160  * 8.  Poll for I2CSR[MBB] to get set.
 161  * 9.  Issue read to I2CDR.
 162  * 10. Poll for I2CSR[MIF] to be set.
 163  * 11. I2CCR - 82h
 164  * 12. Workaround complete. Skip the next steps.
 165  * 13. Issue read to I2CDR.
 166  * 14. Poll for I2CSR[MIF] to be set.
 167  * 15. I2CCR - 80h
 168  */
 169 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
 170 {
 171         int ret;
 172         u32 val;
 173
 174         writeccr(i2c, CCR_MEN | CCR_MSTA);
 175         ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
 176         if (ret) {
 177                 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
 178                 return;
 179         }
 180
 181         val = readb(i2c->base + MPC_I2C_SR);
 182
 183         if (val & CSR_MAL) {
 184                 writeccr(i2c, 0x00);
 185                 writeccr(i2c, CCR_MSTA | CCR_RSVD);
 186                 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
 187                 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
 188                 if (ret) {
 189                         dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
 190                         return;
 191                 }
 192                 val = readb(i2c->base + MPC_I2C_DR);
 193                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
 194                 if (ret) {
 195                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
 196                         return;
 197                 }
 198                 writeccr(i2c, CCR_MEN | CCR_RSVD);
 199         } else {
 200                 val = readb(i2c->base + MPC_I2C_DR);
 201                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
 202                 if (ret) {
 203                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
 204                         return;
 205                 }
 206                 writeccr(i2c, CCR_MEN);
 207         }
 208 }
 209
 210 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
 211 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
 212         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
 213         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
 214         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
 215         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
 216         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
 217         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
 218         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
 219         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
 220         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
 221         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
 222         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
 223         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
 224         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
 225         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
 226         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
 227         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
 228         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
 229         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
 230 };
 231
 232 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
 233                                           u32 *real_clk)
 234 {
 235         const struct mpc_i2c_divider *div = NULL;
 236         unsigned int pvr = mfspr(SPRN_PVR);
 237         u32 divider;
 238         int i;
 239
 240         if (clock == MPC_I2C_CLOCK_LEGACY) {
 241                 /* see below - default fdr = 0x3f -> div = 2048 */
 242                 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
 243                 return -EINVAL;
 244         }
 245
 246         /* Determine divider value */
 247         divider = mpc5xxx_get_bus_frequency(node) / clock;
 248
 249         /*
 250          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 251          * is equal to or lower than the requested speed.
 252          */
 253         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
 254                 div = &mpc_i2c_dividers_52xx[i];
 255                 /* Old MPC5200 rev A CPUs do not support the high bits */
 256                 if (div->fdr & 0xc0 && pvr == 0x80822011)
 257                         continue;
 258                 if (div->divider >= divider)
 259                         break;
 260         }
 261
 262         *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
 263         return (int)div->fdr;
 264 }
 265
 266 static void mpc_i2c_setup_52xx(struct device_node *node,
 267                                          struct mpc_i2c *i2c,
 268                                          u32 clock)
 269 {
 270         int ret, fdr;
 271
 272         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 273                 dev_dbg(i2c->dev, "using fdr %d\n",
 274                         readb(i2c->base + MPC_I2C_FDR));
 275                 return;
 276         }
 277
 278         ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
 279         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
 280
 281         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 282
 283         if (ret >= 0)
 284                 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
 285                          fdr);
 286 }
 287 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
 288 static void mpc_i2c_setup_52xx(struct device_node *node,
 289                                          struct mpc_i2c *i2c,
 290                                          u32 clock)
 291 {
 292 }
 293 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
 294
 295 #ifdef CONFIG_PPC_MPC512x
 296 static void mpc_i2c_setup_512x(struct device_node *node,
 297                                          struct mpc_i2c *i2c,
 298                                          u32 clock)
 299 {
 300         struct device_node *node_ctrl;
 301         void __iomem *ctrl;
 302         const u32 *pval;
 303         u32 idx;
 304
 305         /* Enable I2C interrupts for mpc5121 */
 306         node_ctrl = of_find_compatible_node(NULL, NULL,
 307                                             "fsl,mpc5121-i2c-ctrl");
 308         if (node_ctrl) {
 309                 ctrl = of_iomap(node_ctrl, 0);
 310                 if (ctrl) {
 311                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
 312                         pval = of_get_property(node, "reg", NULL);
 313                         idx = (*pval & 0xff) / 0x20;
 314                         setbits32(ctrl, 1 << (24 + idx * 2));
 315                         iounmap(ctrl);
 316                 }
 317                 of_node_put(node_ctrl);
 318         }
 319
 320         /* The clock setup for the 52xx works also fine for the 512x */
 321         mpc_i2c_setup_52xx(node, i2c, clock);
 322 }
 323 #else /* CONFIG_PPC_MPC512x */
 324 static void mpc_i2c_setup_512x(struct device_node *node,
 325                                          struct mpc_i2c *i2c,
 326                                          u32 clock)
 327 {
 328 }
 329 #endif /* CONFIG_PPC_MPC512x */
 330
 331 #ifdef CONFIG_FSL_SOC
 332 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
 333         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
 334         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
 335         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
 336         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
 337         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
 338         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
 339         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
 340         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
 341         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
 342         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
 343         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
 344         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
 345         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
 346         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
 347         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
 348         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
 349         {49152, 0x011e}, {61440, 0x011f}
 350 };
 351
 352 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
 353 {
 354         struct device_node *node;
 355         u32 __iomem *reg;
 356         u32 val = 0;
 357
 358         node = of_find_node_by_name(NULL, "global-utilities");
 359         if (node) {
 360                 const u32 *prop = of_get_property(node, "reg", NULL);
 361                 if (prop) {
 362                         /*
 363                          * Map and check POR Device Status Register 2
 364                          * (PORDEVSR2) at 0xE0014. Note than while MPC8533
 365                          * and MPC8544 indicate SEC frequency ratio
 366                          * configuration as bit 26 in PORDEVSR2, other MPC8xxx
 367                          * parts may store it differently or may not have it
 368                          * at all.
 369                          */
 370                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
 371                         if (!reg)
 372                                 printk(KERN_ERR
 373                                        "Error: couldn't map PORDEVSR2\n");
 374                         else
 375                                 val = in_be32(reg) & 0x00000020; /* sec-cfg */
 376                         iounmap(reg);
 377                 }
 378         }
 379         of_node_put(node);
 380
 381         return val;
 382 }
 383
 384 static u32 mpc_i2c_get_prescaler_8xxx(void)
 385 {
 386         /*
 387          * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
 388          * may have prescaler 1, 2, or 3, depending on the power-on
 389          * configuration.
 390          */
 391         u32 prescaler = 1;
 392
 393         /* mpc85xx */
 394         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
 395                 || pvr_version_is(PVR_VER_E500MC)
 396                 || pvr_version_is(PVR_VER_E5500)
 397                 || pvr_version_is(PVR_VER_E6500)) {
 398                 unsigned int svr = mfspr(SPRN_SVR);
 399
 400                 if ((SVR_SOC_VER(svr) == SVR_8540)
 401                         || (SVR_SOC_VER(svr) == SVR_8541)
 402                         || (SVR_SOC_VER(svr) == SVR_8560)
 403                         || (SVR_SOC_VER(svr) == SVR_8555)
 404                         || (SVR_SOC_VER(svr) == SVR_8610))
 405                         /* the above 85xx SoCs have prescaler 1 */
 406                         prescaler = 1;
 407                 else if ((SVR_SOC_VER(svr) == SVR_8533)
 408                         || (SVR_SOC_VER(svr) == SVR_8544))
 409                         /* the above 85xx SoCs have prescaler 3 or 2 */
 410                         prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
 411                 else
 412                         /* all the other 85xx have prescaler 2 */
 413                         prescaler = 2;
 414         }
 415
 416         return prescaler;
 417 }
 418
 419 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
 420                                           u32 *real_clk)
 421 {
 422         const struct mpc_i2c_divider *div = NULL;
 423         u32 prescaler = mpc_i2c_get_prescaler_8xxx();
 424         u32 divider;
 425         int i;
 426
 427         if (clock == MPC_I2C_CLOCK_LEGACY) {
 428                 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
 429                 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
 430                 return -EINVAL;
 431         }
 432
 433         divider = fsl_get_sys_freq() / clock / prescaler;
 434
 435         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
 436                  fsl_get_sys_freq(), clock, divider);
 437
 438         /*
 439          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 440          * is equal to or lower than the requested speed.
 441          */
 442         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
 443                 div = &mpc_i2c_dividers_8xxx[i];
 444                 if (div->divider >= divider)
 445                         break;
 446         }
 447
 448         *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
 449         return (int)div->fdr;
 450 }
 451
 452 static void mpc_i2c_setup_8xxx(struct device_node *node,
 453                                          struct mpc_i2c *i2c,
 454                                          u32 clock)
 455 {
 456         int ret, fdr;
 457
 458         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 459                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
 460                         readb(i2c->base + MPC_I2C_DFSRR),
 461                         readb(i2c->base + MPC_I2C_FDR));
 462                 return;
 463         }
 464
 465         ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
 466         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
 467
 468         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 469         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
 470
 471         if (ret >= 0)
 472                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
 473                          i2c->real_clk, fdr >> 8, fdr & 0xff);
 474 }
 475
 476 #else /* !CONFIG_FSL_SOC */
 477 static void mpc_i2c_setup_8xxx(struct device_node *node,
 478                                          struct mpc_i2c *i2c,
 479                                          u32 clock)
 480 {
 481 }
 482 #endif /* CONFIG_FSL_SOC */
 483
 484 static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc)
 485 {
 486         i2c->rc = rc;
 487         i2c->block = 0;
 488         i2c->cntl_bits = CCR_MEN;
 489         writeccr(i2c, i2c->cntl_bits);
 490         wake_up(&i2c->waitq);
 491 }
 492
 493 static void mpc_i2c_do_action(struct mpc_i2c *i2c)
 494 {
 495         struct i2c_msg *msg = &i2c->msgs[i2c->curr_msg];
 496         int dir = 0;
 497         int recv_len = 0;
 498         u8 byte;
 499
 500         dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]);
 501
 502         i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK);
 503
 504         if (msg->flags & I2C_M_RD)
 505                 dir = 1;
 506         if (msg->flags & I2C_M_RECV_LEN)
 507                 recv_len = 1;
 508
 509         switch (i2c->action) {
 510         case MPC_I2C_ACTION_RESTART:
 511                 i2c->cntl_bits |= CCR_RSTA;
 512                 fallthrough;
 513
 514         case MPC_I2C_ACTION_START:
 515                 i2c->cntl_bits |= CCR_MSTA | CCR_MTX;
 516                 writeccr(i2c, i2c->cntl_bits);
 517                 writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR);
 518                 i2c->expect_rxack = 1;
 519                 i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE;
 520                 break;
 521
 522         case MPC_I2C_ACTION_READ_BEGIN:
 523                 if (msg->len) {
 524                         if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
 525                                 i2c->cntl_bits |= CCR_TXAK;
 526
 527                         writeccr(i2c, i2c->cntl_bits);
 528                         /* Dummy read */
 529                         readb(i2c->base + MPC_I2C_DR);
 530                 }
 531                 i2c->action = MPC_I2C_ACTION_READ_BYTE;
 532                 break;
 533
 534         case MPC_I2C_ACTION_READ_BYTE:
 535                 if (i2c->byte_posn || !recv_len) {
 536                         /* Generate Tx ACK on next to last byte */
 537                         if (i2c->byte_posn == msg->len - 2)
 538                                 i2c->cntl_bits |= CCR_TXAK;
 539                         /* Do not generate stop on last byte */
 540                         if (i2c->byte_posn == msg->len - 1)
 541                                 i2c->cntl_bits |= CCR_MTX;
 542
 543                         writeccr(i2c, i2c->cntl_bits);
 544                 }
 545
 546                 byte = readb(i2c->base + MPC_I2C_DR);
 547
 548                 if (i2c->byte_posn == 0 && recv_len) {
 549                         if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) {
 550                                 mpc_i2c_finish(i2c, -EPROTO);
 551                                 return;
 552                         }
 553                         msg->len += byte;
 554                         /*
 555                          * For block reads, generate Tx ACK here if data length
 556                          * is 1 byte (total length is 2 bytes).
 557                          */
 558                         if (msg->len == 2) {
 559                                 i2c->cntl_bits |= CCR_TXAK;
 560                                 writeccr(i2c, i2c->cntl_bits);
 561                         }
 562                 }
 563
 564                 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte);
 565                 msg->buf[i2c->byte_posn++] = byte;
 566                 break;
 567
 568         case MPC_I2C_ACTION_WRITE:
 569                 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action],
 570                         msg->buf[i2c->byte_posn]);
 571                 writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR);
 572                 i2c->expect_rxack = 1;
 573                 break;
 574
 575         case MPC_I2C_ACTION_STOP:
 576                 mpc_i2c_finish(i2c, 0);
 577                 break;
 578
 579         default:
 580                 WARN(1, "Unexpected action %d\n", i2c->action);
 581                 break;
 582         }
 583
 584         if (msg->len == i2c->byte_posn) {
 585                 i2c->curr_msg++;
 586                 i2c->byte_posn = 0;
 587
 588                 if (i2c->curr_msg == i2c->num_msgs) {
 589                         i2c->action = MPC_I2C_ACTION_STOP;
 590                         /*
 591                          * We don't get another interrupt on read so
 592                          * finish the transfer now
 593                          */
 594                         if (dir)
 595                                 mpc_i2c_finish(i2c, 0);
 596                 } else {
 597                         i2c->action = MPC_I2C_ACTION_RESTART;
 598                 }
 599         }
 600 }
 601
 602 static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status)
 603 {
 604         spin_lock(&i2c->lock);
 605
 606         if (!(status & CSR_MCF)) {
 607                 dev_dbg(i2c->dev, "unfinished\n");
 608                 mpc_i2c_finish(i2c, -EIO);
 609                 goto out;
 610         }
 611
 612         if (status & CSR_MAL) {
 613                 dev_dbg(i2c->dev, "arbitration lost\n");
 614                 mpc_i2c_finish(i2c, -EAGAIN);
 615                 goto out;
 616         }
 617
 618         if (i2c->expect_rxack && (status & CSR_RXAK)) {
 619                 dev_dbg(i2c->dev, "no Rx ACK\n");
 620                 mpc_i2c_finish(i2c, -ENXIO);
 621                 goto out;
 622         }
 623         i2c->expect_rxack = 0;
 624
 625         mpc_i2c_do_action(i2c);
 626
 627 out:
 628         spin_unlock(&i2c->lock);
 629 }
 630
 631 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
 632 {
 633         struct mpc_i2c *i2c = dev_id;
 634         u8 status;
 635
 636         status = readb(i2c->base + MPC_I2C_SR);
 637         if (status & CSR_MIF) {
 638                 writeb(0, i2c->base + MPC_I2C_SR);
 639                 mpc_i2c_do_intr(i2c, status);
 640                 return IRQ_HANDLED;
 641         }
 642         return IRQ_NONE;
 643 }
 644
 645 static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c)
 646 {
 647         long time_left;
 648
 649         time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout);
 650         if (!time_left)
 651                 return -ETIMEDOUT;
 652         if (time_left < 0)
 653                 return time_left;
 654
 655         return 0;
 656 }
 657
 658 static int mpc_i2c_execute_msg(struct mpc_i2c *i2c)
 659 {
 660         unsigned long orig_jiffies;
 661         unsigned long flags;
 662         int ret;
 663
 664         spin_lock_irqsave(&i2c->lock, flags);
 665
 666         i2c->curr_msg = 0;
 667         i2c->rc = 0;
 668         i2c->byte_posn = 0;
 669         i2c->block = 1;
 670         i2c->action = MPC_I2C_ACTION_START;
 671
 672         i2c->cntl_bits = CCR_MEN | CCR_MIEN;
 673         writeb(0, i2c->base + MPC_I2C_SR);
 674         writeccr(i2c, i2c->cntl_bits);
 675
 676         mpc_i2c_do_action(i2c);
 677
 678         spin_unlock_irqrestore(&i2c->lock, flags);
 679
 680         ret = mpc_i2c_wait_for_completion(i2c);
 681         if (ret)
 682                 i2c->rc = ret;
 683
 684         if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT)
 685                 i2c_recover_bus(&i2c->adap);
 686
 687         orig_jiffies = jiffies;
 688         /* Wait until STOP is seen, allow up to 1 s */
 689         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 690                 if (time_after(jiffies, orig_jiffies + HZ)) {
 691                         u8 status = readb(i2c->base + MPC_I2C_SR);
 692
 693                         dev_dbg(i2c->dev, "timeout\n");
 694                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
 695                                 writeb(status & ~CSR_MAL,
 696                                        i2c->base + MPC_I2C_SR);
 697                                 i2c_recover_bus(&i2c->adap);
 698                         }
 699                         return -EIO;
 700                 }
 701                 cond_resched();
 702         }
 703
 704         return i2c->rc;
 705 }
 706
 707 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 708 {
 709         int rc, ret = num;
 710         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 711         int i;
 712
 713         dev_dbg(i2c->dev, "num = %d\n", num);
 714         for (i = 0; i < num; i++)
 715                 dev_dbg(i2c->dev, "  addr = %02x, flags = %02x, len = %d, %*ph\n",
 716                         msgs[i].addr, msgs[i].flags, msgs[i].len,
 717                         msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len,
 718                         msgs[i].buf);
 719
 720         WARN_ON(i2c->msgs != NULL);
 721         i2c->msgs = msgs;
 722         i2c->num_msgs = num;
 723
 724         rc = mpc_i2c_execute_msg(i2c);
 725         if (rc < 0)
 726                 ret = rc;
 727
 728         i2c->num_msgs = 0;
 729         i2c->msgs = NULL;
 730
 731         return ret;
 732 }
 733
 734 static u32 mpc_functionality(struct i2c_adapter *adap)
 735 {
 736         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 737           | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
 738 }
 739
 740 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
 741 {
 742         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 743
 744         if (i2c->has_errata_A004447)
 745                 mpc_i2c_fixup_A004447(i2c);
 746         else
 747                 mpc_i2c_fixup(i2c);
 748
 749         return 0;
 750 }
 751
 752 static const struct i2c_algorithm mpc_algo = {
 753         .master_xfer = mpc_xfer,
 754         .functionality = mpc_functionality,
 755 };
 756
 757 static struct i2c_adapter mpc_ops = {
 758         .owner = THIS_MODULE,
 759         .algo = &mpc_algo,
 760         .timeout = HZ,
 761 };
 762
 763 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
 764         .recover_bus = fsl_i2c_bus_recovery,
 765 };
 766
 767 static int fsl_i2c_probe(struct platform_device *op)
 768 {
 769         const struct mpc_i2c_data *data;
 770         struct mpc_i2c *i2c;
 771         const u32 *prop;
 772         u32 clock = MPC_I2C_CLOCK_LEGACY;
 773         int result = 0;
 774         int plen;
 775         struct clk *clk;
 776         int err;
 777
 778         i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL);
 779         if (!i2c)
 780                 return -ENOMEM;
 781
 782         i2c->dev = &op->dev; /* for debug and error output */
 783
 784         init_waitqueue_head(&i2c->waitq);
 785         spin_lock_init(&i2c->lock);
 786
 787         i2c->base = devm_platform_ioremap_resource(op, 0);
 788         if (IS_ERR(i2c->base))
 789                 return PTR_ERR(i2c->base);
 790
 791         i2c->irq = platform_get_irq(op, 0);
 792         if (i2c->irq < 0)
 793                 return i2c->irq;
 794
 795         result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr,
 796                         IRQF_SHARED, "i2c-mpc", i2c);
 797         if (result < 0) {
 798                 dev_err(i2c->dev, "failed to attach interrupt\n");
 799                 return result;
 800         }
 801
 802         /*
 803          * enable clock for the I2C peripheral (non fatal),
 804          * keep a reference upon successful allocation
 805          */
 806         clk = devm_clk_get_optional(&op->dev, NULL);
 807         if (IS_ERR(clk))
 808                 return PTR_ERR(clk);
 809
 810         err = clk_prepare_enable(clk);
 811         if (err) {
 812                 dev_err(&op->dev, "failed to enable clock\n");
 813                 return err;
 814         }
 815
 816         i2c->clk_per = clk;
 817
 818         if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
 819                 clock = MPC_I2C_CLOCK_PRESERVE;
 820         } else {
 821                 prop = of_get_property(op->dev.of_node, "clock-frequency",
 822                                         &plen);
 823                 if (prop && plen == sizeof(u32))
 824                         clock = *prop;
 825         }
 826
 827         data = device_get_match_data(&op->dev);
 828         if (data) {
 829                 data->setup(op->dev.of_node, i2c, clock);
 830         } else {
 831                 /* Backwards compatibility */
 832                 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
 833                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
 834         }
 835
 836         prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
 837         if (prop && plen == sizeof(u32)) {
 838                 mpc_ops.timeout = *prop * HZ / 1000000;
 839                 if (mpc_ops.timeout < 5)
 840                         mpc_ops.timeout = 5;
 841         }
 842         dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
 843
 844         if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
 845                 i2c->has_errata_A004447 = true;
 846
 847         i2c->adap = mpc_ops;
 848         scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
 849                   "MPC adapter (%s)", of_node_full_name(op->dev.of_node));
 850         i2c->adap.dev.parent = &op->dev;
 851         i2c->adap.nr = op->id;
 852         i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
 853         i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
 854         platform_set_drvdata(op, i2c);
 855         i2c_set_adapdata(&i2c->adap, i2c);
 856
 857         result = i2c_add_numbered_adapter(&i2c->adap);
 858         if (result)
 859                 goto fail_add;
 860
 861         return 0;
 862
 863  fail_add:
 864         clk_disable_unprepare(i2c->clk_per);
 865
 866         return result;
 867 };
 868
 869 static int fsl_i2c_remove(struct platform_device *op)
 870 {
 871         struct mpc_i2c *i2c = platform_get_drvdata(op);
 872
 873         i2c_del_adapter(&i2c->adap);
 874
 875         clk_disable_unprepare(i2c->clk_per);
 876
 877         return 0;
 878 };
 879
 880 static int __maybe_unused mpc_i2c_suspend(struct device *dev)
 881 {
 882         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 883
 884         i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
 885         i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
 886
 887         return 0;
 888 }
 889
 890 static int __maybe_unused mpc_i2c_resume(struct device *dev)
 891 {
 892         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 893
 894         writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
 895         writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
 896
 897         return 0;
 898 }
 899 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
 900
 901 static const struct mpc_i2c_data mpc_i2c_data_512x = {
 902         .setup = mpc_i2c_setup_512x,
 903 };
 904
 905 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
 906         .setup = mpc_i2c_setup_52xx,
 907 };
 908
 909 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
 910         .setup = mpc_i2c_setup_8xxx,
 911 };
 912
 913 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
 914         .setup = mpc_i2c_setup_8xxx,
 915 };
 916
 917 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
 918         .setup = mpc_i2c_setup_8xxx,
 919 };
 920
 921 static const struct of_device_id mpc_i2c_of_match[] = {
 922         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 923         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
 924         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 925         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
 926         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
 927         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
 928         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
 929         /* Backward compatibility */
 930         {.compatible = "fsl-i2c", },
 931         {},
 932 };
 933 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
 934
 935 /* Structure for a device driver */
 936 static struct platform_driver mpc_i2c_driver = {
 937         .probe          = fsl_i2c_probe,
 938         .remove         = fsl_i2c_remove,
 939         .driver = {
 940                 .name = DRV_NAME,
 941                 .of_match_table = mpc_i2c_of_match,
 942                 .pm = &mpc_i2c_pm_ops,
 943         },
 944 };
 945
 946 module_platform_driver(mpc_i2c_driver);
 947
 948 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 949 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
 950                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
 951 MODULE_LICENSE("GPL");