2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
54 Features supported by this driver:
58 Block process call transaction no
59 I2C block read transaction yes (doesn't use the block buffer)
62 See the file Documentation/i2c/busses/i2c-i801 for details.
65 #include <linux/module.h>
66 #include <linux/pci.h>
67 #include <linux/kernel.h>
68 #include <linux/stddef.h>
69 #include <linux/delay.h>
70 #include <linux/ioport.h>
71 #include <linux/init.h>
72 #include <linux/i2c.h>
73 #include <linux/acpi.h>
75 #include <linux/dmi.h>
76 #include <linux/slab.h>
78 /* I801 SMBus address offsets */
79 #define SMBHSTSTS(p) (0 + (p)->smba)
80 #define SMBHSTCNT(p) (2 + (p)->smba)
81 #define SMBHSTCMD(p) (3 + (p)->smba)
82 #define SMBHSTADD(p) (4 + (p)->smba)
83 #define SMBHSTDAT0(p) (5 + (p)->smba)
84 #define SMBHSTDAT1(p) (6 + (p)->smba)
85 #define SMBBLKDAT(p) (7 + (p)->smba)
86 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
87 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
88 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
90 /* PCI Address Constants */
92 #define SMBHSTCFG 0x040
94 /* Host configuration bits for SMBHSTCFG */
95 #define SMBHSTCFG_HST_EN 1
96 #define SMBHSTCFG_SMB_SMI_EN 2
97 #define SMBHSTCFG_I2C_EN 4
99 /* Auxiliary control register bits, ICH4+ only */
100 #define SMBAUXCTL_CRC 1
101 #define SMBAUXCTL_E32B 2
103 /* kill bit for SMBHSTCNT */
104 #define SMBHSTCNT_KILL 2
107 #define MAX_TIMEOUT 100
108 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
110 /* I801 command constants */
111 #define I801_QUICK 0x00
112 #define I801_BYTE 0x04
113 #define I801_BYTE_DATA 0x08
114 #define I801_WORD_DATA 0x0C
115 #define I801_PROC_CALL 0x10 /* unimplemented */
116 #define I801_BLOCK_DATA 0x14
117 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
118 #define I801_BLOCK_LAST 0x34
119 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
120 #define I801_START 0x40
121 #define I801_PEC_EN 0x80 /* ICH3 and later */
123 /* I801 Hosts Status register bits */
124 #define SMBHSTSTS_BYTE_DONE 0x80
125 #define SMBHSTSTS_INUSE_STS 0x40
126 #define SMBHSTSTS_SMBALERT_STS 0x20
127 #define SMBHSTSTS_FAILED 0x10
128 #define SMBHSTSTS_BUS_ERR 0x08
129 #define SMBHSTSTS_DEV_ERR 0x04
130 #define SMBHSTSTS_INTR 0x02
131 #define SMBHSTSTS_HOST_BUSY 0x01
133 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
134 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
137 /* Older devices have their ID defined in <linux/pci_ids.h> */
138 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
139 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
140 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
141 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
142 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
143 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
144 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
145 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
146 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
149 struct i2c_adapter adapter;
151 unsigned char original_hstcfg;
152 struct pci_dev *pci_dev;
153 unsigned int features;
156 static struct pci_driver i801_driver;
158 #define FEATURE_SMBUS_PEC (1 << 0)
159 #define FEATURE_BLOCK_BUFFER (1 << 1)
160 #define FEATURE_BLOCK_PROC (1 << 2)
161 #define FEATURE_I2C_BLOCK_READ (1 << 3)
163 static const char *i801_feature_names[] = {
166 "Block process call",
170 static unsigned int disable_features;
171 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
172 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
174 /* Make sure the SMBus host is ready to start transmitting.
175 Return 0 if it is, -EBUSY if it is not. */
176 static int i801_check_pre(struct i801_priv *priv)
180 status = inb_p(SMBHSTSTS(priv));
181 if (status & SMBHSTSTS_HOST_BUSY) {
182 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
186 status &= STATUS_FLAGS;
188 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
190 outb_p(status, SMBHSTSTS(priv));
191 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
193 dev_err(&priv->pci_dev->dev,
194 "Failed clearing status flags (%02x)\n",
203 /* Convert the status register to an error code, and clear it. */
204 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
208 /* If the SMBus is still busy, we give up */
210 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
211 /* try to stop the current command */
212 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
213 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
216 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
219 /* Check if it worked */
220 status = inb_p(SMBHSTSTS(priv));
221 if ((status & SMBHSTSTS_HOST_BUSY) ||
222 !(status & SMBHSTSTS_FAILED))
223 dev_err(&priv->pci_dev->dev,
224 "Failed terminating the transaction\n");
225 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
229 if (status & SMBHSTSTS_FAILED) {
231 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
233 if (status & SMBHSTSTS_DEV_ERR) {
235 dev_dbg(&priv->pci_dev->dev, "No response\n");
237 if (status & SMBHSTSTS_BUS_ERR) {
239 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
243 /* Clear error flags */
244 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
245 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
247 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
248 "flags at end of transaction (%02x)\n",
256 static int i801_transaction(struct i801_priv *priv, int xact)
262 result = i801_check_pre(priv);
266 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
267 * INTREN, SMBSCMD are passed in xact */
268 outb_p(xact | I801_START, SMBHSTCNT(priv));
270 /* We will always wait for a fraction of a second! */
273 status = inb_p(SMBHSTSTS(priv));
274 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
276 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
280 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
284 /* wait for INTR bit as advised by Intel */
285 static void i801_wait_hwpec(struct i801_priv *priv)
292 status = inb_p(SMBHSTSTS(priv));
293 } while ((!(status & SMBHSTSTS_INTR))
294 && (timeout++ < MAX_TIMEOUT));
296 if (timeout > MAX_TIMEOUT)
297 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
299 outb_p(status, SMBHSTSTS(priv));
302 static int i801_block_transaction_by_block(struct i801_priv *priv,
303 union i2c_smbus_data *data,
304 char read_write, int hwpec)
309 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
311 /* Use 32-byte buffer to process this transaction */
312 if (read_write == I2C_SMBUS_WRITE) {
313 len = data->block[0];
314 outb_p(len, SMBHSTDAT0(priv));
315 for (i = 0; i < len; i++)
316 outb_p(data->block[i+1], SMBBLKDAT(priv));
319 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
320 I801_PEC_EN * hwpec);
324 if (read_write == I2C_SMBUS_READ) {
325 len = inb_p(SMBHSTDAT0(priv));
326 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
329 data->block[0] = len;
330 for (i = 0; i < len; i++)
331 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
336 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
337 union i2c_smbus_data *data,
338 char read_write, int command,
347 result = i801_check_pre(priv);
351 len = data->block[0];
353 if (read_write == I2C_SMBUS_WRITE) {
354 outb_p(len, SMBHSTDAT0(priv));
355 outb_p(data->block[1], SMBBLKDAT(priv));
358 for (i = 1; i <= len; i++) {
359 if (i == len && read_write == I2C_SMBUS_READ) {
360 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
361 smbcmd = I801_I2C_BLOCK_LAST;
363 smbcmd = I801_BLOCK_LAST;
365 if (command == I2C_SMBUS_I2C_BLOCK_DATA
366 && read_write == I2C_SMBUS_READ)
367 smbcmd = I801_I2C_BLOCK_DATA;
369 smbcmd = I801_BLOCK_DATA;
371 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
374 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
377 /* We will always wait for a fraction of a second! */
381 status = inb_p(SMBHSTSTS(priv));
382 } while ((!(status & SMBHSTSTS_BYTE_DONE))
383 && (timeout++ < MAX_TIMEOUT));
385 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
389 if (i == 1 && read_write == I2C_SMBUS_READ
390 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
391 len = inb_p(SMBHSTDAT0(priv));
392 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
393 dev_err(&priv->pci_dev->dev,
394 "Illegal SMBus block read size %d\n",
397 while (inb_p(SMBHSTSTS(priv)) &
399 outb_p(SMBHSTSTS_BYTE_DONE,
401 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
404 data->block[0] = len;
407 /* Retrieve/store value in SMBBLKDAT */
408 if (read_write == I2C_SMBUS_READ)
409 data->block[i] = inb_p(SMBBLKDAT(priv));
410 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
411 outb_p(data->block[i+1], SMBBLKDAT(priv));
413 /* signals SMBBLKDAT ready */
414 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
420 static int i801_set_block_buffer_mode(struct i801_priv *priv)
422 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
423 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
428 /* Block transaction function */
429 static int i801_block_transaction(struct i801_priv *priv,
430 union i2c_smbus_data *data, char read_write,
431 int command, int hwpec)
436 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
437 if (read_write == I2C_SMBUS_WRITE) {
438 /* set I2C_EN bit in configuration register */
439 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
440 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
441 hostc | SMBHSTCFG_I2C_EN);
442 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
443 dev_err(&priv->pci_dev->dev,
444 "I2C block read is unsupported!\n");
449 if (read_write == I2C_SMBUS_WRITE
450 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
451 if (data->block[0] < 1)
453 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
454 data->block[0] = I2C_SMBUS_BLOCK_MAX;
456 data->block[0] = 32; /* max for SMBus block reads */
459 /* Experience has shown that the block buffer can only be used for
460 SMBus (not I2C) block transactions, even though the datasheet
461 doesn't mention this limitation. */
462 if ((priv->features & FEATURE_BLOCK_BUFFER)
463 && command != I2C_SMBUS_I2C_BLOCK_DATA
464 && i801_set_block_buffer_mode(priv) == 0)
465 result = i801_block_transaction_by_block(priv, data,
468 result = i801_block_transaction_byte_by_byte(priv, data,
472 if (result == 0 && hwpec)
473 i801_wait_hwpec(priv);
475 if (command == I2C_SMBUS_I2C_BLOCK_DATA
476 && read_write == I2C_SMBUS_WRITE) {
477 /* restore saved configuration register value */
478 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
483 /* Return negative errno on error. */
484 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
485 unsigned short flags, char read_write, u8 command,
486 int size, union i2c_smbus_data *data)
491 struct i801_priv *priv = i2c_get_adapdata(adap);
493 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
494 && size != I2C_SMBUS_QUICK
495 && size != I2C_SMBUS_I2C_BLOCK_DATA;
498 case I2C_SMBUS_QUICK:
499 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
504 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
506 if (read_write == I2C_SMBUS_WRITE)
507 outb_p(command, SMBHSTCMD(priv));
510 case I2C_SMBUS_BYTE_DATA:
511 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
513 outb_p(command, SMBHSTCMD(priv));
514 if (read_write == I2C_SMBUS_WRITE)
515 outb_p(data->byte, SMBHSTDAT0(priv));
516 xact = I801_BYTE_DATA;
518 case I2C_SMBUS_WORD_DATA:
519 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
521 outb_p(command, SMBHSTCMD(priv));
522 if (read_write == I2C_SMBUS_WRITE) {
523 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
524 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
526 xact = I801_WORD_DATA;
528 case I2C_SMBUS_BLOCK_DATA:
529 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
531 outb_p(command, SMBHSTCMD(priv));
534 case I2C_SMBUS_I2C_BLOCK_DATA:
535 /* NB: page 240 of ICH5 datasheet shows that the R/#W
536 * bit should be cleared here, even when reading */
537 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
538 if (read_write == I2C_SMBUS_READ) {
539 /* NB: page 240 of ICH5 datasheet also shows
540 * that DATA1 is the cmd field when reading */
541 outb_p(command, SMBHSTDAT1(priv));
543 outb_p(command, SMBHSTCMD(priv));
547 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
552 if (hwpec) /* enable/disable hardware PEC */
553 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
555 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
559 ret = i801_block_transaction(priv, data, read_write, size,
562 ret = i801_transaction(priv, xact | ENABLE_INT9);
564 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
565 time, so we forcibly disable it after every transaction. Turn off
566 E32B for the same reason. */
568 outb_p(inb_p(SMBAUXCTL(priv)) &
569 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
575 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
578 switch (xact & 0x7f) {
579 case I801_BYTE: /* Result put in SMBHSTDAT0 */
581 data->byte = inb_p(SMBHSTDAT0(priv));
584 data->word = inb_p(SMBHSTDAT0(priv)) +
585 (inb_p(SMBHSTDAT1(priv)) << 8);
592 static u32 i801_func(struct i2c_adapter *adapter)
594 struct i801_priv *priv = i2c_get_adapdata(adapter);
596 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
597 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
598 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
599 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
600 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
601 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
604 static const struct i2c_algorithm smbus_algorithm = {
605 .smbus_xfer = i801_access,
606 .functionality = i801_func,
609 static const struct pci_device_id i801_ids[] = {
610 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
611 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
612 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
613 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
614 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
635 MODULE_DEVICE_TABLE(pci, i801_ids);
637 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
638 static unsigned char apanel_addr;
640 /* Scan the system ROM for the signature "FJKEYINF" */
641 static __init const void __iomem *bios_signature(const void __iomem *bios)
644 const unsigned char signature[] = "FJKEYINF";
646 for (offset = 0; offset < 0x10000; offset += 0x10) {
647 if (check_signature(bios + offset, signature,
648 sizeof(signature)-1))
649 return bios + offset;
654 static void __init input_apanel_init(void)
657 const void __iomem *p;
659 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
660 p = bios_signature(bios);
662 /* just use the first address */
663 apanel_addr = readb(p + 8 + 3) >> 1;
668 static void __init input_apanel_init(void) {}
671 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
672 struct dmi_onboard_device_info {
675 unsigned short i2c_addr;
676 const char *i2c_type;
679 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
680 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
681 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
682 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
685 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
686 struct i2c_adapter *adap)
689 struct i2c_board_info info;
691 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
692 /* & ~0x80, ignore enabled/disabled bit */
693 if ((type & ~0x80) != dmi_devices[i].type)
695 if (strcasecmp(name, dmi_devices[i].name))
698 memset(&info, 0, sizeof(struct i2c_board_info));
699 info.addr = dmi_devices[i].i2c_addr;
700 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
701 i2c_new_device(adap, &info);
706 /* We use our own function to check for onboard devices instead of
707 dmi_find_device() as some buggy BIOS's have the devices we are interested
708 in marked as disabled */
709 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
717 count = (dm->length - sizeof(struct dmi_header)) / 2;
718 for (i = 0; i < count; i++) {
719 const u8 *d = (char *)(dm + 1) + (i * 2);
720 const char *name = ((char *) dm) + dm->length;
727 while (s > 0 && name[0]) {
728 name += strlen(name) + 1;
731 if (name[0] == 0) /* Bogus string reference */
734 dmi_check_onboard_device(type, name, adap);
739 static int __devinit i801_probe(struct pci_dev *dev,
740 const struct pci_device_id *id)
744 struct i801_priv *priv;
746 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
750 i2c_set_adapdata(&priv->adapter, priv);
751 priv->adapter.owner = THIS_MODULE;
752 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
753 priv->adapter.algo = &smbus_algorithm;
756 switch (dev->device) {
758 priv->features |= FEATURE_I2C_BLOCK_READ;
760 case PCI_DEVICE_ID_INTEL_82801DB_3:
761 priv->features |= FEATURE_SMBUS_PEC;
762 priv->features |= FEATURE_BLOCK_BUFFER;
764 case PCI_DEVICE_ID_INTEL_82801CA_3:
765 case PCI_DEVICE_ID_INTEL_82801BA_2:
766 case PCI_DEVICE_ID_INTEL_82801AB_3:
767 case PCI_DEVICE_ID_INTEL_82801AA_3:
771 /* Disable features on user request */
772 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
773 if (priv->features & disable_features & (1 << i))
774 dev_notice(&dev->dev, "%s disabled by user\n",
775 i801_feature_names[i]);
777 priv->features &= ~disable_features;
779 err = pci_enable_device(dev);
781 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
786 /* Determine the address of the SMBus area */
787 priv->smba = pci_resource_start(dev, SMBBAR);
789 dev_err(&dev->dev, "SMBus base address uninitialized, "
795 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
801 err = pci_request_region(dev, SMBBAR, i801_driver.name);
803 dev_err(&dev->dev, "Failed to request SMBus region "
804 "0x%lx-0x%Lx\n", priv->smba,
805 (unsigned long long)pci_resource_end(dev, SMBBAR));
809 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
810 priv->original_hstcfg = temp;
811 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
812 if (!(temp & SMBHSTCFG_HST_EN)) {
813 dev_info(&dev->dev, "Enabling SMBus device\n");
814 temp |= SMBHSTCFG_HST_EN;
816 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
818 if (temp & SMBHSTCFG_SMB_SMI_EN)
819 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
821 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
823 /* Clear special mode bits */
824 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
825 outb_p(inb_p(SMBAUXCTL(priv)) &
826 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
828 /* set up the sysfs linkage to our parent device */
829 priv->adapter.dev.parent = &dev->dev;
831 /* Retry up to 3 times on lost arbitration */
832 priv->adapter.retries = 3;
834 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
835 "SMBus I801 adapter at %04lx", priv->smba);
836 err = i2c_add_adapter(&priv->adapter);
838 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
842 /* Register optional slaves */
843 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
845 struct i2c_board_info info;
847 memset(&info, 0, sizeof(struct i2c_board_info));
848 info.addr = apanel_addr;
849 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
850 i2c_new_device(&priv->adapter, &info);
853 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
854 if (dmi_name_in_vendors("FUJITSU"))
855 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
858 pci_set_drvdata(dev, priv);
862 pci_release_region(dev, SMBBAR);
868 static void __devexit i801_remove(struct pci_dev *dev)
870 struct i801_priv *priv = pci_get_drvdata(dev);
872 i2c_del_adapter(&priv->adapter);
873 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
874 pci_release_region(dev, SMBBAR);
875 pci_set_drvdata(dev, NULL);
878 * do not call pci_disable_device(dev) since it can cause hard hangs on
879 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
884 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
886 struct i801_priv *priv = pci_get_drvdata(dev);
889 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
890 pci_set_power_state(dev, pci_choose_state(dev, mesg));
894 static int i801_resume(struct pci_dev *dev)
896 pci_set_power_state(dev, PCI_D0);
897 pci_restore_state(dev);
898 return pci_enable_device(dev);
901 #define i801_suspend NULL
902 #define i801_resume NULL
905 static struct pci_driver i801_driver = {
906 .name = "i801_smbus",
907 .id_table = i801_ids,
909 .remove = __devexit_p(i801_remove),
910 .suspend = i801_suspend,
911 .resume = i801_resume,
914 static int __init i2c_i801_init(void)
917 return pci_register_driver(&i801_driver);
920 static void __exit i2c_i801_exit(void)
922 pci_unregister_driver(&i801_driver);
925 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
926 "Jean Delvare <khali@linux-fr.org>");
927 MODULE_DESCRIPTION("I801 SMBus driver");
928 MODULE_LICENSE("GPL");
930 module_init(i2c_i801_init);
931 module_exit(i2c_i801_exit);