1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
11 #include <linux/acpi.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/export.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/swab.h>
25 #include <linux/types.h>
27 #include "i2c-designware-core.h"
29 static char *abort_sources[] = {
30 [ABRT_7B_ADDR_NOACK] =
31 "slave address not acknowledged (7bit mode)",
32 [ABRT_10ADDR1_NOACK] =
33 "first address byte not acknowledged (10bit mode)",
34 [ABRT_10ADDR2_NOACK] =
35 "second address byte not acknowledged (10bit mode)",
37 "data not acknowledged",
39 "no acknowledgement for a general call",
41 "read after general call",
43 "start byte acknowledged",
44 [ABRT_SBYTE_NORSTRT] =
45 "trying to send start byte when restart is disabled",
46 [ABRT_10B_RD_NORSTRT] =
47 "trying to read when restart is disabled (10bit mode)",
49 "trying to use disabled adapter",
52 [ABRT_SLAVE_FLUSH_TXFIFO] =
53 "read command so flush old data in the TX FIFO",
54 [ABRT_SLAVE_ARBLOST] =
55 "slave lost the bus while transmitting data to a remote master",
56 [ABRT_SLAVE_RD_INTX] =
57 "incorrect slave-transmitter mode configuration",
60 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
64 if (dev->flags & ACCESS_16BIT)
65 value = readw_relaxed(dev->base + offset) |
66 (readw_relaxed(dev->base + offset + 2) << 16);
68 value = readl_relaxed(dev->base + offset);
70 if (dev->flags & ACCESS_SWAP)
76 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
78 if (dev->flags & ACCESS_SWAP)
81 if (dev->flags & ACCESS_16BIT) {
82 writew_relaxed((u16)b, dev->base + offset);
83 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
85 writel_relaxed(b, dev->base + offset);
90 * i2c_dw_set_reg_access() - Set register access flags
91 * @dev: device private data
93 * Autodetects needed register access mode and sets access flags accordingly.
94 * This must be called before doing any other register access.
96 int i2c_dw_set_reg_access(struct dw_i2c_dev *dev)
101 ret = i2c_dw_acquire_lock(dev);
105 reg = dw_readl(dev, DW_IC_COMP_TYPE);
106 i2c_dw_release_lock(dev);
108 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
109 /* Configure register endianness access */
110 dev->flags |= ACCESS_SWAP;
111 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
112 /* Configure register access mode 16bit */
113 dev->flags |= ACCESS_16BIT;
114 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
116 "Unknown Synopsys component type: 0x%08x\n", reg);
123 static const u32 supported_speeds[] = {
124 I2C_MAX_HIGH_SPEED_MODE_FREQ,
125 I2C_MAX_FAST_MODE_PLUS_FREQ,
126 I2C_MAX_FAST_MODE_FREQ,
127 I2C_MAX_STANDARD_MODE_FREQ,
130 int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
132 struct i2c_timings *t = &dev->timings;
136 * Only standard mode at 100kHz, fast mode at 400kHz,
137 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
139 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
140 if (t->bus_freq_hz == supported_speeds[i])
145 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
150 EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
154 #include <linux/dmi.h>
157 * The HCNT/LCNT information coming from ACPI should be the most accurate
158 * for given platform. However, some systems get it wrong. On such systems
159 * we get better results by calculating those based on the input clock.
161 static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
163 .ident = "Dell Inspiron 7348",
165 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
166 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
172 static void i2c_dw_acpi_params(struct device *device, char method[],
173 u16 *hcnt, u16 *lcnt, u32 *sda_hold)
175 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
176 acpi_handle handle = ACPI_HANDLE(device);
177 union acpi_object *obj;
179 if (dmi_check_system(i2c_dw_no_acpi_params))
182 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
185 obj = (union acpi_object *)buf.pointer;
186 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
187 const union acpi_object *objs = obj->package.elements;
189 *hcnt = (u16)objs[0].integer.value;
190 *lcnt = (u16)objs[1].integer.value;
191 *sda_hold = (u32)objs[2].integer.value;
197 int i2c_dw_acpi_configure(struct device *device)
199 struct dw_i2c_dev *dev = dev_get_drvdata(device);
200 struct i2c_timings *t = &dev->timings;
201 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
203 dev->tx_fifo_depth = 32;
204 dev->rx_fifo_depth = 32;
207 * Try to get SDA hold time and *CNT values from an ACPI method for
208 * selected speed modes.
210 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
211 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
212 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
213 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
215 switch (t->bus_freq_hz) {
216 case I2C_MAX_STANDARD_MODE_FREQ:
217 dev->sda_hold_time = ss_ht;
219 case I2C_MAX_FAST_MODE_PLUS_FREQ:
220 dev->sda_hold_time = fp_ht;
222 case I2C_MAX_HIGH_SPEED_MODE_FREQ:
223 dev->sda_hold_time = hs_ht;
225 case I2C_MAX_FAST_MODE_FREQ:
227 dev->sda_hold_time = fs_ht;
233 EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
235 void i2c_dw_acpi_adjust_bus_speed(struct device *device)
237 struct dw_i2c_dev *dev = dev_get_drvdata(device);
238 struct i2c_timings *t = &dev->timings;
242 acpi_speed = i2c_acpi_find_bus_speed(device);
244 * Some DSTDs use a non standard speed, round down to the lowest
247 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
248 if (acpi_speed >= supported_speeds[i])
251 acpi_speed = i < ARRAY_SIZE(supported_speeds) ? supported_speeds[i] : 0;
254 * Find bus speed from the "clock-frequency" device property, ACPI
255 * or by using fast mode if neither is set.
257 if (acpi_speed && t->bus_freq_hz)
258 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
259 else if (acpi_speed || t->bus_freq_hz)
260 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
262 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
264 EXPORT_SYMBOL_GPL(i2c_dw_acpi_adjust_bus_speed);
266 #endif /* CONFIG_ACPI */
268 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
271 * DesignWare I2C core doesn't seem to have solid strategy to meet
272 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
273 * will result in violation of the tHD;STA spec.
277 * Conditional expression:
279 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
281 * This is based on the DW manuals, and represents an ideal
282 * configuration. The resulting I2C bus speed will be
283 * faster than any of the others.
285 * If your hardware is free from tHD;STA issue, try this one.
287 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
290 * Conditional expression:
292 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
294 * This is just experimental rule; the tHD;STA period turned
295 * out to be proportinal to (_HCNT + 3). With this setting,
296 * we could meet both tHIGH and tHD;STA timing specs.
298 * If unsure, you'd better to take this alternative.
300 * The reason why we need to take into account "tf" here,
301 * is the same as described in i2c_dw_scl_lcnt().
303 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
307 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
310 * Conditional expression:
312 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
314 * DW I2C core starts counting the SCL CNTs for the LOW period
315 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
316 * In order to meet the tLOW timing spec, we need to take into
317 * account the fall time of SCL signal (tf). Default tf value
318 * should be 0.3 us, for safety.
320 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
323 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
328 ret = i2c_dw_acquire_lock(dev);
332 /* Configure SDA Hold Time if required */
333 reg = dw_readl(dev, DW_IC_COMP_VERSION);
334 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
335 if (!dev->sda_hold_time) {
336 /* Keep previous hold time setting if no one set it */
337 dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
341 * Workaround for avoiding TX arbitration lost in case I2C
342 * slave pulls SDA down "too quickly" after falling edge of
343 * SCL by enabling non-zero SDA RX hold. Specification says it
344 * extends incoming SDA low to high transition while SCL is
345 * high but it appears to help also above issue.
347 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
348 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
350 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
351 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
352 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
353 } else if (dev->set_sda_hold_time) {
354 dev->set_sda_hold_time(dev);
355 } else if (dev->sda_hold_time) {
357 "Hardware too old to adjust SDA hold time.\n");
358 dev->sda_hold_time = 0;
361 i2c_dw_release_lock(dev);
366 void __i2c_dw_disable(struct dw_i2c_dev *dev)
371 __i2c_dw_disable_nowait(dev);
373 * The enable status register may be unimplemented, but
374 * in that case this test reads zero and exits the loop.
376 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == 0)
380 * Wait 10 times the signaling period of the highest I2C
381 * transfer supported by the driver (for 400KHz this is
382 * 25us) as described in the DesignWare I2C databook.
384 usleep_range(25, 250);
387 dev_warn(dev->dev, "timeout in disabling adapter\n");
390 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
393 * Clock is not necessary if we got LCNT/HCNT values directly from
396 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
398 return dev->get_clk_rate_khz(dev);
401 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
405 if (IS_ERR(dev->clk))
406 return PTR_ERR(dev->clk);
409 /* Optional interface clock */
410 ret = clk_prepare_enable(dev->pclk);
414 ret = clk_prepare_enable(dev->clk);
416 clk_disable_unprepare(dev->pclk);
421 clk_disable_unprepare(dev->clk);
422 clk_disable_unprepare(dev->pclk);
426 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
428 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
432 if (!dev->acquire_lock)
435 ret = dev->acquire_lock();
439 dev_err(dev->dev, "couldn't acquire bus ownership\n");
444 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
446 if (dev->release_lock)
451 * Waiting for bus not busy
453 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
455 int timeout = TIMEOUT;
457 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
459 dev_warn(dev->dev, "timeout waiting for bus ready\n");
460 i2c_recover_bus(&dev->adapter);
462 if (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY)
467 usleep_range(1000, 1100);
473 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
475 unsigned long abort_source = dev->abort_source;
478 if (abort_source & DW_IC_TX_ABRT_NOACK) {
479 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
481 "%s: %s\n", __func__, abort_sources[i]);
485 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
486 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
488 if (abort_source & DW_IC_TX_ARB_LOST)
490 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
491 return -EINVAL; /* wrong msgs[] data */
496 void i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
498 u32 param, tx_fifo_depth, rx_fifo_depth;
501 * Try to detect the FIFO depth if not set by interface driver,
502 * the depth could be from 2 to 256 from HW spec.
504 param = dw_readl(dev, DW_IC_COMP_PARAM_1);
505 tx_fifo_depth = ((param >> 16) & 0xff) + 1;
506 rx_fifo_depth = ((param >> 8) & 0xff) + 1;
507 if (!dev->tx_fifo_depth) {
508 dev->tx_fifo_depth = tx_fifo_depth;
509 dev->rx_fifo_depth = rx_fifo_depth;
510 } else if (tx_fifo_depth >= 2) {
511 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
513 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
518 u32 i2c_dw_func(struct i2c_adapter *adap)
520 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
522 return dev->functionality;
525 void i2c_dw_disable(struct dw_i2c_dev *dev)
527 /* Disable controller */
528 __i2c_dw_disable(dev);
530 /* Disable all interrupts */
531 dw_writel(dev, 0, DW_IC_INTR_MASK);
532 dw_readl(dev, DW_IC_CLR_INTR);
535 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
537 dw_writel(dev, 0, DW_IC_INTR_MASK);
540 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
541 MODULE_LICENSE("GPL");