drivers/hwtracing/coresight/coresight-etm4x-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/kernel.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/device.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/fs.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/smp.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/stat.h>
  20 #include <linux/clk.h>
  21 #include <linux/cpu.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-pmu.h>
  25 #include <linux/pm_wakeup.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/property.h>
  33
  34 #include <asm/barrier.h>
  35 #include <asm/sections.h>
  36 #include <asm/sysreg.h>
  37 #include <asm/local.h>
  38 #include <asm/virt.h>
  39
  40 #include "coresight-etm4x.h"
  41 #include "coresight-etm-perf.h"
  42 #include "coresight-etm4x-cfg.h"
  43 #include "coresight-self-hosted-trace.h"
  44 #include "coresight-syscfg.h"
  45
  46 static int boot_enable;
  47 module_param(boot_enable, int, 0444);
  48 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  49
  50 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  51 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  52 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  53
  54 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  55 module_param(pm_save_enable, int, 0444);
  56 MODULE_PARM_DESC(pm_save_enable,
  57         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  58
  59 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  60 static void etm4_set_default_config(struct etmv4_config *config);
  61 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  62                                   struct perf_event *event);
  63 static u64 etm4_get_access_type(struct etmv4_config *config);
  64
  65 static enum cpuhp_state hp_online;
  66
  67 struct etm4_init_arg {
  68         unsigned int            pid;
  69         struct etmv4_drvdata    *drvdata;
  70         struct csdev_access     *csa;
  71 };
  72
  73 /*
  74  * Check if TRCSSPCICRn(i) is implemented for a given instance.
  75  *
  76  * TRCSSPCICRn is implemented only if :
  77  *      TRCSSPCICR<n> is present only if all of the following are true:
  78  *              TRCIDR4.NUMSSCC > n.
  79  *              TRCIDR4.NUMPC > 0b0000 .
  80  *              TRCSSCSR<n>.PC == 0b1
  81  */
  82 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
  83 {
  84         return (n < drvdata->nr_ss_cmp) &&
  85                drvdata->nr_pe &&
  86                (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
  87 }
  88
  89 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  90 {
  91         u64 res = 0;
  92
  93         switch (offset) {
  94         ETM4x_READ_SYSREG_CASES(res)
  95         default :
  96                 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
  97                          offset);
  98         }
  99
 100         if (!_relaxed)
 101                 __iormb(res);   /* Imitate the !relaxed I/O helpers */
 102
 103         return res;
 104 }
 105
 106 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 107 {
 108         if (!_relaxed)
 109                 __iowmb();      /* Imitate the !relaxed I/O helpers */
 110         if (!_64bit)
 111                 val &= GENMASK(31, 0);
 112
 113         switch (offset) {
 114         ETM4x_WRITE_SYSREG_CASES(val)
 115         default :
 116                 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
 117                         offset);
 118         }
 119 }
 120
 121 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
 122 {
 123         u64 res = 0;
 124
 125         switch (offset) {
 126         ETE_READ_CASES(res)
 127         default :
 128                 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
 129                                     offset);
 130         }
 131
 132         if (!_relaxed)
 133                 __iormb(res);   /* Imitate the !relaxed I/O helpers */
 134
 135         return res;
 136 }
 137
 138 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 139 {
 140         if (!_relaxed)
 141                 __iowmb();      /* Imitate the !relaxed I/O helpers */
 142         if (!_64bit)
 143                 val &= GENMASK(31, 0);
 144
 145         switch (offset) {
 146         ETE_WRITE_CASES(val)
 147         default :
 148                 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
 149                                     offset);
 150         }
 151 }
 152
 153 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
 154                                struct csdev_access *csa)
 155 {
 156         u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
 157
 158         drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
 159 }
 160
 161 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
 162                               struct csdev_access *csa, u32 val)
 163 {
 164         val = !!val;
 165
 166         switch (drvdata->os_lock_model) {
 167         case ETM_OSLOCK_PRESENT:
 168                 etm4x_relaxed_write32(csa, val, TRCOSLAR);
 169                 break;
 170         case ETM_OSLOCK_PE:
 171                 write_sysreg_s(val, SYS_OSLAR_EL1);
 172                 break;
 173         default:
 174                 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
 175                              smp_processor_id(), drvdata->os_lock_model);
 176                 fallthrough;
 177         case ETM_OSLOCK_NI:
 178                 return;
 179         }
 180         isb();
 181 }
 182
 183 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
 184                                       struct csdev_access *csa)
 185 {
 186         WARN_ON(drvdata->cpu != smp_processor_id());
 187
 188         /* Writing 0 to OS Lock unlocks the trace unit registers */
 189         etm_write_os_lock(drvdata, csa, 0x0);
 190         drvdata->os_unlock = true;
 191 }
 192
 193 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
 194 {
 195         if (!WARN_ON(!drvdata->csdev))
 196                 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
 197 }
 198
 199 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 200 {
 201         if (WARN_ON(!drvdata->csdev))
 202                 return;
 203         /* Writing 0x1 to OS Lock locks the trace registers */
 204         etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
 205         drvdata->os_unlock = false;
 206 }
 207
 208 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
 209                          struct csdev_access *csa)
 210 {
 211         /* Software Lock is only accessible via memory mapped interface */
 212         if (csa->io_mem)
 213                 CS_LOCK(csa->base);
 214 }
 215
 216 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
 217                            struct csdev_access *csa)
 218 {
 219         if (csa->io_mem)
 220                 CS_UNLOCK(csa->base);
 221 }
 222
 223 static int etm4_cpu_id(struct coresight_device *csdev)
 224 {
 225         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 226
 227         return drvdata->cpu;
 228 }
 229
 230 static int etm4_trace_id(struct coresight_device *csdev)
 231 {
 232         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 233
 234         return drvdata->trcid;
 235 }
 236
 237 struct etm4_enable_arg {
 238         struct etmv4_drvdata *drvdata;
 239         int rc;
 240 };
 241
 242 /*
 243  * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
 244  * When the CPU supports FEAT_TRF, we could move the ETM to a trace
 245  * prohibited state by filtering the Exception levels via TRFCR_EL1.
 246  */
 247 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
 248 {
 249         /* If the CPU doesn't support FEAT_TRF, nothing to do */
 250         if (!drvdata->trfcr)
 251                 return;
 252         cpu_prohibit_trace();
 253 }
 254
 255 /*
 256  * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
 257  * as configured by the drvdata->config.mode for the current
 258  * session. Even though we have TRCVICTLR bits to filter the
 259  * trace in the ELs, it doesn't prevent the ETM from generating
 260  * a packet (e.g, TraceInfo) that might contain the addresses from
 261  * the excluded levels. Thus we use the additional controls provided
 262  * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
 263  * is generated for the excluded ELs.
 264  */
 265 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
 266 {
 267         u64 trfcr = drvdata->trfcr;
 268
 269         /* If the CPU doesn't support FEAT_TRF, nothing to do */
 270         if (!trfcr)
 271                 return;
 272
 273         if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
 274                 trfcr &= ~TRFCR_ELx_ExTRE;
 275         if (drvdata->config.mode & ETM_MODE_EXCL_USER)
 276                 trfcr &= ~TRFCR_ELx_E0TRE;
 277
 278         write_trfcr(trfcr);
 279 }
 280
 281 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
 282
 283 #define HISI_HIP08_AMBA_ID              0x000b6d01
 284 #define ETM4_AMBA_MASK                  0xfffff
 285 #define HISI_HIP08_CORE_COMMIT_MASK     0x3000
 286 #define HISI_HIP08_CORE_COMMIT_SHIFT    12
 287 #define HISI_HIP08_CORE_COMMIT_FULL     0b00
 288 #define HISI_HIP08_CORE_COMMIT_LVL_1    0b01
 289 #define HISI_HIP08_CORE_COMMIT_REG      sys_reg(3, 1, 15, 2, 5)
 290
 291 struct etm4_arch_features {
 292         void (*arch_callback)(bool enable);
 293 };
 294
 295 static bool etm4_hisi_match_pid(unsigned int id)
 296 {
 297         return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
 298 }
 299
 300 static void etm4_hisi_config_core_commit(bool enable)
 301 {
 302         u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
 303                     HISI_HIP08_CORE_COMMIT_FULL;
 304         u64 val;
 305
 306         /*
 307          * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
 308          * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
 309          * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
 310          * speed(minimun value). So bit 12 and 13 should be cleared together.
 311          */
 312         val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
 313         val &= ~HISI_HIP08_CORE_COMMIT_MASK;
 314         val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
 315         write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
 316 }
 317
 318 static struct etm4_arch_features etm4_features[] = {
 319         [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
 320                 .arch_callback = etm4_hisi_config_core_commit,
 321         },
 322         {},
 323 };
 324
 325 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 326 {
 327         struct etm4_arch_features *ftr;
 328         int bit;
 329
 330         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 331                 ftr = &etm4_features[bit];
 332
 333                 if (ftr->arch_callback)
 334                         ftr->arch_callback(true);
 335         }
 336 }
 337
 338 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 339 {
 340         struct etm4_arch_features *ftr;
 341         int bit;
 342
 343         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 344                 ftr = &etm4_features[bit];
 345
 346                 if (ftr->arch_callback)
 347                         ftr->arch_callback(false);
 348         }
 349 }
 350
 351 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 352                                       unsigned int id)
 353 {
 354         if (etm4_hisi_match_pid(id))
 355                 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
 356 }
 357 #else
 358 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 359 {
 360 }
 361
 362 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 363 {
 364 }
 365
 366 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 367                                      unsigned int id)
 368 {
 369 }
 370 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
 371
 372 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 373 {
 374         int i, rc;
 375         struct etmv4_config *config = &drvdata->config;
 376         struct coresight_device *csdev = drvdata->csdev;
 377         struct device *etm_dev = &csdev->dev;
 378         struct csdev_access *csa = &csdev->access;
 379
 380
 381         etm4_cs_unlock(drvdata, csa);
 382         etm4_enable_arch_specific(drvdata);
 383
 384         etm4_os_unlock(drvdata);
 385
 386         rc = coresight_claim_device_unlocked(csdev);
 387         if (rc)
 388                 goto done;
 389
 390         /* Disable the trace unit before programming trace registers */
 391         etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
 392
 393         /*
 394          * If we use system instructions, we need to synchronize the
 395          * write to the TRCPRGCTLR, before accessing the TRCSTATR.
 396          * See ARM IHI0064F, section
 397          * "4.3.7 Synchronization of register updates"
 398          */
 399         if (!csa->io_mem)
 400                 isb();
 401
 402         /* wait for TRCSTATR.IDLE to go up */
 403         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 404                 dev_err(etm_dev,
 405                         "timeout while waiting for Idle Trace Status\n");
 406         if (drvdata->nr_pe)
 407                 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
 408         etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
 409         /* nothing specific implemented */
 410         etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
 411         etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
 412         etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
 413         if (drvdata->stallctl)
 414                 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
 415         etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
 416         etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
 417         etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
 418         etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
 419         etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
 420         etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
 421         etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
 422         etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
 423         if (drvdata->nr_pe_cmp)
 424                 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
 425         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 426                 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
 427         etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
 428         etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
 429         etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
 430         for (i = 0; i < drvdata->nr_cntr; i++) {
 431                 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
 432                 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
 433                 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
 434         }
 435
 436         /*
 437          * Resource selector pair 0 is always implemented and reserved.  As
 438          * such start at 2.
 439          */
 440         for (i = 2; i < drvdata->nr_resource * 2; i++)
 441                 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
 442
 443         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 444                 /* always clear status bit on restart if using single-shot */
 445                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 446                         config->ss_status[i] &= ~BIT(31);
 447                 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
 448                 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
 449                 if (etm4x_sspcicrn_present(drvdata, i))
 450                         etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
 451         }
 452         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 453                 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
 454                 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
 455         }
 456         for (i = 0; i < drvdata->numcidc; i++)
 457                 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
 458         etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
 459         if (drvdata->numcidc > 4)
 460                 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
 461
 462         for (i = 0; i < drvdata->numvmidc; i++)
 463                 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
 464         etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
 465         if (drvdata->numvmidc > 4)
 466                 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
 467
 468         if (!drvdata->skip_power_up) {
 469                 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
 470
 471                 /*
 472                  * Request to keep the trace unit powered and also
 473                  * emulation of powerdown
 474                  */
 475                 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
 476         }
 477
 478         /*
 479          * ETE mandates that the TRCRSR is written to before
 480          * enabling it.
 481          */
 482         if (etm4x_is_ete(drvdata))
 483                 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
 484
 485         etm4x_allow_trace(drvdata);
 486         /* Enable the trace unit */
 487         etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
 488
 489         /* Synchronize the register updates for sysreg access */
 490         if (!csa->io_mem)
 491                 isb();
 492
 493         /* wait for TRCSTATR.IDLE to go back down to '0' */
 494         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 495                 dev_err(etm_dev,
 496                         "timeout while waiting for Idle Trace Status\n");
 497
 498         /*
 499          * As recommended by section 4.3.7 ("Synchronization when using the
 500          * memory-mapped interface") of ARM IHI 0064D
 501          */
 502         dsb(sy);
 503         isb();
 504
 505 done:
 506         etm4_cs_lock(drvdata, csa);
 507
 508         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 509                 drvdata->cpu, rc);
 510         return rc;
 511 }
 512
 513 static void etm4_enable_hw_smp_call(void *info)
 514 {
 515         struct etm4_enable_arg *arg = info;
 516
 517         if (WARN_ON(!arg))
 518                 return;
 519         arg->rc = etm4_enable_hw(arg->drvdata);
 520 }
 521
 522 /*
 523  * The goal of function etm4_config_timestamp_event() is to configure a
 524  * counter that will tell the tracer to emit a timestamp packet when it
 525  * reaches zero.  This is done in order to get a more fine grained idea
 526  * of when instructions are executed so that they can be correlated
 527  * with execution on other CPUs.
 528  *
 529  * To do this the counter itself is configured to self reload and
 530  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 531  * there a resource selector is configured with the counter and the
 532  * timestamp control register to use the resource selector to trigger the
 533  * event that will insert a timestamp packet in the stream.
 534  */
 535 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 536 {
 537         int ctridx, ret = -EINVAL;
 538         int counter, rselector;
 539         u32 val = 0;
 540         struct etmv4_config *config = &drvdata->config;
 541
 542         /* No point in trying if we don't have at least one counter */
 543         if (!drvdata->nr_cntr)
 544                 goto out;
 545
 546         /* Find a counter that hasn't been initialised */
 547         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 548                 if (config->cntr_val[ctridx] == 0)
 549                         break;
 550
 551         /* All the counters have been configured already, bail out */
 552         if (ctridx == drvdata->nr_cntr) {
 553                 pr_debug("%s: no available counter found\n", __func__);
 554                 ret = -ENOSPC;
 555                 goto out;
 556         }
 557
 558         /*
 559          * Searching for an available resource selector to use, starting at
 560          * '2' since every implementation has at least 2 resource selector.
 561          * ETMIDR4 gives the number of resource selector _pairs_,
 562          * hence multiply by 2.
 563          */
 564         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 565                 if (!config->res_ctrl[rselector])
 566                         break;
 567
 568         if (rselector == drvdata->nr_resource * 2) {
 569                 pr_debug("%s: no available resource selector found\n",
 570                          __func__);
 571                 ret = -ENOSPC;
 572                 goto out;
 573         }
 574
 575         /* Remember what counter we used */
 576         counter = 1 << ctridx;
 577
 578         /*
 579          * Initialise original and reload counter value to the smallest
 580          * possible value in order to get as much precision as we can.
 581          */
 582         config->cntr_val[ctridx] = 1;
 583         config->cntrldvr[ctridx] = 1;
 584
 585         /* Set the trace counter control register */
 586         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 587                0x0 << 7         |  /* Select single resource selector */
 588                0x1;                /* Resource selector 1, i.e always true */
 589
 590         config->cntr_ctrl[ctridx] = val;
 591
 592         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 593               counter << 0;       /* Counter to use */
 594
 595         config->res_ctrl[rselector] = val;
 596
 597         val = 0x0 << 7          | /* Select single resource selector */
 598               rselector;          /* Resource selector */
 599
 600         config->ts_ctrl = val;
 601
 602         ret = 0;
 603 out:
 604         return ret;
 605 }
 606
 607 static int etm4_parse_event_config(struct coresight_device *csdev,
 608                                    struct perf_event *event)
 609 {
 610         int ret = 0;
 611         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 612         struct etmv4_config *config = &drvdata->config;
 613         struct perf_event_attr *attr = &event->attr;
 614         unsigned long cfg_hash;
 615         int preset;
 616
 617         /* Clear configuration from previous run */
 618         memset(config, 0, sizeof(struct etmv4_config));
 619
 620         if (attr->exclude_kernel)
 621                 config->mode = ETM_MODE_EXCL_KERN;
 622
 623         if (attr->exclude_user)
 624                 config->mode = ETM_MODE_EXCL_USER;
 625
 626         /* Always start from the default config */
 627         etm4_set_default_config(config);
 628
 629         /* Configure filters specified on the perf cmd line, if any. */
 630         ret = etm4_set_event_filters(drvdata, event);
 631         if (ret)
 632                 goto out;
 633
 634         /* Go from generic option to ETMv4 specifics */
 635         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 636                 config->cfg |= BIT(4);
 637                 /* TRM: Must program this for cycacc to work */
 638                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 639         }
 640         if (attr->config & BIT(ETM_OPT_TS)) {
 641                 /*
 642                  * Configure timestamps to be emitted at regular intervals in
 643                  * order to correlate instructions executed on different CPUs
 644                  * (CPU-wide trace scenarios).
 645                  */
 646                 ret = etm4_config_timestamp_event(drvdata);
 647
 648                 /*
 649                  * No need to go further if timestamp intervals can't
 650                  * be configured.
 651                  */
 652                 if (ret)
 653                         goto out;
 654
 655                 /* bit[11], Global timestamp tracing bit */
 656                 config->cfg |= BIT(11);
 657         }
 658
 659         if (attr->config & BIT(ETM_OPT_CTXTID))
 660                 /* bit[6], Context ID tracing bit */
 661                 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
 662
 663         /*
 664          * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
 665          * for recording CONTEXTIDR_EL2.  Do not enable VMID tracing if the
 666          * kernel is not running in EL2.
 667          */
 668         if (attr->config & BIT(ETM_OPT_CTXTID2)) {
 669                 if (!is_kernel_in_hyp_mode()) {
 670                         ret = -EINVAL;
 671                         goto out;
 672                 }
 673                 config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT);
 674         }
 675
 676         /* return stack - enable if selected and supported */
 677         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 678                 /* bit[12], Return stack enable bit */
 679                 config->cfg |= BIT(12);
 680
 681         /*
 682          * Set any selected configuration and preset.
 683          *
 684          * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
 685          * in the perf attributes defined in coresight-etm-perf.c.
 686          * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
 687          * A zero configid means no configuration active, preset = 0 means no preset selected.
 688          */
 689         if (attr->config2 & GENMASK_ULL(63, 32)) {
 690                 cfg_hash = (u32)(attr->config2 >> 32);
 691                 preset = attr->config & 0xF;
 692                 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
 693         }
 694
 695 out:
 696         return ret;
 697 }
 698
 699 static int etm4_enable_perf(struct coresight_device *csdev,
 700                             struct perf_event *event)
 701 {
 702         int ret = 0;
 703         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 704
 705         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 706                 ret = -EINVAL;
 707                 goto out;
 708         }
 709
 710         /* Configure the tracer based on the session's specifics */
 711         ret = etm4_parse_event_config(csdev, event);
 712         if (ret)
 713                 goto out;
 714         /* And enable it */
 715         ret = etm4_enable_hw(drvdata);
 716
 717 out:
 718         return ret;
 719 }
 720
 721 static int etm4_enable_sysfs(struct coresight_device *csdev)
 722 {
 723         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 724         struct etm4_enable_arg arg = { };
 725         unsigned long cfg_hash;
 726         int ret, preset;
 727
 728         /* enable any config activated by configfs */
 729         cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
 730         if (cfg_hash) {
 731                 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
 732                 if (ret)
 733                         return ret;
 734         }
 735
 736         spin_lock(&drvdata->spinlock);
 737
 738         /*
 739          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 740          * ensures that register writes occur when cpu is powered.
 741          */
 742         arg.drvdata = drvdata;
 743         ret = smp_call_function_single(drvdata->cpu,
 744                                        etm4_enable_hw_smp_call, &arg, 1);
 745         if (!ret)
 746                 ret = arg.rc;
 747         if (!ret)
 748                 drvdata->sticky_enable = true;
 749         spin_unlock(&drvdata->spinlock);
 750
 751         if (!ret)
 752                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 753         return ret;
 754 }
 755
 756 static int etm4_enable(struct coresight_device *csdev,
 757                        struct perf_event *event, u32 mode)
 758 {
 759         int ret;
 760         u32 val;
 761         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 762
 763         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 764
 765         /* Someone is already using the tracer */
 766         if (val)
 767                 return -EBUSY;
 768
 769         switch (mode) {
 770         case CS_MODE_SYSFS:
 771                 ret = etm4_enable_sysfs(csdev);
 772                 break;
 773         case CS_MODE_PERF:
 774                 ret = etm4_enable_perf(csdev, event);
 775                 break;
 776         default:
 777                 ret = -EINVAL;
 778         }
 779
 780         /* The tracer didn't start */
 781         if (ret)
 782                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 783
 784         return ret;
 785 }
 786
 787 static void etm4_disable_hw(void *info)
 788 {
 789         u32 control;
 790         struct etmv4_drvdata *drvdata = info;
 791         struct etmv4_config *config = &drvdata->config;
 792         struct coresight_device *csdev = drvdata->csdev;
 793         struct device *etm_dev = &csdev->dev;
 794         struct csdev_access *csa = &csdev->access;
 795         int i;
 796
 797         etm4_cs_unlock(drvdata, csa);
 798         etm4_disable_arch_specific(drvdata);
 799
 800         if (!drvdata->skip_power_up) {
 801                 /* power can be removed from the trace unit now */
 802                 control = etm4x_relaxed_read32(csa, TRCPDCR);
 803                 control &= ~TRCPDCR_PU;
 804                 etm4x_relaxed_write32(csa, control, TRCPDCR);
 805         }
 806
 807         control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
 808
 809         /* EN, bit[0] Trace unit enable bit */
 810         control &= ~0x1;
 811
 812         /*
 813          * If the CPU supports v8.4 Trace filter Control,
 814          * set the ETM to trace prohibited region.
 815          */
 816         etm4x_prohibit_trace(drvdata);
 817         /*
 818          * Make sure everything completes before disabling, as recommended
 819          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 820          * SSTATUS") of ARM IHI 0064D
 821          */
 822         dsb(sy);
 823         isb();
 824         /* Trace synchronization barrier, is a nop if not supported */
 825         tsb_csync();
 826         etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
 827
 828         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 829         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
 830                 dev_err(etm_dev,
 831                         "timeout while waiting for PM stable Trace Status\n");
 832         /* read the status of the single shot comparators */
 833         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 834                 config->ss_status[i] =
 835                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
 836         }
 837
 838         /* read back the current counter values */
 839         for (i = 0; i < drvdata->nr_cntr; i++) {
 840                 config->cntr_val[i] =
 841                         etm4x_relaxed_read32(csa, TRCCNTVRn(i));
 842         }
 843
 844         coresight_disclaim_device_unlocked(csdev);
 845         etm4_cs_lock(drvdata, csa);
 846
 847         dev_dbg(&drvdata->csdev->dev,
 848                 "cpu: %d disable smp call done\n", drvdata->cpu);
 849 }
 850
 851 static int etm4_disable_perf(struct coresight_device *csdev,
 852                              struct perf_event *event)
 853 {
 854         u32 control;
 855         struct etm_filters *filters = event->hw.addr_filters;
 856         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 857         struct perf_event_attr *attr = &event->attr;
 858
 859         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 860                 return -EINVAL;
 861
 862         etm4_disable_hw(drvdata);
 863         /*
 864          * The config_id occupies bits 63:32 of the config2 perf event attr
 865          * field. If this is non-zero then we will have enabled a config.
 866          */
 867         if (attr->config2 & GENMASK_ULL(63, 32))
 868                 cscfg_csdev_disable_active_config(csdev);
 869
 870         /*
 871          * Check if the start/stop logic was active when the unit was stopped.
 872          * That way we can re-enable the start/stop logic when the process is
 873          * scheduled again.  Configuration of the start/stop logic happens in
 874          * function etm4_set_event_filters().
 875          */
 876         control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
 877         /* TRCVICTLR::SSSTATUS, bit[9] */
 878         filters->ssstatus = (control & BIT(9));
 879
 880         return 0;
 881 }
 882
 883 static void etm4_disable_sysfs(struct coresight_device *csdev)
 884 {
 885         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 886
 887         /*
 888          * Taking hotplug lock here protects from clocks getting disabled
 889          * with tracing being left on (crash scenario) if user disable occurs
 890          * after cpu online mask indicates the cpu is offline but before the
 891          * DYING hotplug callback is serviced by the ETM driver.
 892          */
 893         cpus_read_lock();
 894         spin_lock(&drvdata->spinlock);
 895
 896         /*
 897          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 898          * ensures that register writes occur when cpu is powered.
 899          */
 900         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 901
 902         spin_unlock(&drvdata->spinlock);
 903         cpus_read_unlock();
 904
 905         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
 906 }
 907
 908 static void etm4_disable(struct coresight_device *csdev,
 909                          struct perf_event *event)
 910 {
 911         u32 mode;
 912         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 913
 914         /*
 915          * For as long as the tracer isn't disabled another entity can't
 916          * change its status.  As such we can read the status here without
 917          * fearing it will change under us.
 918          */
 919         mode = local_read(&drvdata->mode);
 920
 921         switch (mode) {
 922         case CS_MODE_DISABLED:
 923                 break;
 924         case CS_MODE_SYSFS:
 925                 etm4_disable_sysfs(csdev);
 926                 break;
 927         case CS_MODE_PERF:
 928                 etm4_disable_perf(csdev, event);
 929                 break;
 930         }
 931
 932         if (mode)
 933                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 934 }
 935
 936 static const struct coresight_ops_source etm4_source_ops = {
 937         .cpu_id         = etm4_cpu_id,
 938         .trace_id       = etm4_trace_id,
 939         .enable         = etm4_enable,
 940         .disable        = etm4_disable,
 941 };
 942
 943 static const struct coresight_ops etm4_cs_ops = {
 944         .source_ops     = &etm4_source_ops,
 945 };
 946
 947 static inline bool cpu_supports_sysreg_trace(void)
 948 {
 949         u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
 950
 951         return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
 952 }
 953
 954 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
 955                                     struct csdev_access *csa)
 956 {
 957         u32 devarch;
 958
 959         if (!cpu_supports_sysreg_trace())
 960                 return false;
 961
 962         /*
 963          * ETMs implementing sysreg access must implement TRCDEVARCH.
 964          */
 965         devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
 966         switch (devarch & ETM_DEVARCH_ID_MASK) {
 967         case ETM_DEVARCH_ETMv4x_ARCH:
 968                 *csa = (struct csdev_access) {
 969                         .io_mem = false,
 970                         .read   = etm4x_sysreg_read,
 971                         .write  = etm4x_sysreg_write,
 972                 };
 973                 break;
 974         case ETM_DEVARCH_ETE_ARCH:
 975                 *csa = (struct csdev_access) {
 976                         .io_mem = false,
 977                         .read   = ete_sysreg_read,
 978                         .write  = ete_sysreg_write,
 979                 };
 980                 break;
 981         default:
 982                 return false;
 983         }
 984
 985         drvdata->arch = etm_devarch_to_arch(devarch);
 986         return true;
 987 }
 988
 989 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
 990                                    struct csdev_access *csa)
 991 {
 992         u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
 993         u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
 994
 995         /*
 996          * All ETMs must implement TRCDEVARCH to indicate that
 997          * the component is an ETMv4. To support any broken
 998          * implementations we fall back to TRCIDR1 check, which
 999          * is not really reliable.
1000          */
1001         if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
1002                 drvdata->arch = etm_devarch_to_arch(devarch);
1003         } else {
1004                 pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
1005                         smp_processor_id(), devarch);
1006
1007                 if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
1008                         return false;
1009                 drvdata->arch = etm_trcidr_to_arch(idr1);
1010         }
1011
1012         *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1013         return true;
1014 }
1015
1016 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1017                                    struct csdev_access *csa)
1018 {
1019         /*
1020          * Always choose the memory mapped io, if there is
1021          * a memory map to prevent sysreg access on broken
1022          * systems.
1023          */
1024         if (drvdata->base)
1025                 return etm4_init_iomem_access(drvdata, csa);
1026
1027         if (etm4_init_sysreg_access(drvdata, csa))
1028                 return true;
1029
1030         return false;
1031 }
1032
1033 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1034 {
1035         u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1036         u64 trfcr;
1037
1038         drvdata->trfcr = 0;
1039         if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT))
1040                 return;
1041
1042         /*
1043          * If the CPU supports v8.4 SelfHosted Tracing, enable
1044          * tracing at the kernel EL and EL0, forcing to use the
1045          * virtual time as the timestamp.
1046          */
1047         trfcr = (TRFCR_ELx_TS_VIRTUAL |
1048                  TRFCR_ELx_ExTRE |
1049                  TRFCR_ELx_E0TRE);
1050
1051         /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1052         if (is_kernel_in_hyp_mode())
1053                 trfcr |= TRFCR_EL2_CX;
1054
1055         drvdata->trfcr = trfcr;
1056 }
1057
1058 static void etm4_init_arch_data(void *info)
1059 {
1060         u32 etmidr0;
1061         u32 etmidr2;
1062         u32 etmidr3;
1063         u32 etmidr4;
1064         u32 etmidr5;
1065         struct etm4_init_arg *init_arg = info;
1066         struct etmv4_drvdata *drvdata;
1067         struct csdev_access *csa;
1068         int i;
1069
1070         drvdata = init_arg->drvdata;
1071         csa = init_arg->csa;
1072
1073         /*
1074          * If we are unable to detect the access mechanism,
1075          * or unable to detect the trace unit type, fail
1076          * early.
1077          */
1078         if (!etm4_init_csdev_access(drvdata, csa))
1079                 return;
1080
1081         /* Detect the support for OS Lock before we actually use it */
1082         etm_detect_os_lock(drvdata, csa);
1083
1084         /* Make sure all registers are accessible */
1085         etm4_os_unlock_csa(drvdata, csa);
1086         etm4_cs_unlock(drvdata, csa);
1087
1088         etm4_check_arch_features(drvdata, init_arg->pid);
1089
1090         /* find all capabilities of the tracing unit */
1091         etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1092
1093         /* INSTP0, bits[2:1] P0 tracing support field */
1094         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
1095                 drvdata->instrp0 = true;
1096         else
1097                 drvdata->instrp0 = false;
1098
1099         /* TRCBB, bit[5] Branch broadcast tracing support bit */
1100         if (BMVAL(etmidr0, 5, 5))
1101                 drvdata->trcbb = true;
1102         else
1103                 drvdata->trcbb = false;
1104
1105         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1106         if (BMVAL(etmidr0, 6, 6))
1107                 drvdata->trccond = true;
1108         else
1109                 drvdata->trccond = false;
1110
1111         /* TRCCCI, bit[7] Cycle counting instruction bit */
1112         if (BMVAL(etmidr0, 7, 7))
1113                 drvdata->trccci = true;
1114         else
1115                 drvdata->trccci = false;
1116
1117         /* RETSTACK, bit[9] Return stack bit */
1118         if (BMVAL(etmidr0, 9, 9))
1119                 drvdata->retstack = true;
1120         else
1121                 drvdata->retstack = false;
1122
1123         /* NUMEVENT, bits[11:10] Number of events field */
1124         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
1125         /* QSUPP, bits[16:15] Q element support field */
1126         drvdata->q_support = BMVAL(etmidr0, 15, 16);
1127         /* TSSIZE, bits[28:24] Global timestamp size field */
1128         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
1129
1130         /* maximum size of resources */
1131         etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1132         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1133         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
1134         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1135         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
1136         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1137         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
1138
1139         etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1140         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1141         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
1142         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1143         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
1144         drvdata->config.s_ex_level = drvdata->s_ex_level;
1145         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1146         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
1147
1148         /*
1149          * TRCERR, bit[24] whether a trace unit can trace a
1150          * system error exception.
1151          */
1152         if (BMVAL(etmidr3, 24, 24))
1153                 drvdata->trc_error = true;
1154         else
1155                 drvdata->trc_error = false;
1156
1157         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1158         if (BMVAL(etmidr3, 25, 25))
1159                 drvdata->syncpr = true;
1160         else
1161                 drvdata->syncpr = false;
1162
1163         /* STALLCTL, bit[26] is stall control implemented? */
1164         if (BMVAL(etmidr3, 26, 26))
1165                 drvdata->stallctl = true;
1166         else
1167                 drvdata->stallctl = false;
1168
1169         /* SYSSTALL, bit[27] implementation can support stall control? */
1170         if (BMVAL(etmidr3, 27, 27))
1171                 drvdata->sysstall = true;
1172         else
1173                 drvdata->sysstall = false;
1174
1175         /*
1176          * NUMPROC - the number of PEs available for tracing, 5bits
1177          *         = TRCIDR3.bits[13:12]bits[30:28]
1178          *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1179          *  bits[3:0] = TRCIDR3.bits[30:28]
1180          */
1181         drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
1182
1183         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1184         if (BMVAL(etmidr3, 31, 31))
1185                 drvdata->nooverflow = true;
1186         else
1187                 drvdata->nooverflow = false;
1188
1189         /* number of resources trace unit supports */
1190         etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1191         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1192         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
1193         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1194         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
1195         /*
1196          * NUMRSPAIR, bits[19:16]
1197          * The number of resource pairs conveyed by the HW starts at 0, i.e a
1198          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1199          * As such add 1 to the value of NUMRSPAIR for a better representation.
1200          *
1201          * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1202          * the default TRUE and FALSE resource selectors are omitted.
1203          * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1204          */
1205         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
1206         if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1207                 drvdata->nr_resource += 1;
1208         /*
1209          * NUMSSCC, bits[23:20] the number of single-shot
1210          * comparator control for tracing. Read any status regs as these
1211          * also contain RO capability data.
1212          */
1213         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
1214         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1215                 drvdata->config.ss_status[i] =
1216                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1217         }
1218         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1219         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
1220         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1221         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
1222
1223         etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1224         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1225         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
1226         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1227         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
1228         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1229         if (BMVAL(etmidr5, 22, 22))
1230                 drvdata->atbtrig = true;
1231         else
1232                 drvdata->atbtrig = false;
1233         /*
1234          * LPOVERRIDE, bit[23] implementation supports
1235          * low-power state override
1236          */
1237         if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
1238                 drvdata->lpoverride = true;
1239         else
1240                 drvdata->lpoverride = false;
1241         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1242         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
1243         /* NUMCNTR, bits[30:28] number of counters available for tracing */
1244         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1245         etm4_cs_lock(drvdata, csa);
1246         cpu_detect_trace_filtering(drvdata);
1247 }
1248
1249 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1250 {
1251         return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT;
1252 }
1253
1254 /* Set ELx trace filter access in the TRCVICTLR register */
1255 static void etm4_set_victlr_access(struct etmv4_config *config)
1256 {
1257         config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1258         config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1259 }
1260
1261 static void etm4_set_default_config(struct etmv4_config *config)
1262 {
1263         /* disable all events tracing */
1264         config->eventctrl0 = 0x0;
1265         config->eventctrl1 = 0x0;
1266
1267         /* disable stalling */
1268         config->stall_ctrl = 0x0;
1269
1270         /* enable trace synchronization every 4096 bytes, if available */
1271         config->syncfreq = 0xC;
1272
1273         /* disable timestamp event */
1274         config->ts_ctrl = 0x0;
1275
1276         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1277         config->vinst_ctrl = BIT(0);
1278
1279         /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1280         etm4_set_victlr_access(config);
1281 }
1282
1283 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1284 {
1285         u64 access_type = 0;
1286
1287         /*
1288          * EXLEVEL_NS, for NonSecure Exception levels.
1289          * The mask here is a generic value and must be
1290          * shifted to the corresponding field for the registers
1291          */
1292         if (!is_kernel_in_hyp_mode()) {
1293                 /* Stay away from hypervisor mode for non-VHE */
1294                 access_type =  ETM_EXLEVEL_NS_HYP;
1295                 if (config->mode & ETM_MODE_EXCL_KERN)
1296                         access_type |= ETM_EXLEVEL_NS_OS;
1297         } else if (config->mode & ETM_MODE_EXCL_KERN) {
1298                 access_type = ETM_EXLEVEL_NS_HYP;
1299         }
1300
1301         if (config->mode & ETM_MODE_EXCL_USER)
1302                 access_type |= ETM_EXLEVEL_NS_APP;
1303
1304         return access_type;
1305 }
1306
1307 /*
1308  * Construct the exception level masks for a given config.
1309  * This must be shifted to the corresponding register field
1310  * for usage.
1311  */
1312 static u64 etm4_get_access_type(struct etmv4_config *config)
1313 {
1314         /* All Secure exception levels are excluded from the trace */
1315         return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1316 }
1317
1318 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1319 {
1320         return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1321 }
1322
1323 static void etm4_set_comparator_filter(struct etmv4_config *config,
1324                                        u64 start, u64 stop, int comparator)
1325 {
1326         u64 access_type = etm4_get_comparator_access_type(config);
1327
1328         /* First half of default address comparator */
1329         config->addr_val[comparator] = start;
1330         config->addr_acc[comparator] = access_type;
1331         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1332
1333         /* Second half of default address comparator */
1334         config->addr_val[comparator + 1] = stop;
1335         config->addr_acc[comparator + 1] = access_type;
1336         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1337
1338         /*
1339          * Configure the ViewInst function to include this address range
1340          * comparator.
1341          *
1342          * @comparator is divided by two since it is the index in the
1343          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1344          * address range comparator _pairs_.
1345          *
1346          * Therefore:
1347          *      index 0 -> compatator pair 0
1348          *      index 2 -> comparator pair 1
1349          *      index 4 -> comparator pair 2
1350          *      ...
1351          *      index 14 -> comparator pair 7
1352          */
1353         config->viiectlr |= BIT(comparator / 2);
1354 }
1355
1356 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1357                                        u64 address, int comparator,
1358                                        enum etm_addr_type type)
1359 {
1360         int shift;
1361         u64 access_type = etm4_get_comparator_access_type(config);
1362
1363         /* Configure the comparator */
1364         config->addr_val[comparator] = address;
1365         config->addr_acc[comparator] = access_type;
1366         config->addr_type[comparator] = type;
1367
1368         /*
1369          * Configure ViewInst Start-Stop control register.
1370          * Addresses configured to start tracing go from bit 0 to n-1,
1371          * while those configured to stop tracing from 16 to 16 + n-1.
1372          */
1373         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1374         config->vissctlr |= BIT(shift + comparator);
1375 }
1376
1377 static void etm4_set_default_filter(struct etmv4_config *config)
1378 {
1379         /* Trace everything 'default' filter achieved by no filtering */
1380         config->viiectlr = 0x0;
1381
1382         /*
1383          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1384          * in the started state
1385          */
1386         config->vinst_ctrl |= BIT(9);
1387         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1388
1389         /* No start-stop filtering for ViewInst */
1390         config->vissctlr = 0x0;
1391 }
1392
1393 static void etm4_set_default(struct etmv4_config *config)
1394 {
1395         if (WARN_ON_ONCE(!config))
1396                 return;
1397
1398         /*
1399          * Make default initialisation trace everything
1400          *
1401          * This is done by a minimum default config sufficient to enable
1402          * full instruction trace - with a default filter for trace all
1403          * achieved by having no filtering.
1404          */
1405         etm4_set_default_config(config);
1406         etm4_set_default_filter(config);
1407 }
1408
1409 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1410 {
1411         int nr_comparator, index = 0;
1412         struct etmv4_config *config = &drvdata->config;
1413
1414         /*
1415          * nr_addr_cmp holds the number of comparator _pair_, so time 2
1416          * for the total number of comparators.
1417          */
1418         nr_comparator = drvdata->nr_addr_cmp * 2;
1419
1420         /* Go through the tally of comparators looking for a free one. */
1421         while (index < nr_comparator) {
1422                 switch (type) {
1423                 case ETM_ADDR_TYPE_RANGE:
1424                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1425                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1426                                 return index;
1427
1428                         /* Address range comparators go in pairs */
1429                         index += 2;
1430                         break;
1431                 case ETM_ADDR_TYPE_START:
1432                 case ETM_ADDR_TYPE_STOP:
1433                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1434                                 return index;
1435
1436                         /* Start/stop address can have odd indexes */
1437                         index += 1;
1438                         break;
1439                 default:
1440                         return -EINVAL;
1441                 }
1442         }
1443
1444         /* If we are here all the comparators have been used. */
1445         return -ENOSPC;
1446 }
1447
1448 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1449                                   struct perf_event *event)
1450 {
1451         int i, comparator, ret = 0;
1452         u64 address;
1453         struct etmv4_config *config = &drvdata->config;
1454         struct etm_filters *filters = event->hw.addr_filters;
1455
1456         if (!filters)
1457                 goto default_filter;
1458
1459         /* Sync events with what Perf got */
1460         perf_event_addr_filters_sync(event);
1461
1462         /*
1463          * If there are no filters to deal with simply go ahead with
1464          * the default filter, i.e the entire address range.
1465          */
1466         if (!filters->nr_filters)
1467                 goto default_filter;
1468
1469         for (i = 0; i < filters->nr_filters; i++) {
1470                 struct etm_filter *filter = &filters->etm_filter[i];
1471                 enum etm_addr_type type = filter->type;
1472
1473                 /* See if a comparator is free. */
1474                 comparator = etm4_get_next_comparator(drvdata, type);
1475                 if (comparator < 0) {
1476                         ret = comparator;
1477                         goto out;
1478                 }
1479
1480                 switch (type) {
1481                 case ETM_ADDR_TYPE_RANGE:
1482                         etm4_set_comparator_filter(config,
1483                                                    filter->start_addr,
1484                                                    filter->stop_addr,
1485                                                    comparator);
1486                         /*
1487                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1488                          * in the started state
1489                          */
1490                         config->vinst_ctrl |= BIT(9);
1491
1492                         /* No start-stop filtering for ViewInst */
1493                         config->vissctlr = 0x0;
1494                         break;
1495                 case ETM_ADDR_TYPE_START:
1496                 case ETM_ADDR_TYPE_STOP:
1497                         /* Get the right start or stop address */
1498                         address = (type == ETM_ADDR_TYPE_START ?
1499                                    filter->start_addr :
1500                                    filter->stop_addr);
1501
1502                         /* Configure comparator */
1503                         etm4_set_start_stop_filter(config, address,
1504                                                    comparator, type);
1505
1506                         /*
1507                          * If filters::ssstatus == 1, trace acquisition was
1508                          * started but the process was yanked away before the
1509                          * the stop address was hit.  As such the start/stop
1510                          * logic needs to be re-started so that tracing can
1511                          * resume where it left.
1512                          *
1513                          * The start/stop logic status when a process is
1514                          * scheduled out is checked in function
1515                          * etm4_disable_perf().
1516                          */
1517                         if (filters->ssstatus)
1518                                 config->vinst_ctrl |= BIT(9);
1519
1520                         /* No include/exclude filtering for ViewInst */
1521                         config->viiectlr = 0x0;
1522                         break;
1523                 default:
1524                         ret = -EINVAL;
1525                         goto out;
1526                 }
1527         }
1528
1529         goto out;
1530
1531
1532 default_filter:
1533         etm4_set_default_filter(config);
1534
1535 out:
1536         return ret;
1537 }
1538
1539 void etm4_config_trace_mode(struct etmv4_config *config)
1540 {
1541         u32 mode;
1542
1543         mode = config->mode;
1544         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1545
1546         /* excluding kernel AND user space doesn't make sense */
1547         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1548
1549         /* nothing to do if neither flags are set */
1550         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1551                 return;
1552
1553         etm4_set_victlr_access(config);
1554 }
1555
1556 static int etm4_online_cpu(unsigned int cpu)
1557 {
1558         if (!etmdrvdata[cpu])
1559                 return 0;
1560
1561         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1562                 coresight_enable(etmdrvdata[cpu]->csdev);
1563         return 0;
1564 }
1565
1566 static int etm4_starting_cpu(unsigned int cpu)
1567 {
1568         if (!etmdrvdata[cpu])
1569                 return 0;
1570
1571         spin_lock(&etmdrvdata[cpu]->spinlock);
1572         if (!etmdrvdata[cpu]->os_unlock)
1573                 etm4_os_unlock(etmdrvdata[cpu]);
1574
1575         if (local_read(&etmdrvdata[cpu]->mode))
1576                 etm4_enable_hw(etmdrvdata[cpu]);
1577         spin_unlock(&etmdrvdata[cpu]->spinlock);
1578         return 0;
1579 }
1580
1581 static int etm4_dying_cpu(unsigned int cpu)
1582 {
1583         if (!etmdrvdata[cpu])
1584                 return 0;
1585
1586         spin_lock(&etmdrvdata[cpu]->spinlock);
1587         if (local_read(&etmdrvdata[cpu]->mode))
1588                 etm4_disable_hw(etmdrvdata[cpu]);
1589         spin_unlock(&etmdrvdata[cpu]->spinlock);
1590         return 0;
1591 }
1592
1593 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1594 {
1595         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1596 }
1597
1598 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1599 {
1600         int i, ret = 0;
1601         struct etmv4_save_state *state;
1602         struct coresight_device *csdev = drvdata->csdev;
1603         struct csdev_access *csa;
1604         struct device *etm_dev;
1605
1606         if (WARN_ON(!csdev))
1607                 return -ENODEV;
1608
1609         etm_dev = &csdev->dev;
1610         csa = &csdev->access;
1611
1612         /*
1613          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1614          * of ARM IHI 0064D
1615          */
1616         dsb(sy);
1617         isb();
1618
1619         etm4_cs_unlock(drvdata, csa);
1620         /* Lock the OS lock to disable trace and external debugger access */
1621         etm4_os_lock(drvdata);
1622
1623         /* wait for TRCSTATR.PMSTABLE to go up */
1624         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1625                 dev_err(etm_dev,
1626                         "timeout while waiting for PM Stable Status\n");
1627                 etm4_os_unlock(drvdata);
1628                 ret = -EBUSY;
1629                 goto out;
1630         }
1631
1632         state = drvdata->save_state;
1633
1634         state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1635         if (drvdata->nr_pe)
1636                 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1637         state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1638         state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1639         state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1640         state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1641         if (drvdata->stallctl)
1642                 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1643         state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1644         state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1645         state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1646         state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1647         state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1648         state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1649
1650         state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1651         state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1652         state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1653         if (drvdata->nr_pe_cmp)
1654                 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1655         state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1656         state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1657         state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1658
1659         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1660                 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1661
1662         state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1663         state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1664         state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1665
1666         for (i = 0; i < drvdata->nr_cntr; i++) {
1667                 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1668                 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1669                 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1670         }
1671
1672         for (i = 0; i < drvdata->nr_resource * 2; i++)
1673                 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1674
1675         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1676                 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1677                 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1678                 if (etm4x_sspcicrn_present(drvdata, i))
1679                         state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1680         }
1681
1682         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1683                 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1684                 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1685         }
1686
1687         /*
1688          * Data trace stream is architecturally prohibited for A profile cores
1689          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1690          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1691          * unit") of ARM IHI 0064D.
1692          */
1693
1694         for (i = 0; i < drvdata->numcidc; i++)
1695                 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1696
1697         for (i = 0; i < drvdata->numvmidc; i++)
1698                 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1699
1700         state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1701         if (drvdata->numcidc > 4)
1702                 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1703
1704         state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1705         if (drvdata->numvmidc > 4)
1706                 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1707
1708         state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1709
1710         if (!drvdata->skip_power_up)
1711                 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1712
1713         /* wait for TRCSTATR.IDLE to go up */
1714         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1715                 dev_err(etm_dev,
1716                         "timeout while waiting for Idle Trace Status\n");
1717                 etm4_os_unlock(drvdata);
1718                 ret = -EBUSY;
1719                 goto out;
1720         }
1721
1722         drvdata->state_needs_restore = true;
1723
1724         /*
1725          * Power can be removed from the trace unit now. We do this to
1726          * potentially save power on systems that respect the TRCPDCR_PU
1727          * despite requesting software to save/restore state.
1728          */
1729         if (!drvdata->skip_power_up)
1730                 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1731                                       TRCPDCR);
1732 out:
1733         etm4_cs_lock(drvdata, csa);
1734         return ret;
1735 }
1736
1737 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1738 {
1739         int ret = 0;
1740
1741         /* Save the TRFCR irrespective of whether the ETM is ON */
1742         if (drvdata->trfcr)
1743                 drvdata->save_trfcr = read_trfcr();
1744         /*
1745          * Save and restore the ETM Trace registers only if
1746          * the ETM is active.
1747          */
1748         if (local_read(&drvdata->mode) && drvdata->save_state)
1749                 ret = __etm4_cpu_save(drvdata);
1750         return ret;
1751 }
1752
1753 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1754 {
1755         int i;
1756         struct etmv4_save_state *state = drvdata->save_state;
1757         struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1758         struct csdev_access *csa = &tmp_csa;
1759
1760         etm4_cs_unlock(drvdata, csa);
1761         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1762
1763         etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1764         if (drvdata->nr_pe)
1765                 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1766         etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1767         etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1768         etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1769         etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1770         if (drvdata->stallctl)
1771                 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1772         etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1773         etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1774         etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1775         etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1776         etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1777         etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1778
1779         etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1780         etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1781         etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1782         if (drvdata->nr_pe_cmp)
1783                 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1784         etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1785         etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1786         etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1787
1788         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1789                 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1790
1791         etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1792         etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1793         etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1794
1795         for (i = 0; i < drvdata->nr_cntr; i++) {
1796                 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1797                 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1798                 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1799         }
1800
1801         for (i = 0; i < drvdata->nr_resource * 2; i++)
1802                 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1803
1804         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1805                 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1806                 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1807                 if (etm4x_sspcicrn_present(drvdata, i))
1808                         etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1809         }
1810
1811         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1812                 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1813                 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1814         }
1815
1816         for (i = 0; i < drvdata->numcidc; i++)
1817                 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1818
1819         for (i = 0; i < drvdata->numvmidc; i++)
1820                 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1821
1822         etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1823         if (drvdata->numcidc > 4)
1824                 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1825
1826         etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1827         if (drvdata->numvmidc > 4)
1828                 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1829
1830         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1831
1832         if (!drvdata->skip_power_up)
1833                 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1834
1835         drvdata->state_needs_restore = false;
1836
1837         /*
1838          * As recommended by section 4.3.7 ("Synchronization when using the
1839          * memory-mapped interface") of ARM IHI 0064D
1840          */
1841         dsb(sy);
1842         isb();
1843
1844         /* Unlock the OS lock to re-enable trace and external debug access */
1845         etm4_os_unlock(drvdata);
1846         etm4_cs_lock(drvdata, csa);
1847 }
1848
1849 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1850 {
1851         if (drvdata->trfcr)
1852                 write_trfcr(drvdata->save_trfcr);
1853         if (drvdata->state_needs_restore)
1854                 __etm4_cpu_restore(drvdata);
1855 }
1856
1857 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1858                               void *v)
1859 {
1860         struct etmv4_drvdata *drvdata;
1861         unsigned int cpu = smp_processor_id();
1862
1863         if (!etmdrvdata[cpu])
1864                 return NOTIFY_OK;
1865
1866         drvdata = etmdrvdata[cpu];
1867
1868         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1869                 return NOTIFY_BAD;
1870
1871         switch (cmd) {
1872         case CPU_PM_ENTER:
1873                 if (etm4_cpu_save(drvdata))
1874                         return NOTIFY_BAD;
1875                 break;
1876         case CPU_PM_EXIT:
1877         case CPU_PM_ENTER_FAILED:
1878                 etm4_cpu_restore(drvdata);
1879                 break;
1880         default:
1881                 return NOTIFY_DONE;
1882         }
1883
1884         return NOTIFY_OK;
1885 }
1886
1887 static struct notifier_block etm4_cpu_pm_nb = {
1888         .notifier_call = etm4_cpu_pm_notify,
1889 };
1890
1891 /* Setup PM. Deals with error conditions and counts */
1892 static int __init etm4_pm_setup(void)
1893 {
1894         int ret;
1895
1896         ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1897         if (ret)
1898                 return ret;
1899
1900         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1901                                         "arm/coresight4:starting",
1902                                         etm4_starting_cpu, etm4_dying_cpu);
1903
1904         if (ret)
1905                 goto unregister_notifier;
1906
1907         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1908                                         "arm/coresight4:online",
1909                                         etm4_online_cpu, NULL);
1910
1911         /* HP dyn state ID returned in ret on success */
1912         if (ret > 0) {
1913                 hp_online = ret;
1914                 return 0;
1915         }
1916
1917         /* failed dyn state - remove others */
1918         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1919
1920 unregister_notifier:
1921         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1922         return ret;
1923 }
1924
1925 static void etm4_pm_clear(void)
1926 {
1927         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1928         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1929         if (hp_online) {
1930                 cpuhp_remove_state_nocalls(hp_online);
1931                 hp_online = 0;
1932         }
1933 }
1934
1935 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
1936 {
1937         int ret;
1938         struct coresight_platform_data *pdata = NULL;
1939         struct etmv4_drvdata *drvdata;
1940         struct coresight_desc desc = { 0 };
1941         struct etm4_init_arg init_arg = { 0 };
1942         u8 major, minor;
1943         char *type_name;
1944
1945         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1946         if (!drvdata)
1947                 return -ENOMEM;
1948
1949         dev_set_drvdata(dev, drvdata);
1950
1951         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1952                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1953                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1954
1955         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1956                 drvdata->save_state = devm_kmalloc(dev,
1957                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1958                 if (!drvdata->save_state)
1959                         return -ENOMEM;
1960         }
1961
1962         drvdata->base = base;
1963
1964         spin_lock_init(&drvdata->spinlock);
1965
1966         drvdata->cpu = coresight_get_cpu(dev);
1967         if (drvdata->cpu < 0)
1968                 return drvdata->cpu;
1969
1970         init_arg.drvdata = drvdata;
1971         init_arg.csa = &desc.access;
1972         init_arg.pid = etm_pid;
1973
1974         if (smp_call_function_single(drvdata->cpu,
1975                                 etm4_init_arch_data,  &init_arg, 1))
1976                 dev_err(dev, "ETM arch init failed\n");
1977
1978         if (!drvdata->arch)
1979                 return -EINVAL;
1980
1981         /* TRCPDCR is not accessible with system instructions. */
1982         if (!desc.access.io_mem ||
1983             fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1984                 drvdata->skip_power_up = true;
1985
1986         major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
1987         minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
1988
1989         if (etm4x_is_ete(drvdata)) {
1990                 type_name = "ete";
1991                 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
1992                 major -= 4;
1993         } else {
1994                 type_name = "etm";
1995         }
1996
1997         desc.name = devm_kasprintf(dev, GFP_KERNEL,
1998                                    "%s%d", type_name, drvdata->cpu);
1999         if (!desc.name)
2000                 return -ENOMEM;
2001
2002         etm4_init_trace_id(drvdata);
2003         etm4_set_default(&drvdata->config);
2004
2005         pdata = coresight_get_platform_data(dev);
2006         if (IS_ERR(pdata))
2007                 return PTR_ERR(pdata);
2008
2009         dev->platform_data = pdata;
2010
2011         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
2012         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2013         desc.ops = &etm4_cs_ops;
2014         desc.pdata = pdata;
2015         desc.dev = dev;
2016         desc.groups = coresight_etmv4_groups;
2017         drvdata->csdev = coresight_register(&desc);
2018         if (IS_ERR(drvdata->csdev))
2019                 return PTR_ERR(drvdata->csdev);
2020
2021         ret = etm_perf_symlink(drvdata->csdev, true);
2022         if (ret) {
2023                 coresight_unregister(drvdata->csdev);
2024                 return ret;
2025         }
2026
2027         /* register with config infrastructure & load any current features */
2028         ret = etm4_cscfg_register(drvdata->csdev);
2029         if (ret) {
2030                 coresight_unregister(drvdata->csdev);
2031                 return ret;
2032         }
2033
2034         etmdrvdata[drvdata->cpu] = drvdata;
2035
2036         dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2037                  drvdata->cpu, type_name, major, minor);
2038
2039         if (boot_enable) {
2040                 coresight_enable(drvdata->csdev);
2041                 drvdata->boot_enable = true;
2042         }
2043
2044         return 0;
2045 }
2046
2047 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2048 {
2049         void __iomem *base;
2050         struct device *dev = &adev->dev;
2051         struct resource *res = &adev->res;
2052         int ret;
2053
2054         /* Validity for the resource is already checked by the AMBA core */
2055         base = devm_ioremap_resource(dev, res);
2056         if (IS_ERR(base))
2057                 return PTR_ERR(base);
2058
2059         ret = etm4_probe(dev, base, id->id);
2060         if (!ret)
2061                 pm_runtime_put(&adev->dev);
2062
2063         return ret;
2064 }
2065
2066 static int etm4_probe_platform_dev(struct platform_device *pdev)
2067 {
2068         int ret;
2069
2070         pm_runtime_get_noresume(&pdev->dev);
2071         pm_runtime_set_active(&pdev->dev);
2072         pm_runtime_enable(&pdev->dev);
2073
2074         /*
2075          * System register based devices could match the
2076          * HW by reading appropriate registers on the HW
2077          * and thus we could skip the PID.
2078          */
2079         ret = etm4_probe(&pdev->dev, NULL, 0);
2080
2081         pm_runtime_put(&pdev->dev);
2082         return ret;
2083 }
2084
2085 static struct amba_cs_uci_id uci_id_etm4[] = {
2086         {
2087                 /*  ETMv4 UCI data */
2088                 .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
2089                 .devarch_mask   = ETM_DEVARCH_ID_MASK,
2090                 .devtype        = 0x00000013,
2091         }
2092 };
2093
2094 static void clear_etmdrvdata(void *info)
2095 {
2096         int cpu = *(int *)info;
2097
2098         etmdrvdata[cpu] = NULL;
2099 }
2100
2101 static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
2102 {
2103         etm_perf_symlink(drvdata->csdev, false);
2104         /*
2105          * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2106          * and CPU hotplug call backs.
2107          */
2108         cpus_read_lock();
2109         /*
2110          * The readers for etmdrvdata[] are CPU hotplug call backs
2111          * and PM notification call backs. Change etmdrvdata[i] on
2112          * CPU i ensures these call backs has consistent view
2113          * inside one call back function.
2114          */
2115         if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2116                 etmdrvdata[drvdata->cpu] = NULL;
2117
2118         cpus_read_unlock();
2119
2120         cscfg_unregister_csdev(drvdata->csdev);
2121         coresight_unregister(drvdata->csdev);
2122
2123         return 0;
2124 }
2125
2126 static void __exit etm4_remove_amba(struct amba_device *adev)
2127 {
2128         struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2129
2130         if (drvdata)
2131                 etm4_remove_dev(drvdata);
2132 }
2133
2134 static int __exit etm4_remove_platform_dev(struct platform_device *pdev)
2135 {
2136         int ret = 0;
2137         struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2138
2139         if (drvdata)
2140                 ret = etm4_remove_dev(drvdata);
2141         pm_runtime_disable(&pdev->dev);
2142         return ret;
2143 }
2144
2145 static const struct amba_id etm4_ids[] = {
2146         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
2147         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
2148         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
2149         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
2150         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2151         CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2152         CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2153         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2154         CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2155         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2156         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2157         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2158         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2159         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2160         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2161         CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2162         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2163         CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2164         CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2165         {},
2166 };
2167
2168 MODULE_DEVICE_TABLE(amba, etm4_ids);
2169
2170 static struct amba_driver etm4x_amba_driver = {
2171         .drv = {
2172                 .name   = "coresight-etm4x",
2173                 .owner  = THIS_MODULE,
2174                 .suppress_bind_attrs = true,
2175         },
2176         .probe          = etm4_probe_amba,
2177         .remove         = etm4_remove_amba,
2178         .id_table       = etm4_ids,
2179 };
2180
2181 static const struct of_device_id etm4_sysreg_match[] = {
2182         { .compatible   = "arm,coresight-etm4x-sysreg" },
2183         { .compatible   = "arm,embedded-trace-extension" },
2184         {}
2185 };
2186
2187 static struct platform_driver etm4_platform_driver = {
2188         .probe          = etm4_probe_platform_dev,
2189         .remove         = etm4_remove_platform_dev,
2190         .driver                 = {
2191                 .name                   = "coresight-etm4x",
2192                 .of_match_table         = etm4_sysreg_match,
2193                 .suppress_bind_attrs    = true,
2194         },
2195 };
2196
2197 static int __init etm4x_init(void)
2198 {
2199         int ret;
2200
2201         ret = etm4_pm_setup();
2202
2203         /* etm4_pm_setup() does its own cleanup - exit on error */
2204         if (ret)
2205                 return ret;
2206
2207         ret = amba_driver_register(&etm4x_amba_driver);
2208         if (ret) {
2209                 pr_err("Error registering etm4x AMBA driver\n");
2210                 goto clear_pm;
2211         }
2212
2213         ret = platform_driver_register(&etm4_platform_driver);
2214         if (!ret)
2215                 return 0;
2216
2217         pr_err("Error registering etm4x platform driver\n");
2218         amba_driver_unregister(&etm4x_amba_driver);
2219
2220 clear_pm:
2221         etm4_pm_clear();
2222         return ret;
2223 }
2224
2225 static void __exit etm4x_exit(void)
2226 {
2227         amba_driver_unregister(&etm4x_amba_driver);
2228         platform_driver_unregister(&etm4_platform_driver);
2229         etm4_pm_clear();
2230 }
2231
2232 module_init(etm4x_init);
2233 module_exit(etm4x_exit);
2234
2235 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2236 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2237 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2238 MODULE_LICENSE("GPL v2");