1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023 Intel Corporation
6 #include <linux/hwmon-sysfs.h>
7 #include <linux/hwmon.h>
8 #include <linux/types.h>
10 #include <drm/drm_managed.h>
11 #include "regs/xe_gt_regs.h"
12 #include "regs/xe_mchbar_regs.h"
13 #include "xe_device.h"
18 #include "xe_pcode_api.h"
23 REG_PKG_POWER_SKU_UNIT,
25 REG_PKG_ENERGY_STATUS,
28 enum xe_hwmon_reg_operation {
35 * SF_* - scale factors for particular quantities according to hwmon spec.
37 #define SF_POWER 1000000 /* microwatts */
38 #define SF_CURR 1000 /* milliamperes */
39 #define SF_VOLTAGE 1000 /* millivolts */
40 #define SF_ENERGY 1000000 /* microjoules */
41 #define SF_TIME 1000 /* milliseconds */
44 * struct xe_hwmon_energy_info - to accumulate energy
46 struct xe_hwmon_energy_info {
47 /** @reg_val_prev: previous energy reg val */
49 /** @accum_energy: accumulated energy */
54 * struct xe_hwmon - xe hwmon data structure
57 /** @hwmon_dev: hwmon device for xe */
58 struct device *hwmon_dev;
59 /** @gt: primary gt */
61 /** @hwmon_lock: lock for rw attributes*/
62 struct mutex hwmon_lock;
63 /** @scl_shift_power: pkg power unit */
65 /** @scl_shift_energy: pkg energy unit */
67 /** @scl_shift_time: pkg time unit */
69 /** @ei: Energy info for energy1_input */
70 struct xe_hwmon_energy_info ei;
73 static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
75 struct xe_device *xe = gt_to_xe(hwmon->gt);
76 struct xe_reg reg = XE_REG(0);
79 case REG_PKG_RAPL_LIMIT:
80 if (xe->info.platform == XE_DG2)
81 reg = PCU_CR_PACKAGE_RAPL_LIMIT;
82 else if (xe->info.platform == XE_PVC)
83 reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
85 case REG_PKG_POWER_SKU:
86 if (xe->info.platform == XE_DG2)
87 reg = PCU_CR_PACKAGE_POWER_SKU;
88 else if (xe->info.platform == XE_PVC)
89 reg = PVC_GT0_PACKAGE_POWER_SKU;
91 case REG_PKG_POWER_SKU_UNIT:
92 if (xe->info.platform == XE_DG2)
93 reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
94 else if (xe->info.platform == XE_PVC)
95 reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
97 case REG_GT_PERF_STATUS:
98 if (xe->info.platform == XE_DG2)
101 case REG_PKG_ENERGY_STATUS:
102 if (xe->info.platform == XE_DG2)
103 reg = PCU_CR_PACKAGE_ENERGY_STATUS;
104 else if (xe->info.platform == XE_PVC)
105 reg = PVC_GT0_PLATFORM_ENERGY_STATUS;
108 drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg);
115 static void xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
116 enum xe_hwmon_reg_operation operation, u64 *value,
121 reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
128 *value = xe_mmio_read32(hwmon->gt, reg);
131 *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
134 *value = xe_mmio_read64_2x32(hwmon->gt, reg);
137 drm_warn(>_to_xe(hwmon->gt)->drm, "Invalid xe hwmon reg operation: %d\n",
143 #define PL1_DISABLE 0
146 * HW allows arbitrary PL1 limits to be set but silently clamps these values to
147 * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
148 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
149 * clamped values when read.
151 static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
153 u64 reg_val, min, max;
155 mutex_lock(&hwmon->hwmon_lock);
157 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ32, ®_val, 0, 0);
158 /* Check if PL1 limit is disabled */
159 if (!(reg_val & PKG_PWR_LIM_1_EN)) {
160 *value = PL1_DISABLE;
164 reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
165 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
167 xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ64, ®_val, 0, 0);
168 min = REG_FIELD_GET(PKG_MIN_PWR, reg_val);
169 min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
170 max = REG_FIELD_GET(PKG_MAX_PWR, reg_val);
171 max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
174 *value = clamp_t(u64, *value, min, max);
176 mutex_unlock(&hwmon->hwmon_lock);
179 static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
184 mutex_lock(&hwmon->hwmon_lock);
186 /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
187 if (value == PL1_DISABLE) {
188 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, ®_val,
189 PKG_PWR_LIM_1_EN, 0);
190 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ32, ®_val,
191 PKG_PWR_LIM_1_EN, 0);
193 if (reg_val & PKG_PWR_LIM_1_EN) {
199 /* Computation in 64-bits to avoid overflow. Round to nearest. */
200 reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
201 reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
203 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, ®_val,
204 PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
206 mutex_unlock(&hwmon->hwmon_lock);
210 static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
214 xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ32, ®_val, 0, 0);
215 reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
216 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
220 * xe_hwmon_energy_get - Obtain energy value
222 * The underlying energy hardware register is 32-bits and is subject to
223 * overflow. How long before overflow? For example, with an example
224 * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
225 * a power draw of 1000 watts, the 32-bit counter will overflow in
226 * approximately 4.36 minutes.
229 * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
230 * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
232 * The function significantly increases overflow duration (from 4.36
233 * minutes) by accumulating the energy register into a 'long' as allowed by
234 * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
235 * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
236 * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
237 * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
240 xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
242 struct xe_hwmon_energy_info *ei = &hwmon->ei;
245 xe_hwmon_process_reg(hwmon, REG_PKG_ENERGY_STATUS, REG_READ32,
248 if (reg_val >= ei->reg_val_prev)
249 ei->accum_energy += reg_val - ei->reg_val_prev;
251 ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
253 ei->reg_val_prev = reg_val;
255 *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
256 hwmon->scl_shift_energy);
260 xe_hwmon_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
263 struct xe_hwmon *hwmon = dev_get_drvdata(dev);
264 u32 x, y, x_w = 2; /* 2 bits */
267 xe_device_mem_access_get(gt_to_xe(hwmon->gt));
269 mutex_lock(&hwmon->hwmon_lock);
271 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
272 REG_READ32, &r, 0, 0);
274 mutex_unlock(&hwmon->hwmon_lock);
276 xe_device_mem_access_put(gt_to_xe(hwmon->gt));
278 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
279 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
282 * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
283 * = (4 | x) << (y - 2)
285 * Here (y - 2) ensures a 1.x fixed point representation of 1.x
286 * As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75
288 * As y can be < 2, we compute tau4 = (4 | x) << y
289 * and then add 2 when doing the final right shift to account for units
291 tau4 = ((1 << x_w) | x) << y;
293 /* val in hwmon interface units (millisec) */
294 out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
296 return sysfs_emit(buf, "%llu\n", out);
300 xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr,
301 const char *buf, size_t count)
303 struct xe_hwmon *hwmon = dev_get_drvdata(dev);
304 u32 x, y, rxy, x_w = 2; /* 2 bits */
305 u64 tau4, r, max_win;
309 ret = kstrtoul(buf, 0, &val);
314 * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12.
315 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds.
317 * The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register.
318 * However, it is observed that existing discrete GPUs does not provide correct
319 * PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs
320 * this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU.
322 #define PKG_MAX_WIN_DEFAULT 0x12ull
325 * val must be < max in hwmon interface units. The steps below are
326 * explained in xe_hwmon_power1_max_interval_show()
328 r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
329 x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
330 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
331 tau4 = ((1 << x_w) | x) << y;
332 max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
337 /* val in hw units */
338 val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
341 * Convert val to 1.x * power(2,y)
343 * x = (val - (1 << y)) >> (y - 2)
350 x = (val - (1ul << y)) << x_w >> y;
353 rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
355 xe_device_mem_access_get(gt_to_xe(hwmon->gt));
357 mutex_lock(&hwmon->hwmon_lock);
359 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, (u64 *)&r,
360 PKG_PWR_LIM_1_TIME, rxy);
362 mutex_unlock(&hwmon->hwmon_lock);
364 xe_device_mem_access_put(gt_to_xe(hwmon->gt));
369 static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
370 xe_hwmon_power1_max_interval_show,
371 xe_hwmon_power1_max_interval_store, 0);
373 static struct attribute *hwmon_attributes[] = {
374 &sensor_dev_attr_power1_max_interval.dev_attr.attr,
378 static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
379 struct attribute *attr, int index)
381 struct device *dev = kobj_to_dev(kobj);
382 struct xe_hwmon *hwmon = dev_get_drvdata(dev);
385 xe_device_mem_access_get(gt_to_xe(hwmon->gt));
387 if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
388 ret = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? attr->mode : 0;
390 xe_device_mem_access_put(gt_to_xe(hwmon->gt));
395 static const struct attribute_group hwmon_attrgroup = {
396 .attrs = hwmon_attributes,
397 .is_visible = xe_hwmon_attributes_visible,
400 static const struct attribute_group *hwmon_groups[] = {
405 static const struct hwmon_channel_info *hwmon_info[] = {
406 HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
407 HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
408 HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
409 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
413 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
414 static int xe_hwmon_pcode_read_i1(struct xe_gt *gt, u32 *uval)
416 /* Avoid Illegal Subcommand error */
417 if (gt_to_xe(gt)->info.platform == XE_DG2)
420 return xe_pcode_read(gt, PCODE_MBOX(PCODE_POWER_SETUP,
421 POWER_SETUP_SUBCOMMAND_READ_I1, 0),
425 static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval)
427 return xe_pcode_write(gt, PCODE_MBOX(PCODE_POWER_SETUP,
428 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0),
432 static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, long *value, u32 scale_factor)
437 mutex_lock(&hwmon->hwmon_lock);
439 ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval);
443 *value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
444 scale_factor, POWER_SETUP_I1_SHIFT);
446 mutex_unlock(&hwmon->hwmon_lock);
450 static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, long value, u32 scale_factor)
455 mutex_lock(&hwmon->hwmon_lock);
457 uval = DIV_ROUND_CLOSEST_ULL(value << POWER_SETUP_I1_SHIFT, scale_factor);
458 ret = xe_hwmon_pcode_write_i1(hwmon->gt, uval);
460 mutex_unlock(&hwmon->hwmon_lock);
464 static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, long *value)
468 xe_hwmon_process_reg(hwmon, REG_GT_PERF_STATUS,
469 REG_READ32, ®_val, 0, 0);
470 /* HW register value in units of 2.5 millivolt */
471 *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
475 xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
480 case hwmon_power_max:
481 return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
482 case hwmon_power_rated_max:
483 return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
484 case hwmon_power_crit:
485 return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) ||
486 !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
493 xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
496 case hwmon_power_max:
497 xe_hwmon_power_max_read(hwmon, val);
499 case hwmon_power_rated_max:
500 xe_hwmon_power_rated_max_read(hwmon, val);
502 case hwmon_power_crit:
503 return xe_hwmon_power_curr_crit_read(hwmon, val, SF_POWER);
510 xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
513 case hwmon_power_max:
514 return xe_hwmon_power_max_write(hwmon, val);
515 case hwmon_power_crit:
516 return xe_hwmon_power_curr_crit_write(hwmon, val, SF_POWER);
523 xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr)
528 case hwmon_curr_crit:
529 return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) ||
530 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
537 xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, long *val)
540 case hwmon_curr_crit:
541 return xe_hwmon_power_curr_crit_read(hwmon, val, SF_CURR);
548 xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, long val)
551 case hwmon_curr_crit:
552 return xe_hwmon_power_curr_crit_write(hwmon, val, SF_CURR);
559 xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr)
563 return xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS) ? 0444 : 0;
570 xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, long *val)
574 xe_hwmon_get_voltage(hwmon, val);
582 xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr)
585 case hwmon_energy_input:
586 return xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS) ? 0444 : 0;
593 xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, long *val)
596 case hwmon_energy_input:
597 xe_hwmon_energy_get(hwmon, val);
605 xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
606 u32 attr, int channel)
608 struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
611 xe_device_mem_access_get(gt_to_xe(hwmon->gt));
615 ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
618 ret = xe_hwmon_curr_is_visible(hwmon, attr);
621 ret = xe_hwmon_in_is_visible(hwmon, attr);
624 ret = xe_hwmon_energy_is_visible(hwmon, attr);
631 xe_device_mem_access_put(gt_to_xe(hwmon->gt));
637 xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
638 int channel, long *val)
640 struct xe_hwmon *hwmon = dev_get_drvdata(dev);
643 xe_device_mem_access_get(gt_to_xe(hwmon->gt));
647 ret = xe_hwmon_power_read(hwmon, attr, channel, val);
650 ret = xe_hwmon_curr_read(hwmon, attr, val);
653 ret = xe_hwmon_in_read(hwmon, attr, val);
656 ret = xe_hwmon_energy_read(hwmon, attr, val);
663 xe_device_mem_access_put(gt_to_xe(hwmon->gt));
669 xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
670 int channel, long val)
672 struct xe_hwmon *hwmon = dev_get_drvdata(dev);
675 xe_device_mem_access_get(gt_to_xe(hwmon->gt));
679 ret = xe_hwmon_power_write(hwmon, attr, channel, val);
682 ret = xe_hwmon_curr_write(hwmon, attr, val);
689 xe_device_mem_access_put(gt_to_xe(hwmon->gt));
694 static const struct hwmon_ops hwmon_ops = {
695 .is_visible = xe_hwmon_is_visible,
696 .read = xe_hwmon_read,
697 .write = xe_hwmon_write,
700 static const struct hwmon_chip_info hwmon_chip_info = {
706 xe_hwmon_get_preregistration_info(struct xe_device *xe)
708 struct xe_hwmon *hwmon = xe->hwmon;
710 u64 val_sku_unit = 0;
713 * The contents of register PKG_POWER_SKU_UNIT do not change,
714 * so read it once and store the shift values.
716 if (xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT)) {
717 xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT,
718 REG_READ32, &val_sku_unit, 0, 0);
719 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
720 hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
721 hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
725 * Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the
726 * first value of the energy register read
728 if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, 0))
729 xe_hwmon_energy_get(hwmon, &energy);
732 static void xe_hwmon_mutex_destroy(void *arg)
734 struct xe_hwmon *hwmon = arg;
736 mutex_destroy(&hwmon->hwmon_lock);
739 void xe_hwmon_register(struct xe_device *xe)
741 struct device *dev = xe->drm.dev;
742 struct xe_hwmon *hwmon;
744 /* hwmon is available only for dGfx */
748 hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
754 mutex_init(&hwmon->hwmon_lock);
755 if (devm_add_action_or_reset(dev, xe_hwmon_mutex_destroy, hwmon))
758 /* primary GT to access device level properties */
759 hwmon->gt = xe->tiles[0].primary_gt;
761 xe_hwmon_get_preregistration_info(xe);
763 drm_dbg(&xe->drm, "Register xe hwmon interface\n");
765 /* hwmon_dev points to device hwmon<i> */
766 hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon,
770 if (IS_ERR(hwmon->hwmon_dev)) {
771 drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);