1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 NVIDIA Corporation
7 #include <linux/clk-provider.h>
8 #include <linux/debugfs.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/reset.h>
17 #include <soc/tegra/pmc.h>
19 #include <drm/display/drm_dp_helper.h>
20 #include <drm/display/drm_scdc_helper.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_debugfs.h>
23 #include <drm/drm_file.h>
24 #include <drm/drm_panel.h>
25 #include <drm/drm_simple_kms_helper.h>
34 #define SOR_REKEY 0x38
36 struct tegra_sor_hdmi_settings {
37 unsigned long frequency;
56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
58 .frequency = 54000000,
70 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
71 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
73 .frequency = 75000000,
85 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
86 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
88 .frequency = 150000000,
100 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
101 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
103 .frequency = 300000000,
111 .bg_vref_level = 0xa,
115 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
116 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
118 .frequency = 600000000,
126 .bg_vref_level = 0x8,
130 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
131 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
137 .frequency = 75000000,
145 .bg_vref_level = 0x8,
149 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
150 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
152 .frequency = 150000000,
160 .bg_vref_level = 0x8,
164 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
165 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
167 .frequency = 300000000,
175 .bg_vref_level = 0xf,
179 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
180 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
182 .frequency = 600000000,
190 .bg_vref_level = 0xe,
194 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
195 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
202 .frequency = 54000000,
214 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
215 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
217 .frequency = 75000000,
229 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
230 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
232 .frequency = 150000000,
238 .tx_pu_value = 0x66 /* 0 */,
243 .sparepll = 0x00, /* 0x34 */
244 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
245 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
247 .frequency = 300000000,
259 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
260 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
262 .frequency = 600000000,
274 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
275 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
281 .frequency = 54000000,
293 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
294 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
296 .frequency = 75000000,
308 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
309 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
311 .frequency = 150000000,
317 .tx_pu_value = 0x66 /* 0 */,
322 .sparepll = 0x00, /* 0x34 */
323 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
324 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
326 .frequency = 300000000,
338 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
339 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
341 .frequency = 600000000,
353 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
354 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
358 struct tegra_sor_regs {
359 unsigned int head_state0;
360 unsigned int head_state1;
361 unsigned int head_state2;
362 unsigned int head_state3;
363 unsigned int head_state4;
364 unsigned int head_state5;
369 unsigned int dp_padctl0;
370 unsigned int dp_padctl2;
373 struct tegra_sor_soc {
380 const struct tegra_sor_regs *regs;
383 const struct tegra_sor_hdmi_settings *settings;
384 unsigned int num_settings;
389 const u8 (*voltage_swing)[4][4];
390 const u8 (*pre_emphasis)[4][4];
391 const u8 (*post_cursor)[4][4];
392 const u8 (*tx_pu)[4][4];
397 struct tegra_sor_ops {
399 int (*probe)(struct tegra_sor *sor);
400 void (*audio_enable)(struct tegra_sor *sor);
401 void (*audio_disable)(struct tegra_sor *sor);
405 struct host1x_client client;
406 struct tegra_output output;
409 const struct tegra_sor_soc *soc;
414 struct reset_control *rst;
415 struct clk *clk_parent;
416 struct clk *clk_safe;
424 struct drm_dp_link link;
425 struct drm_dp_aux *aux;
427 struct drm_info_list *debugfs_files;
429 const struct tegra_sor_ops *ops;
430 enum tegra_io_pad pad;
433 struct tegra_sor_hdmi_settings *settings;
434 unsigned int num_settings;
436 struct regulator *avdd_io_supply;
437 struct regulator *vdd_pll_supply;
438 struct regulator *hdmi_supply;
440 struct delayed_work scdc;
443 struct tegra_hda_format format;
446 struct tegra_sor_state {
447 struct drm_connector_state base;
449 unsigned int link_speed;
454 static inline struct tegra_sor_state *
455 to_sor_state(struct drm_connector_state *state)
457 return container_of(state, struct tegra_sor_state, base);
460 struct tegra_sor_config {
473 static inline struct tegra_sor *
474 host1x_client_to_sor(struct host1x_client *client)
476 return container_of(client, struct tegra_sor, client);
479 static inline struct tegra_sor *to_sor(struct tegra_output *output)
481 return container_of(output, struct tegra_sor, output);
484 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
486 u32 value = readl(sor->regs + (offset << 2));
488 trace_sor_readl(sor->dev, offset, value);
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
496 trace_sor_writel(sor->dev, offset, value);
497 writel(value, sor->regs + (offset << 2));
500 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
504 clk_disable_unprepare(sor->clk);
506 err = clk_set_parent(sor->clk_out, parent);
510 err = clk_prepare_enable(sor->clk);
517 struct tegra_clk_sor_pad {
519 struct tegra_sor *sor;
522 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
524 return container_of(hw, struct tegra_clk_sor_pad, hw);
527 static const char * const tegra_clk_sor_pad_parents[2][2] = {
528 { "pll_d_out0", "pll_dp" },
529 { "pll_d2_out0", "pll_dp" },
533 * Implementing ->set_parent() here isn't really required because the parent
534 * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
535 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
536 * Tegra186 and later SoC generations where the BPMP implements this clock
537 * and doesn't expose the mux via the common clock framework.
540 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
542 struct tegra_clk_sor_pad *pad = to_pad(hw);
543 struct tegra_sor *sor = pad->sor;
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
547 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
551 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
555 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
564 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
566 struct tegra_clk_sor_pad *pad = to_pad(hw);
567 struct tegra_sor *sor = pad->sor;
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
573 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
574 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
575 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
579 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
580 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
588 static const struct clk_ops tegra_clk_sor_pad_ops = {
589 .determine_rate = clk_hw_determine_rate_no_reparent,
590 .set_parent = tegra_clk_sor_pad_set_parent,
591 .get_parent = tegra_clk_sor_pad_get_parent,
594 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
597 struct tegra_clk_sor_pad *pad;
598 struct clk_init_data init;
601 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
603 return ERR_PTR(-ENOMEM);
609 init.parent_names = tegra_clk_sor_pad_parents[sor->index];
610 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
611 init.ops = &tegra_clk_sor_pad_ops;
613 pad->hw.init = &init;
615 clk = devm_clk_register(sor->dev, &pad->hw);
620 static void tegra_sor_filter_rates(struct tegra_sor *sor)
622 struct drm_dp_link *link = &sor->link;
625 /* Tegra only supports RBR, HBR and HBR2 */
626 for (i = 0; i < link->num_rates; i++) {
627 switch (link->rates[i]) {
634 DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
641 drm_dp_link_update_rates(link);
644 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
646 unsigned long timeout;
650 * Clear or set the PD_TXD bit corresponding to each lane, depending
651 * on whether it is used or not.
653 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
656 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
657 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
659 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
660 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
663 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
665 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
668 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
670 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
672 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
674 /* start lane sequencer */
675 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
676 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
677 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
679 timeout = jiffies + msecs_to_jiffies(250);
681 while (time_before(jiffies, timeout)) {
682 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
683 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
686 usleep_range(250, 1000);
689 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
695 static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
697 unsigned long timeout;
700 /* power down all lanes */
701 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
702 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
703 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
704 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
706 /* start lane sequencer */
707 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
708 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
709 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
711 timeout = jiffies + msecs_to_jiffies(250);
713 while (time_before(jiffies, timeout)) {
714 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
715 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
718 usleep_range(25, 100);
721 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
727 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
731 /* pre-charge all used lanes */
732 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
735 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
736 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
738 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
739 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
742 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
744 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
747 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
749 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
751 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
753 usleep_range(15, 100);
755 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
756 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
757 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
758 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
761 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
763 u32 mask = 0x08, adj = 0, value;
765 /* enable pad calibration logic */
766 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
767 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
768 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
770 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
771 value |= SOR_PLL1_TMDS_TERM;
772 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
777 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
778 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
779 value |= SOR_PLL1_TMDS_TERMADJ(adj);
780 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
782 usleep_range(100, 200);
784 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
785 if (value & SOR_PLL1_TERM_COMPOUT)
791 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
792 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
793 value |= SOR_PLL1_TMDS_TERMADJ(adj);
794 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
796 /* disable pad calibration logic */
797 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
798 value |= SOR_DP_PADCTL_PAD_CAL_PD;
799 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
802 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
804 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
805 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
806 const struct tegra_sor_soc *soc = sor->soc;
807 u32 pattern = 0, tx_pu = 0, value;
810 for (value = 0, i = 0; i < link->lanes; i++) {
811 u8 vs = link->train.request.voltage_swing[i];
812 u8 pe = link->train.request.pre_emphasis[i];
813 u8 pc = link->train.request.post_cursor[i];
814 u8 shift = sor->soc->lane_map[i] << 3;
816 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
817 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
818 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
820 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
821 tx_pu = sor->soc->tx_pu[pc][vs][pe];
823 switch (link->train.pattern) {
824 case DP_TRAINING_PATTERN_DISABLE:
825 value = SOR_DP_TPG_SCRAMBLER_GALIOS |
826 SOR_DP_TPG_PATTERN_NONE;
829 case DP_TRAINING_PATTERN_1:
830 value = SOR_DP_TPG_SCRAMBLER_NONE |
831 SOR_DP_TPG_PATTERN_TRAIN1;
834 case DP_TRAINING_PATTERN_2:
835 value = SOR_DP_TPG_SCRAMBLER_NONE |
836 SOR_DP_TPG_PATTERN_TRAIN2;
839 case DP_TRAINING_PATTERN_3:
840 value = SOR_DP_TPG_SCRAMBLER_NONE |
841 SOR_DP_TPG_PATTERN_TRAIN3;
848 if (link->caps.channel_coding)
849 value |= SOR_DP_TPG_CHANNEL_CODING;
851 pattern = pattern << 8 | value;
854 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
855 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
857 if (link->caps.tps3_supported)
858 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
860 tegra_sor_writel(sor, pattern, SOR_DP_TPG);
862 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
863 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
864 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
865 value |= SOR_DP_PADCTL_TX_PU(tx_pu);
866 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
868 usleep_range(20, 100);
873 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
875 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
876 unsigned int rate, lanes;
880 rate = drm_dp_link_rate_to_bw_code(link->rate);
883 /* configure link speed and lane count */
884 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
885 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
886 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
887 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
889 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
890 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
891 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
893 if (link->caps.enhanced_framing)
894 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
896 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
898 usleep_range(400, 1000);
900 /* configure load pulse position adjustment */
901 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
902 value &= ~SOR_PLL1_LOADADJ_MASK;
905 case DP_LINK_BW_1_62:
906 value |= SOR_PLL1_LOADADJ(0x3);
910 value |= SOR_PLL1_LOADADJ(0x4);
914 value |= SOR_PLL1_LOADADJ(0x6);
918 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
920 /* use alternate scrambler reset for eDP */
921 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
924 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
926 value |= SOR_DP_SPARE_PANEL_INTERNAL;
928 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
930 err = tegra_sor_power_down_lanes(sor);
932 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
936 /* power up and pre-charge lanes */
937 err = tegra_sor_power_up_lanes(sor, lanes);
939 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
940 lanes, (lanes != 1) ? "s" : "", err);
944 tegra_sor_dp_precharge(sor, lanes);
949 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
950 .apply_training = tegra_sor_dp_link_apply_training,
951 .configure = tegra_sor_dp_link_configure,
954 static void tegra_sor_super_update(struct tegra_sor *sor)
956 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
957 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
958 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
961 static void tegra_sor_update(struct tegra_sor *sor)
963 tegra_sor_writel(sor, 0, SOR_STATE0);
964 tegra_sor_writel(sor, 1, SOR_STATE0);
965 tegra_sor_writel(sor, 0, SOR_STATE0);
968 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
972 value = tegra_sor_readl(sor, SOR_PWM_DIV);
973 value &= ~SOR_PWM_DIV_MASK;
974 value |= 0x400; /* period */
975 tegra_sor_writel(sor, value, SOR_PWM_DIV);
977 value = tegra_sor_readl(sor, SOR_PWM_CTL);
978 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
979 value |= 0x400; /* duty cycle */
980 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
981 value |= SOR_PWM_CTL_TRIGGER;
982 tegra_sor_writel(sor, value, SOR_PWM_CTL);
984 timeout = jiffies + msecs_to_jiffies(timeout);
986 while (time_before(jiffies, timeout)) {
987 value = tegra_sor_readl(sor, SOR_PWM_CTL);
988 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
991 usleep_range(25, 100);
997 static int tegra_sor_attach(struct tegra_sor *sor)
999 unsigned long value, timeout;
1001 /* wake up in normal mode */
1002 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1003 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1004 value |= SOR_SUPER_STATE_MODE_NORMAL;
1005 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1006 tegra_sor_super_update(sor);
1009 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1010 value |= SOR_SUPER_STATE_ATTACHED;
1011 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1012 tegra_sor_super_update(sor);
1014 timeout = jiffies + msecs_to_jiffies(250);
1016 while (time_before(jiffies, timeout)) {
1017 value = tegra_sor_readl(sor, SOR_TEST);
1018 if ((value & SOR_TEST_ATTACHED) != 0)
1021 usleep_range(25, 100);
1027 static int tegra_sor_wakeup(struct tegra_sor *sor)
1029 unsigned long value, timeout;
1031 timeout = jiffies + msecs_to_jiffies(250);
1033 /* wait for head to wake up */
1034 while (time_before(jiffies, timeout)) {
1035 value = tegra_sor_readl(sor, SOR_TEST);
1036 value &= SOR_TEST_HEAD_MODE_MASK;
1038 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1041 usleep_range(25, 100);
1047 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1051 value = tegra_sor_readl(sor, SOR_PWR);
1052 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1053 tegra_sor_writel(sor, value, SOR_PWR);
1055 timeout = jiffies + msecs_to_jiffies(timeout);
1057 while (time_before(jiffies, timeout)) {
1058 value = tegra_sor_readl(sor, SOR_PWR);
1059 if ((value & SOR_PWR_TRIGGER) == 0)
1062 usleep_range(25, 100);
1068 struct tegra_sor_params {
1069 /* number of link clocks per line */
1070 unsigned int num_clocks;
1071 /* ratio between input and output */
1073 /* precision factor */
1076 unsigned int active_polarity;
1077 unsigned int active_count;
1078 unsigned int active_frac;
1079 unsigned int tu_size;
1083 static int tegra_sor_compute_params(struct tegra_sor *sor,
1084 struct tegra_sor_params *params,
1085 unsigned int tu_size)
1087 u64 active_sym, active_count, frac, approx;
1088 u32 active_polarity, active_frac = 0;
1089 const u64 f = params->precision;
1092 active_sym = params->ratio * tu_size;
1093 active_count = div_u64(active_sym, f) * f;
1094 frac = active_sym - active_count;
1096 /* fraction < 0.5 */
1097 if (frac >= (f / 2)) {
1098 active_polarity = 1;
1101 active_polarity = 0;
1105 frac = div_u64(f * f, frac); /* 1/fraction */
1106 if (frac <= (15 * f)) {
1107 active_frac = div_u64(frac, f);
1110 if (active_polarity)
1113 active_frac = active_polarity ? 1 : 15;
1117 if (active_frac == 1)
1118 active_polarity = 0;
1120 if (active_polarity == 1) {
1122 approx = active_count + (active_frac * (f - 1)) * f;
1123 approx = div_u64(approx, active_frac * f);
1125 approx = active_count + f;
1129 approx = active_count + div_u64(f, active_frac);
1131 approx = active_count;
1134 error = div_s64(active_sym - approx, tu_size);
1135 error *= params->num_clocks;
1137 if (error <= 0 && abs(error) < params->error) {
1138 params->active_count = div_u64(active_count, f);
1139 params->active_polarity = active_polarity;
1140 params->active_frac = active_frac;
1141 params->error = abs(error);
1142 params->tu_size = tu_size;
1151 static int tegra_sor_compute_config(struct tegra_sor *sor,
1152 const struct drm_display_mode *mode,
1153 struct tegra_sor_config *config,
1154 struct drm_dp_link *link)
1156 const u64 f = 100000, link_rate = link->rate * 1000;
1157 const u64 pclk = (u64)mode->clock * 1000;
1158 u64 input, output, watermark, num;
1159 struct tegra_sor_params params;
1160 u32 num_syms_per_line;
1163 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1166 input = pclk * config->bits_per_pixel;
1167 output = link_rate * 8 * link->lanes;
1169 if (input >= output)
1172 memset(¶ms, 0, sizeof(params));
1173 params.ratio = div64_u64(input * f, output);
1174 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1175 params.precision = f;
1176 params.error = 64 * f;
1177 params.tu_size = 64;
1179 for (i = params.tu_size; i >= 32; i--)
1180 if (tegra_sor_compute_params(sor, ¶ms, i))
1183 if (params.active_frac == 0) {
1184 config->active_polarity = 0;
1185 config->active_count = params.active_count;
1187 if (!params.active_polarity)
1188 config->active_count--;
1190 config->tu_size = params.tu_size;
1191 config->active_frac = 1;
1193 config->active_polarity = params.active_polarity;
1194 config->active_count = params.active_count;
1195 config->active_frac = params.active_frac;
1196 config->tu_size = params.tu_size;
1200 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1201 config->active_polarity, config->active_count,
1202 config->tu_size, config->active_frac);
1204 watermark = params.ratio * config->tu_size * (f - params.ratio);
1205 watermark = div_u64(watermark, f);
1207 watermark = div_u64(watermark + params.error, f);
1208 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1209 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1212 if (config->watermark > 30) {
1213 config->watermark = 30;
1215 "unable to compute TU size, forcing watermark to %u\n",
1217 } else if (config->watermark > num_syms_per_line) {
1218 config->watermark = num_syms_per_line;
1219 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1223 /* compute the number of symbols per horizontal blanking interval */
1224 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1225 config->hblank_symbols = div_u64(num, pclk);
1227 if (link->caps.enhanced_framing)
1228 config->hblank_symbols -= 3;
1230 config->hblank_symbols -= 12 / link->lanes;
1232 /* compute the number of symbols per vertical blanking interval */
1233 num = (mode->hdisplay - 25) * link_rate;
1234 config->vblank_symbols = div_u64(num, pclk);
1235 config->vblank_symbols -= 36 / link->lanes + 4;
1237 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1238 config->vblank_symbols);
1243 static void tegra_sor_apply_config(struct tegra_sor *sor,
1244 const struct tegra_sor_config *config)
1248 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1249 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1250 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1251 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1253 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1254 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1255 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1257 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1258 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1260 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1261 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1263 if (config->active_polarity)
1264 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1266 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1268 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1269 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1270 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1272 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1273 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1274 value |= config->hblank_symbols & 0xffff;
1275 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1277 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1278 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1279 value |= config->vblank_symbols & 0xffff;
1280 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1283 static void tegra_sor_mode_set(struct tegra_sor *sor,
1284 const struct drm_display_mode *mode,
1285 struct tegra_sor_state *state)
1287 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1288 unsigned int vbe, vse, hbe, hse, vbs, hbs;
1291 value = tegra_sor_readl(sor, SOR_STATE1);
1292 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1293 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1294 value &= ~SOR_STATE_ASY_OWNER_MASK;
1296 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1297 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1299 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1300 value &= ~SOR_STATE_ASY_HSYNCPOL;
1302 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1303 value |= SOR_STATE_ASY_HSYNCPOL;
1305 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1306 value &= ~SOR_STATE_ASY_VSYNCPOL;
1308 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1309 value |= SOR_STATE_ASY_VSYNCPOL;
1311 switch (state->bpc) {
1313 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1317 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1321 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1325 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1329 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1333 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1337 tegra_sor_writel(sor, value, SOR_STATE1);
1340 * TODO: The video timing programming below doesn't seem to match the
1341 * register definitions.
1344 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1345 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1347 /* sync end = sync width - 1 */
1348 vse = mode->vsync_end - mode->vsync_start - 1;
1349 hse = mode->hsync_end - mode->hsync_start - 1;
1351 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1352 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1354 /* blank end = sync end + back porch */
1355 vbe = vse + (mode->vtotal - mode->vsync_end);
1356 hbe = hse + (mode->htotal - mode->hsync_end);
1358 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1359 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1361 /* blank start = blank end + active */
1362 vbs = vbe + mode->vdisplay;
1363 hbs = hbe + mode->hdisplay;
1365 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1366 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1368 /* XXX interlacing support */
1369 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1372 static int tegra_sor_detach(struct tegra_sor *sor)
1374 unsigned long value, timeout;
1376 /* switch to safe mode */
1377 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1378 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1379 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1380 tegra_sor_super_update(sor);
1382 timeout = jiffies + msecs_to_jiffies(250);
1384 while (time_before(jiffies, timeout)) {
1385 value = tegra_sor_readl(sor, SOR_PWR);
1386 if (value & SOR_PWR_MODE_SAFE)
1390 if ((value & SOR_PWR_MODE_SAFE) == 0)
1394 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1395 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1396 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1397 tegra_sor_super_update(sor);
1400 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1401 value &= ~SOR_SUPER_STATE_ATTACHED;
1402 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1403 tegra_sor_super_update(sor);
1405 timeout = jiffies + msecs_to_jiffies(250);
1407 while (time_before(jiffies, timeout)) {
1408 value = tegra_sor_readl(sor, SOR_TEST);
1409 if ((value & SOR_TEST_ATTACHED) == 0)
1412 usleep_range(25, 100);
1415 if ((value & SOR_TEST_ATTACHED) != 0)
1421 static int tegra_sor_power_down(struct tegra_sor *sor)
1423 unsigned long value, timeout;
1426 value = tegra_sor_readl(sor, SOR_PWR);
1427 value &= ~SOR_PWR_NORMAL_STATE_PU;
1428 value |= SOR_PWR_TRIGGER;
1429 tegra_sor_writel(sor, value, SOR_PWR);
1431 timeout = jiffies + msecs_to_jiffies(250);
1433 while (time_before(jiffies, timeout)) {
1434 value = tegra_sor_readl(sor, SOR_PWR);
1435 if ((value & SOR_PWR_TRIGGER) == 0)
1438 usleep_range(25, 100);
1441 if ((value & SOR_PWR_TRIGGER) != 0)
1444 /* switch to safe parent clock */
1445 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1447 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1451 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1452 value |= SOR_PLL2_PORT_POWERDOWN;
1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1455 usleep_range(20, 100);
1457 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1458 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1459 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1461 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1462 value |= SOR_PLL2_SEQ_PLLCAPPD;
1463 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1464 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1466 usleep_range(20, 100);
1471 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1475 timeout = jiffies + msecs_to_jiffies(timeout);
1477 while (time_before(jiffies, timeout)) {
1478 value = tegra_sor_readl(sor, SOR_CRCA);
1479 if (value & SOR_CRCA_VALID)
1482 usleep_range(100, 200);
1488 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1490 struct drm_info_node *node = s->private;
1491 struct tegra_sor *sor = node->info_ent->data;
1492 struct drm_crtc *crtc = sor->output.encoder.crtc;
1493 struct drm_device *drm = node->minor->dev;
1497 drm_modeset_lock_all(drm);
1499 if (!crtc || !crtc->state->active) {
1504 value = tegra_sor_readl(sor, SOR_STATE1);
1505 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1506 tegra_sor_writel(sor, value, SOR_STATE1);
1508 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1509 value |= SOR_CRC_CNTRL_ENABLE;
1510 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1512 value = tegra_sor_readl(sor, SOR_TEST);
1513 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1514 tegra_sor_writel(sor, value, SOR_TEST);
1516 err = tegra_sor_crc_wait(sor, 100);
1520 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1521 value = tegra_sor_readl(sor, SOR_CRCB);
1523 seq_printf(s, "%08x\n", value);
1526 drm_modeset_unlock_all(drm);
1530 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1532 static const struct debugfs_reg32 tegra_sor_regs[] = {
1533 DEBUGFS_REG32(SOR_CTXSW),
1534 DEBUGFS_REG32(SOR_SUPER_STATE0),
1535 DEBUGFS_REG32(SOR_SUPER_STATE1),
1536 DEBUGFS_REG32(SOR_STATE0),
1537 DEBUGFS_REG32(SOR_STATE1),
1538 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1539 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1540 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1541 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1542 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1543 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1544 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1545 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1546 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1547 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1548 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1549 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1550 DEBUGFS_REG32(SOR_CRC_CNTRL),
1551 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1552 DEBUGFS_REG32(SOR_CLK_CNTRL),
1553 DEBUGFS_REG32(SOR_CAP),
1554 DEBUGFS_REG32(SOR_PWR),
1555 DEBUGFS_REG32(SOR_TEST),
1556 DEBUGFS_REG32(SOR_PLL0),
1557 DEBUGFS_REG32(SOR_PLL1),
1558 DEBUGFS_REG32(SOR_PLL2),
1559 DEBUGFS_REG32(SOR_PLL3),
1560 DEBUGFS_REG32(SOR_CSTM),
1561 DEBUGFS_REG32(SOR_LVDS),
1562 DEBUGFS_REG32(SOR_CRCA),
1563 DEBUGFS_REG32(SOR_CRCB),
1564 DEBUGFS_REG32(SOR_BLANK),
1565 DEBUGFS_REG32(SOR_SEQ_CTL),
1566 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1567 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1568 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1569 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1570 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1571 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1572 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1573 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1574 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1575 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1576 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1577 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1578 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1579 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1580 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1581 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1582 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1583 DEBUGFS_REG32(SOR_PWM_DIV),
1584 DEBUGFS_REG32(SOR_PWM_CTL),
1585 DEBUGFS_REG32(SOR_VCRC_A0),
1586 DEBUGFS_REG32(SOR_VCRC_A1),
1587 DEBUGFS_REG32(SOR_VCRC_B0),
1588 DEBUGFS_REG32(SOR_VCRC_B1),
1589 DEBUGFS_REG32(SOR_CCRC_A0),
1590 DEBUGFS_REG32(SOR_CCRC_A1),
1591 DEBUGFS_REG32(SOR_CCRC_B0),
1592 DEBUGFS_REG32(SOR_CCRC_B1),
1593 DEBUGFS_REG32(SOR_EDATA_A0),
1594 DEBUGFS_REG32(SOR_EDATA_A1),
1595 DEBUGFS_REG32(SOR_EDATA_B0),
1596 DEBUGFS_REG32(SOR_EDATA_B1),
1597 DEBUGFS_REG32(SOR_COUNT_A0),
1598 DEBUGFS_REG32(SOR_COUNT_A1),
1599 DEBUGFS_REG32(SOR_COUNT_B0),
1600 DEBUGFS_REG32(SOR_COUNT_B1),
1601 DEBUGFS_REG32(SOR_DEBUG_A0),
1602 DEBUGFS_REG32(SOR_DEBUG_A1),
1603 DEBUGFS_REG32(SOR_DEBUG_B0),
1604 DEBUGFS_REG32(SOR_DEBUG_B1),
1605 DEBUGFS_REG32(SOR_TRIG),
1606 DEBUGFS_REG32(SOR_MSCHECK),
1607 DEBUGFS_REG32(SOR_XBAR_CTRL),
1608 DEBUGFS_REG32(SOR_XBAR_POL),
1609 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1610 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1611 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1612 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1613 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1614 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1615 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1616 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1617 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1618 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1619 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1620 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1621 DEBUGFS_REG32(SOR_DP_CONFIG0),
1622 DEBUGFS_REG32(SOR_DP_CONFIG1),
1623 DEBUGFS_REG32(SOR_DP_MN0),
1624 DEBUGFS_REG32(SOR_DP_MN1),
1625 DEBUGFS_REG32(SOR_DP_PADCTL0),
1626 DEBUGFS_REG32(SOR_DP_PADCTL1),
1627 DEBUGFS_REG32(SOR_DP_PADCTL2),
1628 DEBUGFS_REG32(SOR_DP_DEBUG0),
1629 DEBUGFS_REG32(SOR_DP_DEBUG1),
1630 DEBUGFS_REG32(SOR_DP_SPARE0),
1631 DEBUGFS_REG32(SOR_DP_SPARE1),
1632 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1633 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1634 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1635 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1636 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1637 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1638 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1639 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1640 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1641 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1642 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1643 DEBUGFS_REG32(SOR_DP_TPG),
1644 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1645 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1646 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1647 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1650 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1652 struct drm_info_node *node = s->private;
1653 struct tegra_sor *sor = node->info_ent->data;
1654 struct drm_crtc *crtc = sor->output.encoder.crtc;
1655 struct drm_device *drm = node->minor->dev;
1659 drm_modeset_lock_all(drm);
1661 if (!crtc || !crtc->state->active) {
1666 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1667 unsigned int offset = tegra_sor_regs[i].offset;
1669 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1670 offset, tegra_sor_readl(sor, offset));
1674 drm_modeset_unlock_all(drm);
1678 static const struct drm_info_list debugfs_files[] = {
1679 { "crc", tegra_sor_show_crc, 0, NULL },
1680 { "regs", tegra_sor_show_regs, 0, NULL },
1683 static int tegra_sor_late_register(struct drm_connector *connector)
1685 struct tegra_output *output = connector_to_output(connector);
1686 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1687 struct drm_minor *minor = connector->dev->primary;
1688 struct dentry *root = connector->debugfs_entry;
1689 struct tegra_sor *sor = to_sor(output);
1691 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1693 if (!sor->debugfs_files)
1696 for (i = 0; i < count; i++)
1697 sor->debugfs_files[i].data = sor;
1699 drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1704 static void tegra_sor_early_unregister(struct drm_connector *connector)
1706 struct tegra_output *output = connector_to_output(connector);
1707 unsigned int count = ARRAY_SIZE(debugfs_files);
1708 struct tegra_sor *sor = to_sor(output);
1710 drm_debugfs_remove_files(sor->debugfs_files, count,
1711 connector->dev->primary);
1712 kfree(sor->debugfs_files);
1713 sor->debugfs_files = NULL;
1716 static void tegra_sor_connector_reset(struct drm_connector *connector)
1718 struct tegra_sor_state *state;
1720 state = kzalloc(sizeof(*state), GFP_KERNEL);
1724 if (connector->state) {
1725 __drm_atomic_helper_connector_destroy_state(connector->state);
1726 kfree(connector->state);
1729 __drm_atomic_helper_connector_reset(connector, &state->base);
1732 static enum drm_connector_status
1733 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1735 struct tegra_output *output = connector_to_output(connector);
1736 struct tegra_sor *sor = to_sor(output);
1739 return drm_dp_aux_detect(sor->aux);
1741 return tegra_output_connector_detect(connector, force);
1744 static struct drm_connector_state *
1745 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1747 struct tegra_sor_state *state = to_sor_state(connector->state);
1748 struct tegra_sor_state *copy;
1750 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1754 __drm_atomic_helper_connector_duplicate_state(connector, ©->base);
1759 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1760 .reset = tegra_sor_connector_reset,
1761 .detect = tegra_sor_connector_detect,
1762 .fill_modes = drm_helper_probe_single_connector_modes,
1763 .destroy = tegra_output_connector_destroy,
1764 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1765 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1766 .late_register = tegra_sor_late_register,
1767 .early_unregister = tegra_sor_early_unregister,
1770 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1772 struct tegra_output *output = connector_to_output(connector);
1773 struct tegra_sor *sor = to_sor(output);
1777 drm_dp_aux_enable(sor->aux);
1779 err = tegra_output_connector_get_modes(connector);
1782 drm_dp_aux_disable(sor->aux);
1787 static enum drm_mode_status
1788 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1789 struct drm_display_mode *mode)
1794 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1795 .get_modes = tegra_sor_connector_get_modes,
1796 .mode_valid = tegra_sor_connector_mode_valid,
1800 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1801 struct drm_crtc_state *crtc_state,
1802 struct drm_connector_state *conn_state)
1804 struct tegra_output *output = encoder_to_output(encoder);
1805 struct tegra_sor_state *state = to_sor_state(conn_state);
1806 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1807 unsigned long pclk = crtc_state->mode.clock * 1000;
1808 struct tegra_sor *sor = to_sor(output);
1809 struct drm_display_info *info;
1812 info = &output->connector.display_info;
1815 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1816 * the pixel clock must be corrected accordingly.
1818 if (pclk >= 340000000) {
1819 state->link_speed = 20;
1820 state->pclk = pclk / 2;
1822 state->link_speed = 10;
1826 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1829 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1833 switch (info->bpc) {
1836 state->bpc = info->bpc;
1840 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1848 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1853 for (i = size; i > 0; i--)
1854 value = (value << 8) | ptr[i - 1];
1859 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1860 const void *data, size_t size)
1862 const u8 *ptr = data;
1863 unsigned long offset;
1868 case HDMI_INFOFRAME_TYPE_AVI:
1869 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1872 case HDMI_INFOFRAME_TYPE_AUDIO:
1873 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1876 case HDMI_INFOFRAME_TYPE_VENDOR:
1877 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1881 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1886 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1887 INFOFRAME_HEADER_VERSION(ptr[1]) |
1888 INFOFRAME_HEADER_LEN(ptr[2]);
1889 tegra_sor_writel(sor, value, offset);
1893 * Each subpack contains 7 bytes, divided into:
1894 * - subpack_low: bytes 0 - 3
1895 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1897 for (i = 3, j = 0; i < size; i += 7, j += 8) {
1898 size_t rem = size - i, num = min_t(size_t, rem, 4);
1900 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1901 tegra_sor_writel(sor, value, offset++);
1903 num = min_t(size_t, rem - num, 3);
1905 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1906 tegra_sor_writel(sor, value, offset++);
1911 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1912 const struct drm_display_mode *mode)
1914 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1915 struct hdmi_avi_infoframe frame;
1919 /* disable AVI infoframe */
1920 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1921 value &= ~INFOFRAME_CTRL_SINGLE;
1922 value &= ~INFOFRAME_CTRL_OTHER;
1923 value &= ~INFOFRAME_CTRL_ENABLE;
1924 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1926 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1927 &sor->output.connector, mode);
1929 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1933 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1935 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1939 tegra_sor_hdmi_write_infopack(sor, buffer, err);
1941 /* enable AVI infoframe */
1942 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1943 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1944 value |= INFOFRAME_CTRL_ENABLE;
1945 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1950 static void tegra_sor_write_eld(struct tegra_sor *sor)
1952 size_t length = drm_eld_size(sor->output.connector.eld), i;
1954 for (i = 0; i < length; i++)
1955 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1956 SOR_AUDIO_HDA_ELD_BUFWR);
1959 * The HDA codec will always report an ELD buffer size of 96 bytes and
1960 * the HDA codec driver will check that each byte read from the buffer
1961 * is valid. Therefore every byte must be written, even if no 96 bytes
1962 * were parsed from EDID.
1964 for (i = length; i < 96; i++)
1965 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1968 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1973 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1974 * is used for interoperability between the HDA codec driver and the
1977 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1978 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1979 tegra_sor_writel(sor, value, SOR_INT_MASK);
1981 tegra_sor_write_eld(sor);
1983 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1984 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1987 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
1989 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
1990 tegra_sor_writel(sor, 0, SOR_INT_MASK);
1991 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
1994 static void tegra_sor_audio_enable(struct tegra_sor *sor)
1998 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2000 /* select HDA audio input */
2001 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2002 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2004 /* inject null samples */
2005 if (sor->format.channels != 2)
2006 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2008 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2010 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2012 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2014 /* enable advertising HBR capability */
2015 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2018 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2020 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2021 struct hdmi_audio_infoframe frame;
2025 err = hdmi_audio_infoframe_init(&frame);
2027 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2031 frame.channels = sor->format.channels;
2033 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2035 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2039 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2041 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2042 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2043 value |= INFOFRAME_CTRL_ENABLE;
2044 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2049 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2053 tegra_sor_audio_enable(sor);
2055 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2057 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2058 SOR_HDMI_SPARE_CTS_RESET(1) |
2059 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2060 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2063 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2064 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2066 /* allow packet to be sent */
2067 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2068 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2070 /* reset N counter and enable lookup */
2071 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2072 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2074 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2075 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2076 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2078 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2079 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2081 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2082 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2084 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2085 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2087 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2088 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2089 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2091 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2092 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2093 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2095 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2096 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2097 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2099 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2100 value &= ~SOR_HDMI_AUDIO_N_RESET;
2101 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2103 tegra_sor_hdmi_enable_audio_infoframe(sor);
2106 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2110 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2111 value &= ~INFOFRAME_CTRL_ENABLE;
2112 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2115 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2117 tegra_sor_hdmi_disable_audio_infoframe(sor);
2120 static struct tegra_sor_hdmi_settings *
2121 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2125 for (i = 0; i < sor->num_settings; i++)
2126 if (frequency <= sor->settings[i].frequency)
2127 return &sor->settings[i];
2132 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2136 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2137 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2138 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2139 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2142 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2144 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false);
2145 drm_scdc_set_scrambling(&sor->output.connector, false);
2147 tegra_sor_hdmi_disable_scrambling(sor);
2150 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2152 if (sor->scdc_enabled) {
2153 cancel_delayed_work_sync(&sor->scdc);
2154 tegra_sor_hdmi_scdc_disable(sor);
2158 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2162 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2163 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2164 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2165 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2168 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2170 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true);
2171 drm_scdc_set_scrambling(&sor->output.connector, true);
2173 tegra_sor_hdmi_enable_scrambling(sor);
2176 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2178 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2180 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) {
2181 DRM_DEBUG_KMS("SCDC not scrambled\n");
2182 tegra_sor_hdmi_scdc_enable(sor);
2185 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2188 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2190 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2191 struct drm_display_mode *mode;
2193 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2195 if (mode->clock >= 340000 && scdc->supported) {
2196 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2197 tegra_sor_hdmi_scdc_enable(sor);
2198 sor->scdc_enabled = true;
2202 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2204 struct tegra_output *output = encoder_to_output(encoder);
2205 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2206 struct tegra_sor *sor = to_sor(output);
2210 tegra_sor_audio_unprepare(sor);
2211 tegra_sor_hdmi_scdc_stop(sor);
2213 err = tegra_sor_detach(sor);
2215 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2217 tegra_sor_writel(sor, 0, SOR_STATE1);
2218 tegra_sor_update(sor);
2220 /* disable display to SOR clock */
2221 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2223 if (!sor->soc->has_nvdisplay)
2224 value &= ~SOR1_TIMING_CYA;
2226 value &= ~SOR_ENABLE(sor->index);
2228 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2230 tegra_dc_commit(dc);
2232 err = tegra_sor_power_down(sor);
2234 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2236 err = tegra_io_pad_power_disable(sor->pad);
2238 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2240 host1x_client_suspend(&sor->client);
2243 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2245 struct tegra_output *output = encoder_to_output(encoder);
2246 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2247 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2248 struct tegra_sor_hdmi_settings *settings;
2249 struct tegra_sor *sor = to_sor(output);
2250 struct tegra_sor_state *state;
2251 struct drm_display_mode *mode;
2252 unsigned long rate, pclk;
2253 unsigned int div, i;
2257 state = to_sor_state(output->connector.state);
2258 mode = &encoder->crtc->state->adjusted_mode;
2259 pclk = mode->clock * 1000;
2261 err = host1x_client_resume(&sor->client);
2263 dev_err(sor->dev, "failed to resume: %d\n", err);
2267 /* switch to safe parent clock */
2268 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2270 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2274 div = clk_get_rate(sor->clk) / 1000000 * 4;
2276 err = tegra_io_pad_power_enable(sor->pad);
2278 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2280 usleep_range(20, 100);
2282 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2283 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2284 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2286 usleep_range(20, 100);
2288 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2289 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2290 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2293 value &= ~SOR_PLL0_VCOPD;
2294 value &= ~SOR_PLL0_PWR;
2295 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2297 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2298 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2301 usleep_range(200, 400);
2303 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2304 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2305 value &= ~SOR_PLL2_PORT_POWERDOWN;
2306 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2308 usleep_range(20, 100);
2310 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2311 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2312 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2313 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2316 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2317 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2320 usleep_range(250, 1000);
2323 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2324 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2325 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2328 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2329 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2332 usleep_range(250, 1000);
2335 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2336 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2337 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2339 if (mode->clock < 340000) {
2340 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2341 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2343 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2344 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2347 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2348 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2350 /* SOR pad PLL stabilization time */
2351 usleep_range(250, 1000);
2353 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2354 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2355 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2356 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2358 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2359 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2360 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2361 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2362 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2363 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2365 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2366 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2367 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2369 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2370 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2371 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2372 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2374 if (!sor->soc->has_nvdisplay) {
2375 /* program the reference clock */
2376 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2377 tegra_sor_writel(sor, value, SOR_REFCLK);
2380 /* XXX not in TRM */
2381 for (value = 0, i = 0; i < 5; i++)
2382 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2383 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2385 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2386 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2389 * Switch the pad clock to the DP clock. Note that we cannot actually
2390 * do this because Tegra186 and later don't support clk_set_parent()
2391 * on the sorX_pad_clkout clocks. We already do the equivalent above
2392 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2395 err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2397 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2403 /* switch the SOR clock to the pad clock */
2404 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2406 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2411 /* switch the output clock to the parent pixel clock */
2412 err = clk_set_parent(sor->clk, sor->clk_parent);
2414 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2419 /* adjust clock rate for HDMI 2.0 modes */
2420 rate = clk_get_rate(sor->clk_parent);
2422 if (mode->clock >= 340000)
2425 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2427 clk_set_rate(sor->clk, rate);
2429 if (!sor->soc->has_nvdisplay) {
2430 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2432 /* XXX is this the proper check? */
2433 if (mode->clock < 75000)
2434 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2436 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2439 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2441 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2442 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2443 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2445 if (!dc->soc->has_nvdisplay) {
2446 /* H_PULSE2 setup */
2447 pulse_start = h_ref_to_sync +
2448 (mode->hsync_end - mode->hsync_start) +
2449 (mode->htotal - mode->hsync_end) - 10;
2451 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2452 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2453 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2455 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2456 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2458 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2459 value |= H_PULSE2_ENABLE;
2460 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2463 /* infoframe setup */
2464 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2466 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2468 /* XXX HDMI audio support not implemented yet */
2469 tegra_sor_hdmi_disable_audio_infoframe(sor);
2471 /* use single TMDS protocol */
2472 value = tegra_sor_readl(sor, SOR_STATE1);
2473 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2474 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2475 tegra_sor_writel(sor, value, SOR_STATE1);
2477 /* power up pad calibration */
2478 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2479 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2480 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2482 /* production settings */
2483 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2485 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2486 mode->clock * 1000);
2490 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2491 value &= ~SOR_PLL0_ICHPMP_MASK;
2492 value &= ~SOR_PLL0_FILTER_MASK;
2493 value &= ~SOR_PLL0_VCOCAP_MASK;
2494 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2495 value |= SOR_PLL0_FILTER(settings->filter);
2496 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2497 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2499 /* XXX not in TRM */
2500 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2501 value &= ~SOR_PLL1_LOADADJ_MASK;
2502 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2503 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2504 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2505 value |= SOR_PLL1_TMDS_TERM;
2506 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2508 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2509 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2510 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2511 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2512 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2513 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2514 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2515 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2516 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2517 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2519 value = settings->drive_current[3] << 24 |
2520 settings->drive_current[2] << 16 |
2521 settings->drive_current[1] << 8 |
2522 settings->drive_current[0] << 0;
2523 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2525 value = settings->preemphasis[3] << 24 |
2526 settings->preemphasis[2] << 16 |
2527 settings->preemphasis[1] << 8 |
2528 settings->preemphasis[0] << 0;
2529 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2531 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2532 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2533 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2534 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2535 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2537 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2538 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2539 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2540 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2542 /* power down pad calibration */
2543 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2544 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2545 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2547 if (!dc->soc->has_nvdisplay) {
2548 /* miscellaneous display controller settings */
2549 value = VSYNC_H_POSITION(1);
2550 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2553 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2554 value &= ~DITHER_CONTROL_MASK;
2555 value &= ~BASE_COLOR_SIZE_MASK;
2557 switch (state->bpc) {
2559 value |= BASE_COLOR_SIZE_666;
2563 value |= BASE_COLOR_SIZE_888;
2567 value |= BASE_COLOR_SIZE_101010;
2571 value |= BASE_COLOR_SIZE_121212;
2575 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2576 value |= BASE_COLOR_SIZE_888;
2580 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2582 /* XXX set display head owner */
2583 value = tegra_sor_readl(sor, SOR_STATE1);
2584 value &= ~SOR_STATE_ASY_OWNER_MASK;
2585 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2586 tegra_sor_writel(sor, value, SOR_STATE1);
2588 err = tegra_sor_power_up(sor, 250);
2590 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2592 /* configure dynamic range of output */
2593 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2594 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2595 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2596 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2598 /* configure colorspace */
2599 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2600 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2601 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2602 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2604 tegra_sor_mode_set(sor, mode, state);
2606 tegra_sor_update(sor);
2608 /* program preamble timing in SOR (XXX) */
2609 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2610 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2611 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2613 err = tegra_sor_attach(sor);
2615 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2617 /* enable display to SOR clock and generate HDMI preamble */
2618 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2620 if (!sor->soc->has_nvdisplay)
2621 value |= SOR1_TIMING_CYA;
2623 value |= SOR_ENABLE(sor->index);
2625 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2627 if (dc->soc->has_nvdisplay) {
2628 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2629 value &= ~PROTOCOL_MASK;
2630 value |= PROTOCOL_SINGLE_TMDS_A;
2631 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2634 tegra_dc_commit(dc);
2636 err = tegra_sor_wakeup(sor);
2638 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2640 tegra_sor_hdmi_scdc_start(sor);
2641 tegra_sor_audio_prepare(sor);
2644 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2645 .disable = tegra_sor_hdmi_disable,
2646 .enable = tegra_sor_hdmi_enable,
2647 .atomic_check = tegra_sor_encoder_atomic_check,
2650 static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2652 struct tegra_output *output = encoder_to_output(encoder);
2653 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2654 struct tegra_sor *sor = to_sor(output);
2659 drm_panel_disable(output->panel);
2662 * Do not attempt to power down a DP link if we're not connected since
2663 * the AUX transactions would just be timing out.
2665 if (output->connector.status != connector_status_disconnected) {
2666 err = drm_dp_link_power_down(sor->aux, &sor->link);
2668 dev_err(sor->dev, "failed to power down link: %d\n",
2672 err = tegra_sor_detach(sor);
2674 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2676 tegra_sor_writel(sor, 0, SOR_STATE1);
2677 tegra_sor_update(sor);
2679 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2680 value &= ~SOR_ENABLE(sor->index);
2681 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2682 tegra_dc_commit(dc);
2684 value = tegra_sor_readl(sor, SOR_STATE1);
2685 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2686 value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2687 value &= ~SOR_STATE_ASY_OWNER_MASK;
2688 tegra_sor_writel(sor, value, SOR_STATE1);
2689 tegra_sor_update(sor);
2691 /* switch to safe parent clock */
2692 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2694 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2696 err = tegra_sor_power_down(sor);
2698 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2700 err = tegra_io_pad_power_disable(sor->pad);
2702 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2704 err = drm_dp_aux_disable(sor->aux);
2706 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2709 drm_panel_unprepare(output->panel);
2711 host1x_client_suspend(&sor->client);
2714 static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2716 struct tegra_output *output = encoder_to_output(encoder);
2717 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2718 struct tegra_sor *sor = to_sor(output);
2719 struct tegra_sor_config config;
2720 struct tegra_sor_state *state;
2721 struct drm_display_mode *mode;
2722 struct drm_display_info *info;
2727 state = to_sor_state(output->connector.state);
2728 mode = &encoder->crtc->state->adjusted_mode;
2729 info = &output->connector.display_info;
2731 err = host1x_client_resume(&sor->client);
2733 dev_err(sor->dev, "failed to resume: %d\n", err);
2737 /* switch to safe parent clock */
2738 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2740 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2742 err = tegra_io_pad_power_enable(sor->pad);
2744 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2746 usleep_range(20, 100);
2748 err = drm_dp_aux_enable(sor->aux);
2750 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2752 err = drm_dp_link_probe(sor->aux, &sor->link);
2754 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2756 tegra_sor_filter_rates(sor);
2758 err = drm_dp_link_choose(&sor->link, mode, info);
2760 dev_err(sor->dev, "failed to choose link: %d\n", err);
2763 drm_panel_prepare(output->panel);
2765 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2766 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2767 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2769 usleep_range(20, 40);
2771 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2772 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2773 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2776 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2780 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2781 value |= SOR_PLL2_SEQ_PLLCAPPD;
2782 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2784 usleep_range(200, 400);
2786 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2787 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2788 value &= ~SOR_PLL2_PORT_POWERDOWN;
2789 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2791 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2792 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2795 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2797 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2799 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2801 usleep_range(200, 400);
2803 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2804 /* XXX not in TRM */
2806 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2808 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2810 value |= SOR_DP_SPARE_SEQ_ENABLE;
2811 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2813 /* XXX not in TRM */
2814 tegra_sor_writel(sor, 0, SOR_LVDS);
2816 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2817 value &= ~SOR_PLL0_ICHPMP_MASK;
2818 value &= ~SOR_PLL0_VCOCAP_MASK;
2819 value |= SOR_PLL0_ICHPMP(0x1);
2820 value |= SOR_PLL0_VCOCAP(0x3);
2821 value |= SOR_PLL0_RESISTOR_EXT;
2822 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2824 /* XXX not in TRM */
2825 for (value = 0, i = 0; i < 5; i++)
2826 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2827 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2829 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2830 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2833 * Switch the pad clock to the DP clock. Note that we cannot actually
2834 * do this because Tegra186 and later don't support clk_set_parent()
2835 * on the sorX_pad_clkout clocks. We already do the equivalent above
2836 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2839 err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2841 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2847 /* switch the SOR clock to the pad clock */
2848 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2850 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2855 /* switch the output clock to the parent pixel clock */
2856 err = clk_set_parent(sor->clk, sor->clk_parent);
2858 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2863 /* use DP-A protocol */
2864 value = tegra_sor_readl(sor, SOR_STATE1);
2865 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2866 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2867 tegra_sor_writel(sor, value, SOR_STATE1);
2870 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2871 value |= SOR_DP_LINKCTL_ENABLE;
2872 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2874 tegra_sor_dp_term_calibrate(sor);
2876 err = drm_dp_link_train(&sor->link);
2878 dev_err(sor->dev, "link training failed: %d\n", err);
2880 dev_dbg(sor->dev, "link training succeeded\n");
2882 err = drm_dp_link_power_up(sor->aux, &sor->link);
2884 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2886 /* compute configuration */
2887 memset(&config, 0, sizeof(config));
2888 config.bits_per_pixel = state->bpc * 3;
2890 err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2892 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2894 tegra_sor_apply_config(sor, &config);
2895 tegra_sor_mode_set(sor, mode, state);
2897 if (output->panel) {
2898 /* CSTM (LVDS, link A/B, upper) */
2899 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2901 tegra_sor_writel(sor, value, SOR_CSTM);
2904 err = tegra_sor_setup_pwm(sor, 250);
2906 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2909 tegra_sor_update(sor);
2911 err = tegra_sor_power_up(sor, 250);
2913 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2915 /* attach and wake up */
2916 err = tegra_sor_attach(sor);
2918 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2920 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2921 value |= SOR_ENABLE(sor->index);
2922 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2924 tegra_dc_commit(dc);
2926 err = tegra_sor_wakeup(sor);
2928 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2931 drm_panel_enable(output->panel);
2934 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2935 .disable = tegra_sor_dp_disable,
2936 .enable = tegra_sor_dp_enable,
2937 .atomic_check = tegra_sor_encoder_atomic_check,
2940 static void tegra_sor_disable_regulator(void *data)
2942 struct regulator *reg = data;
2944 regulator_disable(reg);
2947 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg)
2951 err = regulator_enable(reg);
2955 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
2958 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2962 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
2963 if (IS_ERR(sor->avdd_io_supply))
2964 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply),
2965 "cannot get AVDD I/O supply\n");
2967 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
2969 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2974 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
2975 if (IS_ERR(sor->vdd_pll_supply))
2976 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply),
2977 "cannot get VDD PLL supply\n");
2979 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
2981 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2986 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2987 if (IS_ERR(sor->hdmi_supply))
2988 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply),
2989 "cannot get HDMI supply\n");
2991 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply);
2993 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2997 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3002 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3004 .probe = tegra_sor_hdmi_probe,
3005 .audio_enable = tegra_sor_hdmi_audio_enable,
3006 .audio_disable = tegra_sor_hdmi_audio_disable,
3009 static int tegra_sor_dp_probe(struct tegra_sor *sor)
3013 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3014 if (IS_ERR(sor->avdd_io_supply))
3015 return PTR_ERR(sor->avdd_io_supply);
3017 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
3021 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3022 if (IS_ERR(sor->vdd_pll_supply))
3023 return PTR_ERR(sor->vdd_pll_supply);
3025 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
3032 static const struct tegra_sor_ops tegra_sor_dp_ops = {
3034 .probe = tegra_sor_dp_probe,
3037 static int tegra_sor_init(struct host1x_client *client)
3039 struct drm_device *drm = dev_get_drvdata(client->host);
3040 const struct drm_encoder_helper_funcs *helpers = NULL;
3041 struct tegra_sor *sor = host1x_client_to_sor(client);
3042 int connector = DRM_MODE_CONNECTOR_Unknown;
3043 int encoder = DRM_MODE_ENCODER_NONE;
3047 if (sor->ops == &tegra_sor_hdmi_ops) {
3048 connector = DRM_MODE_CONNECTOR_HDMIA;
3049 encoder = DRM_MODE_ENCODER_TMDS;
3050 helpers = &tegra_sor_hdmi_helpers;
3051 } else if (sor->soc->supports_lvds) {
3052 connector = DRM_MODE_CONNECTOR_LVDS;
3053 encoder = DRM_MODE_ENCODER_LVDS;
3056 if (sor->output.panel) {
3057 connector = DRM_MODE_CONNECTOR_eDP;
3058 encoder = DRM_MODE_ENCODER_TMDS;
3059 helpers = &tegra_sor_dp_helpers;
3061 connector = DRM_MODE_CONNECTOR_DisplayPort;
3062 encoder = DRM_MODE_ENCODER_TMDS;
3063 helpers = &tegra_sor_dp_helpers;
3066 sor->link.ops = &tegra_sor_dp_link_ops;
3067 sor->link.aux = sor->aux;
3070 sor->output.dev = sor->dev;
3072 drm_connector_init_with_ddc(drm, &sor->output.connector,
3073 &tegra_sor_connector_funcs,
3076 drm_connector_helper_add(&sor->output.connector,
3077 &tegra_sor_connector_helper_funcs);
3078 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3080 drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
3081 drm_encoder_helper_add(&sor->output.encoder, helpers);
3083 drm_connector_attach_encoder(&sor->output.connector,
3084 &sor->output.encoder);
3085 drm_connector_register(&sor->output.connector);
3087 err = tegra_output_init(drm, &sor->output);
3089 dev_err(client->dev, "failed to initialize output: %d\n", err);
3093 tegra_output_find_possible_crtcs(&sor->output, drm);
3096 err = drm_dp_aux_attach(sor->aux, &sor->output);
3098 dev_err(sor->dev, "failed to attach DP: %d\n", err);
3104 * XXX: Remove this reset once proper hand-over from firmware to
3105 * kernel is possible.
3108 err = pm_runtime_resume_and_get(sor->dev);
3110 dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
3114 err = reset_control_acquire(sor->rst);
3116 dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3121 err = reset_control_assert(sor->rst);
3123 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3129 err = clk_prepare_enable(sor->clk);
3131 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3135 usleep_range(1000, 3000);
3138 err = reset_control_deassert(sor->rst);
3140 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3142 clk_disable_unprepare(sor->clk);
3146 reset_control_release(sor->rst);
3147 pm_runtime_put(sor->dev);
3150 err = clk_prepare_enable(sor->clk_safe);
3152 clk_disable_unprepare(sor->clk);
3156 err = clk_prepare_enable(sor->clk_dp);
3158 clk_disable_unprepare(sor->clk_safe);
3159 clk_disable_unprepare(sor->clk);
3167 pm_runtime_put(sor->dev);
3172 static int tegra_sor_exit(struct host1x_client *client)
3174 struct tegra_sor *sor = host1x_client_to_sor(client);
3177 tegra_output_exit(&sor->output);
3180 err = drm_dp_aux_detach(sor->aux);
3182 dev_err(sor->dev, "failed to detach DP: %d\n", err);
3187 clk_disable_unprepare(sor->clk_safe);
3188 clk_disable_unprepare(sor->clk_dp);
3189 clk_disable_unprepare(sor->clk);
3194 static int tegra_sor_runtime_suspend(struct host1x_client *client)
3196 struct tegra_sor *sor = host1x_client_to_sor(client);
3197 struct device *dev = client->dev;
3201 err = reset_control_assert(sor->rst);
3203 dev_err(dev, "failed to assert reset: %d\n", err);
3207 reset_control_release(sor->rst);
3210 usleep_range(1000, 2000);
3212 clk_disable_unprepare(sor->clk);
3213 pm_runtime_put_sync(dev);
3218 static int tegra_sor_runtime_resume(struct host1x_client *client)
3220 struct tegra_sor *sor = host1x_client_to_sor(client);
3221 struct device *dev = client->dev;
3224 err = pm_runtime_resume_and_get(dev);
3226 dev_err(dev, "failed to get runtime PM: %d\n", err);
3230 err = clk_prepare_enable(sor->clk);
3232 dev_err(dev, "failed to enable clock: %d\n", err);
3236 usleep_range(1000, 2000);
3239 err = reset_control_acquire(sor->rst);
3241 dev_err(dev, "failed to acquire reset: %d\n", err);
3245 err = reset_control_deassert(sor->rst);
3247 dev_err(dev, "failed to deassert reset: %d\n", err);
3255 reset_control_release(sor->rst);
3257 clk_disable_unprepare(sor->clk);
3259 pm_runtime_put_sync(dev);
3263 static const struct host1x_client_ops sor_client_ops = {
3264 .init = tegra_sor_init,
3265 .exit = tegra_sor_exit,
3266 .suspend = tegra_sor_runtime_suspend,
3267 .resume = tegra_sor_runtime_resume,
3270 static const u8 tegra124_sor_xbar_cfg[5] = {
3274 static const struct tegra_sor_regs tegra124_sor_regs = {
3275 .head_state0 = 0x05,
3276 .head_state1 = 0x07,
3277 .head_state2 = 0x09,
3278 .head_state3 = 0x0b,
3279 .head_state4 = 0x0d,
3280 .head_state5 = 0x0f,
3289 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3290 static const u8 tegra124_sor_lane_map[4] = {
3294 static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3296 { 0x13, 0x19, 0x1e, 0x28 },
3297 { 0x1e, 0x25, 0x2d, },
3301 { 0x12, 0x17, 0x1b, 0x25 },
3302 { 0x1c, 0x23, 0x2a, },
3306 { 0x12, 0x16, 0x1a, 0x22 },
3307 { 0x1b, 0x20, 0x27, },
3311 { 0x11, 0x14, 0x17, 0x1f },
3312 { 0x19, 0x1e, 0x24, },
3318 static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3320 { 0x00, 0x09, 0x13, 0x25 },
3321 { 0x00, 0x0f, 0x1e, },
3325 { 0x00, 0x0a, 0x14, 0x28 },
3326 { 0x00, 0x0f, 0x1e, },
3330 { 0x00, 0x0a, 0x14, 0x28 },
3331 { 0x00, 0x0f, 0x1e, },
3335 { 0x00, 0x0a, 0x14, 0x28 },
3336 { 0x00, 0x0f, 0x1e, },
3342 static const u8 tegra124_sor_post_cursor[4][4][4] = {
3344 { 0x00, 0x00, 0x00, 0x00 },
3345 { 0x00, 0x00, 0x00, },
3349 { 0x02, 0x02, 0x04, 0x05 },
3350 { 0x02, 0x04, 0x05, },
3354 { 0x04, 0x05, 0x08, 0x0b },
3355 { 0x05, 0x09, 0x0b, },
3359 { 0x05, 0x09, 0x0b, 0x12 },
3360 { 0x09, 0x0d, 0x12, },
3366 static const u8 tegra124_sor_tx_pu[4][4][4] = {
3368 { 0x20, 0x30, 0x40, 0x60 },
3369 { 0x30, 0x40, 0x60, },
3373 { 0x20, 0x20, 0x30, 0x50 },
3374 { 0x30, 0x40, 0x50, },
3378 { 0x20, 0x20, 0x30, 0x40, },
3379 { 0x30, 0x30, 0x40, },
3383 { 0x20, 0x20, 0x20, 0x40, },
3384 { 0x30, 0x30, 0x40, },
3390 static const struct tegra_sor_soc tegra124_sor = {
3391 .supports_lvds = true,
3392 .supports_hdmi = false,
3393 .supports_dp = true,
3394 .supports_audio = false,
3395 .supports_hdcp = false,
3396 .regs = &tegra124_sor_regs,
3397 .has_nvdisplay = false,
3398 .xbar_cfg = tegra124_sor_xbar_cfg,
3399 .lane_map = tegra124_sor_lane_map,
3400 .voltage_swing = tegra124_sor_voltage_swing,
3401 .pre_emphasis = tegra124_sor_pre_emphasis,
3402 .post_cursor = tegra124_sor_post_cursor,
3403 .tx_pu = tegra124_sor_tx_pu,
3406 static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3408 { 0x00, 0x08, 0x12, 0x24 },
3409 { 0x01, 0x0e, 0x1d, },
3413 { 0x00, 0x08, 0x12, 0x24 },
3414 { 0x00, 0x0e, 0x1d, },
3418 { 0x00, 0x08, 0x12, 0x24 },
3419 { 0x00, 0x0e, 0x1d, },
3423 { 0x00, 0x08, 0x12, 0x24 },
3424 { 0x00, 0x0e, 0x1d, },
3430 static const struct tegra_sor_soc tegra132_sor = {
3431 .supports_lvds = true,
3432 .supports_hdmi = false,
3433 .supports_dp = true,
3434 .supports_audio = false,
3435 .supports_hdcp = false,
3436 .regs = &tegra124_sor_regs,
3437 .has_nvdisplay = false,
3438 .xbar_cfg = tegra124_sor_xbar_cfg,
3439 .lane_map = tegra124_sor_lane_map,
3440 .voltage_swing = tegra124_sor_voltage_swing,
3441 .pre_emphasis = tegra132_sor_pre_emphasis,
3442 .post_cursor = tegra124_sor_post_cursor,
3443 .tx_pu = tegra124_sor_tx_pu,
3446 static const struct tegra_sor_regs tegra210_sor_regs = {
3447 .head_state0 = 0x05,
3448 .head_state1 = 0x07,
3449 .head_state2 = 0x09,
3450 .head_state3 = 0x0b,
3451 .head_state4 = 0x0d,
3452 .head_state5 = 0x0f,
3461 static const u8 tegra210_sor_xbar_cfg[5] = {
3465 static const u8 tegra210_sor_lane_map[4] = {
3469 static const struct tegra_sor_soc tegra210_sor = {
3470 .supports_lvds = false,
3471 .supports_hdmi = false,
3472 .supports_dp = true,
3473 .supports_audio = false,
3474 .supports_hdcp = false,
3476 .regs = &tegra210_sor_regs,
3477 .has_nvdisplay = false,
3479 .xbar_cfg = tegra210_sor_xbar_cfg,
3480 .lane_map = tegra210_sor_lane_map,
3481 .voltage_swing = tegra124_sor_voltage_swing,
3482 .pre_emphasis = tegra124_sor_pre_emphasis,
3483 .post_cursor = tegra124_sor_post_cursor,
3484 .tx_pu = tegra124_sor_tx_pu,
3487 static const struct tegra_sor_soc tegra210_sor1 = {
3488 .supports_lvds = false,
3489 .supports_hdmi = true,
3490 .supports_dp = true,
3491 .supports_audio = true,
3492 .supports_hdcp = true,
3494 .regs = &tegra210_sor_regs,
3495 .has_nvdisplay = false,
3497 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3498 .settings = tegra210_sor_hdmi_defaults,
3499 .xbar_cfg = tegra210_sor_xbar_cfg,
3500 .lane_map = tegra210_sor_lane_map,
3501 .voltage_swing = tegra124_sor_voltage_swing,
3502 .pre_emphasis = tegra124_sor_pre_emphasis,
3503 .post_cursor = tegra124_sor_post_cursor,
3504 .tx_pu = tegra124_sor_tx_pu,
3507 static const struct tegra_sor_regs tegra186_sor_regs = {
3508 .head_state0 = 0x151,
3509 .head_state1 = 0x154,
3510 .head_state2 = 0x157,
3511 .head_state3 = 0x15a,
3512 .head_state4 = 0x15d,
3513 .head_state5 = 0x160,
3518 .dp_padctl0 = 0x168,
3519 .dp_padctl2 = 0x16a,
3522 static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3524 { 0x13, 0x19, 0x1e, 0x28 },
3525 { 0x1e, 0x25, 0x2d, },
3529 { 0x12, 0x16, 0x1b, 0x25 },
3530 { 0x1c, 0x23, 0x2a, },
3534 { 0x12, 0x16, 0x1a, 0x22 },
3535 { 0x1b, 0x20, 0x27, },
3539 { 0x11, 0x14, 0x17, 0x1f },
3540 { 0x19, 0x1e, 0x24, },
3546 static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3548 { 0x00, 0x08, 0x12, 0x24 },
3549 { 0x01, 0x0e, 0x1d, },
3553 { 0x00, 0x08, 0x12, 0x24 },
3554 { 0x00, 0x0e, 0x1d, },
3558 { 0x00, 0x08, 0x14, 0x24 },
3559 { 0x00, 0x0e, 0x1d, },
3563 { 0x00, 0x08, 0x12, 0x24 },
3564 { 0x00, 0x0e, 0x1d, },
3570 static const struct tegra_sor_soc tegra186_sor = {
3571 .supports_lvds = false,
3572 .supports_hdmi = true,
3573 .supports_dp = true,
3574 .supports_audio = true,
3575 .supports_hdcp = true,
3577 .regs = &tegra186_sor_regs,
3578 .has_nvdisplay = true,
3580 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3581 .settings = tegra186_sor_hdmi_defaults,
3582 .xbar_cfg = tegra124_sor_xbar_cfg,
3583 .lane_map = tegra124_sor_lane_map,
3584 .voltage_swing = tegra186_sor_voltage_swing,
3585 .pre_emphasis = tegra186_sor_pre_emphasis,
3586 .post_cursor = tegra124_sor_post_cursor,
3587 .tx_pu = tegra124_sor_tx_pu,
3590 static const struct tegra_sor_regs tegra194_sor_regs = {
3591 .head_state0 = 0x151,
3592 .head_state1 = 0x155,
3593 .head_state2 = 0x159,
3594 .head_state3 = 0x15d,
3595 .head_state4 = 0x161,
3596 .head_state5 = 0x165,
3601 .dp_padctl0 = 0x16e,
3602 .dp_padctl2 = 0x16f,
3605 static const struct tegra_sor_soc tegra194_sor = {
3606 .supports_lvds = false,
3607 .supports_hdmi = true,
3608 .supports_dp = true,
3609 .supports_audio = true,
3610 .supports_hdcp = true,
3612 .regs = &tegra194_sor_regs,
3613 .has_nvdisplay = true,
3615 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3616 .settings = tegra194_sor_hdmi_defaults,
3618 .xbar_cfg = tegra210_sor_xbar_cfg,
3619 .lane_map = tegra124_sor_lane_map,
3620 .voltage_swing = tegra186_sor_voltage_swing,
3621 .pre_emphasis = tegra186_sor_pre_emphasis,
3622 .post_cursor = tegra124_sor_post_cursor,
3623 .tx_pu = tegra124_sor_tx_pu,
3626 static const struct of_device_id tegra_sor_of_match[] = {
3627 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3628 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3629 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3630 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3631 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3632 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3635 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3637 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3639 struct device_node *np = sor->dev->of_node;
3645 if (sor->soc->has_nvdisplay) {
3646 err = of_property_read_u32(np, "nvidia,interface", &value);
3653 * override the default that we already set for Tegra210 and
3656 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3658 if (!sor->soc->supports_audio)
3664 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3666 /* fall back to default per-SoC XBAR configuration */
3667 for (i = 0; i < 5; i++)
3668 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3670 /* copy cells to SOR XBAR configuration */
3671 for (i = 0; i < 5; i++)
3672 sor->xbar_cfg[i] = xbar_cfg[i];
3678 static irqreturn_t tegra_sor_irq(int irq, void *data)
3680 struct tegra_sor *sor = data;
3683 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3684 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3686 if (value & SOR_INT_CODEC_SCRATCH0) {
3687 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3689 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3690 unsigned int format;
3692 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3694 tegra_hda_parse_format(format, &sor->format);
3696 if (sor->ops->audio_enable)
3697 sor->ops->audio_enable(sor);
3699 if (sor->ops->audio_disable)
3700 sor->ops->audio_disable(sor);
3707 static int tegra_sor_probe(struct platform_device *pdev)
3709 struct device_node *np;
3710 struct tegra_sor *sor;
3711 struct resource *regs;
3714 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3718 sor->soc = of_device_get_match_data(&pdev->dev);
3719 sor->output.dev = sor->dev = &pdev->dev;
3721 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3722 sor->soc->num_settings *
3723 sizeof(*sor->settings),
3728 sor->num_settings = sor->soc->num_settings;
3730 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3732 sor->aux = drm_dp_aux_find_by_of_node(np);
3736 return -EPROBE_DEFER;
3738 if (get_device(sor->aux->dev))
3739 sor->output.ddc = &sor->aux->ddc;
3743 if (sor->soc->supports_hdmi) {
3744 sor->ops = &tegra_sor_hdmi_ops;
3745 sor->pad = TEGRA_IO_PAD_HDMI;
3746 } else if (sor->soc->supports_lvds) {
3747 dev_err(&pdev->dev, "LVDS not supported yet\n");
3750 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3754 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3756 * No need to keep this around since we only use it as a check
3757 * to see if a panel is connected (eDP) or not (DP).
3761 sor->ops = &tegra_sor_dp_ops;
3762 sor->pad = TEGRA_IO_PAD_LVDS;
3765 err = tegra_sor_parse_dt(sor);
3769 err = tegra_output_probe(&sor->output);
3771 dev_err_probe(&pdev->dev, err, "failed to probe output\n");
3775 if (sor->ops && sor->ops->probe) {
3776 err = sor->ops->probe(sor);
3778 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3779 sor->ops->name, err);
3784 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3785 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3786 if (IS_ERR(sor->regs)) {
3787 err = PTR_ERR(sor->regs);
3791 err = platform_get_irq(pdev, 0);
3797 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3798 dev_name(sor->dev), sor);
3800 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3804 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3805 if (IS_ERR(sor->rst)) {
3806 err = PTR_ERR(sor->rst);
3808 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3809 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3815 * At this point, the reset control is most likely being used
3816 * by the generic power domain implementation. With any luck
3817 * the power domain will have taken care of resetting the SOR
3818 * and we don't have to do anything.
3823 sor->clk = devm_clk_get(&pdev->dev, NULL);
3824 if (IS_ERR(sor->clk)) {
3825 err = PTR_ERR(sor->clk);
3826 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3830 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3831 struct device_node *np = pdev->dev.of_node;
3835 * For backwards compatibility with Tegra210 device trees,
3836 * fall back to the old clock name "source" if the new "out"
3837 * clock is not available.
3839 if (of_property_match_string(np, "clock-names", "out") < 0)
3844 sor->clk_out = devm_clk_get(&pdev->dev, name);
3845 if (IS_ERR(sor->clk_out)) {
3846 err = PTR_ERR(sor->clk_out);
3847 dev_err(sor->dev, "failed to get %s clock: %d\n",
3852 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3853 sor->clk_out = sor->clk;
3856 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3857 if (IS_ERR(sor->clk_parent)) {
3858 err = PTR_ERR(sor->clk_parent);
3859 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3863 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3864 if (IS_ERR(sor->clk_safe)) {
3865 err = PTR_ERR(sor->clk_safe);
3866 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3870 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3871 if (IS_ERR(sor->clk_dp)) {
3872 err = PTR_ERR(sor->clk_dp);
3873 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3878 * Starting with Tegra186, the BPMP provides an implementation for
3879 * the pad output clock, so we have to look it up from device tree.
3881 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3882 if (IS_ERR(sor->clk_pad)) {
3883 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3884 err = PTR_ERR(sor->clk_pad);
3889 * If the pad output clock is not available, then we assume
3890 * we're on Tegra210 or earlier and have to provide our own
3893 sor->clk_pad = NULL;
3897 * The bootloader may have set up the SOR such that it's module clock
3898 * is sourced by one of the display PLLs. However, that doesn't work
3899 * without properly having set up other bits of the SOR.
3901 err = clk_set_parent(sor->clk_out, sor->clk_safe);
3903 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3907 platform_set_drvdata(pdev, sor);
3908 pm_runtime_enable(&pdev->dev);
3910 host1x_client_init(&sor->client);
3911 sor->client.ops = &sor_client_ops;
3912 sor->client.dev = &pdev->dev;
3915 * On Tegra210 and earlier, provide our own implementation for the
3918 if (!sor->clk_pad) {
3921 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3928 err = host1x_client_resume(&sor->client);
3930 dev_err(sor->dev, "failed to resume: %d\n", err);
3934 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3935 host1x_client_suspend(&sor->client);
3938 if (IS_ERR(sor->clk_pad)) {
3939 err = PTR_ERR(sor->clk_pad);
3940 dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3945 err = __host1x_client_register(&sor->client);
3947 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3955 host1x_client_exit(&sor->client);
3956 pm_runtime_disable(&pdev->dev);
3959 sor->output.ddc = NULL;
3961 tegra_output_remove(&sor->output);
3964 put_device(sor->aux->dev);
3969 static void tegra_sor_remove(struct platform_device *pdev)
3971 struct tegra_sor *sor = platform_get_drvdata(pdev);
3973 host1x_client_unregister(&sor->client);
3975 pm_runtime_disable(&pdev->dev);
3978 put_device(sor->aux->dev);
3979 sor->output.ddc = NULL;
3982 tegra_output_remove(&sor->output);
3985 static int __maybe_unused tegra_sor_suspend(struct device *dev)
3987 struct tegra_sor *sor = dev_get_drvdata(dev);
3990 err = tegra_output_suspend(&sor->output);
3992 dev_err(dev, "failed to suspend output: %d\n", err);
3996 if (sor->hdmi_supply) {
3997 err = regulator_disable(sor->hdmi_supply);
3999 tegra_output_resume(&sor->output);
4007 static int __maybe_unused tegra_sor_resume(struct device *dev)
4009 struct tegra_sor *sor = dev_get_drvdata(dev);
4012 if (sor->hdmi_supply) {
4013 err = regulator_enable(sor->hdmi_supply);
4018 err = tegra_output_resume(&sor->output);
4020 dev_err(dev, "failed to resume output: %d\n", err);
4022 if (sor->hdmi_supply)
4023 regulator_disable(sor->hdmi_supply);
4031 static const struct dev_pm_ops tegra_sor_pm_ops = {
4032 SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4035 struct platform_driver tegra_sor_driver = {
4037 .name = "tegra-sor",
4038 .of_match_table = tegra_sor_of_match,
4039 .pm = &tegra_sor_pm_ops,
4041 .probe = tegra_sor_probe,
4042 .remove_new = tegra_sor_remove,