drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
   4  * Author: Andy Yan <andy.yan@rock-chips.com>
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/delay.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/media-bus-format.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20 #include <linux/swab.h>
  21
  22 #include <drm/drm.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_uapi.h>
  25 #include <drm/drm_blend.h>
  26 #include <drm/drm_crtc.h>
  27 #include <drm/drm_debugfs.h>
  28 #include <drm/drm_flip_work.h>
  29 #include <drm/drm_framebuffer.h>
  30 #include <drm/drm_probe_helper.h>
  31 #include <drm/drm_vblank.h>
  32
  33 #include <uapi/linux/videodev2.h>
  34 #include <dt-bindings/soc/rockchip,vop2.h>
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_vop2.h"
  39 #include "rockchip_rgb.h"
  40
  41 /*
  42  * VOP2 architecture
  43  *
  44  +----------+   +-------------+                                                        +-----------+
  45  |  Cluster |   | Sel 1 from 6|                                                        | 1 from 3  |
  46  |  window0 |   |    Layer0   |                                                        |    RGB    |
  47  +----------+   +-------------+              +---------------+    +-------------+      +-----------+
  48  +----------+   +-------------+              |N from 6 layers|    |             |
  49  |  Cluster |   | Sel 1 from 6|              |   Overlay0    +--->| Video Port0 |      +-----------+
  50  |  window1 |   |    Layer1   |              |               |    |             |      | 1 from 3  |
  51  +----------+   +-------------+              +---------------+    +-------------+      |   LVDS    |
  52  +----------+   +-------------+                                                        +-----------+
  53  |  Esmart  |   | Sel 1 from 6|
  54  |  window0 |   |   Layer2    |              +---------------+    +-------------+      +-----------+
  55  +----------+   +-------------+              |N from 6 Layers|    |             | +--> | 1 from 3  |
  56  +----------+   +-------------+   -------->  |   Overlay1    +--->| Video Port1 |      |   MIPI    |
  57  |  Esmart  |   | Sel 1 from 6|   -------->  |               |    |             |      +-----------+
  58  |  Window1 |   |   Layer3    |              +---------------+    +-------------+
  59  +----------+   +-------------+                                                        +-----------+
  60  +----------+   +-------------+                                                        | 1 from 3  |
  61  |  Smart   |   | Sel 1 from 6|              +---------------+    +-------------+      |   HDMI    |
  62  |  Window0 |   |    Layer4   |              |N from 6 Layers|    |             |      +-----------+
  63  +----------+   +-------------+              |   Overlay2    +--->| Video Port2 |
  64  +----------+   +-------------+              |               |    |             |      +-----------+
  65  |  Smart   |   | Sel 1 from 6|              +---------------+    +-------------+      |  1 from 3 |
  66  |  Window1 |   |    Layer5   |                                                        |    eDP    |
  67  +----------+   +-------------+                                                        +-----------+
  68  *
  69  */
  70
  71 enum vop2_data_format {
  72         VOP2_FMT_ARGB8888 = 0,
  73         VOP2_FMT_RGB888,
  74         VOP2_FMT_RGB565,
  75         VOP2_FMT_XRGB101010,
  76         VOP2_FMT_YUV420SP,
  77         VOP2_FMT_YUV422SP,
  78         VOP2_FMT_YUV444SP,
  79         VOP2_FMT_YUYV422 = 8,
  80         VOP2_FMT_YUYV420,
  81         VOP2_FMT_VYUY422,
  82         VOP2_FMT_VYUY420,
  83         VOP2_FMT_YUV420SP_TILE_8x4 = 0x10,
  84         VOP2_FMT_YUV420SP_TILE_16x2,
  85         VOP2_FMT_YUV422SP_TILE_8x4,
  86         VOP2_FMT_YUV422SP_TILE_16x2,
  87         VOP2_FMT_YUV420SP_10,
  88         VOP2_FMT_YUV422SP_10,
  89         VOP2_FMT_YUV444SP_10,
  90 };
  91
  92 enum vop2_afbc_format {
  93         VOP2_AFBC_FMT_RGB565,
  94         VOP2_AFBC_FMT_ARGB2101010 = 2,
  95         VOP2_AFBC_FMT_YUV420_10BIT,
  96         VOP2_AFBC_FMT_RGB888,
  97         VOP2_AFBC_FMT_ARGB8888,
  98         VOP2_AFBC_FMT_YUV420 = 9,
  99         VOP2_AFBC_FMT_YUV422 = 0xb,
 100         VOP2_AFBC_FMT_YUV422_10BIT = 0xe,
 101         VOP2_AFBC_FMT_INVALID = -1,
 102 };
 103
 104 union vop2_alpha_ctrl {
 105         u32 val;
 106         struct {
 107                 /* [0:1] */
 108                 u32 color_mode:1;
 109                 u32 alpha_mode:1;
 110                 /* [2:3] */
 111                 u32 blend_mode:2;
 112                 u32 alpha_cal_mode:1;
 113                 /* [5:7] */
 114                 u32 factor_mode:3;
 115                 /* [8:9] */
 116                 u32 alpha_en:1;
 117                 u32 src_dst_swap:1;
 118                 u32 reserved:6;
 119                 /* [16:23] */
 120                 u32 glb_alpha:8;
 121         } bits;
 122 };
 123
 124 struct vop2_alpha {
 125         union vop2_alpha_ctrl src_color_ctrl;
 126         union vop2_alpha_ctrl dst_color_ctrl;
 127         union vop2_alpha_ctrl src_alpha_ctrl;
 128         union vop2_alpha_ctrl dst_alpha_ctrl;
 129 };
 130
 131 struct vop2_alpha_config {
 132         bool src_premulti_en;
 133         bool dst_premulti_en;
 134         bool src_pixel_alpha_en;
 135         bool dst_pixel_alpha_en;
 136         u16 src_glb_alpha_value;
 137         u16 dst_glb_alpha_value;
 138 };
 139
 140 struct vop2_win {
 141         struct vop2 *vop2;
 142         struct drm_plane base;
 143         const struct vop2_win_data *data;
 144         struct regmap_field *reg[VOP2_WIN_MAX_REG];
 145
 146         /**
 147          * @win_id: graphic window id, a cluster may be split into two
 148          * graphics windows.
 149          */
 150         u8 win_id;
 151         u8 delay;
 152         u32 offset;
 153
 154         enum drm_plane_type type;
 155 };
 156
 157 struct vop2_video_port {
 158         struct drm_crtc crtc;
 159         struct vop2 *vop2;
 160         struct clk *dclk;
 161         unsigned int id;
 162         const struct vop2_video_port_data *data;
 163
 164         struct completion dsp_hold_completion;
 165
 166         /**
 167          * @win_mask: Bitmask of windows attached to the video port;
 168          */
 169         u32 win_mask;
 170
 171         struct vop2_win *primary_plane;
 172         struct drm_pending_vblank_event *event;
 173
 174         unsigned int nlayers;
 175 };
 176
 177 struct vop2 {
 178         struct device *dev;
 179         struct drm_device *drm;
 180         struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
 181
 182         const struct vop2_data *data;
 183         /*
 184          * Number of windows that are registered as plane, may be less than the
 185          * total number of hardware windows.
 186          */
 187         u32 registered_num_wins;
 188
 189         void __iomem *regs;
 190         struct regmap *map;
 191
 192         struct regmap *sys_grf;
 193         struct regmap *vop_grf;
 194         struct regmap *vo1_grf;
 195         struct regmap *sys_pmu;
 196
 197         /* physical map length of vop2 register */
 198         u32 len;
 199
 200         void __iomem *lut_regs;
 201
 202         /* protects crtc enable/disable */
 203         struct mutex vop2_lock;
 204
 205         int irq;
 206
 207         /*
 208          * Some global resources are shared between all video ports(crtcs), so
 209          * we need a ref counter here.
 210          */
 211         unsigned int enable_count;
 212         struct clk *hclk;
 213         struct clk *aclk;
 214         struct clk *pclk;
 215
 216         /* optional internal rgb encoder */
 217         struct rockchip_rgb *rgb;
 218
 219         /* must be put at the end of the struct */
 220         struct vop2_win win[];
 221 };
 222
 223 #define vop2_output_if_is_hdmi(x)       ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
 224                                          (x) == ROCKCHIP_VOP2_EP_HDMI1)
 225
 226 #define vop2_output_if_is_dp(x)         ((x) == ROCKCHIP_VOP2_EP_DP0 || \
 227                                          (x) == ROCKCHIP_VOP2_EP_DP1)
 228
 229 #define vop2_output_if_is_edp(x)        ((x) == ROCKCHIP_VOP2_EP_EDP0 || \
 230                                          (x) == ROCKCHIP_VOP2_EP_EDP1)
 231
 232 #define vop2_output_if_is_mipi(x)       ((x) == ROCKCHIP_VOP2_EP_MIPI0 || \
 233                                          (x) == ROCKCHIP_VOP2_EP_MIPI1)
 234
 235 #define vop2_output_if_is_lvds(x)       ((x) == ROCKCHIP_VOP2_EP_LVDS0 || \
 236                                          (x) == ROCKCHIP_VOP2_EP_LVDS1)
 237
 238 #define vop2_output_if_is_dpi(x)        ((x) == ROCKCHIP_VOP2_EP_RGB0)
 239
 240 static const struct regmap_config vop2_regmap_config;
 241
 242 static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
 243 {
 244         return container_of(crtc, struct vop2_video_port, crtc);
 245 }
 246
 247 static struct vop2_win *to_vop2_win(struct drm_plane *p)
 248 {
 249         return container_of(p, struct vop2_win, base);
 250 }
 251
 252 static void vop2_lock(struct vop2 *vop2)
 253 {
 254         mutex_lock(&vop2->vop2_lock);
 255 }
 256
 257 static void vop2_unlock(struct vop2 *vop2)
 258 {
 259         mutex_unlock(&vop2->vop2_lock);
 260 }
 261
 262 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
 263 {
 264         regmap_write(vop2->map, offset, v);
 265 }
 266
 267 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
 268 {
 269         regmap_write(vp->vop2->map, vp->data->offset + offset, v);
 270 }
 271
 272 static u32 vop2_readl(struct vop2 *vop2, u32 offset)
 273 {
 274         u32 val;
 275
 276         regmap_read(vop2->map, offset, &val);
 277
 278         return val;
 279 }
 280
 281 static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
 282 {
 283         regmap_field_write(win->reg[reg], v);
 284 }
 285
 286 static bool vop2_cluster_window(const struct vop2_win *win)
 287 {
 288         return win->data->feature & WIN_FEATURE_CLUSTER;
 289 }
 290
 291 /*
 292  * Note:
 293  * The write mask function is documented but missing on rk3566/8, writes
 294  * to these bits have no effect. For newer soc(rk3588 and following) the
 295  * write mask is needed for register writes.
 296  *
 297  * GLB_CFG_DONE_EN has no write mask bit.
 298  *
 299  */
 300 static void vop2_cfg_done(struct vop2_video_port *vp)
 301 {
 302         struct vop2 *vop2 = vp->vop2;
 303         u32 val = RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN;
 304
 305         val |= BIT(vp->id) | (BIT(vp->id) << 16);
 306
 307         regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val);
 308 }
 309
 310 static void vop2_win_disable(struct vop2_win *win)
 311 {
 312         vop2_win_write(win, VOP2_WIN_ENABLE, 0);
 313
 314         if (vop2_cluster_window(win))
 315                 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
 316 }
 317
 318 static u32 vop2_get_bpp(const struct drm_format_info *format)
 319 {
 320         switch (format->format) {
 321         case DRM_FORMAT_YUV420_8BIT:
 322                 return 12;
 323         case DRM_FORMAT_YUV420_10BIT:
 324                 return 15;
 325         case DRM_FORMAT_VUY101010:
 326                 return 30;
 327         default:
 328                 return drm_format_info_bpp(format, 0);
 329         }
 330 }
 331
 332 static enum vop2_data_format vop2_convert_format(u32 format)
 333 {
 334         switch (format) {
 335         case DRM_FORMAT_XRGB2101010:
 336         case DRM_FORMAT_ARGB2101010:
 337         case DRM_FORMAT_XBGR2101010:
 338         case DRM_FORMAT_ABGR2101010:
 339                 return VOP2_FMT_XRGB101010;
 340         case DRM_FORMAT_XRGB8888:
 341         case DRM_FORMAT_ARGB8888:
 342         case DRM_FORMAT_XBGR8888:
 343         case DRM_FORMAT_ABGR8888:
 344                 return VOP2_FMT_ARGB8888;
 345         case DRM_FORMAT_RGB888:
 346         case DRM_FORMAT_BGR888:
 347                 return VOP2_FMT_RGB888;
 348         case DRM_FORMAT_RGB565:
 349         case DRM_FORMAT_BGR565:
 350                 return VOP2_FMT_RGB565;
 351         case DRM_FORMAT_NV12:
 352         case DRM_FORMAT_NV21:
 353         case DRM_FORMAT_YUV420_8BIT:
 354                 return VOP2_FMT_YUV420SP;
 355         case DRM_FORMAT_NV15:
 356         case DRM_FORMAT_YUV420_10BIT:
 357                 return VOP2_FMT_YUV420SP_10;
 358         case DRM_FORMAT_NV16:
 359         case DRM_FORMAT_NV61:
 360                 return VOP2_FMT_YUV422SP;
 361         case DRM_FORMAT_NV20:
 362         case DRM_FORMAT_Y210:
 363                 return VOP2_FMT_YUV422SP_10;
 364         case DRM_FORMAT_NV24:
 365         case DRM_FORMAT_NV42:
 366                 return VOP2_FMT_YUV444SP;
 367         case DRM_FORMAT_NV30:
 368                 return VOP2_FMT_YUV444SP_10;
 369         case DRM_FORMAT_YUYV:
 370         case DRM_FORMAT_YVYU:
 371                 return VOP2_FMT_VYUY422;
 372         case DRM_FORMAT_VYUY:
 373         case DRM_FORMAT_UYVY:
 374                 return VOP2_FMT_YUYV422;
 375         default:
 376                 DRM_ERROR("unsupported format[%08x]\n", format);
 377                 return -EINVAL;
 378         }
 379 }
 380
 381 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format)
 382 {
 383         switch (format) {
 384         case DRM_FORMAT_XRGB2101010:
 385         case DRM_FORMAT_ARGB2101010:
 386         case DRM_FORMAT_XBGR2101010:
 387         case DRM_FORMAT_ABGR2101010:
 388                 return VOP2_AFBC_FMT_ARGB2101010;
 389         case DRM_FORMAT_XRGB8888:
 390         case DRM_FORMAT_ARGB8888:
 391         case DRM_FORMAT_XBGR8888:
 392         case DRM_FORMAT_ABGR8888:
 393                 return VOP2_AFBC_FMT_ARGB8888;
 394         case DRM_FORMAT_RGB888:
 395         case DRM_FORMAT_BGR888:
 396                 return VOP2_AFBC_FMT_RGB888;
 397         case DRM_FORMAT_RGB565:
 398         case DRM_FORMAT_BGR565:
 399                 return VOP2_AFBC_FMT_RGB565;
 400         case DRM_FORMAT_YUV420_8BIT:
 401                 return VOP2_AFBC_FMT_YUV420;
 402         case DRM_FORMAT_YUV420_10BIT:
 403                 return VOP2_AFBC_FMT_YUV420_10BIT;
 404         case DRM_FORMAT_YVYU:
 405         case DRM_FORMAT_YUYV:
 406         case DRM_FORMAT_VYUY:
 407         case DRM_FORMAT_UYVY:
 408                 return VOP2_AFBC_FMT_YUV422;
 409         case DRM_FORMAT_Y210:
 410                 return VOP2_AFBC_FMT_YUV422_10BIT;
 411         default:
 412                 return VOP2_AFBC_FMT_INVALID;
 413         }
 414
 415         return VOP2_AFBC_FMT_INVALID;
 416 }
 417
 418 static bool vop2_win_rb_swap(u32 format)
 419 {
 420         switch (format) {
 421         case DRM_FORMAT_XBGR2101010:
 422         case DRM_FORMAT_ABGR2101010:
 423         case DRM_FORMAT_XBGR8888:
 424         case DRM_FORMAT_ABGR8888:
 425         case DRM_FORMAT_BGR888:
 426         case DRM_FORMAT_BGR565:
 427                 return true;
 428         default:
 429                 return false;
 430         }
 431 }
 432
 433 static bool vop2_afbc_uv_swap(u32 format)
 434 {
 435         switch (format) {
 436         case DRM_FORMAT_YUYV:
 437         case DRM_FORMAT_Y210:
 438         case DRM_FORMAT_YUV420_8BIT:
 439         case DRM_FORMAT_YUV420_10BIT:
 440                 return true;
 441         default:
 442                 return false;
 443         }
 444 }
 445
 446 static bool vop2_win_uv_swap(u32 format)
 447 {
 448         switch (format) {
 449         case DRM_FORMAT_NV12:
 450         case DRM_FORMAT_NV16:
 451         case DRM_FORMAT_NV24:
 452         case DRM_FORMAT_NV15:
 453         case DRM_FORMAT_NV20:
 454         case DRM_FORMAT_NV30:
 455         case DRM_FORMAT_YUYV:
 456         case DRM_FORMAT_UYVY:
 457                 return true;
 458         default:
 459                 return false;
 460         }
 461 }
 462
 463 static bool vop2_win_dither_up(u32 format)
 464 {
 465         switch (format) {
 466         case DRM_FORMAT_BGR565:
 467         case DRM_FORMAT_RGB565:
 468                 return true;
 469         default:
 470                 return false;
 471         }
 472 }
 473
 474 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode)
 475 {
 476         /*
 477          * FIXME:
 478          *
 479          * There is no media type for YUV444 output,
 480          * so when out_mode is AAAA or P888, assume output is YUV444 on
 481          * yuv format.
 482          *
 483          * From H/W testing, YUV444 mode need a rb swap.
 484          */
 485         if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
 486             bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
 487             bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
 488             bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
 489             ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
 490               bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
 491              (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
 492               output_mode == ROCKCHIP_OUT_MODE_P888)))
 493                 return true;
 494         else
 495                 return false;
 496 }
 497
 498 static bool vop2_output_rg_swap(struct vop2 *vop2, u32 bus_format)
 499 {
 500         if (vop2->data->soc_id == 3588) {
 501                 if (bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
 502                     bus_format == MEDIA_BUS_FMT_YUV10_1X30)
 503                         return true;
 504         }
 505
 506         return false;
 507 }
 508
 509 static bool is_yuv_output(u32 bus_format)
 510 {
 511         switch (bus_format) {
 512         case MEDIA_BUS_FMT_YUV8_1X24:
 513         case MEDIA_BUS_FMT_YUV10_1X30:
 514         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 515         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 516         case MEDIA_BUS_FMT_YUYV8_2X8:
 517         case MEDIA_BUS_FMT_YVYU8_2X8:
 518         case MEDIA_BUS_FMT_UYVY8_2X8:
 519         case MEDIA_BUS_FMT_VYUY8_2X8:
 520         case MEDIA_BUS_FMT_YUYV8_1X16:
 521         case MEDIA_BUS_FMT_YVYU8_1X16:
 522         case MEDIA_BUS_FMT_UYVY8_1X16:
 523         case MEDIA_BUS_FMT_VYUY8_1X16:
 524                 return true;
 525         default:
 526                 return false;
 527         }
 528 }
 529
 530 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
 531 {
 532         int i;
 533
 534         if (modifier == DRM_FORMAT_MOD_LINEAR)
 535                 return false;
 536
 537         for (i = 0 ; i < plane->modifier_count; i++)
 538                 if (plane->modifiers[i] == modifier)
 539                         return true;
 540
 541         return false;
 542 }
 543
 544 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format,
 545                                         u64 modifier)
 546 {
 547         struct vop2_win *win = to_vop2_win(plane);
 548         struct vop2 *vop2 = win->vop2;
 549
 550         if (modifier == DRM_FORMAT_MOD_INVALID)
 551                 return false;
 552
 553         if (modifier == DRM_FORMAT_MOD_LINEAR)
 554                 return true;
 555
 556         if (!rockchip_afbc(plane, modifier)) {
 557                 drm_dbg_kms(vop2->drm, "Unsupported format modifier 0x%llx\n",
 558                             modifier);
 559
 560                 return false;
 561         }
 562
 563         return vop2_convert_afbc_format(format) >= 0;
 564 }
 565
 566 /*
 567  * 0: Full mode, 16 lines for one tail
 568  * 1: half block mode, 8 lines one tail
 569  */
 570 static bool vop2_half_block_enable(struct drm_plane_state *pstate)
 571 {
 572         if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90))
 573                 return false;
 574         else
 575                 return true;
 576 }
 577
 578 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate,
 579                                       bool afbc_half_block_en)
 580 {
 581         struct drm_rect *src = &pstate->src;
 582         struct drm_framebuffer *fb = pstate->fb;
 583         u32 bpp = vop2_get_bpp(fb->format);
 584         u32 vir_width = (fb->pitches[0] << 3) / bpp;
 585         u32 width = drm_rect_width(src) >> 16;
 586         u32 height = drm_rect_height(src) >> 16;
 587         u32 act_xoffset = src->x1 >> 16;
 588         u32 act_yoffset = src->y1 >> 16;
 589         u32 align16_crop = 0;
 590         u32 align64_crop = 0;
 591         u32 height_tmp;
 592         u8 tx, ty;
 593         u8 bottom_crop_line_num = 0;
 594
 595         /* 16 pixel align */
 596         if (height & 0xf)
 597                 align16_crop = 16 - (height & 0xf);
 598
 599         height_tmp = height + align16_crop;
 600
 601         /* 64 pixel align */
 602         if (height_tmp & 0x3f)
 603                 align64_crop = 64 - (height_tmp & 0x3f);
 604
 605         bottom_crop_line_num = align16_crop + align64_crop;
 606
 607         switch (pstate->rotation &
 608                 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y |
 609                  DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) {
 610         case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
 611                 tx = 16 - ((act_xoffset + width) & 0xf);
 612                 ty = bottom_crop_line_num - act_yoffset;
 613                 break;
 614         case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90:
 615                 tx = bottom_crop_line_num - act_yoffset;
 616                 ty = vir_width - width - act_xoffset;
 617                 break;
 618         case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270:
 619                 tx = act_yoffset;
 620                 ty = act_xoffset;
 621                 break;
 622         case DRM_MODE_REFLECT_X:
 623                 tx = 16 - ((act_xoffset + width) & 0xf);
 624                 ty = act_yoffset;
 625                 break;
 626         case DRM_MODE_REFLECT_Y:
 627                 tx = act_xoffset;
 628                 ty = bottom_crop_line_num - act_yoffset;
 629                 break;
 630         case DRM_MODE_ROTATE_90:
 631                 tx = bottom_crop_line_num - act_yoffset;
 632                 ty = act_xoffset;
 633                 break;
 634         case DRM_MODE_ROTATE_270:
 635                 tx = act_yoffset;
 636                 ty = vir_width - width - act_xoffset;
 637                 break;
 638         case 0:
 639                 tx = act_xoffset;
 640                 ty = act_yoffset;
 641                 break;
 642         }
 643
 644         if (afbc_half_block_en)
 645                 ty &= 0x7f;
 646
 647 #define TRANSFORM_XOFFSET GENMASK(7, 0)
 648 #define TRANSFORM_YOFFSET GENMASK(23, 16)
 649         return FIELD_PREP(TRANSFORM_XOFFSET, tx) |
 650                 FIELD_PREP(TRANSFORM_YOFFSET, ty);
 651 }
 652
 653 /*
 654  * A Cluster window has 2048 x 16 line buffer, which can
 655  * works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
 656  * for Cluster_lb_mode register:
 657  * 0: half mode, for plane input width range 2048 ~ 4096
 658  * 1: half mode, for cluster work at 2 * 2048 plane mode
 659  * 2: half mode, for rotate_90/270 mode
 660  *
 661  */
 662 static int vop2_get_cluster_lb_mode(struct vop2_win *win,
 663                                     struct drm_plane_state *pstate)
 664 {
 665         if ((pstate->rotation & DRM_MODE_ROTATE_270) ||
 666             (pstate->rotation & DRM_MODE_ROTATE_90))
 667                 return 2;
 668         else
 669                 return 0;
 670 }
 671
 672 static u16 vop2_scale_factor(u32 src, u32 dst)
 673 {
 674         u32 fac;
 675         int shift;
 676
 677         if (src == dst)
 678                 return 0;
 679
 680         if (dst < 2)
 681                 return U16_MAX;
 682
 683         if (src < 2)
 684                 return 0;
 685
 686         if (src > dst)
 687                 shift = 12;
 688         else
 689                 shift = 16;
 690
 691         src--;
 692         dst--;
 693
 694         fac = DIV_ROUND_UP(src << shift, dst) - 1;
 695
 696         if (fac > U16_MAX)
 697                 return U16_MAX;
 698
 699         return fac;
 700 }
 701
 702 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
 703                              u32 src_w, u32 src_h, u32 dst_w,
 704                              u32 dst_h, u32 pixel_format)
 705 {
 706         const struct drm_format_info *info;
 707         u16 hor_scl_mode, ver_scl_mode;
 708         u16 hscl_filter_mode, vscl_filter_mode;
 709         u8 gt2 = 0;
 710         u8 gt4 = 0;
 711         u32 val;
 712
 713         info = drm_format_info(pixel_format);
 714
 715         if (src_h >= (4 * dst_h)) {
 716                 gt4 = 1;
 717                 src_h >>= 2;
 718         } else if (src_h >= (2 * dst_h)) {
 719                 gt2 = 1;
 720                 src_h >>= 1;
 721         }
 722
 723         hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 724         ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 725
 726         if (hor_scl_mode == SCALE_UP)
 727                 hscl_filter_mode = VOP2_SCALE_UP_BIC;
 728         else
 729                 hscl_filter_mode = VOP2_SCALE_DOWN_BIL;
 730
 731         if (ver_scl_mode == SCALE_UP)
 732                 vscl_filter_mode = VOP2_SCALE_UP_BIL;
 733         else
 734                 vscl_filter_mode = VOP2_SCALE_DOWN_BIL;
 735
 736         /*
 737          * RK3568 VOP Esmart/Smart dsp_w should be even pixel
 738          * at scale down mode
 739          */
 740         if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
 741                 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
 742                         drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
 743                                 win->data->name, dst_w);
 744                         dst_w++;
 745                 }
 746         }
 747
 748         val = vop2_scale_factor(src_w, dst_w);
 749         vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val);
 750         val = vop2_scale_factor(src_h, dst_h);
 751         vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val);
 752
 753         vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4);
 754         vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2);
 755
 756         vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode);
 757         vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode);
 758
 759         if (vop2_cluster_window(win))
 760                 return;
 761
 762         vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode);
 763         vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
 764
 765         if (info->is_yuv) {
 766                 src_w /= info->hsub;
 767                 src_h /= info->vsub;
 768
 769                 gt4 = 0;
 770                 gt2 = 0;
 771
 772                 if (src_h >= (4 * dst_h)) {
 773                         gt4 = 1;
 774                         src_h >>= 2;
 775                 } else if (src_h >= (2 * dst_h)) {
 776                         gt2 = 1;
 777                         src_h >>= 1;
 778                 }
 779
 780                 hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 781                 ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 782
 783                 val = vop2_scale_factor(src_w, dst_w);
 784                 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
 785
 786                 val = vop2_scale_factor(src_h, dst_h);
 787                 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
 788
 789                 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
 790                 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2);
 791                 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode);
 792                 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode);
 793                 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode);
 794                 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode);
 795         }
 796 }
 797
 798 static int vop2_convert_csc_mode(int csc_mode)
 799 {
 800         switch (csc_mode) {
 801         case V4L2_COLORSPACE_SMPTE170M:
 802         case V4L2_COLORSPACE_470_SYSTEM_M:
 803         case V4L2_COLORSPACE_470_SYSTEM_BG:
 804                 return CSC_BT601L;
 805         case V4L2_COLORSPACE_REC709:
 806         case V4L2_COLORSPACE_SMPTE240M:
 807         case V4L2_COLORSPACE_DEFAULT:
 808                 return CSC_BT709L;
 809         case V4L2_COLORSPACE_JPEG:
 810                 return CSC_BT601F;
 811         case V4L2_COLORSPACE_BT2020:
 812                 return CSC_BT2020;
 813         default:
 814                 return CSC_BT709L;
 815         }
 816 }
 817
 818 /*
 819  * colorspace path:
 820  *      Input        Win csc                     Output
 821  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 822  *    RGB        --> R2Y                  __/
 823  *
 824  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 825  *    RGB        --> 709To2020->R2Y       __/
 826  *
 827  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 828  *    RGB        --> R2Y                  __/
 829  *
 830  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 831  *    RGB        --> 709To2020->R2Y       __/
 832  *
 833  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 834  *    RGB        --> R2Y                  __/
 835  *
 836  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 837  *    RGB        --> R2Y(601)             __/
 838  *
 839  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 840  *    RGB        --> bypass               __/
 841  *
 842  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 843  *
 844  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 845  *
 846  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 847  *
 848  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 849  */
 850
 851 static void vop2_setup_csc_mode(struct vop2_video_port *vp,
 852                                 struct vop2_win *win,
 853                                 struct drm_plane_state *pstate)
 854 {
 855         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
 856         int is_input_yuv = pstate->fb->format->is_yuv;
 857         int is_output_yuv = is_yuv_output(vcstate->bus_format);
 858         int input_csc = V4L2_COLORSPACE_DEFAULT;
 859         int output_csc = vcstate->color_space;
 860         bool r2y_en, y2r_en;
 861         int csc_mode;
 862
 863         if (is_input_yuv && !is_output_yuv) {
 864                 y2r_en = true;
 865                 r2y_en = false;
 866                 csc_mode = vop2_convert_csc_mode(input_csc);
 867         } else if (!is_input_yuv && is_output_yuv) {
 868                 y2r_en = false;
 869                 r2y_en = true;
 870                 csc_mode = vop2_convert_csc_mode(output_csc);
 871         } else {
 872                 y2r_en = false;
 873                 r2y_en = false;
 874                 csc_mode = false;
 875         }
 876
 877         vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en);
 878         vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en);
 879         vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode);
 880 }
 881
 882 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq)
 883 {
 884         struct vop2 *vop2 = vp->vop2;
 885
 886         vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
 887         vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
 888 }
 889
 890 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq)
 891 {
 892         struct vop2 *vop2 = vp->vop2;
 893
 894         vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
 895 }
 896
 897 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
 898 {
 899         int ret;
 900
 901         ret = clk_prepare_enable(vop2->hclk);
 902         if (ret < 0) {
 903                 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
 904                 return ret;
 905         }
 906
 907         ret = clk_prepare_enable(vop2->aclk);
 908         if (ret < 0) {
 909                 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
 910                 goto err;
 911         }
 912
 913         ret = clk_prepare_enable(vop2->pclk);
 914         if (ret < 0) {
 915                 drm_err(vop2->drm, "failed to enable pclk - %d\n", ret);
 916                 goto err1;
 917         }
 918
 919         return 0;
 920 err1:
 921         clk_disable_unprepare(vop2->aclk);
 922 err:
 923         clk_disable_unprepare(vop2->hclk);
 924
 925         return ret;
 926 }
 927
 928 static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2)
 929 {
 930         u32 pd;
 931
 932         pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL);
 933         pd &= ~(VOP2_PD_CLUSTER0 | VOP2_PD_CLUSTER1 | VOP2_PD_CLUSTER2 |
 934                 VOP2_PD_CLUSTER3 | VOP2_PD_ESMART);
 935
 936         vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd);
 937 }
 938
 939 static void vop2_enable(struct vop2 *vop2)
 940 {
 941         int ret;
 942
 943         ret = pm_runtime_resume_and_get(vop2->dev);
 944         if (ret < 0) {
 945                 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
 946                 return;
 947         }
 948
 949         ret = vop2_core_clks_prepare_enable(vop2);
 950         if (ret) {
 951                 pm_runtime_put_sync(vop2->dev);
 952                 return;
 953         }
 954
 955         ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
 956         if (ret) {
 957                 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
 958                 return;
 959         }
 960
 961         if (vop2->data->soc_id == 3566)
 962                 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
 963
 964         if (vop2->data->soc_id == 3588)
 965                 rk3588_vop2_power_domain_enable_all(vop2);
 966
 967         vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
 968
 969         /*
 970          * Disable auto gating, this is a workaround to
 971          * avoid display image shift when a window enabled.
 972          */
 973         regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
 974                           RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN);
 975
 976         vop2_writel(vop2, RK3568_SYS0_INT_CLR,
 977                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
 978         vop2_writel(vop2, RK3568_SYS0_INT_EN,
 979                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
 980         vop2_writel(vop2, RK3568_SYS1_INT_CLR,
 981                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
 982         vop2_writel(vop2, RK3568_SYS1_INT_EN,
 983                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
 984 }
 985
 986 static void vop2_disable(struct vop2 *vop2)
 987 {
 988         rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
 989
 990         pm_runtime_put_sync(vop2->dev);
 991
 992         regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register);
 993
 994         clk_disable_unprepare(vop2->pclk);
 995         clk_disable_unprepare(vop2->aclk);
 996         clk_disable_unprepare(vop2->hclk);
 997 }
 998
 999 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
1000                                      struct drm_atomic_state *state)
1001 {
1002         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1003         struct vop2 *vop2 = vp->vop2;
1004         struct drm_crtc_state *old_crtc_state;
1005         int ret;
1006
1007         vop2_lock(vop2);
1008
1009         old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1010         drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1011
1012         drm_crtc_vblank_off(crtc);
1013
1014         /*
1015          * Vop standby will take effect at end of current frame,
1016          * if dsp hold valid irq happen, it means standby complete.
1017          *
1018          * we must wait standby complete when we want to disable aclk,
1019          * if not, memory bus maybe dead.
1020          */
1021         reinit_completion(&vp->dsp_hold_completion);
1022
1023         vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID);
1024
1025         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY);
1026
1027         ret = wait_for_completion_timeout(&vp->dsp_hold_completion,
1028                                           msecs_to_jiffies(50));
1029         if (!ret)
1030                 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
1031
1032         vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
1033
1034         clk_disable_unprepare(vp->dclk);
1035
1036         vop2->enable_count--;
1037
1038         if (!vop2->enable_count)
1039                 vop2_disable(vop2);
1040
1041         vop2_unlock(vop2);
1042
1043         if (crtc->state->event && !crtc->state->active) {
1044                 spin_lock_irq(&crtc->dev->event_lock);
1045                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1046                 spin_unlock_irq(&crtc->dev->event_lock);
1047
1048                 crtc->state->event = NULL;
1049         }
1050 }
1051
1052 static int vop2_plane_atomic_check(struct drm_plane *plane,
1053                                    struct drm_atomic_state *astate)
1054 {
1055         struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane);
1056         struct drm_framebuffer *fb = pstate->fb;
1057         struct drm_crtc *crtc = pstate->crtc;
1058         struct drm_crtc_state *cstate;
1059         struct vop2_video_port *vp;
1060         struct vop2 *vop2;
1061         const struct vop2_data *vop2_data;
1062         struct drm_rect *dest = &pstate->dst;
1063         struct drm_rect *src = &pstate->src;
1064         int min_scale = FRAC_16_16(1, 8);
1065         int max_scale = FRAC_16_16(8, 1);
1066         int format;
1067         int ret;
1068
1069         if (!crtc)
1070                 return 0;
1071
1072         vp = to_vop2_video_port(crtc);
1073         vop2 = vp->vop2;
1074         vop2_data = vop2->data;
1075
1076         cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc);
1077         if (WARN_ON(!cstate))
1078                 return -EINVAL;
1079
1080         ret = drm_atomic_helper_check_plane_state(pstate, cstate,
1081                                                   min_scale, max_scale,
1082                                                   true, true);
1083         if (ret)
1084                 return ret;
1085
1086         if (!pstate->visible)
1087                 return 0;
1088
1089         format = vop2_convert_format(fb->format->format);
1090         if (format < 0)
1091                 return format;
1092
1093         if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 ||
1094             drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) {
1095                 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
1096                         drm_rect_width(src) >> 16, drm_rect_height(src) >> 16,
1097                         drm_rect_width(dest), drm_rect_height(dest));
1098                 pstate->visible = false;
1099                 return 0;
1100         }
1101
1102         if (drm_rect_width(src) >> 16 > vop2_data->max_input.width ||
1103             drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
1104                 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
1105                         drm_rect_width(src) >> 16,
1106                         drm_rect_height(src) >> 16,
1107                         vop2_data->max_input.width,
1108                         vop2_data->max_input.height);
1109                 return -EINVAL;
1110         }
1111
1112         /*
1113          * Src.x1 can be odd when do clip, but yuv plane start point
1114          * need align with 2 pixel.
1115          */
1116         if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) {
1117                 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
1118                 return -EINVAL;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static void vop2_plane_atomic_disable(struct drm_plane *plane,
1125                                       struct drm_atomic_state *state)
1126 {
1127         struct drm_plane_state *old_pstate = NULL;
1128         struct vop2_win *win = to_vop2_win(plane);
1129         struct vop2 *vop2 = win->vop2;
1130
1131         drm_dbg(vop2->drm, "%s disable\n", win->data->name);
1132
1133         if (state)
1134                 old_pstate = drm_atomic_get_old_plane_state(state, plane);
1135         if (old_pstate && !old_pstate->crtc)
1136                 return;
1137
1138         vop2_win_disable(win);
1139         vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0);
1140 }
1141
1142 /*
1143  * The color key is 10 bit, so all format should
1144  * convert to 10 bit here.
1145  */
1146 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key)
1147 {
1148         struct drm_plane_state *pstate = plane->state;
1149         struct drm_framebuffer *fb = pstate->fb;
1150         struct vop2_win *win = to_vop2_win(plane);
1151         u32 color_key_en = 0;
1152         u32 r = 0;
1153         u32 g = 0;
1154         u32 b = 0;
1155
1156         if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) {
1157                 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0);
1158                 return;
1159         }
1160
1161         switch (fb->format->format) {
1162         case DRM_FORMAT_RGB565:
1163         case DRM_FORMAT_BGR565:
1164                 r = (color_key & 0xf800) >> 11;
1165                 g = (color_key & 0x7e0) >> 5;
1166                 b = (color_key & 0x1f);
1167                 r <<= 5;
1168                 g <<= 4;
1169                 b <<= 5;
1170                 color_key_en = 1;
1171                 break;
1172         case DRM_FORMAT_XRGB8888:
1173         case DRM_FORMAT_ARGB8888:
1174         case DRM_FORMAT_XBGR8888:
1175         case DRM_FORMAT_ABGR8888:
1176         case DRM_FORMAT_RGB888:
1177         case DRM_FORMAT_BGR888:
1178                 r = (color_key & 0xff0000) >> 16;
1179                 g = (color_key & 0xff00) >> 8;
1180                 b = (color_key & 0xff);
1181                 r <<= 2;
1182                 g <<= 2;
1183                 b <<= 2;
1184                 color_key_en = 1;
1185                 break;
1186         }
1187
1188         vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en);
1189         vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b);
1190 }
1191
1192 static void vop2_plane_atomic_update(struct drm_plane *plane,
1193                                      struct drm_atomic_state *state)
1194 {
1195         struct drm_plane_state *pstate = plane->state;
1196         struct drm_crtc *crtc = pstate->crtc;
1197         struct vop2_win *win = to_vop2_win(plane);
1198         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1199         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1200         struct vop2 *vop2 = win->vop2;
1201         struct drm_framebuffer *fb = pstate->fb;
1202         u32 bpp = vop2_get_bpp(fb->format);
1203         u32 actual_w, actual_h, dsp_w, dsp_h;
1204         u32 act_info, dsp_info;
1205         u32 format;
1206         u32 afbc_format;
1207         u32 rb_swap;
1208         u32 uv_swap;
1209         struct drm_rect *src = &pstate->src;
1210         struct drm_rect *dest = &pstate->dst;
1211         u32 afbc_tile_num;
1212         u32 transform_offset;
1213         bool dither_up;
1214         bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false;
1215         bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false;
1216         bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270;
1217         bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90;
1218         struct rockchip_gem_object *rk_obj;
1219         unsigned long offset;
1220         bool half_block_en;
1221         bool afbc_en;
1222         dma_addr_t yrgb_mst;
1223         dma_addr_t uv_mst;
1224
1225         /*
1226          * can't update plane when vop2 is disabled.
1227          */
1228         if (WARN_ON(!crtc))
1229                 return;
1230
1231         if (!pstate->visible) {
1232                 vop2_plane_atomic_disable(plane, state);
1233                 return;
1234         }
1235
1236         afbc_en = rockchip_afbc(plane, fb->modifier);
1237
1238         offset = (src->x1 >> 16) * fb->format->cpp[0];
1239
1240         /*
1241          * AFBC HDR_PTR must set to the zero offset of the framebuffer.
1242          */
1243         if (afbc_en)
1244                 offset = 0;
1245         else if (pstate->rotation & DRM_MODE_REFLECT_Y)
1246                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1247         else
1248                 offset += (src->y1 >> 16) * fb->pitches[0];
1249
1250         rk_obj = to_rockchip_obj(fb->obj[0]);
1251
1252         yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
1253         if (fb->format->is_yuv) {
1254                 int hsub = fb->format->hsub;
1255                 int vsub = fb->format->vsub;
1256
1257                 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub;
1258                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1259
1260                 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en)
1261                         offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub;
1262
1263                 rk_obj = to_rockchip_obj(fb->obj[0]);
1264                 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1];
1265         }
1266
1267         actual_w = drm_rect_width(src) >> 16;
1268         actual_h = drm_rect_height(src) >> 16;
1269         dsp_w = drm_rect_width(dest);
1270
1271         if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
1272                 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
1273                         vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
1274                 dsp_w = adjusted_mode->hdisplay - dest->x1;
1275                 if (dsp_w < 4)
1276                         dsp_w = 4;
1277                 actual_w = dsp_w * actual_w / drm_rect_width(dest);
1278         }
1279
1280         dsp_h = drm_rect_height(dest);
1281
1282         if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
1283                 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
1284                         vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
1285                 dsp_h = adjusted_mode->vdisplay - dest->y1;
1286                 if (dsp_h < 4)
1287                         dsp_h = 4;
1288                 actual_h = dsp_h * actual_h / drm_rect_height(dest);
1289         }
1290
1291         /*
1292          * This is workaround solution for IC design:
1293          * esmart can't support scale down when actual_w % 16 == 1.
1294          */
1295         if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
1296                 if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
1297                         drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n",
1298                                 vp->id, win->data->name, actual_w);
1299                         actual_w -= 1;
1300                 }
1301         }
1302
1303         if (afbc_en && actual_w % 4) {
1304                 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n",
1305                         vp->id, win->data->name, actual_w);
1306                 actual_w = ALIGN_DOWN(actual_w, 4);
1307         }
1308
1309         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1310         dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff);
1311
1312         format = vop2_convert_format(fb->format->format);
1313         half_block_en = vop2_half_block_enable(pstate);
1314
1315         drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",
1316                 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h,
1317                 dest->x1, dest->y1,
1318                 &fb->format->format,
1319                 afbc_en ? "AFBC" : "", &yrgb_mst);
1320
1321         if (vop2_cluster_window(win))
1322                 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, half_block_en);
1323
1324         if (afbc_en) {
1325                 u32 stride;
1326
1327                 /* the afbc superblock is 16 x 16 */
1328                 afbc_format = vop2_convert_afbc_format(fb->format->format);
1329
1330                 /* Enable color transform for YTR */
1331                 if (fb->modifier & AFBC_FORMAT_MOD_YTR)
1332                         afbc_format |= (1 << 4);
1333
1334                 afbc_tile_num = ALIGN(actual_w, 16) >> 4;
1335
1336                 /*
1337                  * AFBC pic_vir_width is count by pixel, this is different
1338                  * with WIN_VIR_STRIDE.
1339                  */
1340                 stride = (fb->pitches[0] << 3) / bpp;
1341                 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270))
1342                         drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
1343                                 vp->id, win->data->name, stride);
1344
1345                 uv_swap = vop2_afbc_uv_swap(fb->format->format);
1346                 /*
1347                  * This is a workaround for crazy IC design, Cluster
1348                  * and Esmart/Smart use different format configuration map:
1349                  * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
1350                  *
1351                  * This is one thing we can make the convert simple:
1352                  * AFBCD decode all the YUV data to YUV444. So we just
1353                  * set all the yuv 10 bit to YUV444_10.
1354                  */
1355                 if (fb->format->is_yuv && bpp == 10)
1356                         format = VOP2_CLUSTER_YUV444_10;
1357
1358                 if (vop2_cluster_window(win))
1359                         vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1);
1360                 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format);
1361                 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap);
1362                 /*
1363                  * On rk3566/8, this bit is auto gating enable,
1364                  * but this function is not work well so we need
1365                  * to disable it for these two platform.
1366                  * On rk3588, and the following new soc(rk3528/rk3576),
1367                  * this bit is gating disable, we should write 1 to
1368                  * disable gating when enable afbc.
1369                  */
1370                 if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568)
1371                         vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0);
1372                 else
1373                         vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 1);
1374
1375                 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0);
1376                 transform_offset = vop2_afbc_transform_offset(pstate, half_block_en);
1377                 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst);
1378                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info);
1379                 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset);
1380                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1));
1381                 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16)));
1382                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride);
1383                 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num);
1384                 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror);
1385                 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270);
1386                 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90);
1387         } else {
1388                 if (vop2_cluster_window(win)) {
1389                         vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0);
1390                         vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, 0);
1391                 }
1392
1393                 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4));
1394         }
1395
1396         vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror);
1397
1398         if (rotate_90 || rotate_270) {
1399                 act_info = swahw32(act_info);
1400                 actual_w = drm_rect_height(src) >> 16;
1401                 actual_h = drm_rect_width(src) >> 16;
1402         }
1403
1404         vop2_win_write(win, VOP2_WIN_FORMAT, format);
1405         vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst);
1406
1407         rb_swap = vop2_win_rb_swap(fb->format->format);
1408         vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap);
1409         if (!vop2_cluster_window(win)) {
1410                 uv_swap = vop2_win_uv_swap(fb->format->format);
1411                 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap);
1412         }
1413
1414         if (fb->format->is_yuv) {
1415                 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4));
1416                 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst);
1417         }
1418
1419         vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format);
1420         if (!vop2_cluster_window(win))
1421                 vop2_plane_setup_color_key(plane, 0);
1422         vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info);
1423         vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info);
1424         vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff));
1425
1426         vop2_setup_csc_mode(vp, win, pstate);
1427
1428         dither_up = vop2_win_dither_up(fb->format->format);
1429         vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up);
1430
1431         vop2_win_write(win, VOP2_WIN_ENABLE, 1);
1432
1433         if (vop2_cluster_window(win)) {
1434                 int lb_mode = vop2_get_cluster_lb_mode(win, pstate);
1435
1436                 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode);
1437                 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1);
1438         }
1439 }
1440
1441 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = {
1442         .atomic_check = vop2_plane_atomic_check,
1443         .atomic_update = vop2_plane_atomic_update,
1444         .atomic_disable = vop2_plane_atomic_disable,
1445 };
1446
1447 static const struct drm_plane_funcs vop2_plane_funcs = {
1448         .update_plane   = drm_atomic_helper_update_plane,
1449         .disable_plane  = drm_atomic_helper_disable_plane,
1450         .destroy = drm_plane_cleanup,
1451         .reset = drm_atomic_helper_plane_reset,
1452         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1453         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1454         .format_mod_supported = rockchip_vop2_mod_supported,
1455 };
1456
1457 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc)
1458 {
1459         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1460
1461         vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD);
1462
1463         return 0;
1464 }
1465
1466 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc)
1467 {
1468         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1469
1470         vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD);
1471 }
1472
1473 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
1474                                  const struct drm_display_mode *mode,
1475                                  struct drm_display_mode *adj_mode)
1476 {
1477         drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V |
1478                                         CRTC_STEREO_DOUBLE);
1479
1480         return true;
1481 }
1482
1483 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl)
1484 {
1485         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1486
1487         switch (vcstate->bus_format) {
1488         case MEDIA_BUS_FMT_RGB565_1X16:
1489                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1490                 break;
1491         case MEDIA_BUS_FMT_RGB666_1X18:
1492         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1493         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
1494                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1495                 *dsp_ctrl |= RGB888_TO_RGB666;
1496                 break;
1497         case MEDIA_BUS_FMT_YUV8_1X24:
1498         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1499                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1500                 break;
1501         default:
1502                 break;
1503         }
1504
1505         if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA)
1506                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1507
1508         *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL,
1509                                 DITHER_DOWN_ALLEGRO);
1510 }
1511
1512 static void vop2_post_config(struct drm_crtc *crtc)
1513 {
1514         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1515         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1516         u16 vtotal = mode->crtc_vtotal;
1517         u16 hdisplay = mode->crtc_hdisplay;
1518         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1519         u16 vdisplay = mode->crtc_vdisplay;
1520         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1521         u32 left_margin = 100, right_margin = 100;
1522         u32 top_margin = 100, bottom_margin = 100;
1523         u16 hsize = hdisplay * (left_margin + right_margin) / 200;
1524         u16 vsize = vdisplay * (top_margin + bottom_margin) / 200;
1525         u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1526         u16 hact_end, vact_end;
1527         u32 val;
1528         u32 bg_dly;
1529         u32 pre_scan_dly;
1530
1531         bg_dly = vp->data->pre_scan_max_dly[3];
1532         vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
1533                     FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
1534
1535         pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
1536         vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
1537
1538         vsize = rounddown(vsize, 2);
1539         hsize = rounddown(hsize, 2);
1540         hact_st += hdisplay * (100 - left_margin) / 200;
1541         hact_end = hact_st + hsize;
1542         val = hact_st << 16;
1543         val |= hact_end;
1544         vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val);
1545         vact_st += vdisplay * (100 - top_margin) / 200;
1546         vact_end = vact_st + vsize;
1547         val = vact_st << 16;
1548         val |= vact_end;
1549         vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val);
1550         val = scl_cal_scale2(vdisplay, vsize) << 16;
1551         val |= scl_cal_scale2(hdisplay, hsize);
1552         vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val);
1553
1554         val = 0;
1555         if (hdisplay != hsize)
1556                 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN;
1557         if (vdisplay != vsize)
1558                 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN;
1559         vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val);
1560
1561         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1562                 u16 vact_st_f1 = vtotal + vact_st + 1;
1563                 u16 vact_end_f1 = vact_st_f1 + vsize;
1564
1565                 val = vact_st_f1 << 16 | vact_end_f1;
1566                 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val);
1567         }
1568
1569         vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
1570 }
1571
1572 static unsigned long rk3568_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags)
1573 {
1574         struct vop2 *vop2 = vp->vop2;
1575         struct drm_crtc *crtc = &vp->crtc;
1576         u32 die, dip;
1577
1578         die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1579         dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1580
1581         switch (id) {
1582         case ROCKCHIP_VOP2_EP_RGB0:
1583                 die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX;
1584                 die |= RK3568_SYS_DSP_INFACE_EN_RGB |
1585                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id);
1586                 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1587                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1588                 if (polflags & POLFLAG_DCLK_INV)
1589                         regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1590                 else
1591                         regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1592                 break;
1593         case ROCKCHIP_VOP2_EP_HDMI0:
1594                 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
1595                 die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
1596                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
1597                 dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
1598                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
1599                 break;
1600         case ROCKCHIP_VOP2_EP_EDP0:
1601                 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
1602                 die |= RK3568_SYS_DSP_INFACE_EN_EDP |
1603                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
1604                 dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
1605                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
1606                 break;
1607         case ROCKCHIP_VOP2_EP_MIPI0:
1608                 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;
1609                 die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 |
1610                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id);
1611                 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1612                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1613                 break;
1614         case ROCKCHIP_VOP2_EP_MIPI1:
1615                 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX;
1616                 die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 |
1617                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1618                 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1619                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1620                 break;
1621         case ROCKCHIP_VOP2_EP_LVDS0:
1622                 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX;
1623                 die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 |
1624                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id);
1625                 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1626                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1627                 break;
1628         case ROCKCHIP_VOP2_EP_LVDS1:
1629                 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX;
1630                 die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 |
1631                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id);
1632                 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1633                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1634                 break;
1635         default:
1636                 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1637                 return 0;
1638         }
1639
1640         dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
1641
1642         vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1643         vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1644
1645         return crtc->state->adjusted_mode.crtc_clock  * 1000LL;
1646 }
1647
1648 /*
1649  * calc the dclk on rk3588
1650  * the available div of dclk is 1, 2, 4
1651  */
1652 static unsigned long rk3588_calc_dclk(unsigned long child_clk, unsigned long max_dclk)
1653 {
1654         if (child_clk * 4 <= max_dclk)
1655                 return child_clk * 4;
1656         else if (child_clk * 2 <= max_dclk)
1657                 return child_clk * 2;
1658         else if (child_clk <= max_dclk)
1659                 return child_clk;
1660         else
1661                 return 0;
1662 }
1663
1664 /*
1665  * 4 pixclk/cycle on rk3588
1666  * RGB/eDP/HDMI: if_pixclk >= dclk_core
1667  * DP: dp_pixclk = dclk_out <= dclk_core
1668  * DSI: mipi_pixclk <= dclk_out <= dclk_core
1669  */
1670 static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
1671                                          int *dclk_core_div, int *dclk_out_div,
1672                                          int *if_pixclk_div, int *if_dclk_div)
1673 {
1674         struct vop2 *vop2 = vp->vop2;
1675         struct drm_crtc *crtc = &vp->crtc;
1676         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1677         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1678         int output_mode = vcstate->output_mode;
1679         unsigned long v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
1680         unsigned long dclk_core_rate = v_pixclk >> 2;
1681         unsigned long dclk_rate = v_pixclk;
1682         unsigned long dclk_out_rate;
1683         unsigned long if_pixclk_rate;
1684         int K = 1;
1685
1686         if (vop2_output_if_is_hdmi(id)) {
1687                 /*
1688                  * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate
1689                  * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate
1690                  */
1691                 if (output_mode == ROCKCHIP_OUT_MODE_YUV420) {
1692                         dclk_rate = dclk_rate >> 1;
1693                         K = 2;
1694                 }
1695
1696                 if_pixclk_rate = (dclk_core_rate << 1) / K;
1697                 /*
1698                  * if_dclk_rate = dclk_core_rate / K;
1699                  * *if_pixclk_div = dclk_rate / if_pixclk_rate;
1700                  * *if_dclk_div = dclk_rate / if_dclk_rate;
1701                  */
1702                 *if_pixclk_div = 2;
1703                 *if_dclk_div = 4;
1704         } else if (vop2_output_if_is_edp(id)) {
1705                 /*
1706                  * edp_pixclk = edp_dclk > dclk_core
1707                  */
1708                 if_pixclk_rate = v_pixclk / K;
1709                 dclk_rate = if_pixclk_rate * K;
1710                 /*
1711                  * *if_pixclk_div = dclk_rate / if_pixclk_rate;
1712                  * *if_dclk_div = *if_pixclk_div;
1713                  */
1714                 *if_pixclk_div = K;
1715                 *if_dclk_div = K;
1716         } else if (vop2_output_if_is_dp(id)) {
1717                 if (output_mode == ROCKCHIP_OUT_MODE_YUV420)
1718                         dclk_out_rate = v_pixclk >> 3;
1719                 else
1720                         dclk_out_rate = v_pixclk >> 2;
1721
1722                 dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
1723                 if (!dclk_rate) {
1724                         drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n",
1725                                 dclk_out_rate);
1726                         return 0;
1727                 }
1728                 *dclk_out_div = dclk_rate / dclk_out_rate;
1729         } else if (vop2_output_if_is_mipi(id)) {
1730                 if_pixclk_rate = dclk_core_rate / K;
1731                 /*
1732                  * dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4
1733                  */
1734                 dclk_out_rate = if_pixclk_rate;
1735                 /*
1736                  * dclk_rate = N * dclk_core_rate N = (1,2,4 ),
1737                  * we get a little factor here
1738                  */
1739                 dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
1740                 if (!dclk_rate) {
1741                         drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n",
1742                                 dclk_out_rate);
1743                         return 0;
1744                 }
1745                 *dclk_out_div = dclk_rate / dclk_out_rate;
1746                 /*
1747                  * mipi pixclk == dclk_out
1748                  */
1749                 *if_pixclk_div = 1;
1750         } else if (vop2_output_if_is_dpi(id)) {
1751                 dclk_rate = v_pixclk;
1752         }
1753
1754         *dclk_core_div = dclk_rate / dclk_core_rate;
1755         *if_pixclk_div = ilog2(*if_pixclk_div);
1756         *if_dclk_div = ilog2(*if_dclk_div);
1757         *dclk_core_div = ilog2(*dclk_core_div);
1758         *dclk_out_div = ilog2(*dclk_out_div);
1759
1760         drm_dbg(vop2->drm, "dclk: %ld, pixclk_div: %d, dclk_div: %d\n",
1761                 dclk_rate, *if_pixclk_div, *if_dclk_div);
1762
1763         return dclk_rate;
1764 }
1765
1766 /*
1767  * MIPI port mux on rk3588:
1768  * 0: Video Port2
1769  * 1: Video Port3
1770  * 3: Video Port 1(MIPI1 only)
1771  */
1772 static u32 rk3588_get_mipi_port_mux(int vp_id)
1773 {
1774         if (vp_id == 1)
1775                 return 3;
1776         else if (vp_id == 3)
1777                 return 1;
1778         else
1779                 return 0;
1780 }
1781
1782 static u32 rk3588_get_hdmi_pol(u32 flags)
1783 {
1784         u32 val;
1785
1786         val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0;
1787         val |= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0;
1788
1789         return val;
1790 }
1791
1792 static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags)
1793 {
1794         struct vop2 *vop2 = vp->vop2;
1795         int dclk_core_div, dclk_out_div, if_pixclk_div, if_dclk_div;
1796         unsigned long clock;
1797         u32 die, dip, div, vp_clk_div, val;
1798
1799         clock = rk3588_calc_cru_cfg(vp, id, &dclk_core_div, &dclk_out_div,
1800                                     &if_pixclk_div, &if_dclk_div);
1801         if (!clock)
1802                 return 0;
1803
1804         vp_clk_div = FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_CORE_DIV, dclk_core_div);
1805         vp_clk_div |= FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_OUT_DIV, dclk_out_div);
1806
1807         die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1808         dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1809         div = vop2_readl(vop2, RK3568_DSP_IF_CTRL);
1810
1811         switch (id) {
1812         case ROCKCHIP_VOP2_EP_HDMI0:
1813                 div &= ~RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV;
1814                 div &= ~RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV;
1815                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div);
1816                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div);
1817                 die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX;
1818                 die |= RK3588_SYS_DSP_INFACE_EN_HDMI0 |
1819                             FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id);
1820                 val = rk3588_get_hdmi_pol(polflags);
1821                 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1));
1822                 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5));
1823                 break;
1824         case ROCKCHIP_VOP2_EP_HDMI1:
1825                 div &= ~RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV;
1826                 div &= ~RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV;
1827                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV, if_dclk_div);
1828                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV, if_pixclk_div);
1829                 die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX;
1830                 die |= RK3588_SYS_DSP_INFACE_EN_HDMI1 |
1831                             FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id);
1832                 val = rk3588_get_hdmi_pol(polflags);
1833                 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 4, 4));
1834                 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 8, 7));
1835                 break;
1836         case ROCKCHIP_VOP2_EP_EDP0:
1837                 div &= ~RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV;
1838                 div &= ~RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV;
1839                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div);
1840                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div);
1841                 die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX;
1842                 die |= RK3588_SYS_DSP_INFACE_EN_EDP0 |
1843                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id);
1844                 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 0, 0));
1845                 break;
1846         case ROCKCHIP_VOP2_EP_EDP1:
1847                 div &= ~RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV;
1848                 div &= ~RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV;
1849                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div);
1850                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div);
1851                 die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX;
1852                 die |= RK3588_SYS_DSP_INFACE_EN_EDP1 |
1853                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id);
1854                 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 3, 3));
1855                 break;
1856         case ROCKCHIP_VOP2_EP_MIPI0:
1857                 div &= ~RK3588_DSP_IF_MIPI0_PCLK_DIV;
1858                 div |= FIELD_PREP(RK3588_DSP_IF_MIPI0_PCLK_DIV, if_pixclk_div);
1859                 die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX;
1860                 val = rk3588_get_mipi_port_mux(vp->id);
1861                 die |= RK3588_SYS_DSP_INFACE_EN_MIPI0 |
1862                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX, !!val);
1863                 break;
1864         case ROCKCHIP_VOP2_EP_MIPI1:
1865                 div &= ~RK3588_DSP_IF_MIPI1_PCLK_DIV;
1866                 div |= FIELD_PREP(RK3588_DSP_IF_MIPI1_PCLK_DIV, if_pixclk_div);
1867                 die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX;
1868                 val = rk3588_get_mipi_port_mux(vp->id);
1869                 die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 |
1870                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, val);
1871                 break;
1872         case ROCKCHIP_VOP2_EP_DP0:
1873                 die &= ~RK3588_SYS_DSP_INFACE_EN_DP0_MUX;
1874                 die |= RK3588_SYS_DSP_INFACE_EN_DP0 |
1875                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP0_MUX, vp->id);
1876                 dip &= ~RK3588_DSP_IF_POL__DP0_PIN_POL;
1877                 dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP0_PIN_POL, polflags);
1878                 break;
1879         case ROCKCHIP_VOP2_EP_DP1:
1880                 die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX;
1881                 die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 |
1882                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1883                 dip &= ~RK3588_DSP_IF_POL__DP1_PIN_POL;
1884                 dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP1_PIN_POL, polflags);
1885                 break;
1886         default:
1887                 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1888                 return 0;
1889         }
1890
1891         dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
1892
1893         vop2_vp_write(vp, RK3588_VP_CLK_CTRL, vp_clk_div);
1894         vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1895         vop2_writel(vop2, RK3568_DSP_IF_CTRL, div);
1896         vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1897
1898         return clock;
1899 }
1900
1901 static unsigned long vop2_set_intf_mux(struct vop2_video_port *vp, int ep_id, u32 polflags)
1902 {
1903         struct vop2 *vop2 = vp->vop2;
1904
1905         if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568)
1906                 return rk3568_set_intf_mux(vp, ep_id, polflags);
1907         else if (vop2->data->soc_id == 3588)
1908                 return rk3588_set_intf_mux(vp, ep_id, polflags);
1909         else
1910                 return 0;
1911 }
1912
1913 static int us_to_vertical_line(struct drm_display_mode *mode, int us)
1914 {
1915         return us * mode->clock / mode->htotal / 1000;
1916 }
1917
1918 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
1919                                     struct drm_atomic_state *state)
1920 {
1921         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1922         struct vop2 *vop2 = vp->vop2;
1923         const struct vop2_data *vop2_data = vop2->data;
1924         const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
1925         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1926         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1927         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1928         unsigned long clock = mode->crtc_clock * 1000;
1929         u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1930         u16 hdisplay = mode->crtc_hdisplay;
1931         u16 htotal = mode->crtc_htotal;
1932         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1933         u16 hact_end = hact_st + hdisplay;
1934         u16 vdisplay = mode->crtc_vdisplay;
1935         u16 vtotal = mode->crtc_vtotal;
1936         u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
1937         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1938         u16 vact_end = vact_st + vdisplay;
1939         u8 out_mode;
1940         u32 dsp_ctrl = 0;
1941         int act_end;
1942         u32 val, polflags;
1943         int ret;
1944         struct drm_encoder *encoder;
1945
1946         drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
1947                 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
1948                 drm_mode_vrefresh(mode), vcstate->output_type, vp->id);
1949
1950         vop2_lock(vop2);
1951
1952         ret = clk_prepare_enable(vp->dclk);
1953         if (ret < 0) {
1954                 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
1955                         vp->id, ret);
1956                 vop2_unlock(vop2);
1957                 return;
1958         }
1959
1960         if (!vop2->enable_count)
1961                 vop2_enable(vop2);
1962
1963         vop2->enable_count++;
1964
1965         vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);
1966
1967         vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);
1968
1969         polflags = 0;
1970         if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
1971                 polflags |= POLFLAG_DCLK_INV;
1972         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1973                 polflags |= BIT(HSYNC_POSITIVE);
1974         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1975                 polflags |= BIT(VSYNC_POSITIVE);
1976
1977         drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
1978                 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
1979
1980                 /*
1981                  * for drive a high resolution(4KP120, 8K), vop on rk3588/rk3576 need
1982                  * process multi(1/2/4/8) pixels per cycle, so the dclk feed by the
1983                  * system cru may be the 1/2 or 1/4 of mode->clock.
1984                  */
1985                 clock = vop2_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags);
1986         }
1987
1988         if (!clock) {
1989                 vop2_unlock(vop2);
1990                 return;
1991         }
1992
1993         if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1994             !(vp_data->feature & VOP2_VP_FEATURE_OUTPUT_10BIT))
1995                 out_mode = ROCKCHIP_OUT_MODE_P888;
1996         else
1997                 out_mode = vcstate->output_mode;
1998
1999         dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode);
2000
2001         if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
2002                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;
2003         if (vop2_output_rg_swap(vop2, vcstate->bus_format))
2004                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RG_SWAP;
2005
2006         if (vcstate->yuv_overlay)
2007                 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;
2008
2009         vop2_dither_setup(crtc, &dsp_ctrl);
2010
2011         vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len);
2012         val = hact_st << 16;
2013         val |= hact_end;
2014         vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val);
2015
2016         val = vact_st << 16;
2017         val |= vact_end;
2018         vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val);
2019
2020         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2021                 u16 vact_st_f1 = vtotal + vact_st + 1;
2022                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
2023
2024                 val = vact_st_f1 << 16 | vact_end_f1;
2025                 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val);
2026
2027                 val = vtotal << 16 | (vtotal + vsync_len);
2028                 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val);
2029                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE;
2030                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL;
2031                 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN;
2032                 vtotal += vtotal + 1;
2033                 act_end = vact_end_f1;
2034         } else {
2035                 act_end = vact_end;
2036         }
2037
2038         vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
2039                     (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end);
2040
2041         vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
2042
2043         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2044                 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
2045                 clock *= 2;
2046         }
2047
2048         vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
2049
2050         clk_set_rate(vp->dclk, clock);
2051
2052         vop2_post_config(crtc);
2053
2054         vop2_cfg_done(vp);
2055
2056         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
2057
2058         drm_crtc_vblank_on(crtc);
2059
2060         vop2_unlock(vop2);
2061 }
2062
2063 static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
2064                                   struct drm_atomic_state *state)
2065 {
2066         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2067         struct drm_plane *plane;
2068         int nplanes = 0;
2069         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
2070
2071         drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
2072                 nplanes++;
2073
2074         if (nplanes > vp->nlayers)
2075                 return -EINVAL;
2076
2077         return 0;
2078 }
2079
2080 static bool is_opaque(u16 alpha)
2081 {
2082         return (alpha >> 8) == 0xff;
2083 }
2084
2085 static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config,
2086                              struct vop2_alpha *alpha)
2087 {
2088         int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1;
2089         int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1;
2090         int src_color_mode = alpha_config->src_premulti_en ?
2091                                 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
2092         int dst_color_mode = alpha_config->dst_premulti_en ?
2093                                 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
2094
2095         alpha->src_color_ctrl.val = 0;
2096         alpha->dst_color_ctrl.val = 0;
2097         alpha->src_alpha_ctrl.val = 0;
2098         alpha->dst_alpha_ctrl.val = 0;
2099
2100         if (!alpha_config->src_pixel_alpha_en)
2101                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
2102         else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en)
2103                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX;
2104         else
2105                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
2106
2107         alpha->src_color_ctrl.bits.alpha_en = 1;
2108
2109         if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) {
2110                 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
2111                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
2112         } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) {
2113                 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
2114                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE;
2115         } else {
2116                 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL;
2117                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
2118         }
2119         alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8;
2120         alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
2121         alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
2122
2123         alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
2124         alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
2125         alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
2126         alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8;
2127         alpha->dst_color_ctrl.bits.color_mode = dst_color_mode;
2128         alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
2129
2130         alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
2131         alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode;
2132         alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
2133         alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE;
2134
2135         alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
2136         if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
2137                 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX;
2138         else
2139                 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
2140         alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION;
2141         alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
2142 }
2143
2144 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id)
2145 {
2146         struct vop2_video_port *vp;
2147         int used_layer = 0;
2148         int i;
2149
2150         for (i = 0; i < port_id; i++) {
2151                 vp = &vop2->vps[i];
2152                 used_layer += hweight32(vp->win_mask);
2153         }
2154
2155         return used_layer;
2156 }
2157
2158 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)
2159 {
2160         u32 offset = (main_win->data->phys_id * 0x10);
2161         struct vop2_alpha_config alpha_config;
2162         struct vop2_alpha alpha;
2163         struct drm_plane_state *bottom_win_pstate;
2164         bool src_pixel_alpha_en = false;
2165         u16 src_glb_alpha_val, dst_glb_alpha_val;
2166         bool premulti_en = false;
2167         bool swap = false;
2168
2169         /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
2170         bottom_win_pstate = main_win->base.state;
2171         src_glb_alpha_val = 0;
2172         dst_glb_alpha_val = main_win->base.state->alpha;
2173
2174         if (!bottom_win_pstate->fb)
2175                 return;
2176
2177         alpha_config.src_premulti_en = premulti_en;
2178         alpha_config.dst_premulti_en = false;
2179         alpha_config.src_pixel_alpha_en = src_pixel_alpha_en;
2180         alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
2181         alpha_config.src_glb_alpha_value = src_glb_alpha_val;
2182         alpha_config.dst_glb_alpha_value = dst_glb_alpha_val;
2183         vop2_parse_alpha(&alpha_config, &alpha);
2184
2185         alpha.src_color_ctrl.bits.src_dst_swap = swap;
2186         vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,
2187                     alpha.src_color_ctrl.val);
2188         vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,
2189                     alpha.dst_color_ctrl.val);
2190         vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,
2191                     alpha.src_alpha_ctrl.val);
2192         vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,
2193                     alpha.dst_alpha_ctrl.val);
2194 }
2195
2196 static void vop2_setup_alpha(struct vop2_video_port *vp)
2197 {
2198         struct vop2 *vop2 = vp->vop2;
2199         struct drm_framebuffer *fb;
2200         struct vop2_alpha_config alpha_config;
2201         struct vop2_alpha alpha;
2202         struct drm_plane *plane;
2203         int pixel_alpha_en;
2204         int premulti_en, gpremulti_en = 0;
2205         int mixer_id;
2206         u32 offset;
2207         bool bottom_layer_alpha_en = false;
2208         u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE;
2209
2210         mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
2211         alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
2212
2213         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2214                 struct vop2_win *win = to_vop2_win(plane);
2215
2216                 if (plane->state->normalized_zpos == 0 &&
2217                     !is_opaque(plane->state->alpha) &&
2218                     !vop2_cluster_window(win)) {
2219                         /*
2220                          * If bottom layer have global alpha effect [except cluster layer,
2221                          * because cluster have deal with bottom layer global alpha value
2222                          * at cluster mix], bottom layer mix need deal with global alpha.
2223                          */
2224                         bottom_layer_alpha_en = true;
2225                         dst_global_alpha = plane->state->alpha;
2226                 }
2227         }
2228
2229         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2230                 struct vop2_win *win = to_vop2_win(plane);
2231                 int zpos = plane->state->normalized_zpos;
2232
2233                 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
2234                         premulti_en = 1;
2235                 else
2236                         premulti_en = 0;
2237
2238                 plane = &win->base;
2239                 fb = plane->state->fb;
2240
2241                 pixel_alpha_en = fb->format->has_alpha;
2242
2243                 alpha_config.src_premulti_en = premulti_en;
2244
2245                 if (bottom_layer_alpha_en && zpos == 1) {
2246                         gpremulti_en = premulti_en;
2247                         /* Cd = Cs + (1 - As) * Cd * Agd */
2248                         alpha_config.dst_premulti_en = false;
2249                         alpha_config.src_pixel_alpha_en = pixel_alpha_en;
2250                         alpha_config.src_glb_alpha_value = plane->state->alpha;
2251                         alpha_config.dst_glb_alpha_value = dst_global_alpha;
2252                 } else if (vop2_cluster_window(win)) {
2253                         /* Mix output data only have pixel alpha */
2254                         alpha_config.dst_premulti_en = true;
2255                         alpha_config.src_pixel_alpha_en = true;
2256                         alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2257                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2258                 } else {
2259                         /* Cd = Cs + (1 - As) * Cd */
2260                         alpha_config.dst_premulti_en = true;
2261                         alpha_config.src_pixel_alpha_en = pixel_alpha_en;
2262                         alpha_config.src_glb_alpha_value = plane->state->alpha;
2263                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2264                 }
2265
2266                 vop2_parse_alpha(&alpha_config, &alpha);
2267
2268                 offset = (mixer_id + zpos - 1) * 0x10;
2269                 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,
2270                             alpha.src_color_ctrl.val);
2271                 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,
2272                             alpha.dst_color_ctrl.val);
2273                 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,
2274                             alpha.src_alpha_ctrl.val);
2275                 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,
2276                             alpha.dst_alpha_ctrl.val);
2277         }
2278
2279         if (vp->id == 0) {
2280                 if (bottom_layer_alpha_en) {
2281                         /* Transfer pixel alpha to hdr mix */
2282                         alpha_config.src_premulti_en = gpremulti_en;
2283                         alpha_config.dst_premulti_en = true;
2284                         alpha_config.src_pixel_alpha_en = true;
2285                         alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2286                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2287                         vop2_parse_alpha(&alpha_config, &alpha);
2288
2289                         vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,
2290                                     alpha.src_color_ctrl.val);
2291                         vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,
2292                                     alpha.dst_color_ctrl.val);
2293                         vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,
2294                                     alpha.src_alpha_ctrl.val);
2295                         vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,
2296                                     alpha.dst_alpha_ctrl.val);
2297                 } else {
2298                         vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);
2299                 }
2300         }
2301 }
2302
2303 static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
2304 {
2305         struct vop2 *vop2 = vp->vop2;
2306         struct drm_plane *plane;
2307         u32 layer_sel = 0;
2308         u32 port_sel;
2309         unsigned int nlayer, ofs;
2310         u32 ovl_ctrl;
2311         int i;
2312         struct vop2_video_port *vp0 = &vop2->vps[0];
2313         struct vop2_video_port *vp1 = &vop2->vps[1];
2314         struct vop2_video_port *vp2 = &vop2->vps[2];
2315         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
2316
2317         ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
2318         ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;
2319         if (vcstate->yuv_overlay)
2320                 ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id);
2321         else
2322                 ovl_ctrl &= ~RK3568_OVL_CTRL__YUV_MODE(vp->id);
2323
2324         vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl);
2325
2326         port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
2327         port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT;
2328
2329         if (vp0->nlayers)
2330                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX,
2331                                      vp0->nlayers - 1);
2332         else
2333                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8);
2334
2335         if (vp1->nlayers)
2336                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX,
2337                                      (vp0->nlayers + vp1->nlayers - 1));
2338         else
2339                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
2340
2341         if (vp2->nlayers)
2342                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX,
2343                         (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1));
2344         else
2345                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
2346
2347         layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
2348
2349         ofs = 0;
2350         for (i = 0; i < vp->id; i++)
2351                 ofs += vop2->vps[i].nlayers;
2352
2353         nlayer = 0;
2354         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2355                 struct vop2_win *win = to_vop2_win(plane);
2356
2357                 switch (win->data->phys_id) {
2358                 case ROCKCHIP_VOP2_CLUSTER0:
2359                         port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0;
2360                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id);
2361                         break;
2362                 case ROCKCHIP_VOP2_CLUSTER1:
2363                         port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1;
2364                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id);
2365                         break;
2366                 case ROCKCHIP_VOP2_CLUSTER2:
2367                         port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER2;
2368                         port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER2, vp->id);
2369                         break;
2370                 case ROCKCHIP_VOP2_CLUSTER3:
2371                         port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER3;
2372                         port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER3, vp->id);
2373                         break;
2374                 case ROCKCHIP_VOP2_ESMART0:
2375                         port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0;
2376                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id);
2377                         break;
2378                 case ROCKCHIP_VOP2_ESMART1:
2379                         port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1;
2380                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id);
2381                         break;
2382                 case ROCKCHIP_VOP2_ESMART2:
2383                         port_sel &= ~RK3588_OVL_PORT_SEL__ESMART2;
2384                         port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART2, vp->id);
2385                         break;
2386                 case ROCKCHIP_VOP2_ESMART3:
2387                         port_sel &= ~RK3588_OVL_PORT_SEL__ESMART3;
2388                         port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART3, vp->id);
2389                         break;
2390                 case ROCKCHIP_VOP2_SMART0:
2391                         port_sel &= ~RK3568_OVL_PORT_SEL__SMART0;
2392                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id);
2393                         break;
2394                 case ROCKCHIP_VOP2_SMART1:
2395                         port_sel &= ~RK3568_OVL_PORT_SEL__SMART1;
2396                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id);
2397                         break;
2398                 }
2399
2400                 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs,
2401                                                           0x7);
2402                 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs,
2403                                                          win->data->layer_sel_id);
2404                 nlayer++;
2405         }
2406
2407         /* configure unused layers to 0x5 (reserved) */
2408         for (; nlayer < vp->nlayers; nlayer++) {
2409                 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7);
2410                 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5);
2411         }
2412
2413         vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
2414         vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
2415 }
2416
2417 static void vop2_setup_dly_for_windows(struct vop2 *vop2)
2418 {
2419         struct vop2_win *win;
2420         int i = 0;
2421         u32 cdly = 0, sdly = 0;
2422
2423         for (i = 0; i < vop2->data->win_size; i++) {
2424                 u32 dly;
2425
2426                 win = &vop2->win[i];
2427                 dly = win->delay;
2428
2429                 switch (win->data->phys_id) {
2430                 case ROCKCHIP_VOP2_CLUSTER0:
2431                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly);
2432                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly);
2433                         break;
2434                 case ROCKCHIP_VOP2_CLUSTER1:
2435                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly);
2436                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly);
2437                         break;
2438                 case ROCKCHIP_VOP2_ESMART0:
2439                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly);
2440                         break;
2441                 case ROCKCHIP_VOP2_ESMART1:
2442                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly);
2443                         break;
2444                 case ROCKCHIP_VOP2_SMART0:
2445                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly);
2446                         break;
2447                 case ROCKCHIP_VOP2_SMART1:
2448                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly);
2449                         break;
2450                 }
2451         }
2452
2453         vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);
2454         vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);
2455 }
2456
2457 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc,
2458                                    struct drm_atomic_state *state)
2459 {
2460         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2461         struct vop2 *vop2 = vp->vop2;
2462         struct drm_plane *plane;
2463
2464         vp->win_mask = 0;
2465
2466         drm_atomic_crtc_for_each_plane(plane, crtc) {
2467                 struct vop2_win *win = to_vop2_win(plane);
2468
2469                 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT];
2470
2471                 vp->win_mask |= BIT(win->data->phys_id);
2472
2473                 if (vop2_cluster_window(win))
2474                         vop2_setup_cluster_alpha(vop2, win);
2475         }
2476
2477         if (!vp->win_mask)
2478                 return;
2479
2480         vop2_setup_layer_mixer(vp);
2481         vop2_setup_alpha(vp);
2482         vop2_setup_dly_for_windows(vop2);
2483 }
2484
2485 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
2486                                    struct drm_atomic_state *state)
2487 {
2488         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2489
2490         vop2_post_config(crtc);
2491
2492         vop2_cfg_done(vp);
2493
2494         spin_lock_irq(&crtc->dev->event_lock);
2495
2496         if (crtc->state->event) {
2497                 WARN_ON(drm_crtc_vblank_get(crtc));
2498                 vp->event = crtc->state->event;
2499                 crtc->state->event = NULL;
2500         }
2501
2502         spin_unlock_irq(&crtc->dev->event_lock);
2503 }
2504
2505 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
2506         .mode_fixup = vop2_crtc_mode_fixup,
2507         .atomic_check = vop2_crtc_atomic_check,
2508         .atomic_begin = vop2_crtc_atomic_begin,
2509         .atomic_flush = vop2_crtc_atomic_flush,
2510         .atomic_enable = vop2_crtc_atomic_enable,
2511         .atomic_disable = vop2_crtc_atomic_disable,
2512 };
2513
2514 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
2515 {
2516         struct rockchip_crtc_state *vcstate;
2517
2518         if (WARN_ON(!crtc->state))
2519                 return NULL;
2520
2521         vcstate = kmemdup(to_rockchip_crtc_state(crtc->state),
2522                           sizeof(*vcstate), GFP_KERNEL);
2523         if (!vcstate)
2524                 return NULL;
2525
2526         __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
2527
2528         return &vcstate->base;
2529 }
2530
2531 static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
2532                                     struct drm_crtc_state *state)
2533 {
2534         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
2535
2536         __drm_atomic_helper_crtc_destroy_state(&vcstate->base);
2537         kfree(vcstate);
2538 }
2539
2540 static void vop2_crtc_reset(struct drm_crtc *crtc)
2541 {
2542         struct rockchip_crtc_state *vcstate =
2543                 kzalloc(sizeof(*vcstate), GFP_KERNEL);
2544
2545         if (crtc->state)
2546                 vop2_crtc_destroy_state(crtc, crtc->state);
2547
2548         if (vcstate)
2549                 __drm_atomic_helper_crtc_reset(crtc, &vcstate->base);
2550         else
2551                 __drm_atomic_helper_crtc_reset(crtc, NULL);
2552 }
2553
2554 static const struct drm_crtc_funcs vop2_crtc_funcs = {
2555         .set_config = drm_atomic_helper_set_config,
2556         .page_flip = drm_atomic_helper_page_flip,
2557         .destroy = drm_crtc_cleanup,
2558         .reset = vop2_crtc_reset,
2559         .atomic_duplicate_state = vop2_crtc_duplicate_state,
2560         .atomic_destroy_state = vop2_crtc_destroy_state,
2561         .enable_vblank = vop2_crtc_enable_vblank,
2562         .disable_vblank = vop2_crtc_disable_vblank,
2563 };
2564
2565 static irqreturn_t vop2_isr(int irq, void *data)
2566 {
2567         struct vop2 *vop2 = data;
2568         const struct vop2_data *vop2_data = vop2->data;
2569         u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM];
2570         int ret = IRQ_NONE;
2571         int i;
2572
2573         /*
2574          * The irq is shared with the iommu. If the runtime-pm state of the
2575          * vop2-device is disabled the irq has to be targeted at the iommu.
2576          */
2577         if (!pm_runtime_get_if_in_use(vop2->dev))
2578                 return IRQ_NONE;
2579
2580         for (i = 0; i < vop2_data->nr_vps; i++) {
2581                 struct vop2_video_port *vp = &vop2->vps[i];
2582                 struct drm_crtc *crtc = &vp->crtc;
2583                 u32 irqs;
2584
2585                 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
2586                 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
2587
2588                 if (irqs & VP_INT_DSP_HOLD_VALID) {
2589                         complete(&vp->dsp_hold_completion);
2590                         ret = IRQ_HANDLED;
2591                 }
2592
2593                 if (irqs & VP_INT_FS_FIELD) {
2594                         drm_crtc_handle_vblank(crtc);
2595                         spin_lock(&crtc->dev->event_lock);
2596                         if (vp->event) {
2597                                 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
2598
2599                                 if (!(val & BIT(vp->id))) {
2600                                         drm_crtc_send_vblank_event(crtc, vp->event);
2601                                         vp->event = NULL;
2602                                         drm_crtc_vblank_put(crtc);
2603                                 }
2604                         }
2605                         spin_unlock(&crtc->dev->event_lock);
2606
2607                         ret = IRQ_HANDLED;
2608                 }
2609
2610                 if (irqs & VP_INT_POST_BUF_EMPTY) {
2611                         drm_err_ratelimited(vop2->drm,
2612                                             "POST_BUF_EMPTY irq err at vp%d\n",
2613                                             vp->id);
2614                         ret = IRQ_HANDLED;
2615                 }
2616         }
2617
2618         axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
2619         vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
2620         axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
2621         vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
2622
2623         for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) {
2624                 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) {
2625                         drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
2626                         ret = IRQ_HANDLED;
2627                 }
2628         }
2629
2630         pm_runtime_put(vop2->dev);
2631
2632         return ret;
2633 }
2634
2635 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,
2636                            unsigned long possible_crtcs)
2637 {
2638         const struct vop2_win_data *win_data = win->data;
2639         unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2640                                   BIT(DRM_MODE_BLEND_PREMULTI) |
2641                                   BIT(DRM_MODE_BLEND_COVERAGE);
2642         int ret;
2643
2644         ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,
2645                                        &vop2_plane_funcs, win_data->formats,
2646                                        win_data->nformats,
2647                                        win_data->format_modifiers,
2648                                        win->type, win_data->name);
2649         if (ret) {
2650                 drm_err(vop2->drm, "failed to initialize plane %d\n", ret);
2651                 return ret;
2652         }
2653
2654         drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs);
2655
2656         if (win->data->supported_rotations)
2657                 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0,
2658                                                    DRM_MODE_ROTATE_0 |
2659                                                    win->data->supported_rotations);
2660         drm_plane_create_alpha_property(&win->base);
2661         drm_plane_create_blend_mode_property(&win->base, blend_caps);
2662         drm_plane_create_zpos_property(&win->base, win->win_id, 0,
2663                                        vop2->registered_num_wins - 1);
2664
2665         return 0;
2666 }
2667
2668 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2)
2669 {
2670         int i;
2671
2672         for (i = 0; i < vop2->data->nr_vps; i++) {
2673                 struct vop2_video_port *vp = &vop2->vps[i];
2674
2675                 if (!vp->crtc.port)
2676                         continue;
2677                 if (vp->primary_plane)
2678                         continue;
2679
2680                 return vp;
2681         }
2682
2683         return NULL;
2684 }
2685
2686 static int vop2_create_crtcs(struct vop2 *vop2)
2687 {
2688         const struct vop2_data *vop2_data = vop2->data;
2689         struct drm_device *drm = vop2->drm;
2690         struct device *dev = vop2->dev;
2691         struct drm_plane *plane;
2692         struct device_node *port;
2693         struct vop2_video_port *vp;
2694         int i, nvp, nvps = 0;
2695         int ret;
2696
2697         for (i = 0; i < vop2_data->nr_vps; i++) {
2698                 const struct vop2_video_port_data *vp_data;
2699                 struct device_node *np;
2700                 char dclk_name[9];
2701
2702                 vp_data = &vop2_data->vp[i];
2703                 vp = &vop2->vps[i];
2704                 vp->vop2 = vop2;
2705                 vp->id = vp_data->id;
2706                 vp->data = vp_data;
2707
2708                 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
2709                 vp->dclk = devm_clk_get(vop2->dev, dclk_name);
2710                 if (IS_ERR(vp->dclk)) {
2711                         drm_err(vop2->drm, "failed to get %s\n", dclk_name);
2712                         return PTR_ERR(vp->dclk);
2713                 }
2714
2715                 np = of_graph_get_remote_node(dev->of_node, i, -1);
2716                 if (!np) {
2717                         drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);
2718                         continue;
2719                 }
2720                 of_node_put(np);
2721
2722                 port = of_graph_get_port_by_id(dev->of_node, i);
2723                 if (!port) {
2724                         drm_err(vop2->drm, "no port node found for video_port%d\n", i);
2725                         return -ENOENT;
2726                 }
2727
2728                 vp->crtc.port = port;
2729                 nvps++;
2730         }
2731
2732         nvp = 0;
2733         for (i = 0; i < vop2->registered_num_wins; i++) {
2734                 struct vop2_win *win = &vop2->win[i];
2735                 u32 possible_crtcs = 0;
2736
2737                 if (vop2->data->soc_id == 3566) {
2738                         /*
2739                          * On RK3566 these windows don't have an independent
2740                          * framebuffer. They share the framebuffer with smart0,
2741                          * esmart0 and cluster0 respectively.
2742                          */
2743                         switch (win->data->phys_id) {
2744                         case ROCKCHIP_VOP2_SMART1:
2745                         case ROCKCHIP_VOP2_ESMART1:
2746                         case ROCKCHIP_VOP2_CLUSTER1:
2747                                 continue;
2748                         }
2749                 }
2750
2751                 if (win->type == DRM_PLANE_TYPE_PRIMARY) {
2752                         vp = find_vp_without_primary(vop2);
2753                         if (vp) {
2754                                 possible_crtcs = BIT(nvp);
2755                                 vp->primary_plane = win;
2756                                 nvp++;
2757                         } else {
2758                                 /* change the unused primary window to overlay window */
2759                                 win->type = DRM_PLANE_TYPE_OVERLAY;
2760                         }
2761                 }
2762
2763                 if (win->type == DRM_PLANE_TYPE_OVERLAY)
2764                         possible_crtcs = (1 << nvps) - 1;
2765
2766                 ret = vop2_plane_init(vop2, win, possible_crtcs);
2767                 if (ret) {
2768                         drm_err(vop2->drm, "failed to init plane %s: %d\n",
2769                                 win->data->name, ret);
2770                         return ret;
2771                 }
2772         }
2773
2774         for (i = 0; i < vop2_data->nr_vps; i++) {
2775                 vp = &vop2->vps[i];
2776
2777                 if (!vp->crtc.port)
2778                         continue;
2779
2780                 plane = &vp->primary_plane->base;
2781
2782                 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL,
2783                                                 &vop2_crtc_funcs,
2784                                                 "video_port%d", vp->id);
2785                 if (ret) {
2786                         drm_err(vop2->drm, "crtc init for video_port%d failed\n", i);
2787                         return ret;
2788                 }
2789
2790                 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs);
2791
2792                 init_completion(&vp->dsp_hold_completion);
2793         }
2794
2795         /*
2796          * On the VOP2 it's very hard to change the number of layers on a VP
2797          * during runtime, so we distribute the layers equally over the used
2798          * VPs
2799          */
2800         for (i = 0; i < vop2->data->nr_vps; i++) {
2801                 struct vop2_video_port *vp = &vop2->vps[i];
2802
2803                 if (vp->crtc.port)
2804                         vp->nlayers = vop2_data->win_size / nvps;
2805         }
2806
2807         return 0;
2808 }
2809
2810 static void vop2_destroy_crtcs(struct vop2 *vop2)
2811 {
2812         struct drm_device *drm = vop2->drm;
2813         struct list_head *crtc_list = &drm->mode_config.crtc_list;
2814         struct list_head *plane_list = &drm->mode_config.plane_list;
2815         struct drm_crtc *crtc, *tmpc;
2816         struct drm_plane *plane, *tmpp;
2817
2818         list_for_each_entry_safe(plane, tmpp, plane_list, head)
2819                 drm_plane_cleanup(plane);
2820
2821         /*
2822          * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane()
2823          * references the CRTC.
2824          */
2825         list_for_each_entry_safe(crtc, tmpc, crtc_list, head) {
2826                 of_node_put(crtc->port);
2827                 drm_crtc_cleanup(crtc);
2828         }
2829 }
2830
2831 static int vop2_find_rgb_encoder(struct vop2 *vop2)
2832 {
2833         struct device_node *node = vop2->dev->of_node;
2834         struct device_node *endpoint;
2835         int i;
2836
2837         for (i = 0; i < vop2->data->nr_vps; i++) {
2838                 endpoint = of_graph_get_endpoint_by_regs(node, i,
2839                                                          ROCKCHIP_VOP2_EP_RGB0);
2840                 if (!endpoint)
2841                         continue;
2842
2843                 of_node_put(endpoint);
2844                 return i;
2845         }
2846
2847         return -ENOENT;
2848 }
2849
2850 static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
2851         [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0),
2852         [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5),
2853         [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14),
2854         [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18),
2855         [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31),
2856         [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31),
2857         [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31),
2858         [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31),
2859         [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31),
2860         [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19),
2861         [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15),
2862         [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31),
2863         [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8),
2864         [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9),
2865         [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11),
2866
2867         /* Scale */
2868         [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15),
2869         [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31),
2870         [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15),
2871         [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13),
2872         [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3),
2873         [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28),
2874         [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29),
2875
2876         /* cluster regs */
2877         [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1),
2878         [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0),
2879         [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7),
2880
2881         /* afbc regs */
2882         [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6),
2883         [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9),
2884         [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10),
2885         [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4),
2886         [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7),
2887         [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8),
2888         [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31),
2889         [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31),
2890         [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15),
2891         [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
2892         [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
2893         [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
2894         [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
2895         [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
2896         [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
2897         [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2),
2898         [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3),
2899         [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff },
2900         [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff },
2901         [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff },
2902         [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff },
2903         [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff },
2904         [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2905         [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2906         [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff },
2907         [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2908         [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff },
2909         [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2910         [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff },
2911         [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff },
2912 };
2913
2914 static int vop2_cluster_init(struct vop2_win *win)
2915 {
2916         struct vop2 *vop2 = win->vop2;
2917         struct reg_field *cluster_regs;
2918         int ret, i;
2919
2920         cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs),
2921                                GFP_KERNEL);
2922         if (!cluster_regs)
2923                 return -ENOMEM;
2924
2925         for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++)
2926                 if (cluster_regs[i].reg != 0xffffffff)
2927                         cluster_regs[i].reg += win->offset;
2928
2929         ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2930                                            cluster_regs,
2931                                            ARRAY_SIZE(vop2_cluster_regs));
2932
2933         kfree(cluster_regs);
2934
2935         return ret;
2936 };
2937
2938 static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
2939         [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0),
2940         [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5),
2941         [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12),
2942         [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14),
2943         [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16),
2944         [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31),
2945         [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31),
2946         [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28),
2947         [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31),
2948         [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31),
2949         [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17),
2950         [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15),
2951         [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31),
2952         [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0),
2953         [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1),
2954         [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3),
2955         [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31),
2956         [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29),
2957         [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31),
2958
2959         /* Scale */
2960         [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15),
2961         [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31),
2962         [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15),
2963         [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31),
2964         [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1),
2965         [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3),
2966         [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5),
2967         [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7),
2968         [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9),
2969         [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11),
2970         [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13),
2971         [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15),
2972         [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17),
2973         [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8),
2974         [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9),
2975         [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10),
2976         [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11),
2977         [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff },
2978         [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff },
2979         [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff },
2980         [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff },
2981         [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff },
2982         [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff },
2983         [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff },
2984         [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff },
2985         [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff },
2986         [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff },
2987         [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff },
2988         [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff },
2989         [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff },
2990         [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff },
2991         [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
2992         [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff },
2993         [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff },
2994         [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff },
2995         [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff },
2996 };
2997
2998 static int vop2_esmart_init(struct vop2_win *win)
2999 {
3000         struct vop2 *vop2 = win->vop2;
3001         struct reg_field *esmart_regs;
3002         int ret, i;
3003
3004         esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs),
3005                               GFP_KERNEL);
3006         if (!esmart_regs)
3007                 return -ENOMEM;
3008
3009         for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++)
3010                 if (esmart_regs[i].reg != 0xffffffff)
3011                         esmart_regs[i].reg += win->offset;
3012
3013         ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
3014                                            esmart_regs,
3015                                            ARRAY_SIZE(vop2_esmart_regs));
3016
3017         kfree(esmart_regs);
3018
3019         return ret;
3020 };
3021
3022 static int vop2_win_init(struct vop2 *vop2)
3023 {
3024         const struct vop2_data *vop2_data = vop2->data;
3025         struct vop2_win *win;
3026         int i, ret;
3027
3028         for (i = 0; i < vop2_data->win_size; i++) {
3029                 const struct vop2_win_data *win_data = &vop2_data->win[i];
3030
3031                 win = &vop2->win[i];
3032                 win->data = win_data;
3033                 win->type = win_data->type;
3034                 win->offset = win_data->base;
3035                 win->win_id = i;
3036                 win->vop2 = vop2;
3037                 if (vop2_cluster_window(win))
3038                         ret = vop2_cluster_init(win);
3039                 else
3040                         ret = vop2_esmart_init(win);
3041                 if (ret)
3042                         return ret;
3043         }
3044
3045         vop2->registered_num_wins = vop2_data->win_size;
3046
3047         return 0;
3048 }
3049
3050 /*
3051  * The window registers are only updated when config done is written.
3052  * Until that they read back the old value. As we read-modify-write
3053  * these registers mark them as non-volatile. This makes sure we read
3054  * the new values from the regmap register cache.
3055  */
3056 static const struct regmap_range vop2_nonvolatile_range[] = {
3057         regmap_reg_range(0x1000, 0x23ff),
3058 };
3059
3060 static const struct regmap_access_table vop2_volatile_table = {
3061         .no_ranges = vop2_nonvolatile_range,
3062         .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range),
3063 };
3064
3065 static const struct regmap_config vop2_regmap_config = {
3066         .reg_bits       = 32,
3067         .val_bits       = 32,
3068         .reg_stride     = 4,
3069         .max_register   = 0x3000,
3070         .name           = "vop2",
3071         .volatile_table = &vop2_volatile_table,
3072         .cache_type     = REGCACHE_MAPLE,
3073 };
3074
3075 static int vop2_bind(struct device *dev, struct device *master, void *data)
3076 {
3077         struct platform_device *pdev = to_platform_device(dev);
3078         const struct vop2_data *vop2_data;
3079         struct drm_device *drm = data;
3080         struct vop2 *vop2;
3081         struct resource *res;
3082         size_t alloc_size;
3083         int ret;
3084
3085         vop2_data = of_device_get_match_data(dev);
3086         if (!vop2_data)
3087                 return -ENODEV;
3088
3089         /* Allocate vop2 struct and its vop2_win array */
3090         alloc_size = struct_size(vop2, win, vop2_data->win_size);
3091         vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
3092         if (!vop2)
3093                 return -ENOMEM;
3094
3095         vop2->dev = dev;
3096         vop2->data = vop2_data;
3097         vop2->drm = drm;
3098
3099         dev_set_drvdata(dev, vop2);
3100
3101         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop");
3102         if (!res) {
3103                 drm_err(vop2->drm, "failed to get vop2 register byname\n");
3104                 return -EINVAL;
3105         }
3106
3107         vop2->regs = devm_ioremap_resource(dev, res);
3108         if (IS_ERR(vop2->regs))
3109                 return PTR_ERR(vop2->regs);
3110         vop2->len = resource_size(res);
3111
3112         vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);
3113         if (IS_ERR(vop2->map))
3114                 return PTR_ERR(vop2->map);
3115
3116         ret = vop2_win_init(vop2);
3117         if (ret)
3118                 return ret;
3119
3120         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut");
3121         if (res) {
3122                 vop2->lut_regs = devm_ioremap_resource(dev, res);
3123                 if (IS_ERR(vop2->lut_regs))
3124                         return PTR_ERR(vop2->lut_regs);
3125         }
3126         if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_GRF) {
3127                 vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
3128                 if (IS_ERR(vop2->sys_grf))
3129                         return dev_err_probe(dev, PTR_ERR(vop2->sys_grf), "cannot get sys_grf");
3130         }
3131
3132         if (vop2_data->feature & VOP2_FEATURE_HAS_VOP_GRF) {
3133                 vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf");
3134                 if (IS_ERR(vop2->vop_grf))
3135                         return dev_err_probe(dev, PTR_ERR(vop2->vop_grf), "cannot get vop_grf");
3136         }
3137
3138         if (vop2_data->feature & VOP2_FEATURE_HAS_VO1_GRF) {
3139                 vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf");
3140                 if (IS_ERR(vop2->vo1_grf))
3141                         return dev_err_probe(dev, PTR_ERR(vop2->vo1_grf), "cannot get vo1_grf");
3142         }
3143
3144         if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_PMU) {
3145                 vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
3146                 if (IS_ERR(vop2->sys_pmu))
3147                         return dev_err_probe(dev, PTR_ERR(vop2->sys_pmu), "cannot get sys_pmu");
3148         }
3149
3150         vop2->hclk = devm_clk_get(vop2->dev, "hclk");
3151         if (IS_ERR(vop2->hclk)) {
3152                 drm_err(vop2->drm, "failed to get hclk source\n");
3153                 return PTR_ERR(vop2->hclk);
3154         }
3155
3156         vop2->aclk = devm_clk_get(vop2->dev, "aclk");
3157         if (IS_ERR(vop2->aclk)) {
3158                 drm_err(vop2->drm, "failed to get aclk source\n");
3159                 return PTR_ERR(vop2->aclk);
3160         }
3161
3162         vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop");
3163         if (IS_ERR(vop2->pclk)) {
3164                 drm_err(vop2->drm, "failed to get pclk source\n");
3165                 return PTR_ERR(vop2->pclk);
3166         }
3167
3168         vop2->irq = platform_get_irq(pdev, 0);
3169         if (vop2->irq < 0) {
3170                 drm_err(vop2->drm, "cannot find irq for vop2\n");
3171                 return vop2->irq;
3172         }
3173
3174         mutex_init(&vop2->vop2_lock);
3175
3176         ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
3177         if (ret)
3178                 return ret;
3179
3180         ret = vop2_create_crtcs(vop2);
3181         if (ret)
3182                 return ret;
3183
3184         ret = vop2_find_rgb_encoder(vop2);
3185         if (ret >= 0) {
3186                 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
3187                                               vop2->drm, ret);
3188                 if (IS_ERR(vop2->rgb)) {
3189                         if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) {
3190                                 ret = PTR_ERR(vop2->rgb);
3191                                 goto err_crtcs;
3192                         }
3193                         vop2->rgb = NULL;
3194                 }
3195         }
3196
3197         rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
3198
3199         pm_runtime_enable(&pdev->dev);
3200
3201         return 0;
3202
3203 err_crtcs:
3204         vop2_destroy_crtcs(vop2);
3205
3206         return ret;
3207 }
3208
3209 static void vop2_unbind(struct device *dev, struct device *master, void *data)
3210 {
3211         struct vop2 *vop2 = dev_get_drvdata(dev);
3212
3213         pm_runtime_disable(dev);
3214
3215         if (vop2->rgb)
3216                 rockchip_rgb_fini(vop2->rgb);
3217
3218         vop2_destroy_crtcs(vop2);
3219 }
3220
3221 const struct component_ops vop2_component_ops = {
3222         .bind = vop2_bind,
3223         .unbind = vop2_unbind,
3224 };
3225 EXPORT_SYMBOL_GPL(vop2_component_ops);