drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_atomic_uapi.h>
  19 #include <drm/drm_crtc.h>
  20 #include <drm/drm_crtc_helper.h>
  21 #include <drm/drm_flip_work.h>
  22 #include <drm/drm_gem_framebuffer_helper.h>
  23 #include <drm/drm_plane_helper.h>
  24 #ifdef CONFIG_DRM_ANALOGIX_DP
  25 #include <drm/bridge/analogix_dp.h>
  26 #endif
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/clk.h>
  32 #include <linux/iopoll.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/component.h>
  37 #include <linux/overflow.h>
  38
  39 #include <linux/reset.h>
  40 #include <linux/delay.h>
  41
  42 #include "rockchip_drm_drv.h"
  43 #include "rockchip_drm_gem.h"
  44 #include "rockchip_drm_fb.h"
  45 #include "rockchip_drm_psr.h"
  46 #include "rockchip_drm_vop.h"
  47 #include "rockchip_rgb.h"
  48
  49 #define VOP_WIN_SET(vop, win, name, v) \
  50                 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
  51 #define VOP_SCL_SET(vop, win, name, v) \
  52                 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
  53 #define VOP_SCL_SET_EXT(vop, win, name, v) \
  54                 vop_reg_set(vop, &win->phy->scl->ext->name, \
  55                             win->base, ~0, v, #name)
  56
  57 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
  58         do { \
  59                 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
  60                         vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
  61         } while (0)
  62
  63 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
  64         do { \
  65                 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
  66                         vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
  67         } while (0)
  68
  69 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  70                 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
  71
  72 #define VOP_REG_SET(vop, group, name, v) \
  73                     vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
  74
  75 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  76         do { \
  77                 int i, reg = 0, mask = 0; \
  78                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  79                         if (vop->data->intr->intrs[i] & type) { \
  80                                 reg |= (v) << i; \
  81                                 mask |= 1 << i; \
  82                         } \
  83                 } \
  84                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
  85         } while (0)
  86 #define VOP_INTR_GET_TYPE(vop, name, type) \
  87                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  88
  89 #define VOP_WIN_GET(vop, win, name) \
  90                 vop_read_reg(vop, win->offset, win->phy->name)
  91
  92 #define VOP_WIN_HAS_REG(win, name) \
  93         (!!(win->phy->name.mask))
  94
  95 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  96                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  97
  98 #define VOP_WIN_TO_INDEX(vop_win) \
  99         ((vop_win) - (vop_win)->vop->win)
 100
 101 #define to_vop(x) container_of(x, struct vop, crtc)
 102 #define to_vop_win(x) container_of(x, struct vop_win, base)
 103
 104 /*
 105  * The coefficients of the following matrix are all fixed points.
 106  * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
 107  * They are all represented in two's complement.
 108  */
 109 static const uint32_t bt601_yuv2rgb[] = {
 110         0x4A8, 0x0,    0x662,
 111         0x4A8, 0x1E6F, 0x1CBF,
 112         0x4A8, 0x812,  0x0,
 113         0x321168, 0x0877CF, 0x2EB127
 114 };
 115
 116 enum vop_pending {
 117         VOP_PENDING_FB_UNREF,
 118 };
 119
 120 struct vop_win {
 121         struct drm_plane base;
 122         const struct vop_win_data *data;
 123         const struct vop_win_yuv2yuv_data *yuv2yuv_data;
 124         struct vop *vop;
 125 };
 126
 127 struct rockchip_rgb;
 128 struct vop {
 129         struct drm_crtc crtc;
 130         struct device *dev;
 131         struct drm_device *drm_dev;
 132         bool is_enabled;
 133
 134         struct completion dsp_hold_completion;
 135
 136         /* protected by dev->event_lock */
 137         struct drm_pending_vblank_event *event;
 138
 139         struct drm_flip_work fb_unref_work;
 140         unsigned long pending;
 141
 142         struct completion line_flag_completion;
 143
 144         const struct vop_data *data;
 145
 146         uint32_t *regsbak;
 147         void __iomem *regs;
 148
 149         /* physical map length of vop register */
 150         uint32_t len;
 151
 152         /* one time only one process allowed to config the register */
 153         spinlock_t reg_lock;
 154         /* lock vop irq reg */
 155         spinlock_t irq_lock;
 156         /* protects crtc enable/disable */
 157         struct mutex vop_lock;
 158
 159         unsigned int irq;
 160
 161         /* vop AHP clk */
 162         struct clk *hclk;
 163         /* vop dclk */
 164         struct clk *dclk;
 165         /* vop share memory frequency */
 166         struct clk *aclk;
 167
 168         /* vop dclk reset */
 169         struct reset_control *dclk_rst;
 170
 171         /* optional internal rgb encoder */
 172         struct rockchip_rgb *rgb;
 173
 174         struct vop_win win[];
 175 };
 176
 177 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 178 {
 179         writel(v, vop->regs + offset);
 180         vop->regsbak[offset >> 2] = v;
 181 }
 182
 183 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 184 {
 185         return readl(vop->regs + offset);
 186 }
 187
 188 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 189                                     const struct vop_reg *reg)
 190 {
 191         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 192 }
 193
 194 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
 195                         uint32_t _offset, uint32_t _mask, uint32_t v,
 196                         const char *reg_name)
 197 {
 198         int offset, mask, shift;
 199
 200         if (!reg || !reg->mask) {
 201                 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
 202                 return;
 203         }
 204
 205         offset = reg->offset + _offset;
 206         mask = reg->mask & _mask;
 207         shift = reg->shift;
 208
 209         if (reg->write_mask) {
 210                 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
 211         } else {
 212                 uint32_t cached_val = vop->regsbak[offset >> 2];
 213
 214                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 215                 vop->regsbak[offset >> 2] = v;
 216         }
 217
 218         if (reg->relaxed)
 219                 writel_relaxed(v, vop->regs + offset);
 220         else
 221                 writel(v, vop->regs + offset);
 222 }
 223
 224 static inline uint32_t vop_get_intr_type(struct vop *vop,
 225                                          const struct vop_reg *reg, int type)
 226 {
 227         uint32_t i, ret = 0;
 228         uint32_t regs = vop_read_reg(vop, 0, reg);
 229
 230         for (i = 0; i < vop->data->intr->nintrs; i++) {
 231                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 232                         ret |= vop->data->intr->intrs[i];
 233         }
 234
 235         return ret;
 236 }
 237
 238 static inline void vop_cfg_done(struct vop *vop)
 239 {
 240         VOP_REG_SET(vop, common, cfg_done, 1);
 241 }
 242
 243 static bool has_rb_swapped(uint32_t format)
 244 {
 245         switch (format) {
 246         case DRM_FORMAT_XBGR8888:
 247         case DRM_FORMAT_ABGR8888:
 248         case DRM_FORMAT_BGR888:
 249         case DRM_FORMAT_BGR565:
 250                 return true;
 251         default:
 252                 return false;
 253         }
 254 }
 255
 256 static enum vop_data_format vop_convert_format(uint32_t format)
 257 {
 258         switch (format) {
 259         case DRM_FORMAT_XRGB8888:
 260         case DRM_FORMAT_ARGB8888:
 261         case DRM_FORMAT_XBGR8888:
 262         case DRM_FORMAT_ABGR8888:
 263                 return VOP_FMT_ARGB8888;
 264         case DRM_FORMAT_RGB888:
 265         case DRM_FORMAT_BGR888:
 266                 return VOP_FMT_RGB888;
 267         case DRM_FORMAT_RGB565:
 268         case DRM_FORMAT_BGR565:
 269                 return VOP_FMT_RGB565;
 270         case DRM_FORMAT_NV12:
 271                 return VOP_FMT_YUV420SP;
 272         case DRM_FORMAT_NV16:
 273                 return VOP_FMT_YUV422SP;
 274         case DRM_FORMAT_NV24:
 275                 return VOP_FMT_YUV444SP;
 276         default:
 277                 DRM_ERROR("unsupported format[%08x]\n", format);
 278                 return -EINVAL;
 279         }
 280 }
 281
 282 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 283                                   uint32_t dst, bool is_horizontal,
 284                                   int vsu_mode, int *vskiplines)
 285 {
 286         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 287
 288         if (vskiplines)
 289                 *vskiplines = 0;
 290
 291         if (is_horizontal) {
 292                 if (mode == SCALE_UP)
 293                         val = GET_SCL_FT_BIC(src, dst);
 294                 else if (mode == SCALE_DOWN)
 295                         val = GET_SCL_FT_BILI_DN(src, dst);
 296         } else {
 297                 if (mode == SCALE_UP) {
 298                         if (vsu_mode == SCALE_UP_BIL)
 299                                 val = GET_SCL_FT_BILI_UP(src, dst);
 300                         else
 301                                 val = GET_SCL_FT_BIC(src, dst);
 302                 } else if (mode == SCALE_DOWN) {
 303                         if (vskiplines) {
 304                                 *vskiplines = scl_get_vskiplines(src, dst);
 305                                 val = scl_get_bili_dn_vskip(src, dst,
 306                                                             *vskiplines);
 307                         } else {
 308                                 val = GET_SCL_FT_BILI_DN(src, dst);
 309                         }
 310                 }
 311         }
 312
 313         return val;
 314 }
 315
 316 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 317                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 318                              uint32_t dst_h, uint32_t pixel_format)
 319 {
 320         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 321         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 322         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 323         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 324         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 325         const struct drm_format_info *info;
 326         bool is_yuv = false;
 327         uint16_t cbcr_src_w = src_w / hsub;
 328         uint16_t cbcr_src_h = src_h / vsub;
 329         uint16_t vsu_mode;
 330         uint16_t lb_mode;
 331         uint32_t val;
 332         int vskiplines;
 333
 334         info = drm_format_info(pixel_format);
 335
 336         if (info->is_yuv)
 337                 is_yuv = true;
 338
 339         if (dst_w > 3840) {
 340                 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
 341                 return;
 342         }
 343
 344         if (!win->phy->scl->ext) {
 345                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 346                             scl_cal_scale2(src_w, dst_w));
 347                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 348                             scl_cal_scale2(src_h, dst_h));
 349                 if (is_yuv) {
 350                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 351                                     scl_cal_scale2(cbcr_src_w, dst_w));
 352                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 353                                     scl_cal_scale2(cbcr_src_h, dst_h));
 354                 }
 355                 return;
 356         }
 357
 358         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 359         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 360
 361         if (is_yuv) {
 362                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 363                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 364                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 365                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 366                 else
 367                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 368         } else {
 369                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 370                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 371                 else
 372                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 373         }
 374
 375         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 376         if (lb_mode == LB_RGB_3840X2) {
 377                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 378                         DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
 379                         return;
 380                 }
 381                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 382                         DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
 383                         return;
 384                 }
 385                 vsu_mode = SCALE_UP_BIL;
 386         } else if (lb_mode == LB_RGB_2560X4) {
 387                 vsu_mode = SCALE_UP_BIL;
 388         } else {
 389                 vsu_mode = SCALE_UP_BIC;
 390         }
 391
 392         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 393                                 true, 0, NULL);
 394         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 395         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 396                                 false, vsu_mode, &vskiplines);
 397         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 398
 399         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 400         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 401
 402         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 403         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 404         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 405         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 406         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 407         if (is_yuv) {
 408                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 409                                         dst_w, true, 0, NULL);
 410                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 411                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 412                                         dst_h, false, vsu_mode, &vskiplines);
 413                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 414
 415                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 416                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 417                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 418                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 419                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 420                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 421                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 422         }
 423 }
 424
 425 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 426 {
 427         unsigned long flags;
 428
 429         if (WARN_ON(!vop->is_enabled))
 430                 return;
 431
 432         spin_lock_irqsave(&vop->irq_lock, flags);
 433
 434         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 435         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 436
 437         spin_unlock_irqrestore(&vop->irq_lock, flags);
 438 }
 439
 440 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 441 {
 442         unsigned long flags;
 443
 444         if (WARN_ON(!vop->is_enabled))
 445                 return;
 446
 447         spin_lock_irqsave(&vop->irq_lock, flags);
 448
 449         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 450
 451         spin_unlock_irqrestore(&vop->irq_lock, flags);
 452 }
 453
 454 /*
 455  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 456  *     the "FRAME_SYNC" interrupt.
 457  * (2) the active data region of each frame ends at dsp_vact_end
 458  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 459  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 460  *
 461  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 462  * Interrupts
 463  * LINE_FLAG -------------------------------+
 464  * FRAME_SYNC ----+                         |
 465  *                |                         |
 466  *                v                         v
 467  *                | Vsync | Vbp |  Vactive  | Vfp |
 468  *                        ^     ^           ^     ^
 469  *                        |     |           |     |
 470  *                        |     |           |     |
 471  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 472  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 473  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 474  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 475  */
 476 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 477 {
 478         uint32_t line_flag_irq;
 479         unsigned long flags;
 480
 481         spin_lock_irqsave(&vop->irq_lock, flags);
 482
 483         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 484
 485         spin_unlock_irqrestore(&vop->irq_lock, flags);
 486
 487         return !!line_flag_irq;
 488 }
 489
 490 static void vop_line_flag_irq_enable(struct vop *vop)
 491 {
 492         unsigned long flags;
 493
 494         if (WARN_ON(!vop->is_enabled))
 495                 return;
 496
 497         spin_lock_irqsave(&vop->irq_lock, flags);
 498
 499         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 500         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 501
 502         spin_unlock_irqrestore(&vop->irq_lock, flags);
 503 }
 504
 505 static void vop_line_flag_irq_disable(struct vop *vop)
 506 {
 507         unsigned long flags;
 508
 509         if (WARN_ON(!vop->is_enabled))
 510                 return;
 511
 512         spin_lock_irqsave(&vop->irq_lock, flags);
 513
 514         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 515
 516         spin_unlock_irqrestore(&vop->irq_lock, flags);
 517 }
 518
 519 static int vop_core_clks_enable(struct vop *vop)
 520 {
 521         int ret;
 522
 523         ret = clk_enable(vop->hclk);
 524         if (ret < 0)
 525                 return ret;
 526
 527         ret = clk_enable(vop->aclk);
 528         if (ret < 0)
 529                 goto err_disable_hclk;
 530
 531         return 0;
 532
 533 err_disable_hclk:
 534         clk_disable(vop->hclk);
 535         return ret;
 536 }
 537
 538 static void vop_core_clks_disable(struct vop *vop)
 539 {
 540         clk_disable(vop->aclk);
 541         clk_disable(vop->hclk);
 542 }
 543
 544 static int vop_enable(struct drm_crtc *crtc)
 545 {
 546         struct vop *vop = to_vop(crtc);
 547         int ret, i;
 548
 549         ret = pm_runtime_get_sync(vop->dev);
 550         if (ret < 0) {
 551                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
 552                 return ret;
 553         }
 554
 555         ret = vop_core_clks_enable(vop);
 556         if (WARN_ON(ret < 0))
 557                 goto err_put_pm_runtime;
 558
 559         ret = clk_enable(vop->dclk);
 560         if (WARN_ON(ret < 0))
 561                 goto err_disable_core;
 562
 563         /*
 564          * Slave iommu shares power, irq and clock with vop.  It was associated
 565          * automatically with this master device via common driver code.
 566          * Now that we have enabled the clock we attach it to the shared drm
 567          * mapping.
 568          */
 569         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 570         if (ret) {
 571                 DRM_DEV_ERROR(vop->dev,
 572                               "failed to attach dma mapping, %d\n", ret);
 573                 goto err_disable_dclk;
 574         }
 575
 576         spin_lock(&vop->reg_lock);
 577         for (i = 0; i < vop->len; i += 4)
 578                 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
 579
 580         /*
 581          * We need to make sure that all windows are disabled before we
 582          * enable the crtc. Otherwise we might try to scan from a destroyed
 583          * buffer later.
 584          */
 585         for (i = 0; i < vop->data->win_size; i++) {
 586                 struct vop_win *vop_win = &vop->win[i];
 587                 const struct vop_win_data *win = vop_win->data;
 588
 589                 VOP_WIN_SET(vop, win, enable, 0);
 590         }
 591         spin_unlock(&vop->reg_lock);
 592
 593         vop_cfg_done(vop);
 594
 595         /*
 596          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 597          */
 598         vop->is_enabled = true;
 599
 600         spin_lock(&vop->reg_lock);
 601
 602         VOP_REG_SET(vop, common, standby, 1);
 603
 604         spin_unlock(&vop->reg_lock);
 605
 606         drm_crtc_vblank_on(crtc);
 607
 608         return 0;
 609
 610 err_disable_dclk:
 611         clk_disable(vop->dclk);
 612 err_disable_core:
 613         vop_core_clks_disable(vop);
 614 err_put_pm_runtime:
 615         pm_runtime_put_sync(vop->dev);
 616         return ret;
 617 }
 618
 619 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
 620                                     struct drm_crtc_state *old_state)
 621 {
 622         struct vop *vop = to_vop(crtc);
 623
 624         WARN_ON(vop->event);
 625
 626         mutex_lock(&vop->vop_lock);
 627         drm_crtc_vblank_off(crtc);
 628
 629         /*
 630          * Vop standby will take effect at end of current frame,
 631          * if dsp hold valid irq happen, it means standby complete.
 632          *
 633          * we must wait standby complete when we want to disable aclk,
 634          * if not, memory bus maybe dead.
 635          */
 636         reinit_completion(&vop->dsp_hold_completion);
 637         vop_dsp_hold_valid_irq_enable(vop);
 638
 639         spin_lock(&vop->reg_lock);
 640
 641         VOP_REG_SET(vop, common, standby, 1);
 642
 643         spin_unlock(&vop->reg_lock);
 644
 645         wait_for_completion(&vop->dsp_hold_completion);
 646
 647         vop_dsp_hold_valid_irq_disable(vop);
 648
 649         vop->is_enabled = false;
 650
 651         /*
 652          * vop standby complete, so iommu detach is safe.
 653          */
 654         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 655
 656         clk_disable(vop->dclk);
 657         vop_core_clks_disable(vop);
 658         pm_runtime_put(vop->dev);
 659         mutex_unlock(&vop->vop_lock);
 660
 661         if (crtc->state->event && !crtc->state->active) {
 662                 spin_lock_irq(&crtc->dev->event_lock);
 663                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 664                 spin_unlock_irq(&crtc->dev->event_lock);
 665
 666                 crtc->state->event = NULL;
 667         }
 668 }
 669
 670 static void vop_plane_destroy(struct drm_plane *plane)
 671 {
 672         drm_plane_cleanup(plane);
 673 }
 674
 675 static int vop_plane_atomic_check(struct drm_plane *plane,
 676                            struct drm_plane_state *state)
 677 {
 678         struct drm_crtc *crtc = state->crtc;
 679         struct drm_crtc_state *crtc_state;
 680         struct drm_framebuffer *fb = state->fb;
 681         struct vop_win *vop_win = to_vop_win(plane);
 682         const struct vop_win_data *win = vop_win->data;
 683         int ret;
 684         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 685                                         DRM_PLANE_HELPER_NO_SCALING;
 686         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 687                                         DRM_PLANE_HELPER_NO_SCALING;
 688
 689         if (!crtc || !fb)
 690                 return 0;
 691
 692         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 693         if (WARN_ON(!crtc_state))
 694                 return -EINVAL;
 695
 696         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 697                                                   min_scale, max_scale,
 698                                                   true, true);
 699         if (ret)
 700                 return ret;
 701
 702         if (!state->visible)
 703                 return 0;
 704
 705         ret = vop_convert_format(fb->format->format);
 706         if (ret < 0)
 707                 return ret;
 708
 709         /*
 710          * Src.x1 can be odd when do clip, but yuv plane start point
 711          * need align with 2 pixel.
 712          */
 713         if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
 714                 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
 715                 return -EINVAL;
 716         }
 717
 718         if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
 719                 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
 720                 return -EINVAL;
 721         }
 722
 723         return 0;
 724 }
 725
 726 static void vop_plane_atomic_disable(struct drm_plane *plane,
 727                                      struct drm_plane_state *old_state)
 728 {
 729         struct vop_win *vop_win = to_vop_win(plane);
 730         const struct vop_win_data *win = vop_win->data;
 731         struct vop *vop = to_vop(old_state->crtc);
 732
 733         if (!old_state->crtc)
 734                 return;
 735
 736         spin_lock(&vop->reg_lock);
 737
 738         VOP_WIN_SET(vop, win, enable, 0);
 739
 740         spin_unlock(&vop->reg_lock);
 741 }
 742
 743 static void vop_plane_atomic_update(struct drm_plane *plane,
 744                 struct drm_plane_state *old_state)
 745 {
 746         struct drm_plane_state *state = plane->state;
 747         struct drm_crtc *crtc = state->crtc;
 748         struct vop_win *vop_win = to_vop_win(plane);
 749         const struct vop_win_data *win = vop_win->data;
 750         const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
 751         struct vop *vop = to_vop(state->crtc);
 752         struct drm_framebuffer *fb = state->fb;
 753         unsigned int actual_w, actual_h;
 754         unsigned int dsp_stx, dsp_sty;
 755         uint32_t act_info, dsp_info, dsp_st;
 756         struct drm_rect *src = &state->src;
 757         struct drm_rect *dest = &state->dst;
 758         struct drm_gem_object *obj, *uv_obj;
 759         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 760         unsigned long offset;
 761         dma_addr_t dma_addr;
 762         uint32_t val;
 763         bool rb_swap;
 764         int win_index = VOP_WIN_TO_INDEX(vop_win);
 765         int format;
 766         int is_yuv = fb->format->is_yuv;
 767         int i;
 768
 769         /*
 770          * can't update plane when vop is disabled.
 771          */
 772         if (WARN_ON(!crtc))
 773                 return;
 774
 775         if (WARN_ON(!vop->is_enabled))
 776                 return;
 777
 778         if (!state->visible) {
 779                 vop_plane_atomic_disable(plane, old_state);
 780                 return;
 781         }
 782
 783         obj = fb->obj[0];
 784         rk_obj = to_rockchip_obj(obj);
 785
 786         actual_w = drm_rect_width(src) >> 16;
 787         actual_h = drm_rect_height(src) >> 16;
 788         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 789
 790         dsp_info = (drm_rect_height(dest) - 1) << 16;
 791         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 792
 793         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 794         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 795         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 796
 797         offset = (src->x1 >> 16) * fb->format->cpp[0];
 798         offset += (src->y1 >> 16) * fb->pitches[0];
 799         dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 800
 801         /*
 802          * For y-mirroring we need to move address
 803          * to the beginning of the last line.
 804          */
 805         if (state->rotation & DRM_MODE_REFLECT_Y)
 806                 dma_addr += (actual_h - 1) * fb->pitches[0];
 807
 808         format = vop_convert_format(fb->format->format);
 809
 810         spin_lock(&vop->reg_lock);
 811
 812         VOP_WIN_SET(vop, win, format, format);
 813         VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
 814         VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 815         VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
 816         VOP_WIN_SET(vop, win, y_mir_en,
 817                     (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
 818         VOP_WIN_SET(vop, win, x_mir_en,
 819                     (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
 820
 821         if (is_yuv) {
 822                 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
 823                 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
 824                 int bpp = fb->format->cpp[1];
 825
 826                 uv_obj = fb->obj[1];
 827                 rk_uv_obj = to_rockchip_obj(uv_obj);
 828
 829                 offset = (src->x1 >> 16) * bpp / hsub;
 830                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 831
 832                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 833                 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 834                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 835
 836                 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
 837                         VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
 838                                                         win_yuv2yuv,
 839                                                         y2r_coefficients[i],
 840                                                         bt601_yuv2rgb[i]);
 841                 }
 842         }
 843
 844         if (win->phy->scl)
 845                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 846                                     drm_rect_width(dest), drm_rect_height(dest),
 847                                     fb->format->format);
 848
 849         VOP_WIN_SET(vop, win, act_info, act_info);
 850         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 851         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 852
 853         rb_swap = has_rb_swapped(fb->format->format);
 854         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 855
 856         /*
 857          * Blending win0 with the background color doesn't seem to work
 858          * correctly. We only get the background color, no matter the contents
 859          * of the win0 framebuffer.  However, blending pre-multiplied color
 860          * with the default opaque black default background color is a no-op,
 861          * so we can just disable blending to get the correct result.
 862          */
 863         if (fb->format->has_alpha && win_index > 0) {
 864                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 865                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 866                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 867                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 868                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 869                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 870                         SRC_FACTOR_M0(ALPHA_ONE);
 871                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 872         } else {
 873                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 874         }
 875
 876         VOP_WIN_SET(vop, win, enable, 1);
 877         spin_unlock(&vop->reg_lock);
 878 }
 879
 880 static int vop_plane_atomic_async_check(struct drm_plane *plane,
 881                                         struct drm_plane_state *state)
 882 {
 883         struct vop_win *vop_win = to_vop_win(plane);
 884         const struct vop_win_data *win = vop_win->data;
 885         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 886                                         DRM_PLANE_HELPER_NO_SCALING;
 887         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 888                                         DRM_PLANE_HELPER_NO_SCALING;
 889         struct drm_crtc_state *crtc_state;
 890
 891         if (plane != state->crtc->cursor)
 892                 return -EINVAL;
 893
 894         if (!plane->state)
 895                 return -EINVAL;
 896
 897         if (!plane->state->fb)
 898                 return -EINVAL;
 899
 900         if (state->state)
 901                 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 902                                                                 state->crtc);
 903         else /* Special case for asynchronous cursor updates. */
 904                 crtc_state = plane->crtc->state;
 905
 906         return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
 907                                                    min_scale, max_scale,
 908                                                    true, true);
 909 }
 910
 911 static void vop_plane_atomic_async_update(struct drm_plane *plane,
 912                                           struct drm_plane_state *new_state)
 913 {
 914         struct vop *vop = to_vop(plane->state->crtc);
 915         struct drm_plane_state *plane_state;
 916
 917         plane_state = plane->funcs->atomic_duplicate_state(plane);
 918         plane_state->crtc_x = new_state->crtc_x;
 919         plane_state->crtc_y = new_state->crtc_y;
 920         plane_state->crtc_h = new_state->crtc_h;
 921         plane_state->crtc_w = new_state->crtc_w;
 922         plane_state->src_x = new_state->src_x;
 923         plane_state->src_y = new_state->src_y;
 924         plane_state->src_h = new_state->src_h;
 925         plane_state->src_w = new_state->src_w;
 926
 927         if (plane_state->fb != new_state->fb)
 928                 drm_atomic_set_fb_for_plane(plane_state, new_state->fb);
 929
 930         swap(plane_state, plane->state);
 931
 932         if (plane->state->fb && plane->state->fb != new_state->fb) {
 933                 drm_framebuffer_get(plane->state->fb);
 934                 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
 935                 drm_flip_work_queue(&vop->fb_unref_work, plane->state->fb);
 936                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
 937         }
 938
 939         if (vop->is_enabled) {
 940                 rockchip_drm_psr_inhibit_get_state(new_state->state);
 941                 vop_plane_atomic_update(plane, plane->state);
 942                 spin_lock(&vop->reg_lock);
 943                 vop_cfg_done(vop);
 944                 spin_unlock(&vop->reg_lock);
 945                 rockchip_drm_psr_inhibit_put_state(new_state->state);
 946         }
 947
 948         plane->funcs->atomic_destroy_state(plane, plane_state);
 949 }
 950
 951 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 952         .atomic_check = vop_plane_atomic_check,
 953         .atomic_update = vop_plane_atomic_update,
 954         .atomic_disable = vop_plane_atomic_disable,
 955         .atomic_async_check = vop_plane_atomic_async_check,
 956         .atomic_async_update = vop_plane_atomic_async_update,
 957         .prepare_fb = drm_gem_fb_prepare_fb,
 958 };
 959
 960 static const struct drm_plane_funcs vop_plane_funcs = {
 961         .update_plane   = drm_atomic_helper_update_plane,
 962         .disable_plane  = drm_atomic_helper_disable_plane,
 963         .destroy = vop_plane_destroy,
 964         .reset = drm_atomic_helper_plane_reset,
 965         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 966         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 967 };
 968
 969 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 970 {
 971         struct vop *vop = to_vop(crtc);
 972         unsigned long flags;
 973
 974         if (WARN_ON(!vop->is_enabled))
 975                 return -EPERM;
 976
 977         spin_lock_irqsave(&vop->irq_lock, flags);
 978
 979         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
 980         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 981
 982         spin_unlock_irqrestore(&vop->irq_lock, flags);
 983
 984         return 0;
 985 }
 986
 987 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 988 {
 989         struct vop *vop = to_vop(crtc);
 990         unsigned long flags;
 991
 992         if (WARN_ON(!vop->is_enabled))
 993                 return;
 994
 995         spin_lock_irqsave(&vop->irq_lock, flags);
 996
 997         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 998
 999         spin_unlock_irqrestore(&vop->irq_lock, flags);
1000 }
1001
1002 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1003                                 const struct drm_display_mode *mode,
1004                                 struct drm_display_mode *adjusted_mode)
1005 {
1006         struct vop *vop = to_vop(crtc);
1007
1008         adjusted_mode->clock =
1009                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1010
1011         return true;
1012 }
1013
1014 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1015                                    struct drm_crtc_state *old_state)
1016 {
1017         struct vop *vop = to_vop(crtc);
1018         const struct vop_data *vop_data = vop->data;
1019         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1020         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1021         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1022         u16 hdisplay = adjusted_mode->hdisplay;
1023         u16 htotal = adjusted_mode->htotal;
1024         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1025         u16 hact_end = hact_st + hdisplay;
1026         u16 vdisplay = adjusted_mode->vdisplay;
1027         u16 vtotal = adjusted_mode->vtotal;
1028         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1029         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1030         u16 vact_end = vact_st + vdisplay;
1031         uint32_t pin_pol, val;
1032         int ret;
1033
1034         mutex_lock(&vop->vop_lock);
1035
1036         WARN_ON(vop->event);
1037
1038         ret = vop_enable(crtc);
1039         if (ret) {
1040                 mutex_unlock(&vop->vop_lock);
1041                 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1042                 return;
1043         }
1044
1045         pin_pol = BIT(DCLK_INVERT);
1046         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1047                    BIT(HSYNC_POSITIVE) : 0;
1048         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1049                    BIT(VSYNC_POSITIVE) : 0;
1050         VOP_REG_SET(vop, output, pin_pol, pin_pol);
1051         VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1052
1053         switch (s->output_type) {
1054         case DRM_MODE_CONNECTOR_LVDS:
1055                 VOP_REG_SET(vop, output, rgb_en, 1);
1056                 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1057                 break;
1058         case DRM_MODE_CONNECTOR_eDP:
1059                 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1060                 VOP_REG_SET(vop, output, edp_en, 1);
1061                 break;
1062         case DRM_MODE_CONNECTOR_HDMIA:
1063                 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1064                 VOP_REG_SET(vop, output, hdmi_en, 1);
1065                 break;
1066         case DRM_MODE_CONNECTOR_DSI:
1067                 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1068                 VOP_REG_SET(vop, output, mipi_en, 1);
1069                 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1070                             !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1071                 break;
1072         case DRM_MODE_CONNECTOR_DisplayPort:
1073                 pin_pol &= ~BIT(DCLK_INVERT);
1074                 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1075                 VOP_REG_SET(vop, output, dp_en, 1);
1076                 break;
1077         default:
1078                 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1079                               s->output_type);
1080         }
1081
1082         /*
1083          * if vop is not support RGB10 output, need force RGB10 to RGB888.
1084          */
1085         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1086             !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1087                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1088
1089         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8)
1090                 VOP_REG_SET(vop, common, pre_dither_down, 1);
1091         else
1092                 VOP_REG_SET(vop, common, pre_dither_down, 0);
1093
1094         VOP_REG_SET(vop, common, out_mode, s->output_mode);
1095
1096         VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1097         val = hact_st << 16;
1098         val |= hact_end;
1099         VOP_REG_SET(vop, modeset, hact_st_end, val);
1100         VOP_REG_SET(vop, modeset, hpost_st_end, val);
1101
1102         VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1103         val = vact_st << 16;
1104         val |= vact_end;
1105         VOP_REG_SET(vop, modeset, vact_st_end, val);
1106         VOP_REG_SET(vop, modeset, vpost_st_end, val);
1107
1108         VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1109
1110         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1111
1112         VOP_REG_SET(vop, common, standby, 0);
1113         mutex_unlock(&vop->vop_lock);
1114 }
1115
1116 static bool vop_fs_irq_is_pending(struct vop *vop)
1117 {
1118         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1119 }
1120
1121 static void vop_wait_for_irq_handler(struct vop *vop)
1122 {
1123         bool pending;
1124         int ret;
1125
1126         /*
1127          * Spin until frame start interrupt status bit goes low, which means
1128          * that interrupt handler was invoked and cleared it. The timeout of
1129          * 10 msecs is really too long, but it is just a safety measure if
1130          * something goes really wrong. The wait will only happen in the very
1131          * unlikely case of a vblank happening exactly at the same time and
1132          * shouldn't exceed microseconds range.
1133          */
1134         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1135                                         !pending, 0, 10 * 1000);
1136         if (ret)
1137                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1138
1139         synchronize_irq(vop->irq);
1140 }
1141
1142 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1143                                   struct drm_crtc_state *old_crtc_state)
1144 {
1145         struct drm_atomic_state *old_state = old_crtc_state->state;
1146         struct drm_plane_state *old_plane_state, *new_plane_state;
1147         struct vop *vop = to_vop(crtc);
1148         struct drm_plane *plane;
1149         int i;
1150
1151         if (WARN_ON(!vop->is_enabled))
1152                 return;
1153
1154         spin_lock(&vop->reg_lock);
1155
1156         vop_cfg_done(vop);
1157
1158         spin_unlock(&vop->reg_lock);
1159
1160         /*
1161          * There is a (rather unlikely) possiblity that a vblank interrupt
1162          * fired before we set the cfg_done bit. To avoid spuriously
1163          * signalling flip completion we need to wait for it to finish.
1164          */
1165         vop_wait_for_irq_handler(vop);
1166
1167         spin_lock_irq(&crtc->dev->event_lock);
1168         if (crtc->state->event) {
1169                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1170                 WARN_ON(vop->event);
1171
1172                 vop->event = crtc->state->event;
1173                 crtc->state->event = NULL;
1174         }
1175         spin_unlock_irq(&crtc->dev->event_lock);
1176
1177         for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1178                                        new_plane_state, i) {
1179                 if (!old_plane_state->fb)
1180                         continue;
1181
1182                 if (old_plane_state->fb == new_plane_state->fb)
1183                         continue;
1184
1185                 drm_framebuffer_get(old_plane_state->fb);
1186                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1187                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1188                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1189         }
1190 }
1191
1192 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1193         .mode_fixup = vop_crtc_mode_fixup,
1194         .atomic_flush = vop_crtc_atomic_flush,
1195         .atomic_enable = vop_crtc_atomic_enable,
1196         .atomic_disable = vop_crtc_atomic_disable,
1197 };
1198
1199 static void vop_crtc_destroy(struct drm_crtc *crtc)
1200 {
1201         drm_crtc_cleanup(crtc);
1202 }
1203
1204 static void vop_crtc_reset(struct drm_crtc *crtc)
1205 {
1206         if (crtc->state)
1207                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1208         kfree(crtc->state);
1209
1210         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1211         if (crtc->state)
1212                 crtc->state->crtc = crtc;
1213 }
1214
1215 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1216 {
1217         struct rockchip_crtc_state *rockchip_state;
1218
1219         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1220         if (!rockchip_state)
1221                 return NULL;
1222
1223         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1224         return &rockchip_state->base;
1225 }
1226
1227 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1228                                    struct drm_crtc_state *state)
1229 {
1230         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1231
1232         __drm_atomic_helper_crtc_destroy_state(&s->base);
1233         kfree(s);
1234 }
1235
1236 #ifdef CONFIG_DRM_ANALOGIX_DP
1237 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1238 {
1239         struct drm_connector *connector;
1240         struct drm_connector_list_iter conn_iter;
1241
1242         drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1243         drm_for_each_connector_iter(connector, &conn_iter) {
1244                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1245                         drm_connector_list_iter_end(&conn_iter);
1246                         return connector;
1247                 }
1248         }
1249         drm_connector_list_iter_end(&conn_iter);
1250
1251         return NULL;
1252 }
1253
1254 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1255                                    const char *source_name)
1256 {
1257         struct vop *vop = to_vop(crtc);
1258         struct drm_connector *connector;
1259         int ret;
1260
1261         connector = vop_get_edp_connector(vop);
1262         if (!connector)
1263                 return -EINVAL;
1264
1265         if (source_name && strcmp(source_name, "auto") == 0)
1266                 ret = analogix_dp_start_crc(connector);
1267         else if (!source_name)
1268                 ret = analogix_dp_stop_crc(connector);
1269         else
1270                 ret = -EINVAL;
1271
1272         return ret;
1273 }
1274
1275 static int
1276 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1277                            size_t *values_cnt)
1278 {
1279         if (source_name && strcmp(source_name, "auto") != 0)
1280                 return -EINVAL;
1281
1282         *values_cnt = 3;
1283         return 0;
1284 }
1285
1286 #else
1287 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1288                                    const char *source_name)
1289 {
1290         return -ENODEV;
1291 }
1292
1293 static int
1294 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1295                            size_t *values_cnt)
1296 {
1297         return -ENODEV;
1298 }
1299 #endif
1300
1301 static const struct drm_crtc_funcs vop_crtc_funcs = {
1302         .set_config = drm_atomic_helper_set_config,
1303         .page_flip = drm_atomic_helper_page_flip,
1304         .destroy = vop_crtc_destroy,
1305         .reset = vop_crtc_reset,
1306         .atomic_duplicate_state = vop_crtc_duplicate_state,
1307         .atomic_destroy_state = vop_crtc_destroy_state,
1308         .enable_vblank = vop_crtc_enable_vblank,
1309         .disable_vblank = vop_crtc_disable_vblank,
1310         .set_crc_source = vop_crtc_set_crc_source,
1311         .verify_crc_source = vop_crtc_verify_crc_source,
1312 };
1313
1314 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1315 {
1316         struct vop *vop = container_of(work, struct vop, fb_unref_work);
1317         struct drm_framebuffer *fb = val;
1318
1319         drm_crtc_vblank_put(&vop->crtc);
1320         drm_framebuffer_put(fb);
1321 }
1322
1323 static void vop_handle_vblank(struct vop *vop)
1324 {
1325         struct drm_device *drm = vop->drm_dev;
1326         struct drm_crtc *crtc = &vop->crtc;
1327
1328         spin_lock(&drm->event_lock);
1329         if (vop->event) {
1330                 drm_crtc_send_vblank_event(crtc, vop->event);
1331                 drm_crtc_vblank_put(crtc);
1332                 vop->event = NULL;
1333         }
1334         spin_unlock(&drm->event_lock);
1335
1336         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1337                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1338 }
1339
1340 static irqreturn_t vop_isr(int irq, void *data)
1341 {
1342         struct vop *vop = data;
1343         struct drm_crtc *crtc = &vop->crtc;
1344         uint32_t active_irqs;
1345         int ret = IRQ_NONE;
1346
1347         /*
1348          * The irq is shared with the iommu. If the runtime-pm state of the
1349          * vop-device is disabled the irq has to be targeted at the iommu.
1350          */
1351         if (!pm_runtime_get_if_in_use(vop->dev))
1352                 return IRQ_NONE;
1353
1354         if (vop_core_clks_enable(vop)) {
1355                 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1356                 goto out;
1357         }
1358
1359         /*
1360          * interrupt register has interrupt status, enable and clear bits, we
1361          * must hold irq_lock to avoid a race with enable/disable_vblank().
1362         */
1363         spin_lock(&vop->irq_lock);
1364
1365         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1366         /* Clear all active interrupt sources */
1367         if (active_irqs)
1368                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1369
1370         spin_unlock(&vop->irq_lock);
1371
1372         /* This is expected for vop iommu irqs, since the irq is shared */
1373         if (!active_irqs)
1374                 goto out_disable;
1375
1376         if (active_irqs & DSP_HOLD_VALID_INTR) {
1377                 complete(&vop->dsp_hold_completion);
1378                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1379                 ret = IRQ_HANDLED;
1380         }
1381
1382         if (active_irqs & LINE_FLAG_INTR) {
1383                 complete(&vop->line_flag_completion);
1384                 active_irqs &= ~LINE_FLAG_INTR;
1385                 ret = IRQ_HANDLED;
1386         }
1387
1388         if (active_irqs & FS_INTR) {
1389                 drm_crtc_handle_vblank(crtc);
1390                 vop_handle_vblank(vop);
1391                 active_irqs &= ~FS_INTR;
1392                 ret = IRQ_HANDLED;
1393         }
1394
1395         /* Unhandled irqs are spurious. */
1396         if (active_irqs)
1397                 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1398                               active_irqs);
1399
1400 out_disable:
1401         vop_core_clks_disable(vop);
1402 out:
1403         pm_runtime_put(vop->dev);
1404         return ret;
1405 }
1406
1407 static void vop_plane_add_properties(struct drm_plane *plane,
1408                                      const struct vop_win_data *win_data)
1409 {
1410         unsigned int flags = 0;
1411
1412         flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1413         flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1414         if (flags)
1415                 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1416                                                    DRM_MODE_ROTATE_0 | flags);
1417 }
1418
1419 static int vop_create_crtc(struct vop *vop)
1420 {
1421         const struct vop_data *vop_data = vop->data;
1422         struct device *dev = vop->dev;
1423         struct drm_device *drm_dev = vop->drm_dev;
1424         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1425         struct drm_crtc *crtc = &vop->crtc;
1426         struct device_node *port;
1427         int ret;
1428         int i;
1429
1430         /*
1431          * Create drm_plane for primary and cursor planes first, since we need
1432          * to pass them to drm_crtc_init_with_planes, which sets the
1433          * "possible_crtcs" to the newly initialized crtc.
1434          */
1435         for (i = 0; i < vop_data->win_size; i++) {
1436                 struct vop_win *vop_win = &vop->win[i];
1437                 const struct vop_win_data *win_data = vop_win->data;
1438
1439                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1440                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1441                         continue;
1442
1443                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1444                                                0, &vop_plane_funcs,
1445                                                win_data->phy->data_formats,
1446                                                win_data->phy->nformats,
1447                                                NULL, win_data->type, NULL);
1448                 if (ret) {
1449                         DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1450                                       ret);
1451                         goto err_cleanup_planes;
1452                 }
1453
1454                 plane = &vop_win->base;
1455                 drm_plane_helper_add(plane, &plane_helper_funcs);
1456                 vop_plane_add_properties(plane, win_data);
1457                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1458                         primary = plane;
1459                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1460                         cursor = plane;
1461         }
1462
1463         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1464                                         &vop_crtc_funcs, NULL);
1465         if (ret)
1466                 goto err_cleanup_planes;
1467
1468         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1469
1470         /*
1471          * Create drm_planes for overlay windows with possible_crtcs restricted
1472          * to the newly created crtc.
1473          */
1474         for (i = 0; i < vop_data->win_size; i++) {
1475                 struct vop_win *vop_win = &vop->win[i];
1476                 const struct vop_win_data *win_data = vop_win->data;
1477                 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1478
1479                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1480                         continue;
1481
1482                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1483                                                possible_crtcs,
1484                                                &vop_plane_funcs,
1485                                                win_data->phy->data_formats,
1486                                                win_data->phy->nformats,
1487                                                NULL, win_data->type, NULL);
1488                 if (ret) {
1489                         DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1490                                       ret);
1491                         goto err_cleanup_crtc;
1492                 }
1493                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1494                 vop_plane_add_properties(&vop_win->base, win_data);
1495         }
1496
1497         port = of_get_child_by_name(dev->of_node, "port");
1498         if (!port) {
1499                 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1500                               dev->of_node);
1501                 ret = -ENOENT;
1502                 goto err_cleanup_crtc;
1503         }
1504
1505         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1506                            vop_fb_unref_worker);
1507
1508         init_completion(&vop->dsp_hold_completion);
1509         init_completion(&vop->line_flag_completion);
1510         crtc->port = port;
1511
1512         return 0;
1513
1514 err_cleanup_crtc:
1515         drm_crtc_cleanup(crtc);
1516 err_cleanup_planes:
1517         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1518                                  head)
1519                 drm_plane_cleanup(plane);
1520         return ret;
1521 }
1522
1523 static void vop_destroy_crtc(struct vop *vop)
1524 {
1525         struct drm_crtc *crtc = &vop->crtc;
1526         struct drm_device *drm_dev = vop->drm_dev;
1527         struct drm_plane *plane, *tmp;
1528
1529         of_node_put(crtc->port);
1530
1531         /*
1532          * We need to cleanup the planes now.  Why?
1533          *
1534          * The planes are "&vop->win[i].base".  That means the memory is
1535          * all part of the big "struct vop" chunk of memory.  That memory
1536          * was devm allocated and associated with this component.  We need to
1537          * free it ourselves before vop_unbind() finishes.
1538          */
1539         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1540                                  head)
1541                 vop_plane_destroy(plane);
1542
1543         /*
1544          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1545          * references the CRTC.
1546          */
1547         drm_crtc_cleanup(crtc);
1548         drm_flip_work_cleanup(&vop->fb_unref_work);
1549 }
1550
1551 static int vop_initial(struct vop *vop)
1552 {
1553         const struct vop_data *vop_data = vop->data;
1554         struct reset_control *ahb_rst;
1555         int i, ret;
1556
1557         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1558         if (IS_ERR(vop->hclk)) {
1559                 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1560                 return PTR_ERR(vop->hclk);
1561         }
1562         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1563         if (IS_ERR(vop->aclk)) {
1564                 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1565                 return PTR_ERR(vop->aclk);
1566         }
1567         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1568         if (IS_ERR(vop->dclk)) {
1569                 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1570                 return PTR_ERR(vop->dclk);
1571         }
1572
1573         ret = pm_runtime_get_sync(vop->dev);
1574         if (ret < 0) {
1575                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1576                 return ret;
1577         }
1578
1579         ret = clk_prepare(vop->dclk);
1580         if (ret < 0) {
1581                 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1582                 goto err_put_pm_runtime;
1583         }
1584
1585         /* Enable both the hclk and aclk to setup the vop */
1586         ret = clk_prepare_enable(vop->hclk);
1587         if (ret < 0) {
1588                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1589                 goto err_unprepare_dclk;
1590         }
1591
1592         ret = clk_prepare_enable(vop->aclk);
1593         if (ret < 0) {
1594                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1595                 goto err_disable_hclk;
1596         }
1597
1598         /*
1599          * do hclk_reset, reset all vop registers.
1600          */
1601         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1602         if (IS_ERR(ahb_rst)) {
1603                 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1604                 ret = PTR_ERR(ahb_rst);
1605                 goto err_disable_aclk;
1606         }
1607         reset_control_assert(ahb_rst);
1608         usleep_range(10, 20);
1609         reset_control_deassert(ahb_rst);
1610
1611         VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1612         VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1613
1614         for (i = 0; i < vop->len; i += sizeof(u32))
1615                 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1616
1617         VOP_REG_SET(vop, misc, global_regdone_en, 1);
1618         VOP_REG_SET(vop, common, dsp_blank, 0);
1619
1620         for (i = 0; i < vop_data->win_size; i++) {
1621                 const struct vop_win_data *win = &vop_data->win[i];
1622                 int channel = i * 2 + 1;
1623
1624                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1625                 VOP_WIN_SET(vop, win, enable, 0);
1626                 VOP_WIN_SET(vop, win, gate, 1);
1627         }
1628
1629         vop_cfg_done(vop);
1630
1631         /*
1632          * do dclk_reset, let all config take affect.
1633          */
1634         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1635         if (IS_ERR(vop->dclk_rst)) {
1636                 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1637                 ret = PTR_ERR(vop->dclk_rst);
1638                 goto err_disable_aclk;
1639         }
1640         reset_control_assert(vop->dclk_rst);
1641         usleep_range(10, 20);
1642         reset_control_deassert(vop->dclk_rst);
1643
1644         clk_disable(vop->hclk);
1645         clk_disable(vop->aclk);
1646
1647         vop->is_enabled = false;
1648
1649         pm_runtime_put_sync(vop->dev);
1650
1651         return 0;
1652
1653 err_disable_aclk:
1654         clk_disable_unprepare(vop->aclk);
1655 err_disable_hclk:
1656         clk_disable_unprepare(vop->hclk);
1657 err_unprepare_dclk:
1658         clk_unprepare(vop->dclk);
1659 err_put_pm_runtime:
1660         pm_runtime_put_sync(vop->dev);
1661         return ret;
1662 }
1663
1664 /*
1665  * Initialize the vop->win array elements.
1666  */
1667 static void vop_win_init(struct vop *vop)
1668 {
1669         const struct vop_data *vop_data = vop->data;
1670         unsigned int i;
1671
1672         for (i = 0; i < vop_data->win_size; i++) {
1673                 struct vop_win *vop_win = &vop->win[i];
1674                 const struct vop_win_data *win_data = &vop_data->win[i];
1675
1676                 vop_win->data = win_data;
1677                 vop_win->vop = vop;
1678                 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
1679         }
1680 }
1681
1682 /**
1683  * rockchip_drm_wait_vact_end
1684  * @crtc: CRTC to enable line flag
1685  * @mstimeout: millisecond for timeout
1686  *
1687  * Wait for vact_end line flag irq or timeout.
1688  *
1689  * Returns:
1690  * Zero on success, negative errno on failure.
1691  */
1692 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1693 {
1694         struct vop *vop = to_vop(crtc);
1695         unsigned long jiffies_left;
1696         int ret = 0;
1697
1698         if (!crtc || !vop->is_enabled)
1699                 return -ENODEV;
1700
1701         mutex_lock(&vop->vop_lock);
1702         if (mstimeout <= 0) {
1703                 ret = -EINVAL;
1704                 goto out;
1705         }
1706
1707         if (vop_line_flag_irq_is_enabled(vop)) {
1708                 ret = -EBUSY;
1709                 goto out;
1710         }
1711
1712         reinit_completion(&vop->line_flag_completion);
1713         vop_line_flag_irq_enable(vop);
1714
1715         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1716                                                    msecs_to_jiffies(mstimeout));
1717         vop_line_flag_irq_disable(vop);
1718
1719         if (jiffies_left == 0) {
1720                 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
1721                 ret = -ETIMEDOUT;
1722                 goto out;
1723         }
1724
1725 out:
1726         mutex_unlock(&vop->vop_lock);
1727         return ret;
1728 }
1729 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1730
1731 static int vop_bind(struct device *dev, struct device *master, void *data)
1732 {
1733         struct platform_device *pdev = to_platform_device(dev);
1734         const struct vop_data *vop_data;
1735         struct drm_device *drm_dev = data;
1736         struct vop *vop;
1737         struct resource *res;
1738         int ret, irq;
1739
1740         vop_data = of_device_get_match_data(dev);
1741         if (!vop_data)
1742                 return -ENODEV;
1743
1744         /* Allocate vop struct and its vop_win array */
1745         vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
1746                            GFP_KERNEL);
1747         if (!vop)
1748                 return -ENOMEM;
1749
1750         vop->dev = dev;
1751         vop->data = vop_data;
1752         vop->drm_dev = drm_dev;
1753         dev_set_drvdata(dev, vop);
1754
1755         vop_win_init(vop);
1756
1757         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1758         vop->len = resource_size(res);
1759         vop->regs = devm_ioremap_resource(dev, res);
1760         if (IS_ERR(vop->regs))
1761                 return PTR_ERR(vop->regs);
1762
1763         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1764         if (!vop->regsbak)
1765                 return -ENOMEM;
1766
1767         irq = platform_get_irq(pdev, 0);
1768         if (irq < 0) {
1769                 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
1770                 return irq;
1771         }
1772         vop->irq = (unsigned int)irq;
1773
1774         spin_lock_init(&vop->reg_lock);
1775         spin_lock_init(&vop->irq_lock);
1776         mutex_init(&vop->vop_lock);
1777
1778         ret = vop_create_crtc(vop);
1779         if (ret)
1780                 return ret;
1781
1782         pm_runtime_enable(&pdev->dev);
1783
1784         ret = vop_initial(vop);
1785         if (ret < 0) {
1786                 DRM_DEV_ERROR(&pdev->dev,
1787                               "cannot initial vop dev - err %d\n", ret);
1788                 goto err_disable_pm_runtime;
1789         }
1790
1791         ret = devm_request_irq(dev, vop->irq, vop_isr,
1792                                IRQF_SHARED, dev_name(dev), vop);
1793         if (ret)
1794                 goto err_disable_pm_runtime;
1795
1796         if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
1797                 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
1798                 if (IS_ERR(vop->rgb)) {
1799                         ret = PTR_ERR(vop->rgb);
1800                         goto err_disable_pm_runtime;
1801                 }
1802         }
1803
1804         return 0;
1805
1806 err_disable_pm_runtime:
1807         pm_runtime_disable(&pdev->dev);
1808         vop_destroy_crtc(vop);
1809         return ret;
1810 }
1811
1812 static void vop_unbind(struct device *dev, struct device *master, void *data)
1813 {
1814         struct vop *vop = dev_get_drvdata(dev);
1815
1816         if (vop->rgb)
1817                 rockchip_rgb_fini(vop->rgb);
1818
1819         pm_runtime_disable(dev);
1820         vop_destroy_crtc(vop);
1821
1822         clk_unprepare(vop->aclk);
1823         clk_unprepare(vop->hclk);
1824         clk_unprepare(vop->dclk);
1825 }
1826
1827 const struct component_ops vop_component_ops = {
1828         .bind = vop_bind,
1829         .unbind = vop_unbind,
1830 };
1831 EXPORT_SYMBOL_GPL(vop_component_ops);