drivers/gpu/drm/rcar-du/rcar_lvds.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * rcar_lvds.c  --  R-Car LVDS Encoder
   4  *
   5  * Copyright (C) 2013-2018 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_bridge.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drm_probe_helper.h>
  25
  26 #include "rcar_lvds.h"
  27 #include "rcar_lvds_regs.h"
  28
  29 struct rcar_lvds;
  30
  31 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
  32 enum rcar_lvds_mode {
  33         RCAR_LVDS_MODE_JEIDA = 0,
  34         RCAR_LVDS_MODE_MIRROR = 1,
  35         RCAR_LVDS_MODE_VESA = 4,
  36 };
  37
  38 #define RCAR_LVDS_QUIRK_LANES           BIT(0)  /* LVDS lanes 1 and 3 inverted */
  39 #define RCAR_LVDS_QUIRK_GEN3_LVEN       BIT(1)  /* LVEN bit needs to be set on R8A77970/R8A7799x */
  40 #define RCAR_LVDS_QUIRK_PWD             BIT(2)  /* PWD bit available (all of Gen3 but E3) */
  41 #define RCAR_LVDS_QUIRK_EXT_PLL         BIT(3)  /* Has extended PLL */
  42 #define RCAR_LVDS_QUIRK_DUAL_LINK       BIT(4)  /* Supports dual-link operation */
  43
  44 struct rcar_lvds_device_info {
  45         unsigned int gen;
  46         unsigned int quirks;
  47         void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
  48 };
  49
  50 struct rcar_lvds {
  51         struct device *dev;
  52         const struct rcar_lvds_device_info *info;
  53
  54         struct drm_bridge bridge;
  55
  56         struct drm_bridge *next_bridge;
  57         struct drm_connector connector;
  58         struct drm_panel *panel;
  59
  60         void __iomem *mmio;
  61         struct {
  62                 struct clk *mod;                /* CPG module clock */
  63                 struct clk *extal;              /* External clock */
  64                 struct clk *dotclkin[2];        /* External DU clocks */
  65         } clocks;
  66         bool enabled;
  67
  68         struct drm_display_mode display_mode;
  69         enum rcar_lvds_mode mode;
  70 };
  71
  72 #define bridge_to_rcar_lvds(bridge) \
  73         container_of(bridge, struct rcar_lvds, bridge)
  74
  75 #define connector_to_rcar_lvds(connector) \
  76         container_of(connector, struct rcar_lvds, connector)
  77
  78 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
  79 {
  80         iowrite32(data, lvds->mmio + reg);
  81 }
  82
  83 /* -----------------------------------------------------------------------------
  84  * Connector & Panel
  85  */
  86
  87 static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
  88 {
  89         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
  90
  91         return drm_panel_get_modes(lvds->panel);
  92 }
  93
  94 static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
  95                                             struct drm_connector_state *state)
  96 {
  97         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
  98         const struct drm_display_mode *panel_mode;
  99         struct drm_crtc_state *crtc_state;
 100
 101         if (!state->crtc)
 102                 return 0;
 103
 104         if (list_empty(&connector->modes)) {
 105                 dev_dbg(lvds->dev, "connector: empty modes list\n");
 106                 return -EINVAL;
 107         }
 108
 109         panel_mode = list_first_entry(&connector->modes,
 110                                       struct drm_display_mode, head);
 111
 112         /* We're not allowed to modify the resolution. */
 113         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 114         if (IS_ERR(crtc_state))
 115                 return PTR_ERR(crtc_state);
 116
 117         if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
 118             crtc_state->mode.vdisplay != panel_mode->vdisplay)
 119                 return -EINVAL;
 120
 121         /* The flat panel mode is fixed, just copy it to the adjusted mode. */
 122         drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
 123
 124         return 0;
 125 }
 126
 127 static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
 128         .get_modes = rcar_lvds_connector_get_modes,
 129         .atomic_check = rcar_lvds_connector_atomic_check,
 130 };
 131
 132 static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
 133         .reset = drm_atomic_helper_connector_reset,
 134         .fill_modes = drm_helper_probe_single_connector_modes,
 135         .destroy = drm_connector_cleanup,
 136         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 137         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 138 };
 139
 140 /* -----------------------------------------------------------------------------
 141  * PLL Setup
 142  */
 143
 144 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
 145 {
 146         u32 val;
 147
 148         if (freq < 39000000)
 149                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
 150         else if (freq < 61000000)
 151                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
 152         else if (freq < 121000000)
 153                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
 154         else
 155                 val = LVDPLLCR_PLLDLYCNT_150M;
 156
 157         rcar_lvds_write(lvds, LVDPLLCR, val);
 158 }
 159
 160 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
 161 {
 162         u32 val;
 163
 164         if (freq < 42000000)
 165                 val = LVDPLLCR_PLLDIVCNT_42M;
 166         else if (freq < 85000000)
 167                 val = LVDPLLCR_PLLDIVCNT_85M;
 168         else if (freq < 128000000)
 169                 val = LVDPLLCR_PLLDIVCNT_128M;
 170         else
 171                 val = LVDPLLCR_PLLDIVCNT_148M;
 172
 173         rcar_lvds_write(lvds, LVDPLLCR, val);
 174 }
 175
 176 struct pll_info {
 177         unsigned long diff;
 178         unsigned int pll_m;
 179         unsigned int pll_n;
 180         unsigned int pll_e;
 181         unsigned int div;
 182         u32 clksel;
 183 };
 184
 185 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
 186                                      unsigned long target, struct pll_info *pll,
 187                                      u32 clksel, bool dot_clock_only)
 188 {
 189         unsigned int div7 = dot_clock_only ? 1 : 7;
 190         unsigned long output;
 191         unsigned long fin;
 192         unsigned int m_min;
 193         unsigned int m_max;
 194         unsigned int m;
 195         int error;
 196
 197         if (!clk)
 198                 return;
 199
 200         /*
 201          * The LVDS PLL is made of a pre-divider and a multiplier (strangely
 202          * enough called M and N respectively), followed by a post-divider E.
 203          *
 204          *         ,-----.         ,-----.     ,-----.         ,-----.
 205          * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
 206          *         `-----'     ,-> |     |     `-----'   |     `-----'
 207          *                     |   `-----'               |
 208          *                     |         ,-----.         |
 209          *                     `-------- | 1/N | <-------'
 210          *                               `-----'
 211          *
 212          * The clock output by the PLL is then further divided by a programmable
 213          * divider DIV to achieve the desired target frequency. Finally, an
 214          * optional fixed /7 divider is used to convert the bit clock to a pixel
 215          * clock (as LVDS transmits 7 bits per lane per clock sample).
 216          *
 217          *          ,-------.     ,-----.     |\
 218          * Fout --> | 1/DIV | --> | 1/7 | --> | |
 219          *          `-------'  |  `-----'     | | --> dot clock
 220          *                     `------------> | |
 221          *                                    |/
 222          *
 223          * The /7 divider is optional, it is enabled when the LVDS PLL is used
 224          * to drive the LVDS encoder, and disabled when  used to generate a dot
 225          * clock for the DU RGB output, without using the LVDS encoder.
 226          *
 227          * The PLL allowed input frequency range is 12 MHz to 192 MHz.
 228          */
 229
 230         fin = clk_get_rate(clk);
 231         if (fin < 12000000 || fin > 192000000)
 232                 return;
 233
 234         /*
 235          * The comparison frequency range is 12 MHz to 24 MHz, which limits the
 236          * allowed values for the pre-divider M (normal range 1-8).
 237          *
 238          * Fpfd = Fin / M
 239          */
 240         m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
 241         m_max = min_t(unsigned int, 8, fin / 12000000);
 242
 243         for (m = m_min; m <= m_max; ++m) {
 244                 unsigned long fpfd;
 245                 unsigned int n_min;
 246                 unsigned int n_max;
 247                 unsigned int n;
 248
 249                 /*
 250                  * The VCO operating range is 900 Mhz to 1800 MHz, which limits
 251                  * the allowed values for the multiplier N (normal range
 252                  * 60-120).
 253                  *
 254                  * Fvco = Fin * N / M
 255                  */
 256                 fpfd = fin / m;
 257                 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
 258                 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
 259
 260                 for (n = n_min; n < n_max; ++n) {
 261                         unsigned long fvco;
 262                         unsigned int e_min;
 263                         unsigned int e;
 264
 265                         /*
 266                          * The output frequency is limited to 1039.5 MHz,
 267                          * limiting again the allowed values for the
 268                          * post-divider E (normal value 1, 2 or 4).
 269                          *
 270                          * Fout = Fvco / E
 271                          */
 272                         fvco = fpfd * n;
 273                         e_min = fvco > 1039500000 ? 1 : 0;
 274
 275                         for (e = e_min; e < 3; ++e) {
 276                                 unsigned long fout;
 277                                 unsigned long diff;
 278                                 unsigned int div;
 279
 280                                 /*
 281                                  * Finally we have a programable divider after
 282                                  * the PLL, followed by a an optional fixed /7
 283                                  * divider.
 284                                  */
 285                                 fout = fvco / (1 << e) / div7;
 286                                 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
 287                                 diff = abs(fout / div - target);
 288
 289                                 if (diff < pll->diff) {
 290                                         pll->diff = diff;
 291                                         pll->pll_m = m;
 292                                         pll->pll_n = n;
 293                                         pll->pll_e = e;
 294                                         pll->div = div;
 295                                         pll->clksel = clksel;
 296
 297                                         if (diff == 0)
 298                                                 goto done;
 299                                 }
 300                         }
 301                 }
 302         }
 303
 304 done:
 305         output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
 306                / div7 / pll->div;
 307         error = (long)(output - target) * 10000 / (long)target;
 308
 309         dev_dbg(lvds->dev,
 310                 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
 311                 clk, fin, output, target, error / 100,
 312                 error < 0 ? -error % 100 : error % 100,
 313                 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
 314 }
 315
 316 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
 317                                         unsigned int freq, bool dot_clock_only)
 318 {
 319         struct pll_info pll = { .diff = (unsigned long)-1 };
 320         u32 lvdpllcr;
 321
 322         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
 323                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
 324         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
 325                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
 326         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
 327                                  LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
 328
 329         lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
 330                  | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
 331
 332         if (pll.pll_e > 0)
 333                 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
 334                          |  LVDPLLCR_PLLE(pll.pll_e - 1);
 335
 336         if (dot_clock_only)
 337                 lvdpllcr |= LVDPLLCR_OCKSEL;
 338
 339         rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
 340
 341         if (pll.div > 1)
 342                 /*
 343                  * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
 344                  * divisor reset.
 345                  */
 346                 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
 347                                 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
 348         else
 349                 rcar_lvds_write(lvds, LVDDIV, 0);
 350 }
 351
 352 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
 353 {
 354         __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
 355 }
 356
 357 /* -----------------------------------------------------------------------------
 358  * Clock - D3/E3 only
 359  */
 360
 361 int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
 362 {
 363         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 364         int ret;
 365
 366         if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
 367                 return -ENODEV;
 368
 369         dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
 370
 371         WARN_ON(lvds->enabled);
 372
 373         ret = clk_prepare_enable(lvds->clocks.mod);
 374         if (ret < 0)
 375                 return ret;
 376
 377         __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
 378
 379         lvds->enabled = true;
 380         return 0;
 381 }
 382 EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
 383
 384 void rcar_lvds_clk_disable(struct drm_bridge *bridge)
 385 {
 386         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 387
 388         if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
 389                 return;
 390
 391         dev_dbg(lvds->dev, "disabling LVDS PLL\n");
 392
 393         WARN_ON(!lvds->enabled);
 394
 395         rcar_lvds_write(lvds, LVDPLLCR, 0);
 396
 397         clk_disable_unprepare(lvds->clocks.mod);
 398
 399         lvds->enabled = false;
 400 }
 401 EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
 402
 403 /* -----------------------------------------------------------------------------
 404  * Bridge
 405  */
 406
 407 static void rcar_lvds_enable(struct drm_bridge *bridge)
 408 {
 409         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 410         const struct drm_display_mode *mode = &lvds->display_mode;
 411         /*
 412          * FIXME: We should really retrieve the CRTC through the state, but how
 413          * do we get a state pointer?
 414          */
 415         struct drm_crtc *crtc = lvds->bridge.encoder->crtc;
 416         u32 lvdhcr;
 417         u32 lvdcr0;
 418         int ret;
 419
 420         WARN_ON(lvds->enabled);
 421
 422         ret = clk_prepare_enable(lvds->clocks.mod);
 423         if (ret < 0)
 424                 return;
 425
 426         /*
 427          * Hardcode the channels and control signals routing for now.
 428          *
 429          * HSYNC -> CTRL0
 430          * VSYNC -> CTRL1
 431          * DISP  -> CTRL2
 432          * 0     -> CTRL3
 433          */
 434         rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
 435                         LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
 436                         LVDCTRCR_CTR0SEL_HSYNC);
 437
 438         if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
 439                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
 440                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
 441         else
 442                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
 443                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
 444
 445         rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
 446
 447         if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
 448                 /* Disable dual-link mode. */
 449                 rcar_lvds_write(lvds, LVDSTRIPE, 0);
 450         }
 451
 452         /* PLL clock configuration. */
 453         lvds->info->pll_setup(lvds, mode->clock * 1000);
 454
 455         /* Set the LVDS mode and select the input. */
 456         lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
 457         if (drm_crtc_index(crtc) == 2)
 458                 lvdcr0 |= LVDCR0_DUSEL;
 459         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 460
 461         /* Turn all the channels on. */
 462         rcar_lvds_write(lvds, LVDCR1,
 463                         LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
 464                         LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
 465
 466         if (lvds->info->gen < 3) {
 467                 /* Enable LVDS operation and turn the bias circuitry on. */
 468                 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
 469                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 470         }
 471
 472         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 473                 /*
 474                  * Turn the PLL on (simple PLL only, extended PLL is fully
 475                  * controlled through LVDPLLCR).
 476                  */
 477                 lvdcr0 |= LVDCR0_PLLON;
 478                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 479         }
 480
 481         if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
 482                 /* Set LVDS normal mode. */
 483                 lvdcr0 |= LVDCR0_PWD;
 484                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 485         }
 486
 487         if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
 488                 /*
 489                  * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
 490                  * set at the same time, so don't write the register yet.
 491                  */
 492                 lvdcr0 |= LVDCR0_LVEN;
 493                 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
 494                         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 495         }
 496
 497         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 498                 /* Wait for the PLL startup delay (simple PLL only). */
 499                 usleep_range(100, 150);
 500         }
 501
 502         /* Turn the output on. */
 503         lvdcr0 |= LVDCR0_LVRES;
 504         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 505
 506         if (lvds->panel) {
 507                 drm_panel_prepare(lvds->panel);
 508                 drm_panel_enable(lvds->panel);
 509         }
 510
 511         lvds->enabled = true;
 512 }
 513
 514 static void rcar_lvds_disable(struct drm_bridge *bridge)
 515 {
 516         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 517
 518         WARN_ON(!lvds->enabled);
 519
 520         if (lvds->panel) {
 521                 drm_panel_disable(lvds->panel);
 522                 drm_panel_unprepare(lvds->panel);
 523         }
 524
 525         rcar_lvds_write(lvds, LVDCR0, 0);
 526         rcar_lvds_write(lvds, LVDCR1, 0);
 527         rcar_lvds_write(lvds, LVDPLLCR, 0);
 528
 529         clk_disable_unprepare(lvds->clocks.mod);
 530
 531         lvds->enabled = false;
 532 }
 533
 534 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
 535                                  const struct drm_display_mode *mode,
 536                                  struct drm_display_mode *adjusted_mode)
 537 {
 538         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 539         int min_freq;
 540
 541         /*
 542          * The internal LVDS encoder has a restricted clock frequency operating
 543          * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
 544          * 148.5MHz on all other platforms. Clamp the clock accordingly.
 545          */
 546         min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
 547         adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
 548
 549         return true;
 550 }
 551
 552 static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
 553 {
 554         struct drm_display_info *info = &lvds->connector.display_info;
 555         enum rcar_lvds_mode mode;
 556
 557         /*
 558          * There is no API yet to retrieve LVDS mode from a bridge, only panels
 559          * are supported.
 560          */
 561         if (!lvds->panel)
 562                 return;
 563
 564         if (!info->num_bus_formats || !info->bus_formats) {
 565                 dev_err(lvds->dev, "no LVDS bus format reported\n");
 566                 return;
 567         }
 568
 569         switch (info->bus_formats[0]) {
 570         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 571         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 572                 mode = RCAR_LVDS_MODE_JEIDA;
 573                 break;
 574         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 575                 mode = RCAR_LVDS_MODE_VESA;
 576                 break;
 577         default:
 578                 dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
 579                         info->bus_formats[0]);
 580                 return;
 581         }
 582
 583         if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
 584                 mode |= RCAR_LVDS_MODE_MIRROR;
 585
 586         lvds->mode = mode;
 587 }
 588
 589 static void rcar_lvds_mode_set(struct drm_bridge *bridge,
 590                                const struct drm_display_mode *mode,
 591                                const struct drm_display_mode *adjusted_mode)
 592 {
 593         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 594
 595         WARN_ON(lvds->enabled);
 596
 597         lvds->display_mode = *adjusted_mode;
 598
 599         rcar_lvds_get_lvds_mode(lvds);
 600 }
 601
 602 static int rcar_lvds_attach(struct drm_bridge *bridge)
 603 {
 604         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 605         struct drm_connector *connector = &lvds->connector;
 606         struct drm_encoder *encoder = bridge->encoder;
 607         int ret;
 608
 609         /* If we have a next bridge just attach it. */
 610         if (lvds->next_bridge)
 611                 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
 612                                          bridge);
 613
 614         /* Otherwise if we have a panel, create a connector. */
 615         if (!lvds->panel)
 616                 return 0;
 617
 618         ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
 619                                  DRM_MODE_CONNECTOR_LVDS);
 620         if (ret < 0)
 621                 return ret;
 622
 623         drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
 624
 625         ret = drm_connector_attach_encoder(connector, encoder);
 626         if (ret < 0)
 627                 return ret;
 628
 629         return drm_panel_attach(lvds->panel, connector);
 630 }
 631
 632 static void rcar_lvds_detach(struct drm_bridge *bridge)
 633 {
 634         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 635
 636         if (lvds->panel)
 637                 drm_panel_detach(lvds->panel);
 638 }
 639
 640 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
 641         .attach = rcar_lvds_attach,
 642         .detach = rcar_lvds_detach,
 643         .enable = rcar_lvds_enable,
 644         .disable = rcar_lvds_disable,
 645         .mode_fixup = rcar_lvds_mode_fixup,
 646         .mode_set = rcar_lvds_mode_set,
 647 };
 648
 649 /* -----------------------------------------------------------------------------
 650  * Probe & Remove
 651  */
 652
 653 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
 654 {
 655         struct device_node *local_output = NULL;
 656         struct device_node *remote_input = NULL;
 657         struct device_node *remote = NULL;
 658         struct device_node *node;
 659         bool is_bridge = false;
 660         int ret = 0;
 661
 662         local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
 663         if (!local_output) {
 664                 dev_dbg(lvds->dev, "unconnected port@1\n");
 665                 ret = -ENODEV;
 666                 goto done;
 667         }
 668
 669         /*
 670          * Locate the connected entity and infer its type from the number of
 671          * endpoints.
 672          */
 673         remote = of_graph_get_remote_port_parent(local_output);
 674         if (!remote) {
 675                 dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
 676                 ret = -ENODEV;
 677                 goto done;
 678         }
 679
 680         if (!of_device_is_available(remote)) {
 681                 dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
 682                         remote);
 683                 ret = -ENODEV;
 684                 goto done;
 685         }
 686
 687         remote_input = of_graph_get_remote_endpoint(local_output);
 688
 689         for_each_endpoint_of_node(remote, node) {
 690                 if (node != remote_input) {
 691                         /*
 692                          * We've found one endpoint other than the input, this
 693                          * must be a bridge.
 694                          */
 695                         is_bridge = true;
 696                         of_node_put(node);
 697                         break;
 698                 }
 699         }
 700
 701         if (is_bridge) {
 702                 lvds->next_bridge = of_drm_find_bridge(remote);
 703                 if (!lvds->next_bridge)
 704                         ret = -EPROBE_DEFER;
 705         } else {
 706                 lvds->panel = of_drm_find_panel(remote);
 707                 if (IS_ERR(lvds->panel))
 708                         ret = PTR_ERR(lvds->panel);
 709         }
 710
 711 done:
 712         of_node_put(local_output);
 713         of_node_put(remote_input);
 714         of_node_put(remote);
 715
 716         /*
 717          * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
 718          * used for the DPAD output even when the LVDS output is not connected.
 719          * Don't fail probe in that case as the DU will need the bridge to
 720          * control the clock.
 721          */
 722         if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
 723                 return ret == -ENODEV ? 0 : ret;
 724
 725         return ret;
 726 }
 727
 728 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
 729                                        bool optional)
 730 {
 731         struct clk *clk;
 732
 733         clk = devm_clk_get(lvds->dev, name);
 734         if (!IS_ERR(clk))
 735                 return clk;
 736
 737         if (PTR_ERR(clk) == -ENOENT && optional)
 738                 return NULL;
 739
 740         if (PTR_ERR(clk) != -EPROBE_DEFER)
 741                 dev_err(lvds->dev, "failed to get %s clock\n",
 742                         name ? name : "module");
 743
 744         return clk;
 745 }
 746
 747 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
 748 {
 749         lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
 750         if (IS_ERR(lvds->clocks.mod))
 751                 return PTR_ERR(lvds->clocks.mod);
 752
 753         /*
 754          * LVDS encoders without an extended PLL have no external clock inputs.
 755          */
 756         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
 757                 return 0;
 758
 759         lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
 760         if (IS_ERR(lvds->clocks.extal))
 761                 return PTR_ERR(lvds->clocks.extal);
 762
 763         lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
 764         if (IS_ERR(lvds->clocks.dotclkin[0]))
 765                 return PTR_ERR(lvds->clocks.dotclkin[0]);
 766
 767         lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
 768         if (IS_ERR(lvds->clocks.dotclkin[1]))
 769                 return PTR_ERR(lvds->clocks.dotclkin[1]);
 770
 771         /* At least one input to the PLL must be available. */
 772         if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
 773             !lvds->clocks.dotclkin[1]) {
 774                 dev_err(lvds->dev,
 775                         "no input clock (extal, dclkin.0 or dclkin.1)\n");
 776                 return -EINVAL;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int rcar_lvds_probe(struct platform_device *pdev)
 783 {
 784         struct rcar_lvds *lvds;
 785         struct resource *mem;
 786         int ret;
 787
 788         lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
 789         if (lvds == NULL)
 790                 return -ENOMEM;
 791
 792         platform_set_drvdata(pdev, lvds);
 793
 794         lvds->dev = &pdev->dev;
 795         lvds->info = of_device_get_match_data(&pdev->dev);
 796         lvds->enabled = false;
 797
 798         ret = rcar_lvds_parse_dt(lvds);
 799         if (ret < 0)
 800                 return ret;
 801
 802         lvds->bridge.driver_private = lvds;
 803         lvds->bridge.funcs = &rcar_lvds_bridge_ops;
 804         lvds->bridge.of_node = pdev->dev.of_node;
 805
 806         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 807         lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
 808         if (IS_ERR(lvds->mmio))
 809                 return PTR_ERR(lvds->mmio);
 810
 811         ret = rcar_lvds_get_clocks(lvds);
 812         if (ret < 0)
 813                 return ret;
 814
 815         drm_bridge_add(&lvds->bridge);
 816
 817         return 0;
 818 }
 819
 820 static int rcar_lvds_remove(struct platform_device *pdev)
 821 {
 822         struct rcar_lvds *lvds = platform_get_drvdata(pdev);
 823
 824         drm_bridge_remove(&lvds->bridge);
 825
 826         return 0;
 827 }
 828
 829 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
 830         .gen = 2,
 831         .pll_setup = rcar_lvds_pll_setup_gen2,
 832 };
 833
 834 static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
 835         .gen = 2,
 836         .quirks = RCAR_LVDS_QUIRK_LANES,
 837         .pll_setup = rcar_lvds_pll_setup_gen2,
 838 };
 839
 840 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
 841         .gen = 3,
 842         .quirks = RCAR_LVDS_QUIRK_PWD,
 843         .pll_setup = rcar_lvds_pll_setup_gen3,
 844 };
 845
 846 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
 847         .gen = 3,
 848         .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
 849         .pll_setup = rcar_lvds_pll_setup_gen2,
 850 };
 851
 852 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
 853         .gen = 3,
 854         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
 855                 | RCAR_LVDS_QUIRK_DUAL_LINK,
 856         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 857 };
 858
 859 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
 860         .gen = 3,
 861         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
 862                 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
 863         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 864 };
 865
 866 static const struct of_device_id rcar_lvds_of_table[] = {
 867         { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
 868         { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
 869         { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
 870         { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
 871         { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
 872         { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
 873         { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
 874         { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
 875         { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
 876         { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
 877         { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
 878         { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
 879         { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
 880         { }
 881 };
 882
 883 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
 884
 885 static struct platform_driver rcar_lvds_platform_driver = {
 886         .probe          = rcar_lvds_probe,
 887         .remove         = rcar_lvds_remove,
 888         .driver         = {
 889                 .name   = "rcar-lvds",
 890                 .of_match_table = rcar_lvds_of_table,
 891         },
 892 };
 893
 894 module_platform_driver(rcar_lvds_platform_driver);
 895
 896 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
 897 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
 898 MODULE_LICENSE("GPL");