drivers/gpu/drm/rcar-du/rcar_du_kms.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rcar_du_kms.c  --  R-Car Display Unit Mode Setting
   4  *
   5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <drm/drm_atomic.h>
  11 #include <drm/drm_atomic_helper.h>
  12 #include <drm/drm_crtc.h>
  13 #include <drm/drm_device.h>
  14 #include <drm/drm_fb_cma_helper.h>
  15 #include <drm/drm_gem_cma_helper.h>
  16 #include <drm/drm_gem_framebuffer_helper.h>
  17 #include <drm/drm_probe_helper.h>
  18 #include <drm/drm_vblank.h>
  19
  20 #include <linux/of_graph.h>
  21 #include <linux/wait.h>
  22
  23 #include "rcar_du_crtc.h"
  24 #include "rcar_du_drv.h"
  25 #include "rcar_du_encoder.h"
  26 #include "rcar_du_kms.h"
  27 #include "rcar_du_regs.h"
  28 #include "rcar_du_vsp.h"
  29 #include "rcar_du_writeback.h"
  30
  31 /* -----------------------------------------------------------------------------
  32  * Format helpers
  33  */
  34
  35 static const struct rcar_du_format_info rcar_du_format_infos[] = {
  36         {
  37                 .fourcc = DRM_FORMAT_RGB565,
  38                 .v4l2 = V4L2_PIX_FMT_RGB565,
  39                 .bpp = 16,
  40                 .planes = 1,
  41                 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
  42                 .edf = PnDDCR4_EDF_NONE,
  43         }, {
  44                 .fourcc = DRM_FORMAT_ARGB1555,
  45                 .v4l2 = V4L2_PIX_FMT_ARGB555,
  46                 .bpp = 16,
  47                 .planes = 1,
  48                 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
  49                 .edf = PnDDCR4_EDF_NONE,
  50         }, {
  51                 .fourcc = DRM_FORMAT_XRGB1555,
  52                 .v4l2 = V4L2_PIX_FMT_XRGB555,
  53                 .bpp = 16,
  54                 .planes = 1,
  55                 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
  56                 .edf = PnDDCR4_EDF_NONE,
  57         }, {
  58                 .fourcc = DRM_FORMAT_XRGB8888,
  59                 .v4l2 = V4L2_PIX_FMT_XBGR32,
  60                 .bpp = 32,
  61                 .planes = 1,
  62                 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
  63                 .edf = PnDDCR4_EDF_RGB888,
  64         }, {
  65                 .fourcc = DRM_FORMAT_ARGB8888,
  66                 .v4l2 = V4L2_PIX_FMT_ABGR32,
  67                 .bpp = 32,
  68                 .planes = 1,
  69                 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
  70                 .edf = PnDDCR4_EDF_ARGB8888,
  71         }, {
  72                 .fourcc = DRM_FORMAT_UYVY,
  73                 .v4l2 = V4L2_PIX_FMT_UYVY,
  74                 .bpp = 16,
  75                 .planes = 1,
  76                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  77                 .edf = PnDDCR4_EDF_NONE,
  78         }, {
  79                 .fourcc = DRM_FORMAT_YUYV,
  80                 .v4l2 = V4L2_PIX_FMT_YUYV,
  81                 .bpp = 16,
  82                 .planes = 1,
  83                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  84                 .edf = PnDDCR4_EDF_NONE,
  85         }, {
  86                 .fourcc = DRM_FORMAT_NV12,
  87                 .v4l2 = V4L2_PIX_FMT_NV12M,
  88                 .bpp = 12,
  89                 .planes = 2,
  90                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  91                 .edf = PnDDCR4_EDF_NONE,
  92         }, {
  93                 .fourcc = DRM_FORMAT_NV21,
  94                 .v4l2 = V4L2_PIX_FMT_NV21M,
  95                 .bpp = 12,
  96                 .planes = 2,
  97                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  98                 .edf = PnDDCR4_EDF_NONE,
  99         }, {
 100                 .fourcc = DRM_FORMAT_NV16,
 101                 .v4l2 = V4L2_PIX_FMT_NV16M,
 102                 .bpp = 16,
 103                 .planes = 2,
 104                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
 105                 .edf = PnDDCR4_EDF_NONE,
 106         },
 107         /*
 108          * The following formats are not supported on Gen2 and thus have no
 109          * associated .pnmr or .edf settings.
 110          */
 111         {
 112                 .fourcc = DRM_FORMAT_RGB332,
 113                 .v4l2 = V4L2_PIX_FMT_RGB332,
 114                 .bpp = 8,
 115                 .planes = 1,
 116         }, {
 117                 .fourcc = DRM_FORMAT_ARGB4444,
 118                 .v4l2 = V4L2_PIX_FMT_ARGB444,
 119                 .bpp = 16,
 120                 .planes = 1,
 121         }, {
 122                 .fourcc = DRM_FORMAT_XRGB4444,
 123                 .v4l2 = V4L2_PIX_FMT_XRGB444,
 124                 .bpp = 16,
 125                 .planes = 1,
 126         }, {
 127                 .fourcc = DRM_FORMAT_BGR888,
 128                 .v4l2 = V4L2_PIX_FMT_RGB24,
 129                 .bpp = 24,
 130                 .planes = 1,
 131         }, {
 132                 .fourcc = DRM_FORMAT_RGB888,
 133                 .v4l2 = V4L2_PIX_FMT_BGR24,
 134                 .bpp = 24,
 135                 .planes = 1,
 136         }, {
 137                 .fourcc = DRM_FORMAT_BGRA8888,
 138                 .v4l2 = V4L2_PIX_FMT_ARGB32,
 139                 .bpp = 32,
 140                 .planes = 1,
 141         }, {
 142                 .fourcc = DRM_FORMAT_BGRX8888,
 143                 .v4l2 = V4L2_PIX_FMT_XRGB32,
 144                 .bpp = 32,
 145                 .planes = 1,
 146         }, {
 147                 .fourcc = DRM_FORMAT_YVYU,
 148                 .v4l2 = V4L2_PIX_FMT_YVYU,
 149                 .bpp = 16,
 150                 .planes = 1,
 151         }, {
 152                 .fourcc = DRM_FORMAT_NV61,
 153                 .v4l2 = V4L2_PIX_FMT_NV61M,
 154                 .bpp = 16,
 155                 .planes = 2,
 156         }, {
 157                 .fourcc = DRM_FORMAT_YUV420,
 158                 .v4l2 = V4L2_PIX_FMT_YUV420M,
 159                 .bpp = 12,
 160                 .planes = 3,
 161         }, {
 162                 .fourcc = DRM_FORMAT_YVU420,
 163                 .v4l2 = V4L2_PIX_FMT_YVU420M,
 164                 .bpp = 12,
 165                 .planes = 3,
 166         }, {
 167                 .fourcc = DRM_FORMAT_YUV422,
 168                 .v4l2 = V4L2_PIX_FMT_YUV422M,
 169                 .bpp = 16,
 170                 .planes = 3,
 171         }, {
 172                 .fourcc = DRM_FORMAT_YVU422,
 173                 .v4l2 = V4L2_PIX_FMT_YVU422M,
 174                 .bpp = 16,
 175                 .planes = 3,
 176         }, {
 177                 .fourcc = DRM_FORMAT_YUV444,
 178                 .v4l2 = V4L2_PIX_FMT_YUV444M,
 179                 .bpp = 24,
 180                 .planes = 3,
 181         }, {
 182                 .fourcc = DRM_FORMAT_YVU444,
 183                 .v4l2 = V4L2_PIX_FMT_YVU444M,
 184                 .bpp = 24,
 185                 .planes = 3,
 186         },
 187 };
 188
 189 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc)
 190 {
 191         unsigned int i;
 192
 193         for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) {
 194                 if (rcar_du_format_infos[i].fourcc == fourcc)
 195                         return &rcar_du_format_infos[i];
 196         }
 197
 198         return NULL;
 199 }
 200
 201 /* -----------------------------------------------------------------------------
 202  * Frame buffer
 203  */
 204
 205 int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
 206                         struct drm_mode_create_dumb *args)
 207 {
 208         struct rcar_du_device *rcdu = dev->dev_private;
 209         unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
 210         unsigned int align;
 211
 212         /*
 213          * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
 214          * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
 215          */
 216         if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
 217                 align = 128;
 218         else
 219                 align = 16 * args->bpp / 8;
 220
 221         args->pitch = roundup(min_pitch, align);
 222
 223         return drm_gem_cma_dumb_create_internal(file, dev, args);
 224 }
 225
 226 static struct drm_framebuffer *
 227 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
 228                   const struct drm_mode_fb_cmd2 *mode_cmd)
 229 {
 230         struct rcar_du_device *rcdu = dev->dev_private;
 231         const struct rcar_du_format_info *format;
 232         unsigned int max_pitch;
 233         unsigned int align;
 234         unsigned int i;
 235
 236         format = rcar_du_format_info(mode_cmd->pixel_format);
 237         if (format == NULL) {
 238                 dev_dbg(dev->dev, "unsupported pixel format %08x\n",
 239                         mode_cmd->pixel_format);
 240                 return ERR_PTR(-EINVAL);
 241         }
 242
 243         if (rcdu->info->gen < 3) {
 244                 /*
 245                  * On Gen2 the DU limits the pitch to 4095 pixels and requires
 246                  * buffers to be aligned to a 16 pixels boundary (or 128 bytes
 247                  * on some platforms).
 248                  */
 249                 unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
 250
 251                 max_pitch = 4095 * bpp;
 252
 253                 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
 254                         align = 128;
 255                 else
 256                         align = 16 * bpp;
 257         } else {
 258                 /*
 259                  * On Gen3 the memory interface is handled by the VSP that
 260                  * limits the pitch to 65535 bytes and has no alignment
 261                  * constraint.
 262                  */
 263                 max_pitch = 65535;
 264                 align = 1;
 265         }
 266
 267         if (mode_cmd->pitches[0] & (align - 1) ||
 268             mode_cmd->pitches[0] > max_pitch) {
 269                 dev_dbg(dev->dev, "invalid pitch value %u\n",
 270                         mode_cmd->pitches[0]);
 271                 return ERR_PTR(-EINVAL);
 272         }
 273
 274         for (i = 1; i < format->planes; ++i) {
 275                 if (mode_cmd->pitches[i] != mode_cmd->pitches[0]) {
 276                         dev_dbg(dev->dev,
 277                                 "luma and chroma pitches do not match\n");
 278                         return ERR_PTR(-EINVAL);
 279                 }
 280         }
 281
 282         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 283 }
 284
 285 /* -----------------------------------------------------------------------------
 286  * Atomic Check and Update
 287  */
 288
 289 static int rcar_du_atomic_check(struct drm_device *dev,
 290                                 struct drm_atomic_state *state)
 291 {
 292         struct rcar_du_device *rcdu = dev->dev_private;
 293         int ret;
 294
 295         ret = drm_atomic_helper_check(dev, state);
 296         if (ret)
 297                 return ret;
 298
 299         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
 300                 return 0;
 301
 302         return rcar_du_atomic_check_planes(dev, state);
 303 }
 304
 305 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
 306 {
 307         struct drm_device *dev = old_state->dev;
 308         struct rcar_du_device *rcdu = dev->dev_private;
 309         struct drm_crtc_state *crtc_state;
 310         struct drm_crtc *crtc;
 311         unsigned int i;
 312
 313         /*
 314          * Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
 315          * when starting the CRTCs.
 316          */
 317         rcdu->dpad1_source = -1;
 318
 319         for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
 320                 struct rcar_du_crtc_state *rcrtc_state =
 321                         to_rcar_crtc_state(crtc_state);
 322                 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 323
 324                 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
 325                         rcdu->dpad0_source = rcrtc->index;
 326
 327                 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
 328                         rcdu->dpad1_source = rcrtc->index;
 329         }
 330
 331         /* Apply the atomic update. */
 332         drm_atomic_helper_commit_modeset_disables(dev, old_state);
 333         drm_atomic_helper_commit_planes(dev, old_state,
 334                                         DRM_PLANE_COMMIT_ACTIVE_ONLY);
 335         drm_atomic_helper_commit_modeset_enables(dev, old_state);
 336
 337         drm_atomic_helper_commit_hw_done(old_state);
 338         drm_atomic_helper_wait_for_flip_done(dev, old_state);
 339
 340         drm_atomic_helper_cleanup_planes(dev, old_state);
 341 }
 342
 343 /* -----------------------------------------------------------------------------
 344  * Initialization
 345  */
 346
 347 static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
 348         .atomic_commit_tail = rcar_du_atomic_commit_tail,
 349 };
 350
 351 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
 352         .fb_create = rcar_du_fb_create,
 353         .atomic_check = rcar_du_atomic_check,
 354         .atomic_commit = drm_atomic_helper_commit,
 355 };
 356
 357 static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
 358                                      enum rcar_du_output output,
 359                                      struct of_endpoint *ep)
 360 {
 361         struct device_node *entity;
 362         int ret;
 363
 364         /* Locate the connected entity and initialize the encoder. */
 365         entity = of_graph_get_remote_port_parent(ep->local_node);
 366         if (!entity) {
 367                 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
 368                         ep->local_node);
 369                 return -ENODEV;
 370         }
 371
 372         if (!of_device_is_available(entity)) {
 373                 dev_dbg(rcdu->dev,
 374                         "connected entity %pOF is disabled, skipping\n",
 375                         entity);
 376                 of_node_put(entity);
 377                 return -ENODEV;
 378         }
 379
 380         ret = rcar_du_encoder_init(rcdu, output, entity);
 381         if (ret && ret != -EPROBE_DEFER)
 382                 dev_warn(rcdu->dev,
 383                          "failed to initialize encoder %pOF on output %u (%d), skipping\n",
 384                          entity, output, ret);
 385
 386         of_node_put(entity);
 387
 388         return ret;
 389 }
 390
 391 static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
 392 {
 393         struct device_node *np = rcdu->dev->of_node;
 394         struct device_node *ep_node;
 395         unsigned int num_encoders = 0;
 396
 397         /*
 398          * Iterate over the endpoints and create one encoder for each output
 399          * pipeline.
 400          */
 401         for_each_endpoint_of_node(np, ep_node) {
 402                 enum rcar_du_output output;
 403                 struct of_endpoint ep;
 404                 unsigned int i;
 405                 int ret;
 406
 407                 ret = of_graph_parse_endpoint(ep_node, &ep);
 408                 if (ret < 0) {
 409                         of_node_put(ep_node);
 410                         return ret;
 411                 }
 412
 413                 /* Find the output route corresponding to the port number. */
 414                 for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
 415                         if (rcdu->info->routes[i].possible_crtcs &&
 416                             rcdu->info->routes[i].port == ep.port) {
 417                                 output = i;
 418                                 break;
 419                         }
 420                 }
 421
 422                 if (i == RCAR_DU_OUTPUT_MAX) {
 423                         dev_warn(rcdu->dev,
 424                                  "port %u references unexisting output, skipping\n",
 425                                  ep.port);
 426                         continue;
 427                 }
 428
 429                 /* Process the output pipeline. */
 430                 ret = rcar_du_encoders_init_one(rcdu, output, &ep);
 431                 if (ret < 0) {
 432                         if (ret == -EPROBE_DEFER) {
 433                                 of_node_put(ep_node);
 434                                 return ret;
 435                         }
 436
 437                         continue;
 438                 }
 439
 440                 num_encoders++;
 441         }
 442
 443         return num_encoders;
 444 }
 445
 446 static int rcar_du_properties_init(struct rcar_du_device *rcdu)
 447 {
 448         /*
 449          * The color key is expressed as an RGB888 triplet stored in a 32-bit
 450          * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
 451          * or enable source color keying (1).
 452          */
 453         rcdu->props.colorkey =
 454                 drm_property_create_range(rcdu->ddev, 0, "colorkey",
 455                                           0, 0x01ffffff);
 456         if (rcdu->props.colorkey == NULL)
 457                 return -ENOMEM;
 458
 459         return 0;
 460 }
 461
 462 static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
 463 {
 464         const struct device_node *np = rcdu->dev->of_node;
 465         struct of_phandle_args args;
 466         struct {
 467                 struct device_node *np;
 468                 unsigned int crtcs_mask;
 469         } vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
 470         unsigned int vsps_count = 0;
 471         unsigned int cells;
 472         unsigned int i;
 473         int ret;
 474
 475         /*
 476          * First parse the DT vsps property to populate the list of VSPs. Each
 477          * entry contains a pointer to the VSP DT node and a bitmask of the
 478          * connected DU CRTCs.
 479          */
 480         cells = of_property_count_u32_elems(np, "vsps") / rcdu->num_crtcs - 1;
 481         if (cells > 1)
 482                 return -EINVAL;
 483
 484         for (i = 0; i < rcdu->num_crtcs; ++i) {
 485                 unsigned int j;
 486
 487                 ret = of_parse_phandle_with_fixed_args(np, "vsps", cells, i,
 488                                                        &args);
 489                 if (ret < 0)
 490                         goto error;
 491
 492                 /*
 493                  * Add the VSP to the list or update the corresponding existing
 494                  * entry if the VSP has already been added.
 495                  */
 496                 for (j = 0; j < vsps_count; ++j) {
 497                         if (vsps[j].np == args.np)
 498                                 break;
 499                 }
 500
 501                 if (j < vsps_count)
 502                         of_node_put(args.np);
 503                 else
 504                         vsps[vsps_count++].np = args.np;
 505
 506                 vsps[j].crtcs_mask |= BIT(i);
 507
 508                 /* Store the VSP pointer and pipe index in the CRTC. */
 509                 rcdu->crtcs[i].vsp = &rcdu->vsps[j];
 510                 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
 511         }
 512
 513         /*
 514          * Then initialize all the VSPs from the node pointers and CRTCs bitmask
 515          * computed previously.
 516          */
 517         for (i = 0; i < vsps_count; ++i) {
 518                 struct rcar_du_vsp *vsp = &rcdu->vsps[i];
 519
 520                 vsp->index = i;
 521                 vsp->dev = rcdu;
 522
 523                 ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
 524                 if (ret < 0)
 525                         goto error;
 526         }
 527
 528         return 0;
 529
 530 error:
 531         for (i = 0; i < ARRAY_SIZE(vsps); ++i)
 532                 of_node_put(vsps[i].np);
 533
 534         return ret;
 535 }
 536
 537 int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 538 {
 539         static const unsigned int mmio_offsets[] = {
 540                 DU0_REG_OFFSET, DU2_REG_OFFSET
 541         };
 542
 543         struct drm_device *dev = rcdu->ddev;
 544         struct drm_encoder *encoder;
 545         unsigned int dpad0_sources;
 546         unsigned int num_encoders;
 547         unsigned int num_groups;
 548         unsigned int swindex;
 549         unsigned int hwindex;
 550         unsigned int i;
 551         int ret;
 552
 553         drm_mode_config_init(dev);
 554
 555         dev->mode_config.min_width = 0;
 556         dev->mode_config.min_height = 0;
 557         dev->mode_config.normalize_zpos = true;
 558         dev->mode_config.funcs = &rcar_du_mode_config_funcs;
 559         dev->mode_config.helper_private = &rcar_du_mode_config_helper;
 560
 561         if (rcdu->info->gen < 3) {
 562                 dev->mode_config.max_width = 4095;
 563                 dev->mode_config.max_height = 2047;
 564         } else {
 565                 /*
 566                  * The Gen3 DU uses the VSP1 for memory access, and is limited
 567                  * to frame sizes of 8190x8190.
 568                  */
 569                 dev->mode_config.max_width = 8190;
 570                 dev->mode_config.max_height = 8190;
 571         }
 572
 573         rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
 574
 575         ret = rcar_du_properties_init(rcdu);
 576         if (ret < 0)
 577                 return ret;
 578
 579         /*
 580          * Initialize vertical blanking interrupts handling. Start with vblank
 581          * disabled for all CRTCs.
 582          */
 583         ret = drm_vblank_init(dev, rcdu->num_crtcs);
 584         if (ret < 0)
 585                 return ret;
 586
 587         /* Initialize the groups. */
 588         num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
 589
 590         for (i = 0; i < num_groups; ++i) {
 591                 struct rcar_du_group *rgrp = &rcdu->groups[i];
 592
 593                 mutex_init(&rgrp->lock);
 594
 595                 rgrp->dev = rcdu;
 596                 rgrp->mmio_offset = mmio_offsets[i];
 597                 rgrp->index = i;
 598                 /* Extract the channel mask for this group only. */
 599                 rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
 600                                    & GENMASK(1, 0);
 601                 rgrp->num_crtcs = hweight8(rgrp->channels_mask);
 602
 603                 /*
 604                  * If we have more than one CRTCs in this group pre-associate
 605                  * the low-order planes with CRTC 0 and the high-order planes
 606                  * with CRTC 1 to minimize flicker occurring when the
 607                  * association is changed.
 608                  */
 609                 rgrp->dptsr_planes = rgrp->num_crtcs > 1
 610                                    ? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
 611                                    : 0;
 612
 613                 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 614                         ret = rcar_du_planes_init(rgrp);
 615                         if (ret < 0)
 616                                 return ret;
 617                 }
 618         }
 619
 620         /* Initialize the compositors. */
 621         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 622                 ret = rcar_du_vsps_init(rcdu);
 623                 if (ret < 0)
 624                         return ret;
 625         }
 626
 627         /* Create the CRTCs. */
 628         for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
 629                 struct rcar_du_group *rgrp;
 630
 631                 /* Skip unpopulated DU channels. */
 632                 if (!(rcdu->info->channels_mask & BIT(hwindex)))
 633                         continue;
 634
 635                 rgrp = &rcdu->groups[hwindex / 2];
 636
 637                 ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
 638                 if (ret < 0)
 639                         return ret;
 640         }
 641
 642         /* Initialize the encoders. */
 643         ret = rcar_du_encoders_init(rcdu);
 644         if (ret < 0)
 645                 return ret;
 646
 647         if (ret == 0) {
 648                 dev_err(rcdu->dev, "error: no encoder could be initialized\n");
 649                 return -EINVAL;
 650         }
 651
 652         num_encoders = ret;
 653
 654         /*
 655          * Set the possible CRTCs and possible clones. There's always at least
 656          * one way for all encoders to clone each other, set all bits in the
 657          * possible clones field.
 658          */
 659         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 660                 struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
 661                 const struct rcar_du_output_routing *route =
 662                         &rcdu->info->routes[renc->output];
 663
 664                 encoder->possible_crtcs = route->possible_crtcs;
 665                 encoder->possible_clones = (1 << num_encoders) - 1;
 666         }
 667
 668         /* Create the writeback connectors. */
 669         if (rcdu->info->gen >= 3) {
 670                 for (i = 0; i < rcdu->num_crtcs; ++i) {
 671                         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i];
 672
 673                         ret = rcar_du_writeback_init(rcdu, rcrtc);
 674                         if (ret < 0)
 675                                 return ret;
 676                 }
 677         }
 678
 679         /*
 680          * Initialize the default DPAD0 source to the index of the first DU
 681          * channel that can be connected to DPAD0. The exact value doesn't
 682          * matter as it should be overwritten by mode setting for the RGB
 683          * output, but it is nonetheless required to ensure a valid initial
 684          * hardware configuration on Gen3 where DU0 can't always be connected to
 685          * DPAD0.
 686          */
 687         dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
 688         rcdu->dpad0_source = ffs(dpad0_sources) - 1;
 689
 690         drm_mode_config_reset(dev);
 691
 692         drm_kms_helper_poll_init(dev);
 693
 694         return 0;
 695 }