2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
36 #include <drm/drm_cache.h>
38 #include "radeon_trace.h"
41 int radeon_ttm_init(struct radeon_device *rdev);
42 void radeon_ttm_fini(struct radeon_device *rdev);
43 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
46 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
47 * function are calling it.
50 static void radeon_update_memory_usage(struct radeon_bo *bo,
51 unsigned mem_type, int sign)
53 struct radeon_device *rdev = bo->rdev;
54 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
59 atomic64_add(size, &rdev->gtt_usage);
61 atomic64_sub(size, &rdev->gtt_usage);
65 atomic64_add(size, &rdev->vram_usage);
67 atomic64_sub(size, &rdev->vram_usage);
72 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
76 bo = container_of(tbo, struct radeon_bo, tbo);
78 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
80 mutex_lock(&bo->rdev->gem.mutex);
81 list_del_init(&bo->list);
82 mutex_unlock(&bo->rdev->gem.mutex);
83 radeon_bo_clear_surface_reg(bo);
84 WARN_ON(!list_empty(&bo->va));
85 drm_gem_object_release(&bo->gem_base);
89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
91 if (bo->destroy == &radeon_ttm_bo_destroy)
96 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
100 rbo->placement.placement = rbo->placements;
101 rbo->placement.busy_placement = rbo->placements;
102 if (domain & RADEON_GEM_DOMAIN_VRAM) {
103 /* Try placing BOs which don't need CPU access outside of the
104 * CPU accessible part of VRAM
106 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
107 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
108 rbo->placements[c].fpfn =
109 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
110 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
111 TTM_PL_FLAG_UNCACHED |
115 rbo->placements[c].fpfn = 0;
116 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
117 TTM_PL_FLAG_UNCACHED |
121 if (domain & RADEON_GEM_DOMAIN_GTT) {
122 if (rbo->flags & RADEON_GEM_GTT_UC) {
123 rbo->placements[c].fpfn = 0;
124 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
127 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
128 (rbo->rdev->flags & RADEON_IS_AGP)) {
129 rbo->placements[c].fpfn = 0;
130 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
131 TTM_PL_FLAG_UNCACHED |
134 rbo->placements[c].fpfn = 0;
135 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
140 if (domain & RADEON_GEM_DOMAIN_CPU) {
141 if (rbo->flags & RADEON_GEM_GTT_UC) {
142 rbo->placements[c].fpfn = 0;
143 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
146 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
147 rbo->rdev->flags & RADEON_IS_AGP) {
148 rbo->placements[c].fpfn = 0;
149 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
150 TTM_PL_FLAG_UNCACHED |
153 rbo->placements[c].fpfn = 0;
154 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
159 rbo->placements[c].fpfn = 0;
160 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
164 rbo->placement.num_placement = c;
165 rbo->placement.num_busy_placement = c;
167 for (i = 0; i < c; ++i) {
168 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
169 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
170 !rbo->placements[i].fpfn)
171 rbo->placements[i].lpfn =
172 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
174 rbo->placements[i].lpfn = 0;
178 int radeon_bo_create(struct radeon_device *rdev,
179 unsigned long size, int byte_align, bool kernel,
180 u32 domain, u32 flags, struct sg_table *sg,
181 struct reservation_object *resv,
182 struct radeon_bo **bo_ptr)
184 struct radeon_bo *bo;
185 enum ttm_bo_type type;
186 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
190 size = ALIGN(size, PAGE_SIZE);
193 type = ttm_bo_type_kernel;
195 type = ttm_bo_type_sg;
197 type = ttm_bo_type_device;
201 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
202 sizeof(struct radeon_bo));
204 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
207 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
213 bo->surface_reg = -1;
214 INIT_LIST_HEAD(&bo->list);
215 INIT_LIST_HEAD(&bo->va);
216 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
217 RADEON_GEM_DOMAIN_GTT |
218 RADEON_GEM_DOMAIN_CPU);
221 /* PCI GART is always snooped */
222 if (!(rdev->flags & RADEON_IS_PCIE))
223 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
225 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
226 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
228 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
229 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
232 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
233 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
235 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
236 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
237 /* Don't try to enable write-combining when it can't work, or things
239 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
242 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
243 thanks to write-combining
245 if (bo->flags & RADEON_GEM_GTT_WC)
246 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
247 "better performance thanks to write-combining\n");
248 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
250 /* For architectures that don't support WC memory,
251 * mask out the WC flag from the BO
253 if (!drm_arch_can_wc_memory())
254 bo->flags &= ~RADEON_GEM_GTT_WC;
257 radeon_ttm_placement_from_domain(bo, domain);
258 /* Kernel allocation are uninterruptible */
259 down_read(&rdev->pm.mclk_lock);
260 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
261 &bo->placement, page_align, !kernel, NULL,
262 acc_size, sg, resv, &radeon_ttm_bo_destroy);
263 up_read(&rdev->pm.mclk_lock);
264 if (unlikely(r != 0)) {
269 trace_radeon_bo_create(bo);
274 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
285 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
289 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
293 radeon_bo_check_tiling(bo, 0, 0);
297 void radeon_bo_kunmap(struct radeon_bo *bo)
299 if (bo->kptr == NULL)
302 radeon_bo_check_tiling(bo, 0, 0);
303 ttm_bo_kunmap(&bo->kmap);
306 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
311 ttm_bo_reference(&bo->tbo);
315 void radeon_bo_unref(struct radeon_bo **bo)
317 struct ttm_buffer_object *tbo;
318 struct radeon_device *rdev;
329 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
334 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
340 *gpu_addr = radeon_bo_gpu_offset(bo);
342 if (max_offset != 0) {
345 if (domain == RADEON_GEM_DOMAIN_VRAM)
346 domain_start = bo->rdev->mc.vram_start;
348 domain_start = bo->rdev->mc.gtt_start;
349 WARN_ON_ONCE(max_offset <
350 (radeon_bo_gpu_offset(bo) - domain_start));
355 if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
356 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */
360 radeon_ttm_placement_from_domain(bo, domain);
361 for (i = 0; i < bo->placement.num_placement; i++) {
362 /* force to pin into visible video ram */
363 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
364 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
365 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
366 bo->placements[i].lpfn =
367 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
369 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
371 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
374 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
375 if (likely(r == 0)) {
377 if (gpu_addr != NULL)
378 *gpu_addr = radeon_bo_gpu_offset(bo);
379 if (domain == RADEON_GEM_DOMAIN_VRAM)
380 bo->rdev->vram_pin_size += radeon_bo_size(bo);
382 bo->rdev->gart_pin_size += radeon_bo_size(bo);
384 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
389 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
391 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
394 int radeon_bo_unpin(struct radeon_bo *bo)
398 if (!bo->pin_count) {
399 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
405 for (i = 0; i < bo->placement.num_placement; i++) {
406 bo->placements[i].lpfn = 0;
407 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
409 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
410 if (likely(r == 0)) {
411 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
412 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
414 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
416 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
421 int radeon_bo_evict_vram(struct radeon_device *rdev)
423 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
424 if (0 && (rdev->flags & RADEON_IS_IGP)) {
425 if (rdev->mc.igp_sideport_enabled == false)
426 /* Useless to evict on IGP chips */
429 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
432 void radeon_bo_force_delete(struct radeon_device *rdev)
434 struct radeon_bo *bo, *n;
436 if (list_empty(&rdev->gem.objects)) {
439 dev_err(rdev->dev, "Userspace still has active objects !\n");
440 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
441 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
442 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
443 *((unsigned long *)&bo->gem_base.refcount));
444 mutex_lock(&bo->rdev->gem.mutex);
445 list_del_init(&bo->list);
446 mutex_unlock(&bo->rdev->gem.mutex);
447 /* this should unref the ttm bo */
448 drm_gem_object_unreference_unlocked(&bo->gem_base);
452 int radeon_bo_init(struct radeon_device *rdev)
454 /* reserve PAT memory space to WC for VRAM */
455 arch_io_reserve_memtype_wc(rdev->mc.aper_base,
458 /* Add an MTRR for the VRAM */
459 if (!rdev->fastfb_working) {
460 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
463 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
464 rdev->mc.mc_vram_size >> 20,
465 (unsigned long long)rdev->mc.aper_size >> 20);
466 DRM_INFO("RAM width %dbits %cDR\n",
467 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
468 return radeon_ttm_init(rdev);
471 void radeon_bo_fini(struct radeon_device *rdev)
473 radeon_ttm_fini(rdev);
474 arch_phys_wc_del(rdev->mc.vram_mtrr);
475 arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size);
478 /* Returns how many bytes TTM can move per IB.
480 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
482 u64 real_vram_size = rdev->mc.real_vram_size;
483 u64 vram_usage = atomic64_read(&rdev->vram_usage);
485 /* This function is based on the current VRAM usage.
487 * - If all of VRAM is free, allow relocating the number of bytes that
488 * is equal to 1/4 of the size of VRAM for this IB.
490 * - If more than one half of VRAM is occupied, only allow relocating
491 * 1 MB of data for this IB.
493 * - From 0 to one half of used VRAM, the threshold decreases
508 * Note: It's a threshold, not a limit. The threshold must be crossed
509 * for buffer relocations to stop, so any buffer of an arbitrary size
510 * can be moved as long as the threshold isn't crossed before
511 * the relocation takes place. We don't want to disable buffer
512 * relocations completely.
514 * The idea is that buffers should be placed in VRAM at creation time
515 * and TTM should only do a minimum number of relocations during
516 * command submission. In practice, you need to submit at least
517 * a dozen IBs to move all buffers to VRAM if they are in GTT.
519 * Also, things can get pretty crazy under memory pressure and actual
520 * VRAM usage can change a lot, so playing safe even at 50% does
521 * consistently increase performance.
524 u64 half_vram = real_vram_size >> 1;
525 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
526 u64 bytes_moved_threshold = half_free_vram >> 1;
527 return max(bytes_moved_threshold, 1024*1024ull);
530 int radeon_bo_list_validate(struct radeon_device *rdev,
531 struct ww_acquire_ctx *ticket,
532 struct list_head *head, int ring)
534 struct radeon_bo_list *lobj;
535 struct list_head duplicates;
537 u64 bytes_moved = 0, initial_bytes_moved;
538 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
540 INIT_LIST_HEAD(&duplicates);
541 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
542 if (unlikely(r != 0)) {
546 list_for_each_entry(lobj, head, tv.head) {
547 struct radeon_bo *bo = lobj->robj;
548 if (!bo->pin_count) {
549 u32 domain = lobj->prefered_domains;
550 u32 allowed = lobj->allowed_domains;
552 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
554 /* Check if this buffer will be moved and don't move it
555 * if we have moved too many buffers for this IB already.
557 * Note that this allows moving at least one buffer of
558 * any size, because it doesn't take the current "bo"
559 * into account. We don't want to disallow buffer moves
562 if ((allowed & current_domain) != 0 &&
563 (domain & current_domain) == 0 && /* will be moved */
564 bytes_moved > bytes_moved_threshold) {
566 domain = current_domain;
570 radeon_ttm_placement_from_domain(bo, domain);
571 if (ring == R600_RING_TYPE_UVD_INDEX)
572 radeon_uvd_force_into_uvd_segment(bo, allowed);
574 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
575 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
576 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
580 if (r != -ERESTARTSYS &&
581 domain != lobj->allowed_domains) {
582 domain = lobj->allowed_domains;
585 ttm_eu_backoff_reservation(ticket, head);
589 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
590 lobj->tiling_flags = bo->tiling_flags;
593 list_for_each_entry(lobj, &duplicates, tv.head) {
594 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
595 lobj->tiling_flags = lobj->robj->tiling_flags;
601 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
603 struct radeon_device *rdev = bo->rdev;
604 struct radeon_surface_reg *reg;
605 struct radeon_bo *old_object;
609 lockdep_assert_held(&bo->tbo.resv->lock.base);
611 if (!bo->tiling_flags)
614 if (bo->surface_reg >= 0) {
615 reg = &rdev->surface_regs[bo->surface_reg];
621 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
623 reg = &rdev->surface_regs[i];
627 old_object = reg->bo;
628 if (old_object->pin_count == 0)
632 /* if we are all out */
633 if (i == RADEON_GEM_MAX_SURFACES) {
636 /* find someone with a surface reg and nuke their BO */
637 reg = &rdev->surface_regs[steal];
638 old_object = reg->bo;
639 /* blow away the mapping */
640 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
641 ttm_bo_unmap_virtual(&old_object->tbo);
642 old_object->surface_reg = -1;
650 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
651 bo->tbo.mem.start << PAGE_SHIFT,
652 bo->tbo.num_pages << PAGE_SHIFT);
656 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
658 struct radeon_device *rdev = bo->rdev;
659 struct radeon_surface_reg *reg;
661 if (bo->surface_reg == -1)
664 reg = &rdev->surface_regs[bo->surface_reg];
665 radeon_clear_surface_reg(rdev, bo->surface_reg);
668 bo->surface_reg = -1;
671 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
672 uint32_t tiling_flags, uint32_t pitch)
674 struct radeon_device *rdev = bo->rdev;
677 if (rdev->family >= CHIP_CEDAR) {
678 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
680 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
681 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
682 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
683 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
684 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
718 if (stilesplit > 6) {
722 r = radeon_bo_reserve(bo, false);
723 if (unlikely(r != 0))
725 bo->tiling_flags = tiling_flags;
727 radeon_bo_unreserve(bo);
731 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
732 uint32_t *tiling_flags,
735 lockdep_assert_held(&bo->tbo.resv->lock.base);
738 *tiling_flags = bo->tiling_flags;
743 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
747 lockdep_assert_held(&bo->tbo.resv->lock.base);
749 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
753 radeon_bo_clear_surface_reg(bo);
757 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
761 if (bo->surface_reg >= 0)
762 radeon_bo_clear_surface_reg(bo);
766 if ((bo->surface_reg >= 0) && !has_moved)
769 return radeon_bo_get_surface_reg(bo);
772 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
774 struct ttm_mem_reg *new_mem)
776 struct radeon_bo *rbo;
778 if (!radeon_ttm_bo_is_radeon_bo(bo))
781 rbo = container_of(bo, struct radeon_bo, tbo);
782 radeon_bo_check_tiling(rbo, 0, 1);
783 radeon_vm_bo_invalidate(rbo->rdev, rbo);
785 /* update statistics */
789 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
790 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
793 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
795 struct radeon_device *rdev;
796 struct radeon_bo *rbo;
797 unsigned long offset, size, lpfn;
800 if (!radeon_ttm_bo_is_radeon_bo(bo))
802 rbo = container_of(bo, struct radeon_bo, tbo);
803 radeon_bo_check_tiling(rbo, 0, 0);
805 if (bo->mem.mem_type != TTM_PL_VRAM)
808 size = bo->mem.num_pages << PAGE_SHIFT;
809 offset = bo->mem.start << PAGE_SHIFT;
810 if ((offset + size) <= rdev->mc.visible_vram_size)
813 /* Can't move a pinned BO to visible VRAM */
814 if (rbo->pin_count > 0)
817 /* hurrah the memory is not visible ! */
818 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
819 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
820 for (i = 0; i < rbo->placement.num_placement; i++) {
821 /* Force into visible VRAM */
822 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
823 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
824 rbo->placements[i].lpfn = lpfn;
826 r = ttm_bo_validate(bo, &rbo->placement, false, false);
827 if (unlikely(r == -ENOMEM)) {
828 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
829 return ttm_bo_validate(bo, &rbo->placement, false, false);
830 } else if (unlikely(r != 0)) {
834 offset = bo->mem.start << PAGE_SHIFT;
835 /* this should never happen */
836 if ((offset + size) > rdev->mc.visible_vram_size)
842 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
846 r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
847 if (unlikely(r != 0))
850 *mem_type = bo->tbo.mem.mem_type;
852 r = ttm_bo_wait(&bo->tbo, true, no_wait);
853 ttm_bo_unreserve(&bo->tbo);
858 * radeon_bo_fence - add fence to buffer object
860 * @bo: buffer object in question
861 * @fence: fence to add
862 * @shared: true if fence should be added shared
865 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
868 struct reservation_object *resv = bo->tbo.resv;
871 reservation_object_add_shared_fence(resv, &fence->base);
873 reservation_object_add_excl_fence(resv, &fence->base);