drivers/gpu/drm/radeon/radeon_dp_mst.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <drm/drmP.h>
   4 #include <drm/drm_dp_mst_helper.h>
   5 #include <drm/drm_fb_helper.h>
   6
   7 #include "radeon.h"
   8 #include "atom.h"
   9 #include "ni_reg.h"
  10
  11 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
  12
  13 static int radeon_atom_set_enc_offset(int id)
  14 {
  15         static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
  16                                        EVERGREEN_CRTC1_REGISTER_OFFSET,
  17                                        EVERGREEN_CRTC2_REGISTER_OFFSET,
  18                                        EVERGREEN_CRTC3_REGISTER_OFFSET,
  19                                        EVERGREEN_CRTC4_REGISTER_OFFSET,
  20                                        EVERGREEN_CRTC5_REGISTER_OFFSET,
  21                                        0x13830 - 0x7030 };
  22
  23         return offsets[id];
  24 }
  25
  26 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
  27                                      struct radeon_encoder_mst *mst_enc,
  28                                      enum radeon_hpd_id hpd, bool enable)
  29 {
  30         struct drm_device *dev = primary->base.dev;
  31         struct radeon_device *rdev = dev->dev_private;
  32         uint32_t reg;
  33         int retries = 0;
  34         uint32_t temp;
  35
  36         reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
  37
  38         /* set MST mode */
  39         reg &= ~NI_DIG_FE_DIG_MODE(7);
  40         reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
  41
  42         if (enable)
  43                 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  44         else
  45                 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  46
  47         reg |= NI_DIG_HPD_SELECT(hpd);
  48         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
  49         WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
  50
  51         if (enable) {
  52                 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
  53
  54                 do {
  55                         temp = RREG32(NI_DIG_FE_CNTL + offset);
  56                 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
  57                 if (retries == 10000)
  58                         DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
  59         }
  60         return 0;
  61 }
  62
  63 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
  64                                            int stream_number,
  65                                            int fe,
  66                                            int slots)
  67 {
  68         struct drm_device *dev = primary->base.dev;
  69         struct radeon_device *rdev = dev->dev_private;
  70         u32 temp, val;
  71         int retries  = 0;
  72         int satreg, satidx;
  73
  74         satreg = stream_number >> 1;
  75         satidx = stream_number & 1;
  76
  77         temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
  78
  79         val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
  80
  81         val <<= (16 * satidx);
  82
  83         temp &= ~(0xffff << (16 * satidx));
  84
  85         temp |= val;
  86
  87         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  88         WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  89
  90         WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
  91
  92         do {
  93                 unsigned value1, value2;
  94                 udelay(10);
  95                 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
  96
  97                 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
  98                 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
  99
 100                 if (!value1 && !value2)
 101                         break;
 102         } while (retries++ < 50);
 103
 104         if (retries == 10000)
 105                 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
 106
 107         /* MTP 16 ? */
 108         return 0;
 109 }
 110
 111 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
 112                                                struct radeon_encoder *primary)
 113 {
 114         struct drm_device *dev = mst_conn->base.dev;
 115         struct stream_attribs new_attribs[6];
 116         int i;
 117         int idx = 0;
 118         struct radeon_connector *radeon_connector;
 119         struct drm_connector *connector;
 120
 121         memset(new_attribs, 0, sizeof(new_attribs));
 122         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 123                 struct radeon_encoder *subenc;
 124                 struct radeon_encoder_mst *mst_enc;
 125
 126                 radeon_connector = to_radeon_connector(connector);
 127                 if (!radeon_connector->is_mst_connector)
 128                         continue;
 129
 130                 if (radeon_connector->mst_port != mst_conn)
 131                         continue;
 132
 133                 subenc = radeon_connector->mst_encoder;
 134                 mst_enc = subenc->enc_priv;
 135
 136                 if (!mst_enc->enc_active)
 137                         continue;
 138
 139                 new_attribs[idx].fe = mst_enc->fe;
 140                 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
 141                 idx++;
 142         }
 143
 144         for (i = 0; i < idx; i++) {
 145                 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
 146                     new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
 147                         radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
 148                         mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
 149                         mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
 150                 }
 151         }
 152
 153         for (i = idx; i < mst_conn->enabled_attribs; i++) {
 154                 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
 155                 mst_conn->cur_stream_attribs[i].fe = 0;
 156                 mst_conn->cur_stream_attribs[i].slots = 0;
 157         }
 158         mst_conn->enabled_attribs = idx;
 159         return 0;
 160 }
 161
 162 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 163 {
 164         struct drm_device *dev = mst->base.dev;
 165         struct radeon_device *rdev = dev->dev_private;
 166         struct radeon_encoder_mst *mst_enc = mst->enc_priv;
 167         uint32_t val, temp;
 168         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
 169         int retries = 0;
 170         uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
 171         uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 172
 173         val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 174
 175         WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
 176
 177         do {
 178                 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
 179                 udelay(10);
 180         } while ((temp & 0x1) && (retries++ < 10000));
 181
 182         if (retries >= 10000)
 183                 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
 184         return 0;
 185 }
 186
 187 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
 188 {
 189         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 190         struct radeon_connector *master = radeon_connector->mst_port;
 191         struct edid *edid;
 192         int ret = 0;
 193
 194         edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
 195         radeon_connector->edid = edid;
 196         DRM_DEBUG_KMS("edid retrieved %p\n", edid);
 197         if (radeon_connector->edid) {
 198                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 199                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 200                 return ret;
 201         }
 202         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 203
 204         return ret;
 205 }
 206
 207 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
 208 {
 209         return radeon_dp_mst_get_ddc_modes(connector);
 210 }
 211
 212 static enum drm_mode_status
 213 radeon_dp_mst_mode_valid(struct drm_connector *connector,
 214                         struct drm_display_mode *mode)
 215 {
 216         /* TODO - validate mode against available PBN for link */
 217         if (mode->clock < 10000)
 218                 return MODE_CLOCK_LOW;
 219
 220         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 221                 return MODE_H_ILLEGAL;
 222
 223         return MODE_OK;
 224 }
 225
 226 static struct
 227 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
 228 {
 229         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 230
 231         return &radeon_connector->mst_encoder->base;
 232 }
 233
 234 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
 235         .get_modes = radeon_dp_mst_get_modes,
 236         .mode_valid = radeon_dp_mst_mode_valid,
 237         .best_encoder = radeon_mst_best_encoder,
 238 };
 239
 240 static enum drm_connector_status
 241 radeon_dp_mst_detect(struct drm_connector *connector, bool force)
 242 {
 243         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 244         struct radeon_connector *master = radeon_connector->mst_port;
 245
 246         return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port);
 247 }
 248
 249 static void
 250 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
 251 {
 252         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 253         struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
 254
 255         drm_encoder_cleanup(&radeon_encoder->base);
 256         kfree(radeon_encoder);
 257         drm_connector_cleanup(connector);
 258         kfree(radeon_connector);
 259 }
 260
 261 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
 262         .dpms = drm_helper_connector_dpms,
 263         .detect = radeon_dp_mst_detect,
 264         .fill_modes = drm_helper_probe_single_connector_modes,
 265         .destroy = radeon_dp_mst_connector_destroy,
 266 };
 267
 268 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 269                                                          struct drm_dp_mst_port *port,
 270                                                          const char *pathprop)
 271 {
 272         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 273         struct drm_device *dev = master->base.dev;
 274         struct radeon_connector *radeon_connector;
 275         struct drm_connector *connector;
 276
 277         radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
 278         if (!radeon_connector)
 279                 return NULL;
 280
 281         radeon_connector->is_mst_connector = true;
 282         connector = &radeon_connector->base;
 283         radeon_connector->port = port;
 284         radeon_connector->mst_port = master;
 285         DRM_DEBUG_KMS("\n");
 286
 287         drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
 288         drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
 289         radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
 290
 291         drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
 292         drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
 293         drm_mode_connector_set_path_property(connector, pathprop);
 294
 295         return connector;
 296 }
 297
 298 static void radeon_dp_register_mst_connector(struct drm_connector *connector)
 299 {
 300         struct drm_device *dev = connector->dev;
 301         struct radeon_device *rdev = dev->dev_private;
 302
 303         radeon_fb_add_connector(rdev, connector);
 304
 305         drm_connector_register(connector);
 306 }
 307
 308 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 309                                             struct drm_connector *connector)
 310 {
 311         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 312         struct drm_device *dev = master->base.dev;
 313         struct radeon_device *rdev = dev->dev_private;
 314
 315         drm_connector_unregister(connector);
 316         radeon_fb_remove_connector(rdev, connector);
 317         drm_connector_cleanup(connector);
 318
 319         kfree(connector);
 320         DRM_DEBUG_KMS("\n");
 321 }
 322
 323 static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 324 {
 325         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 326         struct drm_device *dev = master->base.dev;
 327
 328         drm_kms_helper_hotplug_event(dev);
 329 }
 330
 331 static const struct drm_dp_mst_topology_cbs mst_cbs = {
 332         .add_connector = radeon_dp_add_mst_connector,
 333         .register_connector = radeon_dp_register_mst_connector,
 334         .destroy_connector = radeon_dp_destroy_mst_connector,
 335         .hotplug = radeon_dp_mst_hotplug,
 336 };
 337
 338 static struct
 339 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
 340 {
 341         struct drm_device *dev = encoder->dev;
 342         struct drm_connector *connector;
 343
 344         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 345                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 346                 if (!connector->encoder)
 347                         continue;
 348                 if (!radeon_connector->is_mst_connector)
 349                         continue;
 350
 351                 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
 352                 if (connector->encoder == encoder)
 353                         return radeon_connector;
 354         }
 355         return NULL;
 356 }
 357
 358 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 359 {
 360         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 361         struct drm_device *dev = crtc->dev;
 362         struct radeon_device *rdev = dev->dev_private;
 363         struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
 364         struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
 365         struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
 366         int dp_clock;
 367         struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
 368
 369         if (radeon_connector) {
 370                 radeon_connector->pixelclock_for_modeset = mode->clock;
 371                 if (radeon_connector->base.display_info.bpc)
 372                         radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
 373                 else
 374                         radeon_crtc->bpc = 8;
 375         }
 376
 377         DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
 378         dp_clock = dig_connector->dp_clock;
 379         radeon_crtc->ss_enabled =
 380                 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 381                                                  ASIC_INTERNAL_SS_ON_DP,
 382                                                  dp_clock);
 383 }
 384
 385 static void
 386 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 387 {
 388         struct drm_device *dev = encoder->dev;
 389         struct radeon_device *rdev = dev->dev_private;
 390         struct radeon_encoder *radeon_encoder, *primary;
 391         struct radeon_encoder_mst *mst_enc;
 392         struct radeon_encoder_atom_dig *dig_enc;
 393         struct radeon_connector *radeon_connector;
 394         struct drm_crtc *crtc;
 395         struct radeon_crtc *radeon_crtc;
 396         int ret, slots;
 397         s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
 398         if (!ASIC_IS_DCE5(rdev)) {
 399                 DRM_ERROR("got mst dpms on non-DCE5\n");
 400                 return;
 401         }
 402
 403         radeon_connector = radeon_mst_find_connector(encoder);
 404         if (!radeon_connector)
 405                 return;
 406
 407         radeon_encoder = to_radeon_encoder(encoder);
 408
 409         mst_enc = radeon_encoder->enc_priv;
 410
 411         primary = mst_enc->primary;
 412
 413         dig_enc = primary->enc_priv;
 414
 415         crtc = encoder->crtc;
 416         DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
 417
 418         switch (mode) {
 419         case DRM_MODE_DPMS_ON:
 420                 dig_enc->active_mst_links++;
 421
 422                 radeon_crtc = to_radeon_crtc(crtc);
 423
 424                 if (dig_enc->active_mst_links == 1) {
 425                         mst_enc->fe = dig_enc->dig_encoder;
 426                         mst_enc->fe_from_be = true;
 427                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 428
 429                         atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
 430                         atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
 431                                                         0, 0, dig_enc->dig_encoder);
 432
 433                         if (radeon_dp_needs_link_train(mst_enc->connector) ||
 434                             dig_enc->active_mst_links == 1) {
 435                                 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
 436                         }
 437
 438                 } else {
 439                         mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
 440                         if (mst_enc->fe == -1)
 441                                 DRM_ERROR("failed to get frontend for dig encoder\n");
 442                         mst_enc->fe_from_be = false;
 443                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 444                 }
 445
 446                 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
 447                               dig_enc->linkb, radeon_crtc->crtc_id);
 448
 449                 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
 450                                                mst_enc->pbn);
 451                 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
 452                                                radeon_connector->port,
 453                                                mst_enc->pbn, slots);
 454                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 455
 456                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 457                                           radeon_connector->mst_port->hpd.hpd, true);
 458
 459                 mst_enc->enc_active = true;
 460                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 461
 462                 fixed_pbn = drm_int2fixp(mst_enc->pbn);
 463                 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
 464                 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
 465                 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 466
 467                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
 468                                             mst_enc->fe);
 469                 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 470
 471                 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 472
 473                 break;
 474         case DRM_MODE_DPMS_STANDBY:
 475         case DRM_MODE_DPMS_SUSPEND:
 476         case DRM_MODE_DPMS_OFF:
 477                 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
 478
 479                 if (!mst_enc->enc_active)
 480                         return;
 481
 482                 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 483                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 484
 485                 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 486                 /* and this can also fail */
 487                 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 488
 489                 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 490
 491                 mst_enc->enc_active = false;
 492                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 493
 494                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 495                                           radeon_connector->mst_port->hpd.hpd, false);
 496                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
 497                                             mst_enc->fe);
 498
 499                 if (!mst_enc->fe_from_be)
 500                         radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
 501
 502                 mst_enc->fe_from_be = false;
 503                 dig_enc->active_mst_links--;
 504                 if (dig_enc->active_mst_links == 0) {
 505                         /* drop link */
 506                 }
 507
 508                 break;
 509         }
 510
 511 }
 512
 513 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
 514                                    const struct drm_display_mode *mode,
 515                                    struct drm_display_mode *adjusted_mode)
 516 {
 517         struct radeon_encoder_mst *mst_enc;
 518         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 519         struct radeon_connector_atom_dig *dig_connector;
 520         int bpp = 24;
 521
 522         mst_enc = radeon_encoder->enc_priv;
 523
 524         mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
 525
 526         mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
 527         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 528                       mst_enc->primary->active_device, mst_enc->primary->devices,
 529                       mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
 530
 531
 532         drm_mode_set_crtcinfo(adjusted_mode, 0);
 533         dig_connector = mst_enc->connector->con_priv;
 534         dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
 535         dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
 536         DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
 537                       dig_connector->dp_lane_count, dig_connector->dp_clock);
 538         return true;
 539 }
 540
 541 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
 542 {
 543         struct radeon_connector *radeon_connector;
 544         struct radeon_encoder *radeon_encoder, *primary;
 545         struct radeon_encoder_mst *mst_enc;
 546         struct radeon_encoder_atom_dig *dig_enc;
 547
 548         radeon_connector = radeon_mst_find_connector(encoder);
 549         if (!radeon_connector) {
 550                 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
 551                 return;
 552         }
 553         radeon_encoder = to_radeon_encoder(encoder);
 554
 555         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 556
 557         mst_enc = radeon_encoder->enc_priv;
 558
 559         primary = mst_enc->primary;
 560
 561         dig_enc = primary->enc_priv;
 562
 563         mst_enc->port = radeon_connector->port;
 564
 565         if (dig_enc->dig_encoder == -1) {
 566                 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
 567                 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
 568                 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
 569
 570
 571         }
 572         DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
 573 }
 574
 575 static void
 576 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
 577                              struct drm_display_mode *mode,
 578                              struct drm_display_mode *adjusted_mode)
 579 {
 580         DRM_DEBUG_KMS("\n");
 581 }
 582
 583 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
 584 {
 585         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
 586         DRM_DEBUG_KMS("\n");
 587 }
 588
 589 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
 590         .dpms = radeon_mst_encoder_dpms,
 591         .mode_fixup = radeon_mst_mode_fixup,
 592         .prepare = radeon_mst_encoder_prepare,
 593         .mode_set = radeon_mst_encoder_mode_set,
 594         .commit = radeon_mst_encoder_commit,
 595 };
 596
 597 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
 598 {
 599         drm_encoder_cleanup(encoder);
 600         kfree(encoder);
 601 }
 602
 603 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
 604         .destroy = radeon_dp_mst_encoder_destroy,
 605 };
 606
 607 static struct radeon_encoder *
 608 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
 609 {
 610         struct drm_device *dev = connector->base.dev;
 611         struct radeon_device *rdev = dev->dev_private;
 612         struct radeon_encoder *radeon_encoder;
 613         struct radeon_encoder_mst *mst_enc;
 614         struct drm_encoder *encoder;
 615         const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
 616         struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
 617
 618         DRM_DEBUG_KMS("enc master is %p\n", enc_master);
 619         radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
 620         if (!radeon_encoder)
 621                 return NULL;
 622
 623         radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
 624         if (!radeon_encoder->enc_priv) {
 625                 kfree(radeon_encoder);
 626                 return NULL;
 627         }
 628         encoder = &radeon_encoder->base;
 629         switch (rdev->num_crtc) {
 630         case 1:
 631                 encoder->possible_crtcs = 0x1;
 632                 break;
 633         case 2:
 634         default:
 635                 encoder->possible_crtcs = 0x3;
 636                 break;
 637         case 4:
 638                 encoder->possible_crtcs = 0xf;
 639                 break;
 640         case 6:
 641                 encoder->possible_crtcs = 0x3f;
 642                 break;
 643         }
 644
 645         drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
 646                          DRM_MODE_ENCODER_DPMST, NULL);
 647         drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
 648
 649         mst_enc = radeon_encoder->enc_priv;
 650         mst_enc->connector = connector;
 651         mst_enc->primary = to_radeon_encoder(enc_master);
 652         radeon_encoder->is_mst_encoder = true;
 653         return radeon_encoder;
 654 }
 655
 656 int
 657 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
 658 {
 659         struct drm_device *dev = radeon_connector->base.dev;
 660
 661         if (!radeon_connector->ddc_bus->has_aux)
 662                 return 0;
 663
 664         radeon_connector->mst_mgr.cbs = &mst_cbs;
 665         return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
 666                                             &radeon_connector->ddc_bus->aux, 16, 6,
 667                                             radeon_connector->base.base.id);
 668 }
 669
 670 int
 671 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
 672 {
 673         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 674         struct drm_device *dev = radeon_connector->base.dev;
 675         struct radeon_device *rdev = dev->dev_private;
 676         int ret;
 677         u8 msg[1];
 678
 679         if (!radeon_mst)
 680                 return 0;
 681
 682         if (!ASIC_IS_DCE5(rdev))
 683                 return 0;
 684
 685         if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
 686                 return 0;
 687
 688         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
 689                                1);
 690         if (ret) {
 691                 if (msg[0] & DP_MST_CAP) {
 692                         DRM_DEBUG_KMS("Sink is MST capable\n");
 693                         dig_connector->is_mst = true;
 694                 } else {
 695                         DRM_DEBUG_KMS("Sink is not MST capable\n");
 696                         dig_connector->is_mst = false;
 697                 }
 698
 699         }
 700         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 701                                         dig_connector->is_mst);
 702         return dig_connector->is_mst;
 703 }
 704
 705 int
 706 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
 707 {
 708         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 709         int retry;
 710
 711         if (dig_connector->is_mst) {
 712                 u8 esi[16] = { 0 };
 713                 int dret;
 714                 int ret = 0;
 715                 bool handled;
 716
 717                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 718                                        DP_SINK_COUNT_ESI, esi, 8);
 719 go_again:
 720                 if (dret == 8) {
 721                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
 722                         ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
 723
 724                         if (handled) {
 725                                 for (retry = 0; retry < 3; retry++) {
 726                                         int wret;
 727                                         wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
 728                                                                  DP_SINK_COUNT_ESI + 1, &esi[1], 3);
 729                                         if (wret == 3)
 730                                                 break;
 731                                 }
 732
 733                                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 734                                                         DP_SINK_COUNT_ESI, esi, 8);
 735                                 if (dret == 8) {
 736                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
 737                                         goto go_again;
 738                                 }
 739                         } else
 740                                 ret = 0;
 741
 742                         return ret;
 743                 } else {
 744                         DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
 745                         dig_connector->is_mst = false;
 746                         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 747                                                         dig_connector->is_mst);
 748                         /* send a hotplug event */
 749                 }
 750         }
 751         return -EINVAL;
 752 }
 753
 754 #if defined(CONFIG_DEBUG_FS)
 755
 756 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
 757 {
 758         struct drm_info_node *node = (struct drm_info_node *)m->private;
 759         struct drm_device *dev = node->minor->dev;
 760         struct drm_connector *connector;
 761         struct radeon_connector *radeon_connector;
 762         struct radeon_connector_atom_dig *dig_connector;
 763         int i;
 764
 765         drm_modeset_lock_all(dev);
 766         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 767                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 768                         continue;
 769
 770                 radeon_connector = to_radeon_connector(connector);
 771                 dig_connector = radeon_connector->con_priv;
 772                 if (radeon_connector->is_mst_connector)
 773                         continue;
 774                 if (!dig_connector->is_mst)
 775                         continue;
 776                 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
 777
 778                 for (i = 0; i < radeon_connector->enabled_attribs; i++)
 779                         seq_printf(m, "attrib %d: %d %d\n", i,
 780                                    radeon_connector->cur_stream_attribs[i].fe,
 781                                    radeon_connector->cur_stream_attribs[i].slots);
 782         }
 783         drm_modeset_unlock_all(dev);
 784         return 0;
 785 }
 786
 787 static struct drm_info_list radeon_debugfs_mst_list[] = {
 788         {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
 789 };
 790 #endif
 791
 792 int radeon_mst_debugfs_init(struct radeon_device *rdev)
 793 {
 794 #if defined(CONFIG_DEBUG_FS)
 795         return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
 796 #endif
 797         return 0;
 798 }