2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
30 #include <linux/efi.h>
31 #include <linux/pci.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/slab.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/vgaarb.h>
37 #include <drm/drm_cache.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_file.h>
41 #include <drm/drm_framebuffer.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/radeon_drm.h>
45 #include "radeon_device.h"
46 #include "radeon_reg.h"
50 static const char radeon_family_name[][16] = {
116 #if defined(CONFIG_VGA_SWITCHEROO)
117 bool radeon_has_atpx_dgpu_power_cntl(void);
118 bool radeon_is_atpx_hybrid(void);
120 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
121 static inline bool radeon_is_atpx_hybrid(void) { return false; }
124 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
126 struct radeon_px_quirk {
134 static struct radeon_px_quirk radeon_px_quirk_list[] = {
135 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
136 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
138 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
139 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
140 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
142 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
143 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
144 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
146 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
147 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
148 * https://bugs.freedesktop.org/show_bug.cgi?id=101491
150 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
151 /* Asus K73TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
152 * https://bugzilla.kernel.org/show_bug.cgi?id=51381#c52
154 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2123, RADEON_PX_QUIRK_DISABLE_PX },
158 bool radeon_is_px(struct drm_device *dev)
160 struct radeon_device *rdev = dev->dev_private;
162 if (rdev->flags & RADEON_IS_PX)
167 static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
169 struct radeon_px_quirk *p = radeon_px_quirk_list;
171 /* Apply PX quirks */
172 while (p && p->chip_device != 0) {
173 if (rdev->pdev->vendor == p->chip_vendor &&
174 rdev->pdev->device == p->chip_device &&
175 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
176 rdev->pdev->subsystem_device == p->subsys_device) {
177 rdev->px_quirk_flags = p->px_quirk_flags;
183 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
184 rdev->flags &= ~RADEON_IS_PX;
186 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */
187 if (!radeon_is_atpx_hybrid() &&
188 !radeon_has_atpx_dgpu_power_cntl())
189 rdev->flags &= ~RADEON_IS_PX;
193 * radeon_program_register_sequence - program an array of registers.
195 * @rdev: radeon_device pointer
196 * @registers: pointer to the register array
197 * @array_size: size of the register array
199 * Programs an array or registers with and and or masks.
200 * This is a helper for setting golden registers.
202 void radeon_program_register_sequence(struct radeon_device *rdev,
203 const u32 *registers,
204 const u32 array_size)
206 u32 tmp, reg, and_mask, or_mask;
212 for (i = 0; i < array_size; i +=3) {
213 reg = registers[i + 0];
214 and_mask = registers[i + 1];
215 or_mask = registers[i + 2];
217 if (and_mask == 0xffffffff) {
228 void radeon_pci_config_reset(struct radeon_device *rdev)
230 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
234 * radeon_surface_init - Clear GPU surface registers.
236 * @rdev: radeon_device pointer
238 * Clear GPU surface registers (r1xx-r5xx).
240 void radeon_surface_init(struct radeon_device *rdev)
242 /* FIXME: check this out */
243 if (rdev->family < CHIP_R600) {
246 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
247 if (rdev->surface_regs[i].bo)
248 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
250 radeon_clear_surface_reg(rdev, i);
252 /* enable surfaces */
253 WREG32(RADEON_SURFACE_CNTL, 0);
258 * GPU scratch registers helpers function.
261 * radeon_scratch_init - Init scratch register driver information.
263 * @rdev: radeon_device pointer
265 * Init CP scratch register driver information (r1xx-r5xx)
267 void radeon_scratch_init(struct radeon_device *rdev)
271 /* FIXME: check this out */
272 if (rdev->family < CHIP_R300) {
273 rdev->scratch.num_reg = 5;
275 rdev->scratch.num_reg = 7;
277 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
278 for (i = 0; i < rdev->scratch.num_reg; i++) {
279 rdev->scratch.free[i] = true;
280 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
285 * radeon_scratch_get - Allocate a scratch register
287 * @rdev: radeon_device pointer
288 * @reg: scratch register mmio offset
290 * Allocate a CP scratch register for use by the driver (all asics).
291 * Returns 0 on success or -EINVAL on failure.
293 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
297 for (i = 0; i < rdev->scratch.num_reg; i++) {
298 if (rdev->scratch.free[i]) {
299 rdev->scratch.free[i] = false;
300 *reg = rdev->scratch.reg[i];
308 * radeon_scratch_free - Free a scratch register
310 * @rdev: radeon_device pointer
311 * @reg: scratch register mmio offset
313 * Free a CP scratch register allocated for use by the driver (all asics)
315 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
319 for (i = 0; i < rdev->scratch.num_reg; i++) {
320 if (rdev->scratch.reg[i] == reg) {
321 rdev->scratch.free[i] = true;
328 * GPU doorbell aperture helpers function.
331 * radeon_doorbell_init - Init doorbell driver information.
333 * @rdev: radeon_device pointer
335 * Init doorbell driver information (CIK)
336 * Returns 0 on success, error on failure.
338 static int radeon_doorbell_init(struct radeon_device *rdev)
340 /* doorbell bar mapping */
341 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
342 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
344 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
345 if (rdev->doorbell.num_doorbells == 0)
348 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
349 if (rdev->doorbell.ptr == NULL) {
352 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
353 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
355 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
361 * radeon_doorbell_fini - Tear down doorbell driver information.
363 * @rdev: radeon_device pointer
365 * Tear down doorbell driver information (CIK)
367 static void radeon_doorbell_fini(struct radeon_device *rdev)
369 iounmap(rdev->doorbell.ptr);
370 rdev->doorbell.ptr = NULL;
374 * radeon_doorbell_get - Allocate a doorbell entry
376 * @rdev: radeon_device pointer
377 * @doorbell: doorbell index
379 * Allocate a doorbell for use by the driver (all asics).
380 * Returns 0 on success or -EINVAL on failure.
382 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
384 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
385 if (offset < rdev->doorbell.num_doorbells) {
386 __set_bit(offset, rdev->doorbell.used);
395 * radeon_doorbell_free - Free a doorbell entry
397 * @rdev: radeon_device pointer
398 * @doorbell: doorbell index
400 * Free a doorbell allocated for use by the driver (all asics)
402 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
404 if (doorbell < rdev->doorbell.num_doorbells)
405 __clear_bit(doorbell, rdev->doorbell.used);
410 * Writeback is the method by which the GPU updates special pages
411 * in memory with the status of certain GPU events (fences, ring pointers,
416 * radeon_wb_disable - Disable Writeback
418 * @rdev: radeon_device pointer
420 * Disables Writeback (all asics). Used for suspend.
422 void radeon_wb_disable(struct radeon_device *rdev)
424 rdev->wb.enabled = false;
428 * radeon_wb_fini - Disable Writeback and free memory
430 * @rdev: radeon_device pointer
432 * Disables Writeback and frees the Writeback memory (all asics).
433 * Used at driver shutdown.
435 void radeon_wb_fini(struct radeon_device *rdev)
437 radeon_wb_disable(rdev);
438 if (rdev->wb.wb_obj) {
439 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
440 radeon_bo_kunmap(rdev->wb.wb_obj);
441 radeon_bo_unpin(rdev->wb.wb_obj);
442 radeon_bo_unreserve(rdev->wb.wb_obj);
444 radeon_bo_unref(&rdev->wb.wb_obj);
446 rdev->wb.wb_obj = NULL;
451 * radeon_wb_init- Init Writeback driver info and allocate memory
453 * @rdev: radeon_device pointer
455 * Disables Writeback and frees the Writeback memory (all asics).
456 * Used at driver startup.
457 * Returns 0 on success or an -error on failure.
459 int radeon_wb_init(struct radeon_device *rdev)
463 if (rdev->wb.wb_obj == NULL) {
464 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
465 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
468 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
471 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
472 if (unlikely(r != 0)) {
473 radeon_wb_fini(rdev);
476 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
479 radeon_bo_unreserve(rdev->wb.wb_obj);
480 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
481 radeon_wb_fini(rdev);
484 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
485 radeon_bo_unreserve(rdev->wb.wb_obj);
487 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
488 radeon_wb_fini(rdev);
493 /* clear wb memory */
494 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
495 /* disable event_write fences */
496 rdev->wb.use_event = false;
497 /* disabled via module param */
498 if (radeon_no_wb == 1) {
499 rdev->wb.enabled = false;
501 if (rdev->flags & RADEON_IS_AGP) {
502 /* often unreliable on AGP */
503 rdev->wb.enabled = false;
504 } else if (rdev->family < CHIP_R300) {
505 /* often unreliable on pre-r300 */
506 rdev->wb.enabled = false;
508 rdev->wb.enabled = true;
509 /* event_write fences are only available on r600+ */
510 if (rdev->family >= CHIP_R600) {
511 rdev->wb.use_event = true;
515 /* always use writeback/events on NI, APUs */
516 if (rdev->family >= CHIP_PALM) {
517 rdev->wb.enabled = true;
518 rdev->wb.use_event = true;
521 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
527 * radeon_vram_location - try to find VRAM location
528 * @rdev: radeon device structure holding all necessary informations
529 * @mc: memory controller structure holding memory informations
530 * @base: base address at which to put VRAM
532 * Function will place try to place VRAM at base address provided
533 * as parameter (which is so far either PCI aperture address or
534 * for IGP TOM base address).
536 * If there is not enough space to fit the unvisible VRAM in the 32bits
537 * address space then we limit the VRAM size to the aperture.
539 * If we are using AGP and if the AGP aperture doesn't allow us to have
540 * room for all the VRAM than we restrict the VRAM to the PCI aperture
541 * size and print a warning.
543 * This function will never fails, worst case are limiting VRAM.
545 * Note: GTT start, end, size should be initialized before calling this
546 * function on AGP platform.
548 * Note 1: We don't explicitly enforce VRAM start to be aligned on VRAM size,
549 * this shouldn't be a problem as we are using the PCI aperture as a reference.
550 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
553 * Note 2: we use mc_vram_size as on some board we need to program the mc to
554 * cover the whole aperture even if VRAM size is inferior to aperture size
555 * Novell bug 204882 + along with lots of ubuntu ones
557 * Note 3: when limiting vram it's safe to overwritte real_vram_size because
558 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
559 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
562 * Note 4: IGP TOM addr should be the same as the aperture addr, we don't
563 * explicitly check for that thought.
565 * FIXME: when reducing VRAM size align new size on power of 2.
567 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
569 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
571 mc->vram_start = base;
572 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
573 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
574 mc->real_vram_size = mc->aper_size;
575 mc->mc_vram_size = mc->aper_size;
577 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
578 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
579 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
580 mc->real_vram_size = mc->aper_size;
581 mc->mc_vram_size = mc->aper_size;
583 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
584 if (limit && limit < mc->real_vram_size)
585 mc->real_vram_size = limit;
586 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
587 mc->mc_vram_size >> 20, mc->vram_start,
588 mc->vram_end, mc->real_vram_size >> 20);
592 * radeon_gtt_location - try to find GTT location
593 * @rdev: radeon device structure holding all necessary informations
594 * @mc: memory controller structure holding memory informations
596 * Function will place try to place GTT before or after VRAM.
598 * If GTT size is bigger than space left then we ajust GTT size.
599 * Thus function will never fails.
601 * FIXME: when reducing GTT size align new size on power of 2.
603 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
605 u64 size_af, size_bf;
607 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
608 size_bf = mc->vram_start & ~mc->gtt_base_align;
609 if (size_bf > size_af) {
610 if (mc->gtt_size > size_bf) {
611 dev_warn(rdev->dev, "limiting GTT\n");
612 mc->gtt_size = size_bf;
614 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
616 if (mc->gtt_size > size_af) {
617 dev_warn(rdev->dev, "limiting GTT\n");
618 mc->gtt_size = size_af;
620 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
622 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
623 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
624 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
628 * GPU helpers function.
632 * radeon_device_is_virtual - check if we are running is a virtual environment
634 * Check if the asic has been passed through to a VM (all asics).
635 * Used at driver startup.
636 * Returns true if virtual or false if not.
638 bool radeon_device_is_virtual(void)
641 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
648 * radeon_card_posted - check if the hw has already been initialized
650 * @rdev: radeon_device pointer
652 * Check if the asic has been initialized (all asics).
653 * Used at driver startup.
654 * Returns true if initialized or false if not.
656 bool radeon_card_posted(struct radeon_device *rdev)
660 /* for pass through, always force asic_init for CI */
661 if (rdev->family >= CHIP_BONAIRE &&
662 radeon_device_is_virtual())
665 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
666 if (efi_enabled(EFI_BOOT) &&
667 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
668 (rdev->family < CHIP_R600))
671 if (ASIC_IS_NODCE(rdev))
674 /* first check CRTCs */
675 if (ASIC_IS_DCE4(rdev)) {
676 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
677 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
678 if (rdev->num_crtc >= 4) {
679 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
680 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
682 if (rdev->num_crtc >= 6) {
683 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
684 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
686 if (reg & EVERGREEN_CRTC_MASTER_EN)
688 } else if (ASIC_IS_AVIVO(rdev)) {
689 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
690 RREG32(AVIVO_D2CRTC_CONTROL);
691 if (reg & AVIVO_CRTC_EN) {
695 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
696 RREG32(RADEON_CRTC2_GEN_CNTL);
697 if (reg & RADEON_CRTC_EN) {
703 /* then check MEM_SIZE, in case the crtcs are off */
704 if (rdev->family >= CHIP_R600)
705 reg = RREG32(R600_CONFIG_MEMSIZE);
707 reg = RREG32(RADEON_CONFIG_MEMSIZE);
717 * radeon_update_bandwidth_info - update display bandwidth params
719 * @rdev: radeon_device pointer
721 * Used when sclk/mclk are switched or display modes are set.
722 * params are used to calculate display watermarks (all asics)
724 void radeon_update_bandwidth_info(struct radeon_device *rdev)
727 u32 sclk = rdev->pm.current_sclk;
728 u32 mclk = rdev->pm.current_mclk;
730 /* sclk/mclk in Mhz */
731 a.full = dfixed_const(100);
732 rdev->pm.sclk.full = dfixed_const(sclk);
733 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
734 rdev->pm.mclk.full = dfixed_const(mclk);
735 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
737 if (rdev->flags & RADEON_IS_IGP) {
738 a.full = dfixed_const(16);
739 /* core_bandwidth = sclk(Mhz) * 16 */
740 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
745 * radeon_boot_test_post_card - check and possibly initialize the hw
747 * @rdev: radeon_device pointer
749 * Check if the asic is initialized and if not, attempt to initialize
751 * Returns true if initialized or false if not.
753 bool radeon_boot_test_post_card(struct radeon_device *rdev)
755 if (radeon_card_posted(rdev))
759 DRM_INFO("GPU not posted. posting now...\n");
760 if (rdev->is_atom_bios)
761 atom_asic_init(rdev->mode_info.atom_context);
763 radeon_combios_asic_init(rdev->ddev);
766 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
772 * radeon_dummy_page_init - init dummy page used by the driver
774 * @rdev: radeon_device pointer
776 * Allocate the dummy page used by the driver (all asics).
777 * This dummy page is used by the driver as a filler for gart entries
778 * when pages are taken out of the GART
779 * Returns 0 on sucess, -ENOMEM on failure.
781 int radeon_dummy_page_init(struct radeon_device *rdev)
783 if (rdev->dummy_page.page)
785 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
786 if (rdev->dummy_page.page == NULL)
788 rdev->dummy_page.addr = dma_map_page(&rdev->pdev->dev, rdev->dummy_page.page,
789 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
790 if (dma_mapping_error(&rdev->pdev->dev, rdev->dummy_page.addr)) {
791 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
792 __free_page(rdev->dummy_page.page);
793 rdev->dummy_page.page = NULL;
796 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
797 RADEON_GART_PAGE_DUMMY);
802 * radeon_dummy_page_fini - free dummy page used by the driver
804 * @rdev: radeon_device pointer
806 * Frees the dummy page used by the driver (all asics).
808 void radeon_dummy_page_fini(struct radeon_device *rdev)
810 if (rdev->dummy_page.page == NULL)
812 dma_unmap_page(&rdev->pdev->dev, rdev->dummy_page.addr, PAGE_SIZE,
814 __free_page(rdev->dummy_page.page);
815 rdev->dummy_page.page = NULL;
819 /* ATOM accessor methods */
821 * ATOM is an interpreted byte code stored in tables in the vbios. The
822 * driver registers callbacks to access registers and the interpreter
823 * in the driver parses the tables and executes then to program specific
824 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
825 * atombios.h, and atom.c
829 * cail_pll_read - read PLL register
831 * @info: atom card_info pointer
832 * @reg: PLL register offset
834 * Provides a PLL register accessor for the atom interpreter (r4xx+).
835 * Returns the value of the PLL register.
837 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
839 struct radeon_device *rdev = info->dev->dev_private;
842 r = rdev->pll_rreg(rdev, reg);
847 * cail_pll_write - write PLL register
849 * @info: atom card_info pointer
850 * @reg: PLL register offset
851 * @val: value to write to the pll register
853 * Provides a PLL register accessor for the atom interpreter (r4xx+).
855 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
857 struct radeon_device *rdev = info->dev->dev_private;
859 rdev->pll_wreg(rdev, reg, val);
863 * cail_mc_read - read MC (Memory Controller) register
865 * @info: atom card_info pointer
866 * @reg: MC register offset
868 * Provides an MC register accessor for the atom interpreter (r4xx+).
869 * Returns the value of the MC register.
871 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
873 struct radeon_device *rdev = info->dev->dev_private;
876 r = rdev->mc_rreg(rdev, reg);
881 * cail_mc_write - write MC (Memory Controller) register
883 * @info: atom card_info pointer
884 * @reg: MC register offset
885 * @val: value to write to the pll register
887 * Provides a MC register accessor for the atom interpreter (r4xx+).
889 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
891 struct radeon_device *rdev = info->dev->dev_private;
893 rdev->mc_wreg(rdev, reg, val);
897 * cail_reg_write - write MMIO register
899 * @info: atom card_info pointer
900 * @reg: MMIO register offset
901 * @val: value to write to the pll register
903 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
905 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
907 struct radeon_device *rdev = info->dev->dev_private;
913 * cail_reg_read - read MMIO register
915 * @info: atom card_info pointer
916 * @reg: MMIO register offset
918 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
919 * Returns the value of the MMIO register.
921 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
923 struct radeon_device *rdev = info->dev->dev_private;
931 * cail_ioreg_write - write IO register
933 * @info: atom card_info pointer
934 * @reg: IO register offset
935 * @val: value to write to the pll register
937 * Provides a IO register accessor for the atom interpreter (r4xx+).
939 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
941 struct radeon_device *rdev = info->dev->dev_private;
943 WREG32_IO(reg*4, val);
947 * cail_ioreg_read - read IO register
949 * @info: atom card_info pointer
950 * @reg: IO register offset
952 * Provides an IO register accessor for the atom interpreter (r4xx+).
953 * Returns the value of the IO register.
955 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
957 struct radeon_device *rdev = info->dev->dev_private;
960 r = RREG32_IO(reg*4);
965 * radeon_atombios_init - init the driver info and callbacks for atombios
967 * @rdev: radeon_device pointer
969 * Initializes the driver info and register access callbacks for the
970 * ATOM interpreter (r4xx+).
971 * Returns 0 on sucess, -ENOMEM on failure.
972 * Called at driver startup.
974 int radeon_atombios_init(struct radeon_device *rdev)
976 struct card_info *atom_card_info =
977 kzalloc(sizeof(struct card_info), GFP_KERNEL);
982 rdev->mode_info.atom_card_info = atom_card_info;
983 atom_card_info->dev = rdev->ddev;
984 atom_card_info->reg_read = cail_reg_read;
985 atom_card_info->reg_write = cail_reg_write;
986 /* needed for iio ops */
988 atom_card_info->ioreg_read = cail_ioreg_read;
989 atom_card_info->ioreg_write = cail_ioreg_write;
991 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
992 atom_card_info->ioreg_read = cail_reg_read;
993 atom_card_info->ioreg_write = cail_reg_write;
995 atom_card_info->mc_read = cail_mc_read;
996 atom_card_info->mc_write = cail_mc_write;
997 atom_card_info->pll_read = cail_pll_read;
998 atom_card_info->pll_write = cail_pll_write;
1000 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1001 if (!rdev->mode_info.atom_context) {
1002 radeon_atombios_fini(rdev);
1006 mutex_init(&rdev->mode_info.atom_context->mutex);
1007 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1008 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1009 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1014 * radeon_atombios_fini - free the driver info and callbacks for atombios
1016 * @rdev: radeon_device pointer
1018 * Frees the driver info and register access callbacks for the ATOM
1019 * interpreter (r4xx+).
1020 * Called at driver shutdown.
1022 void radeon_atombios_fini(struct radeon_device *rdev)
1024 if (rdev->mode_info.atom_context) {
1025 kfree(rdev->mode_info.atom_context->scratch);
1027 kfree(rdev->mode_info.atom_context);
1028 rdev->mode_info.atom_context = NULL;
1029 kfree(rdev->mode_info.atom_card_info);
1030 rdev->mode_info.atom_card_info = NULL;
1035 * COMBIOS is the bios format prior to ATOM. It provides
1036 * command tables similar to ATOM, but doesn't have a unified
1037 * parser. See radeon_combios.c
1041 * radeon_combios_init - init the driver info for combios
1043 * @rdev: radeon_device pointer
1045 * Initializes the driver info for combios (r1xx-r3xx).
1046 * Returns 0 on sucess.
1047 * Called at driver startup.
1049 int radeon_combios_init(struct radeon_device *rdev)
1051 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1056 * radeon_combios_fini - free the driver info for combios
1058 * @rdev: radeon_device pointer
1060 * Frees the driver info for combios (r1xx-r3xx).
1061 * Called at driver shutdown.
1063 void radeon_combios_fini(struct radeon_device *rdev)
1067 /* if we get transitioned to only one device, take VGA back */
1069 * radeon_vga_set_decode - enable/disable vga decode
1072 * @state: enable/disable vga decode
1074 * Enable/disable vga decode (all asics).
1075 * Returns VGA resource flags.
1077 static unsigned int radeon_vga_set_decode(struct pci_dev *pdev, bool state)
1079 struct drm_device *dev = pci_get_drvdata(pdev);
1080 struct radeon_device *rdev = dev->dev_private;
1081 radeon_vga_set_state(rdev, state);
1083 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1084 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1086 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1090 * radeon_gart_size_auto - Determine a sensible default GART size
1091 * according to ASIC family.
1093 * @family: ASIC family name
1095 static int radeon_gart_size_auto(enum radeon_family family)
1097 /* default to a larger gart size on newer asics */
1098 if (family >= CHIP_TAHITI)
1100 else if (family >= CHIP_RV770)
1107 * radeon_check_arguments - validate module params
1109 * @rdev: radeon_device pointer
1111 * Validates certain module parameters and updates
1112 * the associated values used by the driver (all asics).
1114 static void radeon_check_arguments(struct radeon_device *rdev)
1116 /* vramlimit must be a power of two */
1117 if (radeon_vram_limit != 0 && !is_power_of_2(radeon_vram_limit)) {
1118 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1120 radeon_vram_limit = 0;
1123 if (radeon_gart_size == -1) {
1124 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1126 /* gtt size must be power of two and greater or equal to 32M */
1127 if (radeon_gart_size < 32) {
1128 dev_warn(rdev->dev, "gart size (%d) too small\n",
1130 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1131 } else if (!is_power_of_2(radeon_gart_size)) {
1132 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1134 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1136 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1138 /* AGP mode can only be -1, 1, 2, 4, 8 */
1139 switch (radeon_agpmode) {
1148 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1149 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1154 if (!is_power_of_2(radeon_vm_size)) {
1155 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1160 if (radeon_vm_size < 1) {
1161 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1167 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1169 if (radeon_vm_size > 1024) {
1170 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1175 /* defines number of bits in page table versus page directory,
1176 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1177 * page table and the remaining bits are in the page directory */
1178 if (radeon_vm_block_size == -1) {
1180 /* Total bits covered by PD + PTs */
1181 unsigned bits = ilog2(radeon_vm_size) + 18;
1183 /* Make sure the PD is 4K in size up to 8GB address space.
1184 Above that split equal between PD and PTs */
1185 if (radeon_vm_size <= 8)
1186 radeon_vm_block_size = bits - 9;
1188 radeon_vm_block_size = (bits + 3) / 2;
1190 } else if (radeon_vm_block_size < 9) {
1191 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1192 radeon_vm_block_size);
1193 radeon_vm_block_size = 9;
1196 if (radeon_vm_block_size > 24 ||
1197 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1198 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1199 radeon_vm_block_size);
1200 radeon_vm_block_size = 9;
1205 * radeon_switcheroo_set_state - set switcheroo state
1207 * @pdev: pci dev pointer
1208 * @state: vga_switcheroo state
1210 * Callback for the switcheroo driver. Suspends or resumes the
1211 * the asics before or after it is powered up using ACPI methods.
1213 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1215 struct drm_device *dev = pci_get_drvdata(pdev);
1217 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1220 if (state == VGA_SWITCHEROO_ON) {
1221 pr_info("radeon: switched on\n");
1222 /* don't suspend or resume card normally */
1223 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1225 radeon_resume_kms(dev, true, true);
1227 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1228 drm_kms_helper_poll_enable(dev);
1230 pr_info("radeon: switched off\n");
1231 drm_kms_helper_poll_disable(dev);
1232 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1233 radeon_suspend_kms(dev, true, true, false);
1234 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1239 * radeon_switcheroo_can_switch - see if switcheroo state can change
1241 * @pdev: pci dev pointer
1243 * Callback for the switcheroo driver. Check of the switcheroo
1244 * state can be changed.
1245 * Returns true if the state can be changed, false if not.
1247 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1249 struct drm_device *dev = pci_get_drvdata(pdev);
1252 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1253 * locking inversion with the driver load path. And the access here is
1254 * completely racy anyway. So don't bother with locking for now.
1256 return atomic_read(&dev->open_count) == 0;
1259 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1260 .set_gpu_state = radeon_switcheroo_set_state,
1262 .can_switch = radeon_switcheroo_can_switch,
1266 * radeon_device_init - initialize the driver
1268 * @rdev: radeon_device pointer
1269 * @ddev: drm dev pointer
1270 * @pdev: pci dev pointer
1271 * @flags: driver flags
1273 * Initializes the driver info and hw (all asics).
1274 * Returns 0 for success or an error on failure.
1275 * Called at driver startup.
1277 int radeon_device_init(struct radeon_device *rdev,
1278 struct drm_device *ddev,
1279 struct pci_dev *pdev,
1284 bool runtime = false;
1286 rdev->shutdown = false;
1287 rdev->dev = &pdev->dev;
1290 rdev->flags = flags;
1291 rdev->family = flags & RADEON_FAMILY_MASK;
1292 rdev->is_atom_bios = false;
1293 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1294 rdev->mc.gtt_size = 512 * 1024 * 1024;
1295 rdev->accel_working = false;
1296 /* set up ring ids */
1297 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1298 rdev->ring[i].idx = i;
1300 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
1302 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1303 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1304 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1306 /* mutex initialization are all done here so we
1307 * can recall function without having locking issues */
1308 mutex_init(&rdev->ring_lock);
1309 mutex_init(&rdev->dc_hw_i2c_mutex);
1310 atomic_set(&rdev->ih.lock, 0);
1311 mutex_init(&rdev->gem.mutex);
1312 mutex_init(&rdev->pm.mutex);
1313 mutex_init(&rdev->gpu_clock_mutex);
1314 mutex_init(&rdev->srbm_mutex);
1315 init_rwsem(&rdev->pm.mclk_lock);
1316 init_rwsem(&rdev->exclusive_lock);
1317 init_waitqueue_head(&rdev->irq.vblank_queue);
1318 r = radeon_gem_init(rdev);
1322 radeon_check_arguments(rdev);
1323 /* Adjust VM size here.
1324 * Max GPUVM size for cayman+ is 40 bits.
1326 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1328 /* Set asic functions */
1329 r = radeon_asic_init(rdev);
1333 /* all of the newer IGP chips have an internal gart
1334 * However some rs4xx report as AGP, so remove that here.
1336 if ((rdev->family >= CHIP_RS400) &&
1337 (rdev->flags & RADEON_IS_IGP)) {
1338 rdev->flags &= ~RADEON_IS_AGP;
1341 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1342 radeon_agp_disable(rdev);
1345 /* Set the internal MC address mask
1346 * This is the max address of the GPU's
1347 * internal address space.
1349 if (rdev->family >= CHIP_CAYMAN)
1350 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1351 else if (rdev->family >= CHIP_CEDAR)
1352 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1354 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1357 * PCIE - can handle 40-bits.
1358 * IGP - can handle 40-bits
1359 * AGP - generally dma32 is safest
1360 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1363 if (rdev->flags & RADEON_IS_AGP)
1365 if ((rdev->flags & RADEON_IS_PCI) &&
1366 (rdev->family <= CHIP_RS740))
1369 if (rdev->family == CHIP_CEDAR)
1373 r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
1375 pr_warn("radeon: No suitable DMA available\n");
1378 rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
1380 /* Registers mapping */
1381 /* TODO: block userspace mapping of io register */
1382 spin_lock_init(&rdev->mmio_idx_lock);
1383 spin_lock_init(&rdev->smc_idx_lock);
1384 spin_lock_init(&rdev->pll_idx_lock);
1385 spin_lock_init(&rdev->mc_idx_lock);
1386 spin_lock_init(&rdev->pcie_idx_lock);
1387 spin_lock_init(&rdev->pciep_idx_lock);
1388 spin_lock_init(&rdev->pif_idx_lock);
1389 spin_lock_init(&rdev->cg_idx_lock);
1390 spin_lock_init(&rdev->uvd_idx_lock);
1391 spin_lock_init(&rdev->rcu_idx_lock);
1392 spin_lock_init(&rdev->didt_idx_lock);
1393 spin_lock_init(&rdev->end_idx_lock);
1394 if (rdev->family >= CHIP_BONAIRE) {
1395 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1396 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1398 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1399 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1401 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1402 if (rdev->rmmio == NULL)
1405 /* doorbell bar mapping */
1406 if (rdev->family >= CHIP_BONAIRE)
1407 radeon_doorbell_init(rdev);
1409 /* io port mapping */
1410 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1411 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1412 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1413 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1417 if (rdev->rio_mem == NULL)
1418 DRM_ERROR("Unable to find PCI I/O BAR\n");
1420 if (rdev->flags & RADEON_IS_PX)
1421 radeon_device_handle_px_quirks(rdev);
1423 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1424 /* this will fail for cards that aren't VGA class devices, just
1426 vga_client_register(rdev->pdev, radeon_vga_set_decode);
1428 if (rdev->flags & RADEON_IS_PX)
1430 if (!pci_is_thunderbolt_attached(rdev->pdev))
1431 vga_switcheroo_register_client(rdev->pdev,
1432 &radeon_switcheroo_ops, runtime);
1434 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1436 r = radeon_init(rdev);
1440 radeon_gem_debugfs_init(rdev);
1442 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1443 /* Acceleration not working on AGP card try again
1444 * with fallback to PCI or PCIE GART
1446 radeon_asic_reset(rdev);
1448 radeon_agp_disable(rdev);
1449 r = radeon_init(rdev);
1454 r = radeon_ib_ring_tests(rdev);
1456 DRM_ERROR("ib ring test failed (%d).\n", r);
1459 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1460 * after the CP ring have chew one packet at least. Hence here we stop
1461 * and restart DPM after the radeon_ib_ring_tests().
1463 if (rdev->pm.dpm_enabled &&
1464 (rdev->pm.pm_method == PM_METHOD_DPM) &&
1465 (rdev->family == CHIP_TURKS) &&
1466 (rdev->flags & RADEON_IS_MOBILITY)) {
1467 mutex_lock(&rdev->pm.mutex);
1468 radeon_dpm_disable(rdev);
1469 radeon_dpm_enable(rdev);
1470 mutex_unlock(&rdev->pm.mutex);
1473 if ((radeon_testing & 1)) {
1474 if (rdev->accel_working)
1475 radeon_test_moves(rdev);
1477 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1479 if ((radeon_testing & 2)) {
1480 if (rdev->accel_working)
1481 radeon_test_syncing(rdev);
1483 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1485 if (radeon_benchmarking) {
1486 if (rdev->accel_working)
1487 radeon_benchmark(rdev, radeon_benchmarking);
1489 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1494 /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */
1495 if (radeon_is_px(ddev))
1496 pm_runtime_put_noidle(ddev->dev);
1498 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1503 * radeon_device_fini - tear down the driver
1505 * @rdev: radeon_device pointer
1507 * Tear down the driver info (all asics).
1508 * Called at driver shutdown.
1510 void radeon_device_fini(struct radeon_device *rdev)
1512 DRM_INFO("radeon: finishing device.\n");
1513 rdev->shutdown = true;
1514 /* evict vram memory */
1515 radeon_bo_evict_vram(rdev);
1517 if (!pci_is_thunderbolt_attached(rdev->pdev))
1518 vga_switcheroo_unregister_client(rdev->pdev);
1519 if (rdev->flags & RADEON_IS_PX)
1520 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1521 vga_client_unregister(rdev->pdev);
1523 pci_iounmap(rdev->pdev, rdev->rio_mem);
1524 rdev->rio_mem = NULL;
1525 iounmap(rdev->rmmio);
1527 if (rdev->family >= CHIP_BONAIRE)
1528 radeon_doorbell_fini(rdev);
1536 * radeon_suspend_kms - initiate device suspend
1538 * Puts the hw in the suspend state (all asics).
1539 * Returns 0 for success or an error on failure.
1540 * Called at driver suspend.
1542 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
1543 bool fbcon, bool freeze)
1545 struct radeon_device *rdev;
1546 struct pci_dev *pdev;
1547 struct drm_crtc *crtc;
1548 struct drm_connector *connector;
1551 if (dev == NULL || dev->dev_private == NULL) {
1555 rdev = dev->dev_private;
1556 pdev = to_pci_dev(dev->dev);
1558 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1561 drm_kms_helper_poll_disable(dev);
1563 drm_modeset_lock_all(dev);
1564 /* turn off display hw */
1565 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1566 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1568 drm_modeset_unlock_all(dev);
1570 /* unpin the front buffers and cursors */
1571 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1572 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1573 struct drm_framebuffer *fb = crtc->primary->fb;
1574 struct radeon_bo *robj;
1576 if (radeon_crtc->cursor_bo) {
1577 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1578 r = radeon_bo_reserve(robj, false);
1580 radeon_bo_unpin(robj);
1581 radeon_bo_unreserve(robj);
1585 if (fb == NULL || fb->obj[0] == NULL) {
1588 robj = gem_to_radeon_bo(fb->obj[0]);
1589 /* don't unpin kernel fb objects */
1590 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1591 r = radeon_bo_reserve(robj, false);
1593 radeon_bo_unpin(robj);
1594 radeon_bo_unreserve(robj);
1598 /* evict vram memory */
1599 radeon_bo_evict_vram(rdev);
1601 /* wait for gpu to finish processing current batch */
1602 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1603 r = radeon_fence_wait_empty(rdev, i);
1605 /* delay GPU reset to resume */
1606 radeon_fence_driver_force_completion(rdev, i);
1610 radeon_save_bios_scratch_regs(rdev);
1612 radeon_suspend(rdev);
1613 radeon_hpd_fini(rdev);
1614 /* evict remaining vram memory
1615 * This second call to evict vram is to evict the gart page table
1618 radeon_bo_evict_vram(rdev);
1620 radeon_agp_suspend(rdev);
1622 pci_save_state(pdev);
1623 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1624 rdev->asic->asic_reset(rdev, true);
1625 pci_restore_state(pdev);
1626 } else if (suspend) {
1627 /* Shut down the device */
1628 pci_disable_device(pdev);
1629 pci_set_power_state(pdev, PCI_D3hot);
1634 radeon_fbdev_set_suspend(rdev, 1);
1641 * radeon_resume_kms - initiate device resume
1643 * Bring the hw back to operating state (all asics).
1644 * Returns 0 for success or an error on failure.
1645 * Called at driver resume.
1647 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1649 struct drm_connector *connector;
1650 struct radeon_device *rdev = dev->dev_private;
1651 struct pci_dev *pdev = to_pci_dev(dev->dev);
1652 struct drm_crtc *crtc;
1655 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1662 pci_set_power_state(pdev, PCI_D0);
1663 pci_restore_state(pdev);
1664 if (pci_enable_device(pdev)) {
1670 /* resume AGP if in use */
1671 radeon_agp_resume(rdev);
1672 radeon_resume(rdev);
1674 r = radeon_ib_ring_tests(rdev);
1676 DRM_ERROR("ib ring test failed (%d).\n", r);
1678 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1679 /* do dpm late init */
1680 r = radeon_pm_late_init(rdev);
1682 rdev->pm.dpm_enabled = false;
1683 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1686 /* resume old pm late */
1687 radeon_pm_resume(rdev);
1690 radeon_restore_bios_scratch_regs(rdev);
1693 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1694 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1696 if (radeon_crtc->cursor_bo) {
1697 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1698 r = radeon_bo_reserve(robj, false);
1700 /* Only 27 bit offset for legacy cursor */
1701 r = radeon_bo_pin_restricted(robj,
1702 RADEON_GEM_DOMAIN_VRAM,
1703 ASIC_IS_AVIVO(rdev) ?
1705 &radeon_crtc->cursor_addr);
1707 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1708 radeon_bo_unreserve(robj);
1713 /* init dig PHYs, disp eng pll */
1714 if (rdev->is_atom_bios) {
1715 radeon_atom_encoder_init(rdev);
1716 radeon_atom_disp_eng_pll_init(rdev);
1717 /* turn on the BL */
1718 if (rdev->mode_info.bl_encoder) {
1719 u8 bl_level = radeon_get_backlight_level(rdev,
1720 rdev->mode_info.bl_encoder);
1721 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1725 /* reset hpd state */
1726 radeon_hpd_init(rdev);
1727 /* blat the mode back in */
1729 drm_helper_resume_force_mode(dev);
1730 /* turn on display hw */
1731 drm_modeset_lock_all(dev);
1732 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1733 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1735 drm_modeset_unlock_all(dev);
1738 drm_kms_helper_poll_enable(dev);
1740 /* set the power state here in case we are a PX system or headless */
1741 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1742 radeon_pm_compute_clocks(rdev);
1745 radeon_fbdev_set_suspend(rdev, 0);
1753 * radeon_gpu_reset - reset the asic
1755 * @rdev: radeon device pointer
1757 * Attempt the reset the GPU if it has hung (all asics).
1758 * Returns 0 for success or an error on failure.
1760 int radeon_gpu_reset(struct radeon_device *rdev)
1762 unsigned ring_sizes[RADEON_NUM_RINGS];
1763 uint32_t *ring_data[RADEON_NUM_RINGS];
1770 down_write(&rdev->exclusive_lock);
1772 if (!rdev->needs_reset) {
1773 up_write(&rdev->exclusive_lock);
1777 atomic_inc(&rdev->gpu_reset_counter);
1779 radeon_save_bios_scratch_regs(rdev);
1781 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1782 radeon_suspend(rdev);
1783 radeon_hpd_fini(rdev);
1785 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1786 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1788 if (ring_sizes[i]) {
1790 dev_info(rdev->dev, "Saved %d dwords of commands "
1791 "on ring %d.\n", ring_sizes[i], i);
1795 r = radeon_asic_reset(rdev);
1797 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1798 radeon_resume(rdev);
1801 radeon_restore_bios_scratch_regs(rdev);
1803 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1804 if (!r && ring_data[i]) {
1805 radeon_ring_restore(rdev, &rdev->ring[i],
1806 ring_sizes[i], ring_data[i]);
1808 radeon_fence_driver_force_completion(rdev, i);
1809 kfree(ring_data[i]);
1813 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1814 /* do dpm late init */
1815 r = radeon_pm_late_init(rdev);
1817 rdev->pm.dpm_enabled = false;
1818 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1821 /* resume old pm late */
1822 radeon_pm_resume(rdev);
1825 /* init dig PHYs, disp eng pll */
1826 if (rdev->is_atom_bios) {
1827 radeon_atom_encoder_init(rdev);
1828 radeon_atom_disp_eng_pll_init(rdev);
1829 /* turn on the BL */
1830 if (rdev->mode_info.bl_encoder) {
1831 u8 bl_level = radeon_get_backlight_level(rdev,
1832 rdev->mode_info.bl_encoder);
1833 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1837 /* reset hpd state */
1838 radeon_hpd_init(rdev);
1840 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1842 rdev->in_reset = true;
1843 rdev->needs_reset = false;
1845 downgrade_write(&rdev->exclusive_lock);
1847 drm_helper_resume_force_mode(rdev->ddev);
1849 /* set the power state here in case we are a PX system or headless */
1850 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1851 radeon_pm_compute_clocks(rdev);
1854 r = radeon_ib_ring_tests(rdev);
1858 /* bad news, how to tell it to userspace ? */
1859 dev_info(rdev->dev, "GPU reset failed\n");
1862 rdev->needs_reset = r == -EAGAIN;
1863 rdev->in_reset = false;
1865 up_read(&rdev->exclusive_lock);