2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include "radeon_reg.h"
33 #include "radeon_asic.h"
37 #include "r420_reg_safe.h"
39 void r420_pm_init_profile(struct radeon_device *rdev)
42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
78 static void r420_set_reg_safe(struct radeon_device *rdev)
80 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
81 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
84 void r420_pipes_init(struct radeon_device *rdev)
87 unsigned gb_pipe_select;
90 /* GA_ENHANCE workaround TCL deadlock issue */
91 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
93 /* add idle wait as per freedesktop.org bug 24041 */
94 if (r100_gui_wait_for_idle(rdev)) {
95 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
97 /* get max number of pipes */
98 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
99 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
101 /* SE chips have 1 pipe */
102 if ((rdev->pdev->device == 0x5e4c) ||
103 (rdev->pdev->device == 0x5e4f))
106 rdev->num_gb_pipes = num_pipes;
110 /* force to 1 pipe */
125 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
126 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
127 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
128 WREG32(R300_GB_TILE_CONFIG, tmp);
129 if (r100_gui_wait_for_idle(rdev)) {
130 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
133 tmp = RREG32(R300_DST_PIPE_CONFIG);
134 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
136 WREG32(R300_RB2D_DSTCACHE_MODE,
137 RREG32(R300_RB2D_DSTCACHE_MODE) |
138 R300_DC_AUTOFLUSH_ENABLE |
139 R300_DC_DC_DISABLE_IGNORE_PE);
141 if (r100_gui_wait_for_idle(rdev)) {
142 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
145 if (rdev->family == CHIP_RV530) {
146 tmp = RREG32(RV530_GB_PIPE_SELECT2);
148 rdev->num_z_pipes = 2;
150 rdev->num_z_pipes = 1;
152 rdev->num_z_pipes = 1;
154 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
155 rdev->num_gb_pipes, rdev->num_z_pipes);
158 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
163 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
164 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
165 r = RREG32(R_0001FC_MC_IND_DATA);
166 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
170 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
174 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
175 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
176 S_0001F8_MC_IND_WR_EN(1));
177 WREG32(R_0001FC_MC_IND_DATA, v);
178 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
181 static void r420_debugfs(struct radeon_device *rdev)
183 if (r100_debugfs_rbbm_init(rdev)) {
184 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
186 if (r420_debugfs_pipes_info_init(rdev)) {
187 DRM_ERROR("Failed to register debugfs file for pipes !\n");
191 static void r420_clock_resume(struct radeon_device *rdev)
195 if (radeon_dynclks != -1 && radeon_dynclks)
196 radeon_atom_set_clock_gating(rdev, 1);
197 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
198 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
199 if (rdev->family == CHIP_R420)
200 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
201 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
204 static void r420_cp_errata_init(struct radeon_device *rdev)
207 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
209 /* RV410 and R420 can lock up if CP DMA to host memory happens
210 * while the 2D engine is busy.
212 * The proper workaround is to queue a RESYNC at the beginning
213 * of the CP init, apparently.
215 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
216 r = radeon_ring_lock(rdev, ring, 8);
218 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
219 radeon_ring_write(ring, rdev->config.r300.resync_scratch);
220 radeon_ring_write(ring, 0xDEADBEEF);
221 radeon_ring_unlock_commit(rdev, ring, false);
224 static void r420_cp_errata_fini(struct radeon_device *rdev)
227 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
229 /* Catch the RESYNC we dispatched all the way back,
230 * at the very beginning of the CP init.
232 r = radeon_ring_lock(rdev, ring, 8);
234 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
235 radeon_ring_write(ring, R300_RB3D_DC_FINISH);
236 radeon_ring_unlock_commit(rdev, ring, false);
237 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
240 static int r420_startup(struct radeon_device *rdev)
244 /* set common regs */
245 r100_set_common_regs(rdev);
247 r300_mc_program(rdev);
249 r420_clock_resume(rdev);
250 /* Initialize GART (initialize after TTM so we can allocate
251 * memory through TTM but finalize after TTM) */
252 if (rdev->flags & RADEON_IS_PCIE) {
253 r = rv370_pcie_gart_enable(rdev);
257 if (rdev->flags & RADEON_IS_PCI) {
258 r = r100_pci_gart_enable(rdev);
262 r420_pipes_init(rdev);
264 /* allocate wb buffer */
265 r = radeon_wb_init(rdev);
269 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
271 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
276 if (!rdev->irq.installed) {
277 r = radeon_irq_kms_init(rdev);
283 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
285 r = r100_cp_init(rdev, 1024 * 1024);
287 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
290 r420_cp_errata_init(rdev);
292 r = radeon_ib_pool_init(rdev);
294 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
301 int r420_resume(struct radeon_device *rdev)
305 /* Make sur GART are not working */
306 if (rdev->flags & RADEON_IS_PCIE)
307 rv370_pcie_gart_disable(rdev);
308 if (rdev->flags & RADEON_IS_PCI)
309 r100_pci_gart_disable(rdev);
310 /* Resume clock before doing reset */
311 r420_clock_resume(rdev);
312 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
313 if (radeon_asic_reset(rdev)) {
314 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
315 RREG32(R_000E40_RBBM_STATUS),
316 RREG32(R_0007C0_CP_STAT));
318 /* check if cards are posted or not */
319 if (rdev->is_atom_bios) {
320 atom_asic_init(rdev->mode_info.atom_context);
322 radeon_combios_asic_init(rdev->ddev);
324 /* Resume clock after posting */
325 r420_clock_resume(rdev);
326 /* Initialize surface registers */
327 radeon_surface_init(rdev);
329 rdev->accel_working = true;
330 r = r420_startup(rdev);
332 rdev->accel_working = false;
337 int r420_suspend(struct radeon_device *rdev)
339 radeon_pm_suspend(rdev);
340 r420_cp_errata_fini(rdev);
341 r100_cp_disable(rdev);
342 radeon_wb_disable(rdev);
343 r100_irq_disable(rdev);
344 if (rdev->flags & RADEON_IS_PCIE)
345 rv370_pcie_gart_disable(rdev);
346 if (rdev->flags & RADEON_IS_PCI)
347 r100_pci_gart_disable(rdev);
351 void r420_fini(struct radeon_device *rdev)
353 radeon_pm_fini(rdev);
355 radeon_wb_fini(rdev);
356 radeon_ib_pool_fini(rdev);
357 radeon_gem_fini(rdev);
358 if (rdev->flags & RADEON_IS_PCIE)
359 rv370_pcie_gart_fini(rdev);
360 if (rdev->flags & RADEON_IS_PCI)
361 r100_pci_gart_fini(rdev);
362 radeon_agp_fini(rdev);
363 radeon_irq_kms_fini(rdev);
364 radeon_fence_driver_fini(rdev);
365 radeon_bo_fini(rdev);
366 if (rdev->is_atom_bios) {
367 radeon_atombios_fini(rdev);
369 radeon_combios_fini(rdev);
375 int r420_init(struct radeon_device *rdev)
379 /* Initialize scratch registers */
380 radeon_scratch_init(rdev);
381 /* Initialize surface registers */
382 radeon_surface_init(rdev);
383 /* TODO: disable VGA need to use VGA request */
384 /* restore some register to sane defaults */
385 r100_restore_sanity(rdev);
387 if (!radeon_get_bios(rdev)) {
388 if (ASIC_IS_AVIVO(rdev))
391 if (rdev->is_atom_bios) {
392 r = radeon_atombios_init(rdev);
397 r = radeon_combios_init(rdev);
402 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
403 if (radeon_asic_reset(rdev)) {
405 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
406 RREG32(R_000E40_RBBM_STATUS),
407 RREG32(R_0007C0_CP_STAT));
409 /* check if cards are posted or not */
410 if (radeon_boot_test_post_card(rdev) == false)
413 /* Initialize clocks */
414 radeon_get_clock_info(rdev->ddev);
416 if (rdev->flags & RADEON_IS_AGP) {
417 r = radeon_agp_init(rdev);
419 radeon_agp_disable(rdev);
422 /* initialize memory controller */
426 r = radeon_fence_driver_init(rdev);
431 r = radeon_bo_init(rdev);
435 if (rdev->family == CHIP_R420)
436 r100_enable_bm(rdev);
438 if (rdev->flags & RADEON_IS_PCIE) {
439 r = rv370_pcie_gart_init(rdev);
443 if (rdev->flags & RADEON_IS_PCI) {
444 r = r100_pci_gart_init(rdev);
448 r420_set_reg_safe(rdev);
450 /* Initialize power management */
451 radeon_pm_init(rdev);
453 rdev->accel_working = true;
454 r = r420_startup(rdev);
456 /* Somethings want wront with the accel init stop accel */
457 dev_err(rdev->dev, "Disabling GPU acceleration\n");
459 radeon_wb_fini(rdev);
460 radeon_ib_pool_fini(rdev);
461 radeon_irq_kms_fini(rdev);
462 if (rdev->flags & RADEON_IS_PCIE)
463 rv370_pcie_gart_fini(rdev);
464 if (rdev->flags & RADEON_IS_PCI)
465 r100_pci_gart_fini(rdev);
466 radeon_agp_fini(rdev);
467 rdev->accel_working = false;
475 #if defined(CONFIG_DEBUG_FS)
476 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
478 struct drm_info_node *node = (struct drm_info_node *) m->private;
479 struct drm_device *dev = node->minor->dev;
480 struct radeon_device *rdev = dev->dev_private;
483 tmp = RREG32(R400_GB_PIPE_SELECT);
484 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
485 tmp = RREG32(R300_GB_TILE_CONFIG);
486 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
487 tmp = RREG32(R300_DST_PIPE_CONFIG);
488 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
492 static struct drm_info_list r420_pipes_info_list[] = {
493 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
497 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
499 #if defined(CONFIG_DEBUG_FS)
500 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);