drivers/gpu/drm/r128/r128_state.c

   1 /* r128_state.c -- State support for r128 -*- linux-c -*-
   2  * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
   3  */
   4 /*
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include <drm/r128_drm.h>
  33 #include "r128_drv.h"
  34
  35 /* ================================================================
  36  * CCE hardware state programming functions
  37  */
  38
  39 static void r128_emit_clip_rects(drm_r128_private_t *dev_priv,
  40                                  struct drm_clip_rect *boxes, int count)
  41 {
  42         u32 aux_sc_cntl = 0x00000000;
  43         RING_LOCALS;
  44         DRM_DEBUG("\n");
  45
  46         BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
  47
  48         if (count >= 1) {
  49                 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
  50                 OUT_RING(boxes[0].x1);
  51                 OUT_RING(boxes[0].x2 - 1);
  52                 OUT_RING(boxes[0].y1);
  53                 OUT_RING(boxes[0].y2 - 1);
  54
  55                 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
  56         }
  57         if (count >= 2) {
  58                 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
  59                 OUT_RING(boxes[1].x1);
  60                 OUT_RING(boxes[1].x2 - 1);
  61                 OUT_RING(boxes[1].y1);
  62                 OUT_RING(boxes[1].y2 - 1);
  63
  64                 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
  65         }
  66         if (count >= 3) {
  67                 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
  68                 OUT_RING(boxes[2].x1);
  69                 OUT_RING(boxes[2].x2 - 1);
  70                 OUT_RING(boxes[2].y1);
  71                 OUT_RING(boxes[2].y2 - 1);
  72
  73                 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
  74         }
  75
  76         OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
  77         OUT_RING(aux_sc_cntl);
  78
  79         ADVANCE_RING();
  80 }
  81
  82 static __inline__ void r128_emit_core(drm_r128_private_t *dev_priv)
  83 {
  84         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
  85         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
  86         RING_LOCALS;
  87         DRM_DEBUG("\n");
  88
  89         BEGIN_RING(2);
  90
  91         OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
  92         OUT_RING(ctx->scale_3d_cntl);
  93
  94         ADVANCE_RING();
  95 }
  96
  97 static __inline__ void r128_emit_context(drm_r128_private_t *dev_priv)
  98 {
  99         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 100         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 101         RING_LOCALS;
 102         DRM_DEBUG("\n");
 103
 104         BEGIN_RING(13);
 105
 106         OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
 107         OUT_RING(ctx->dst_pitch_offset_c);
 108         OUT_RING(ctx->dp_gui_master_cntl_c);
 109         OUT_RING(ctx->sc_top_left_c);
 110         OUT_RING(ctx->sc_bottom_right_c);
 111         OUT_RING(ctx->z_offset_c);
 112         OUT_RING(ctx->z_pitch_c);
 113         OUT_RING(ctx->z_sten_cntl_c);
 114         OUT_RING(ctx->tex_cntl_c);
 115         OUT_RING(ctx->misc_3d_state_cntl_reg);
 116         OUT_RING(ctx->texture_clr_cmp_clr_c);
 117         OUT_RING(ctx->texture_clr_cmp_msk_c);
 118         OUT_RING(ctx->fog_color_c);
 119
 120         ADVANCE_RING();
 121 }
 122
 123 static __inline__ void r128_emit_setup(drm_r128_private_t *dev_priv)
 124 {
 125         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 126         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 127         RING_LOCALS;
 128         DRM_DEBUG("\n");
 129
 130         BEGIN_RING(3);
 131
 132         OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
 133         OUT_RING(ctx->setup_cntl);
 134         OUT_RING(ctx->pm4_vc_fpu_setup);
 135
 136         ADVANCE_RING();
 137 }
 138
 139 static __inline__ void r128_emit_masks(drm_r128_private_t *dev_priv)
 140 {
 141         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 142         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 143         RING_LOCALS;
 144         DRM_DEBUG("\n");
 145
 146         BEGIN_RING(5);
 147
 148         OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
 149         OUT_RING(ctx->dp_write_mask);
 150
 151         OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
 152         OUT_RING(ctx->sten_ref_mask_c);
 153         OUT_RING(ctx->plane_3d_mask_c);
 154
 155         ADVANCE_RING();
 156 }
 157
 158 static __inline__ void r128_emit_window(drm_r128_private_t *dev_priv)
 159 {
 160         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 161         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 162         RING_LOCALS;
 163         DRM_DEBUG("\n");
 164
 165         BEGIN_RING(2);
 166
 167         OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
 168         OUT_RING(ctx->window_xy_offset);
 169
 170         ADVANCE_RING();
 171 }
 172
 173 static __inline__ void r128_emit_tex0(drm_r128_private_t *dev_priv)
 174 {
 175         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 176         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 177         drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
 178         int i;
 179         RING_LOCALS;
 180         DRM_DEBUG("\n");
 181
 182         BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
 183
 184         OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
 185                              2 + R128_MAX_TEXTURE_LEVELS));
 186         OUT_RING(tex->tex_cntl);
 187         OUT_RING(tex->tex_combine_cntl);
 188         OUT_RING(ctx->tex_size_pitch_c);
 189         for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++)
 190                 OUT_RING(tex->tex_offset[i]);
 191
 192         OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
 193         OUT_RING(ctx->constant_color_c);
 194         OUT_RING(tex->tex_border_color);
 195
 196         ADVANCE_RING();
 197 }
 198
 199 static __inline__ void r128_emit_tex1(drm_r128_private_t *dev_priv)
 200 {
 201         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 202         drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
 203         int i;
 204         RING_LOCALS;
 205         DRM_DEBUG("\n");
 206
 207         BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
 208
 209         OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
 210         OUT_RING(tex->tex_cntl);
 211         OUT_RING(tex->tex_combine_cntl);
 212         for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++)
 213                 OUT_RING(tex->tex_offset[i]);
 214
 215         OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
 216         OUT_RING(tex->tex_border_color);
 217
 218         ADVANCE_RING();
 219 }
 220
 221 static void r128_emit_state(drm_r128_private_t *dev_priv)
 222 {
 223         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 224         unsigned int dirty = sarea_priv->dirty;
 225
 226         DRM_DEBUG("dirty=0x%08x\n", dirty);
 227
 228         if (dirty & R128_UPLOAD_CORE) {
 229                 r128_emit_core(dev_priv);
 230                 sarea_priv->dirty &= ~R128_UPLOAD_CORE;
 231         }
 232
 233         if (dirty & R128_UPLOAD_CONTEXT) {
 234                 r128_emit_context(dev_priv);
 235                 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
 236         }
 237
 238         if (dirty & R128_UPLOAD_SETUP) {
 239                 r128_emit_setup(dev_priv);
 240                 sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
 241         }
 242
 243         if (dirty & R128_UPLOAD_MASKS) {
 244                 r128_emit_masks(dev_priv);
 245                 sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
 246         }
 247
 248         if (dirty & R128_UPLOAD_WINDOW) {
 249                 r128_emit_window(dev_priv);
 250                 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
 251         }
 252
 253         if (dirty & R128_UPLOAD_TEX0) {
 254                 r128_emit_tex0(dev_priv);
 255                 sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
 256         }
 257
 258         if (dirty & R128_UPLOAD_TEX1) {
 259                 r128_emit_tex1(dev_priv);
 260                 sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
 261         }
 262
 263         /* Turn off the texture cache flushing */
 264         sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
 265
 266         sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
 267 }
 268
 269 #if R128_PERFORMANCE_BOXES
 270 /* ================================================================
 271  * Performance monitoring functions
 272  */
 273
 274 static void r128_clear_box(drm_r128_private_t *dev_priv,
 275                            int x, int y, int w, int h, int r, int g, int b)
 276 {
 277         u32 pitch, offset;
 278         u32 fb_bpp, color;
 279         RING_LOCALS;
 280
 281         switch (dev_priv->fb_bpp) {
 282         case 16:
 283                 fb_bpp = R128_GMC_DST_16BPP;
 284                 color = (((r & 0xf8) << 8) |
 285                          ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
 286                 break;
 287         case 24:
 288                 fb_bpp = R128_GMC_DST_24BPP;
 289                 color = ((r << 16) | (g << 8) | b);
 290                 break;
 291         case 32:
 292                 fb_bpp = R128_GMC_DST_32BPP;
 293                 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
 294                 break;
 295         default:
 296                 return;
 297         }
 298
 299         offset = dev_priv->back_offset;
 300         pitch = dev_priv->back_pitch >> 3;
 301
 302         BEGIN_RING(6);
 303
 304         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 305         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 306                  R128_GMC_BRUSH_SOLID_COLOR |
 307                  fb_bpp |
 308                  R128_GMC_SRC_DATATYPE_COLOR |
 309                  R128_ROP3_P |
 310                  R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
 311
 312         OUT_RING((pitch << 21) | (offset >> 5));
 313         OUT_RING(color);
 314
 315         OUT_RING((x << 16) | y);
 316         OUT_RING((w << 16) | h);
 317
 318         ADVANCE_RING();
 319 }
 320
 321 static void r128_cce_performance_boxes(drm_r128_private_t *dev_priv)
 322 {
 323         if (atomic_read(&dev_priv->idle_count) == 0)
 324                 r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
 325         else
 326                 atomic_set(&dev_priv->idle_count, 0);
 327 }
 328
 329 #endif
 330
 331 /* ================================================================
 332  * CCE command dispatch functions
 333  */
 334
 335 static void r128_print_dirty(const char *msg, unsigned int flags)
 336 {
 337         DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
 338                  msg,
 339                  flags,
 340                  (flags & R128_UPLOAD_CORE) ? "core, " : "",
 341                  (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
 342                  (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
 343                  (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
 344                  (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
 345                  (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
 346                  (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
 347                  (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
 348                  (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
 349 }
 350
 351 static void r128_cce_dispatch_clear(struct drm_device *dev,
 352                                     drm_r128_clear_t *clear)
 353 {
 354         drm_r128_private_t *dev_priv = dev->dev_private;
 355         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 356         int nbox = sarea_priv->nbox;
 357         struct drm_clip_rect *pbox = sarea_priv->boxes;
 358         unsigned int flags = clear->flags;
 359         int i;
 360         RING_LOCALS;
 361         DRM_DEBUG("\n");
 362
 363         if (dev_priv->page_flipping && dev_priv->current_page == 1) {
 364                 unsigned int tmp = flags;
 365
 366                 flags &= ~(R128_FRONT | R128_BACK);
 367                 if (tmp & R128_FRONT)
 368                         flags |= R128_BACK;
 369                 if (tmp & R128_BACK)
 370                         flags |= R128_FRONT;
 371         }
 372
 373         for (i = 0; i < nbox; i++) {
 374                 int x = pbox[i].x1;
 375                 int y = pbox[i].y1;
 376                 int w = pbox[i].x2 - x;
 377                 int h = pbox[i].y2 - y;
 378
 379                 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
 380                           pbox[i].x1, pbox[i].y1, pbox[i].x2,
 381                           pbox[i].y2, flags);
 382
 383                 if (flags & (R128_FRONT | R128_BACK)) {
 384                         BEGIN_RING(2);
 385
 386                         OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
 387                         OUT_RING(clear->color_mask);
 388
 389                         ADVANCE_RING();
 390                 }
 391
 392                 if (flags & R128_FRONT) {
 393                         BEGIN_RING(6);
 394
 395                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 396                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 397                                  R128_GMC_BRUSH_SOLID_COLOR |
 398                                  (dev_priv->color_fmt << 8) |
 399                                  R128_GMC_SRC_DATATYPE_COLOR |
 400                                  R128_ROP3_P |
 401                                  R128_GMC_CLR_CMP_CNTL_DIS |
 402                                  R128_GMC_AUX_CLIP_DIS);
 403
 404                         OUT_RING(dev_priv->front_pitch_offset_c);
 405                         OUT_RING(clear->clear_color);
 406
 407                         OUT_RING((x << 16) | y);
 408                         OUT_RING((w << 16) | h);
 409
 410                         ADVANCE_RING();
 411                 }
 412
 413                 if (flags & R128_BACK) {
 414                         BEGIN_RING(6);
 415
 416                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 417                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 418                                  R128_GMC_BRUSH_SOLID_COLOR |
 419                                  (dev_priv->color_fmt << 8) |
 420                                  R128_GMC_SRC_DATATYPE_COLOR |
 421                                  R128_ROP3_P |
 422                                  R128_GMC_CLR_CMP_CNTL_DIS |
 423                                  R128_GMC_AUX_CLIP_DIS);
 424
 425                         OUT_RING(dev_priv->back_pitch_offset_c);
 426                         OUT_RING(clear->clear_color);
 427
 428                         OUT_RING((x << 16) | y);
 429                         OUT_RING((w << 16) | h);
 430
 431                         ADVANCE_RING();
 432                 }
 433
 434                 if (flags & R128_DEPTH) {
 435                         BEGIN_RING(6);
 436
 437                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 438                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 439                                  R128_GMC_BRUSH_SOLID_COLOR |
 440                                  (dev_priv->depth_fmt << 8) |
 441                                  R128_GMC_SRC_DATATYPE_COLOR |
 442                                  R128_ROP3_P |
 443                                  R128_GMC_CLR_CMP_CNTL_DIS |
 444                                  R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
 445
 446                         OUT_RING(dev_priv->depth_pitch_offset_c);
 447                         OUT_RING(clear->clear_depth);
 448
 449                         OUT_RING((x << 16) | y);
 450                         OUT_RING((w << 16) | h);
 451
 452                         ADVANCE_RING();
 453                 }
 454         }
 455 }
 456
 457 static void r128_cce_dispatch_swap(struct drm_device *dev)
 458 {
 459         drm_r128_private_t *dev_priv = dev->dev_private;
 460         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 461         int nbox = sarea_priv->nbox;
 462         struct drm_clip_rect *pbox = sarea_priv->boxes;
 463         int i;
 464         RING_LOCALS;
 465         DRM_DEBUG("\n");
 466
 467 #if R128_PERFORMANCE_BOXES
 468         /* Do some trivial performance monitoring...
 469          */
 470         r128_cce_performance_boxes(dev_priv);
 471 #endif
 472
 473         for (i = 0; i < nbox; i++) {
 474                 int x = pbox[i].x1;
 475                 int y = pbox[i].y1;
 476                 int w = pbox[i].x2 - x;
 477                 int h = pbox[i].y2 - y;
 478
 479                 BEGIN_RING(7);
 480
 481                 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
 482                 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
 483                          R128_GMC_DST_PITCH_OFFSET_CNTL |
 484                          R128_GMC_BRUSH_NONE |
 485                          (dev_priv->color_fmt << 8) |
 486                          R128_GMC_SRC_DATATYPE_COLOR |
 487                          R128_ROP3_S |
 488                          R128_DP_SRC_SOURCE_MEMORY |
 489                          R128_GMC_CLR_CMP_CNTL_DIS |
 490                          R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
 491
 492                 /* Make this work even if front & back are flipped:
 493                  */
 494                 if (dev_priv->current_page == 0) {
 495                         OUT_RING(dev_priv->back_pitch_offset_c);
 496                         OUT_RING(dev_priv->front_pitch_offset_c);
 497                 } else {
 498                         OUT_RING(dev_priv->front_pitch_offset_c);
 499                         OUT_RING(dev_priv->back_pitch_offset_c);
 500                 }
 501
 502                 OUT_RING((x << 16) | y);
 503                 OUT_RING((x << 16) | y);
 504                 OUT_RING((w << 16) | h);
 505
 506                 ADVANCE_RING();
 507         }
 508
 509         /* Increment the frame counter.  The client-side 3D driver must
 510          * throttle the framerate by waiting for this value before
 511          * performing the swapbuffer ioctl.
 512          */
 513         dev_priv->sarea_priv->last_frame++;
 514
 515         BEGIN_RING(2);
 516
 517         OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
 518         OUT_RING(dev_priv->sarea_priv->last_frame);
 519
 520         ADVANCE_RING();
 521 }
 522
 523 static void r128_cce_dispatch_flip(struct drm_device *dev)
 524 {
 525         drm_r128_private_t *dev_priv = dev->dev_private;
 526         RING_LOCALS;
 527         DRM_DEBUG("page=%d pfCurrentPage=%d\n",
 528                   dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
 529
 530 #if R128_PERFORMANCE_BOXES
 531         /* Do some trivial performance monitoring...
 532          */
 533         r128_cce_performance_boxes(dev_priv);
 534 #endif
 535
 536         BEGIN_RING(4);
 537
 538         R128_WAIT_UNTIL_PAGE_FLIPPED();
 539         OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
 540
 541         if (dev_priv->current_page == 0)
 542                 OUT_RING(dev_priv->back_offset);
 543         else
 544                 OUT_RING(dev_priv->front_offset);
 545
 546         ADVANCE_RING();
 547
 548         /* Increment the frame counter.  The client-side 3D driver must
 549          * throttle the framerate by waiting for this value before
 550          * performing the swapbuffer ioctl.
 551          */
 552         dev_priv->sarea_priv->last_frame++;
 553         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
 554             1 - dev_priv->current_page;
 555
 556         BEGIN_RING(2);
 557
 558         OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
 559         OUT_RING(dev_priv->sarea_priv->last_frame);
 560
 561         ADVANCE_RING();
 562 }
 563
 564 static void r128_cce_dispatch_vertex(struct drm_device *dev, struct drm_buf *buf)
 565 {
 566         drm_r128_private_t *dev_priv = dev->dev_private;
 567         drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 568         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 569         int format = sarea_priv->vc_format;
 570         int offset = buf->bus_address;
 571         int size = buf->used;
 572         int prim = buf_priv->prim;
 573         int i = 0;
 574         RING_LOCALS;
 575         DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
 576
 577         if (0)
 578                 r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
 579
 580         if (buf->used) {
 581                 buf_priv->dispatched = 1;
 582
 583                 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS)
 584                         r128_emit_state(dev_priv);
 585
 586                 do {
 587                         /* Emit the next set of up to three cliprects */
 588                         if (i < sarea_priv->nbox) {
 589                                 r128_emit_clip_rects(dev_priv,
 590                                                      &sarea_priv->boxes[i],
 591                                                      sarea_priv->nbox - i);
 592                         }
 593
 594                         /* Emit the vertex buffer rendering commands */
 595                         BEGIN_RING(5);
 596
 597                         OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
 598                         OUT_RING(offset);
 599                         OUT_RING(size);
 600                         OUT_RING(format);
 601                         OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
 602                                  (size << R128_CCE_VC_CNTL_NUM_SHIFT));
 603
 604                         ADVANCE_RING();
 605
 606                         i += 3;
 607                 } while (i < sarea_priv->nbox);
 608         }
 609
 610         if (buf_priv->discard) {
 611                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 612
 613                 /* Emit the vertex buffer age */
 614                 BEGIN_RING(2);
 615
 616                 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
 617                 OUT_RING(buf_priv->age);
 618
 619                 ADVANCE_RING();
 620
 621                 buf->pending = 1;
 622                 buf->used = 0;
 623                 /* FIXME: Check dispatched field */
 624                 buf_priv->dispatched = 0;
 625         }
 626
 627         dev_priv->sarea_priv->last_dispatch++;
 628
 629         sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
 630         sarea_priv->nbox = 0;
 631 }
 632
 633 static void r128_cce_dispatch_indirect(struct drm_device *dev,
 634                                        struct drm_buf *buf, int start, int end)
 635 {
 636         drm_r128_private_t *dev_priv = dev->dev_private;
 637         drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 638         RING_LOCALS;
 639         DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
 640
 641         if (start != end) {
 642                 int offset = buf->bus_address + start;
 643                 int dwords = (end - start + 3) / sizeof(u32);
 644
 645                 /* Indirect buffer data must be an even number of
 646                  * dwords, so if we've been given an odd number we must
 647                  * pad the data with a Type-2 CCE packet.
 648                  */
 649                 if (dwords & 1) {
 650                         u32 *data = (u32 *)
 651                             ((char *)dev->agp_buffer_map->handle
 652                              + buf->offset + start);
 653                         data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
 654                 }
 655
 656                 buf_priv->dispatched = 1;
 657
 658                 /* Fire off the indirect buffer */
 659                 BEGIN_RING(3);
 660
 661                 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
 662                 OUT_RING(offset);
 663                 OUT_RING(dwords);
 664
 665                 ADVANCE_RING();
 666         }
 667
 668         if (buf_priv->discard) {
 669                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 670
 671                 /* Emit the indirect buffer age */
 672                 BEGIN_RING(2);
 673
 674                 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
 675                 OUT_RING(buf_priv->age);
 676
 677                 ADVANCE_RING();
 678
 679                 buf->pending = 1;
 680                 buf->used = 0;
 681                 /* FIXME: Check dispatched field */
 682                 buf_priv->dispatched = 0;
 683         }
 684
 685         dev_priv->sarea_priv->last_dispatch++;
 686 }
 687
 688 static void r128_cce_dispatch_indices(struct drm_device *dev,
 689                                       struct drm_buf *buf,
 690                                       int start, int end, int count)
 691 {
 692         drm_r128_private_t *dev_priv = dev->dev_private;
 693         drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 694         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 695         int format = sarea_priv->vc_format;
 696         int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset;
 697         int prim = buf_priv->prim;
 698         u32 *data;
 699         int dwords;
 700         int i = 0;
 701         RING_LOCALS;
 702         DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
 703
 704         if (0)
 705                 r128_print_dirty("dispatch_indices", sarea_priv->dirty);
 706
 707         if (start != end) {
 708                 buf_priv->dispatched = 1;
 709
 710                 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS)
 711                         r128_emit_state(dev_priv);
 712
 713                 dwords = (end - start + 3) / sizeof(u32);
 714
 715                 data = (u32 *) ((char *)dev->agp_buffer_map->handle
 716                                 + buf->offset + start);
 717
 718                 data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
 719                                                   dwords - 2));
 720
 721                 data[1] = cpu_to_le32(offset);
 722                 data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
 723                 data[3] = cpu_to_le32(format);
 724                 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
 725                                        (count << 16)));
 726
 727                 if (count & 0x1) {
 728 #ifdef __LITTLE_ENDIAN
 729                         data[dwords - 1] &= 0x0000ffff;
 730 #else
 731                         data[dwords - 1] &= 0xffff0000;
 732 #endif
 733                 }
 734
 735                 do {
 736                         /* Emit the next set of up to three cliprects */
 737                         if (i < sarea_priv->nbox) {
 738                                 r128_emit_clip_rects(dev_priv,
 739                                                      &sarea_priv->boxes[i],
 740                                                      sarea_priv->nbox - i);
 741                         }
 742
 743                         r128_cce_dispatch_indirect(dev, buf, start, end);
 744
 745                         i += 3;
 746                 } while (i < sarea_priv->nbox);
 747         }
 748
 749         if (buf_priv->discard) {
 750                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 751
 752                 /* Emit the vertex buffer age */
 753                 BEGIN_RING(2);
 754
 755                 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
 756                 OUT_RING(buf_priv->age);
 757
 758                 ADVANCE_RING();
 759
 760                 buf->pending = 1;
 761                 /* FIXME: Check dispatched field */
 762                 buf_priv->dispatched = 0;
 763         }
 764
 765         dev_priv->sarea_priv->last_dispatch++;
 766
 767         sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
 768         sarea_priv->nbox = 0;
 769 }
 770
 771 static int r128_cce_dispatch_blit(struct drm_device *dev,
 772                                   struct drm_file *file_priv,
 773                                   drm_r128_blit_t *blit)
 774 {
 775         drm_r128_private_t *dev_priv = dev->dev_private;
 776         struct drm_device_dma *dma = dev->dma;
 777         struct drm_buf *buf;
 778         drm_r128_buf_priv_t *buf_priv;
 779         u32 *data;
 780         int dword_shift, dwords;
 781         RING_LOCALS;
 782         DRM_DEBUG("\n");
 783
 784         /* The compiler won't optimize away a division by a variable,
 785          * even if the only legal values are powers of two.  Thus, we'll
 786          * use a shift instead.
 787          */
 788         switch (blit->format) {
 789         case R128_DATATYPE_ARGB8888:
 790                 dword_shift = 0;
 791                 break;
 792         case R128_DATATYPE_ARGB1555:
 793         case R128_DATATYPE_RGB565:
 794         case R128_DATATYPE_ARGB4444:
 795         case R128_DATATYPE_YVYU422:
 796         case R128_DATATYPE_VYUY422:
 797                 dword_shift = 1;
 798                 break;
 799         case R128_DATATYPE_CI8:
 800         case R128_DATATYPE_RGB8:
 801                 dword_shift = 2;
 802                 break;
 803         default:
 804                 DRM_ERROR("invalid blit format %d\n", blit->format);
 805                 return -EINVAL;
 806         }
 807
 808         /* Flush the pixel cache, and mark the contents as Read Invalid.
 809          * This ensures no pixel data gets mixed up with the texture
 810          * data from the host data blit, otherwise part of the texture
 811          * image may be corrupted.
 812          */
 813         BEGIN_RING(2);
 814
 815         OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
 816         OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
 817
 818         ADVANCE_RING();
 819
 820         /* Dispatch the indirect buffer.
 821          */
 822         buf = dma->buflist[blit->idx];
 823         buf_priv = buf->dev_private;
 824
 825         if (buf->file_priv != file_priv) {
 826                 DRM_ERROR("process %d using buffer owned by %p\n",
 827                           DRM_CURRENTPID, buf->file_priv);
 828                 return -EINVAL;
 829         }
 830         if (buf->pending) {
 831                 DRM_ERROR("sending pending buffer %d\n", blit->idx);
 832                 return -EINVAL;
 833         }
 834
 835         buf_priv->discard = 1;
 836
 837         dwords = (blit->width * blit->height) >> dword_shift;
 838
 839         data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
 840
 841         data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
 842         data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
 843                                R128_GMC_BRUSH_NONE |
 844                                (blit->format << 8) |
 845                                R128_GMC_SRC_DATATYPE_COLOR |
 846                                R128_ROP3_S |
 847                                R128_DP_SRC_SOURCE_HOST_DATA |
 848                                R128_GMC_CLR_CMP_CNTL_DIS |
 849                                R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
 850
 851         data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
 852         data[3] = cpu_to_le32(0xffffffff);
 853         data[4] = cpu_to_le32(0xffffffff);
 854         data[5] = cpu_to_le32((blit->y << 16) | blit->x);
 855         data[6] = cpu_to_le32((blit->height << 16) | blit->width);
 856         data[7] = cpu_to_le32(dwords);
 857
 858         buf->used = (dwords + 8) * sizeof(u32);
 859
 860         r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
 861
 862         /* Flush the pixel cache after the blit completes.  This ensures
 863          * the texture data is written out to memory before rendering
 864          * continues.
 865          */
 866         BEGIN_RING(2);
 867
 868         OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
 869         OUT_RING(R128_PC_FLUSH_GUI);
 870
 871         ADVANCE_RING();
 872
 873         return 0;
 874 }
 875
 876 /* ================================================================
 877  * Tiled depth buffer management
 878  *
 879  * FIXME: These should all set the destination write mask for when we
 880  * have hardware stencil support.
 881  */
 882
 883 static int r128_cce_dispatch_write_span(struct drm_device *dev,
 884                                         drm_r128_depth_t *depth)
 885 {
 886         drm_r128_private_t *dev_priv = dev->dev_private;
 887         int count, x, y;
 888         u32 *buffer;
 889         u8 *mask;
 890         int i, buffer_size, mask_size;
 891         RING_LOCALS;
 892         DRM_DEBUG("\n");
 893
 894         count = depth->n;
 895         if (count > 4096 || count <= 0)
 896                 return -EMSGSIZE;
 897
 898         if (copy_from_user(&x, depth->x, sizeof(x)))
 899                 return -EFAULT;
 900         if (copy_from_user(&y, depth->y, sizeof(y)))
 901                 return -EFAULT;
 902
 903         buffer_size = depth->n * sizeof(u32);
 904         buffer = memdup_user(depth->buffer, buffer_size);
 905         if (IS_ERR(buffer))
 906                 return PTR_ERR(buffer);
 907
 908         mask_size = depth->n;
 909         if (depth->mask) {
 910                 mask = memdup_user(depth->mask, mask_size);
 911                 if (IS_ERR(mask)) {
 912                         kfree(buffer);
 913                         return PTR_ERR(mask);
 914                 }
 915
 916                 for (i = 0; i < count; i++, x++) {
 917                         if (mask[i]) {
 918                                 BEGIN_RING(6);
 919
 920                                 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 921                                 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 922                                          R128_GMC_BRUSH_SOLID_COLOR |
 923                                          (dev_priv->depth_fmt << 8) |
 924                                          R128_GMC_SRC_DATATYPE_COLOR |
 925                                          R128_ROP3_P |
 926                                          R128_GMC_CLR_CMP_CNTL_DIS |
 927                                          R128_GMC_WR_MSK_DIS);
 928
 929                                 OUT_RING(dev_priv->depth_pitch_offset_c);
 930                                 OUT_RING(buffer[i]);
 931
 932                                 OUT_RING((x << 16) | y);
 933                                 OUT_RING((1 << 16) | 1);
 934
 935                                 ADVANCE_RING();
 936                         }
 937                 }
 938
 939                 kfree(mask);
 940         } else {
 941                 for (i = 0; i < count; i++, x++) {
 942                         BEGIN_RING(6);
 943
 944                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 945                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 946                                  R128_GMC_BRUSH_SOLID_COLOR |
 947                                  (dev_priv->depth_fmt << 8) |
 948                                  R128_GMC_SRC_DATATYPE_COLOR |
 949                                  R128_ROP3_P |
 950                                  R128_GMC_CLR_CMP_CNTL_DIS |
 951                                  R128_GMC_WR_MSK_DIS);
 952
 953                         OUT_RING(dev_priv->depth_pitch_offset_c);
 954                         OUT_RING(buffer[i]);
 955
 956                         OUT_RING((x << 16) | y);
 957                         OUT_RING((1 << 16) | 1);
 958
 959                         ADVANCE_RING();
 960                 }
 961         }
 962
 963         kfree(buffer);
 964
 965         return 0;
 966 }
 967
 968 static int r128_cce_dispatch_write_pixels(struct drm_device *dev,
 969                                           drm_r128_depth_t *depth)
 970 {
 971         drm_r128_private_t *dev_priv = dev->dev_private;
 972         int count, *x, *y;
 973         u32 *buffer;
 974         u8 *mask;
 975         int i, xbuf_size, ybuf_size, buffer_size, mask_size;
 976         RING_LOCALS;
 977         DRM_DEBUG("\n");
 978
 979         count = depth->n;
 980         if (count > 4096 || count <= 0)
 981                 return -EMSGSIZE;
 982
 983         xbuf_size = count * sizeof(*x);
 984         ybuf_size = count * sizeof(*y);
 985         x = memdup_user(depth->x, xbuf_size);
 986         if (IS_ERR(x))
 987                 return PTR_ERR(x);
 988         y = memdup_user(depth->y, ybuf_size);
 989         if (IS_ERR(y)) {
 990                 kfree(x);
 991                 return PTR_ERR(y);
 992         }
 993         buffer_size = depth->n * sizeof(u32);
 994         buffer = memdup_user(depth->buffer, buffer_size);
 995         if (IS_ERR(buffer)) {
 996                 kfree(x);
 997                 kfree(y);
 998                 return PTR_ERR(buffer);
 999         }
1000
1001         if (depth->mask) {
1002                 mask_size = depth->n;
1003                 mask = memdup_user(depth->mask, mask_size);
1004                 if (IS_ERR(mask)) {
1005                         kfree(x);
1006                         kfree(y);
1007                         kfree(buffer);
1008                         return PTR_ERR(mask);
1009                 }
1010
1011                 for (i = 0; i < count; i++) {
1012                         if (mask[i]) {
1013                                 BEGIN_RING(6);
1014
1015                                 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1016                                 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1017                                          R128_GMC_BRUSH_SOLID_COLOR |
1018                                          (dev_priv->depth_fmt << 8) |
1019                                          R128_GMC_SRC_DATATYPE_COLOR |
1020                                          R128_ROP3_P |
1021                                          R128_GMC_CLR_CMP_CNTL_DIS |
1022                                          R128_GMC_WR_MSK_DIS);
1023
1024                                 OUT_RING(dev_priv->depth_pitch_offset_c);
1025                                 OUT_RING(buffer[i]);
1026
1027                                 OUT_RING((x[i] << 16) | y[i]);
1028                                 OUT_RING((1 << 16) | 1);
1029
1030                                 ADVANCE_RING();
1031                         }
1032                 }
1033
1034                 kfree(mask);
1035         } else {
1036                 for (i = 0; i < count; i++) {
1037                         BEGIN_RING(6);
1038
1039                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1040                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1041                                  R128_GMC_BRUSH_SOLID_COLOR |
1042                                  (dev_priv->depth_fmt << 8) |
1043                                  R128_GMC_SRC_DATATYPE_COLOR |
1044                                  R128_ROP3_P |
1045                                  R128_GMC_CLR_CMP_CNTL_DIS |
1046                                  R128_GMC_WR_MSK_DIS);
1047
1048                         OUT_RING(dev_priv->depth_pitch_offset_c);
1049                         OUT_RING(buffer[i]);
1050
1051                         OUT_RING((x[i] << 16) | y[i]);
1052                         OUT_RING((1 << 16) | 1);
1053
1054                         ADVANCE_RING();
1055                 }
1056         }
1057
1058         kfree(x);
1059         kfree(y);
1060         kfree(buffer);
1061
1062         return 0;
1063 }
1064
1065 static int r128_cce_dispatch_read_span(struct drm_device *dev,
1066                                        drm_r128_depth_t *depth)
1067 {
1068         drm_r128_private_t *dev_priv = dev->dev_private;
1069         int count, x, y;
1070         RING_LOCALS;
1071         DRM_DEBUG("\n");
1072
1073         count = depth->n;
1074         if (count > 4096 || count <= 0)
1075                 return -EMSGSIZE;
1076
1077         if (copy_from_user(&x, depth->x, sizeof(x)))
1078                 return -EFAULT;
1079         if (copy_from_user(&y, depth->y, sizeof(y)))
1080                 return -EFAULT;
1081
1082         BEGIN_RING(7);
1083
1084         OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1085         OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1086                  R128_GMC_DST_PITCH_OFFSET_CNTL |
1087                  R128_GMC_BRUSH_NONE |
1088                  (dev_priv->depth_fmt << 8) |
1089                  R128_GMC_SRC_DATATYPE_COLOR |
1090                  R128_ROP3_S |
1091                  R128_DP_SRC_SOURCE_MEMORY |
1092                  R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1093
1094         OUT_RING(dev_priv->depth_pitch_offset_c);
1095         OUT_RING(dev_priv->span_pitch_offset_c);
1096
1097         OUT_RING((x << 16) | y);
1098         OUT_RING((0 << 16) | 0);
1099         OUT_RING((count << 16) | 1);
1100
1101         ADVANCE_RING();
1102
1103         return 0;
1104 }
1105
1106 static int r128_cce_dispatch_read_pixels(struct drm_device *dev,
1107                                          drm_r128_depth_t *depth)
1108 {
1109         drm_r128_private_t *dev_priv = dev->dev_private;
1110         int count, *x, *y;
1111         int i, xbuf_size, ybuf_size;
1112         RING_LOCALS;
1113         DRM_DEBUG("\n");
1114
1115         count = depth->n;
1116         if (count > 4096 || count <= 0)
1117                 return -EMSGSIZE;
1118
1119         if (count > dev_priv->depth_pitch)
1120                 count = dev_priv->depth_pitch;
1121
1122         xbuf_size = count * sizeof(*x);
1123         ybuf_size = count * sizeof(*y);
1124         x = kmalloc(xbuf_size, GFP_KERNEL);
1125         if (x == NULL)
1126                 return -ENOMEM;
1127         y = kmalloc(ybuf_size, GFP_KERNEL);
1128         if (y == NULL) {
1129                 kfree(x);
1130                 return -ENOMEM;
1131         }
1132         if (copy_from_user(x, depth->x, xbuf_size)) {
1133                 kfree(x);
1134                 kfree(y);
1135                 return -EFAULT;
1136         }
1137         if (copy_from_user(y, depth->y, ybuf_size)) {
1138                 kfree(x);
1139                 kfree(y);
1140                 return -EFAULT;
1141         }
1142
1143         for (i = 0; i < count; i++) {
1144                 BEGIN_RING(7);
1145
1146                 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1147                 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1148                          R128_GMC_DST_PITCH_OFFSET_CNTL |
1149                          R128_GMC_BRUSH_NONE |
1150                          (dev_priv->depth_fmt << 8) |
1151                          R128_GMC_SRC_DATATYPE_COLOR |
1152                          R128_ROP3_S |
1153                          R128_DP_SRC_SOURCE_MEMORY |
1154                          R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1155
1156                 OUT_RING(dev_priv->depth_pitch_offset_c);
1157                 OUT_RING(dev_priv->span_pitch_offset_c);
1158
1159                 OUT_RING((x[i] << 16) | y[i]);
1160                 OUT_RING((i << 16) | 0);
1161                 OUT_RING((1 << 16) | 1);
1162
1163                 ADVANCE_RING();
1164         }
1165
1166         kfree(x);
1167         kfree(y);
1168
1169         return 0;
1170 }
1171
1172 /* ================================================================
1173  * Polygon stipple
1174  */
1175
1176 static void r128_cce_dispatch_stipple(struct drm_device *dev, u32 *stipple)
1177 {
1178         drm_r128_private_t *dev_priv = dev->dev_private;
1179         int i;
1180         RING_LOCALS;
1181         DRM_DEBUG("\n");
1182
1183         BEGIN_RING(33);
1184
1185         OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
1186         for (i = 0; i < 32; i++)
1187                 OUT_RING(stipple[i]);
1188
1189         ADVANCE_RING();
1190 }
1191
1192 /* ================================================================
1193  * IOCTL functions
1194  */
1195
1196 static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
1197 {
1198         drm_r128_private_t *dev_priv = dev->dev_private;
1199         drm_r128_sarea_t *sarea_priv;
1200         drm_r128_clear_t *clear = data;
1201         DRM_DEBUG("\n");
1202
1203         LOCK_TEST_WITH_RETURN(dev, file_priv);
1204
1205         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1206
1207         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1208
1209         sarea_priv = dev_priv->sarea_priv;
1210
1211         if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1212                 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1213
1214         r128_cce_dispatch_clear(dev, clear);
1215         COMMIT_RING();
1216
1217         /* Make sure we restore the 3D state next time.
1218          */
1219         dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
1220
1221         return 0;
1222 }
1223
1224 static int r128_do_init_pageflip(struct drm_device *dev)
1225 {
1226         drm_r128_private_t *dev_priv = dev->dev_private;
1227         DRM_DEBUG("\n");
1228
1229         dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1230         dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
1231
1232         R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1233         R128_WRITE(R128_CRTC_OFFSET_CNTL,
1234                    dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
1235
1236         dev_priv->page_flipping = 1;
1237         dev_priv->current_page = 0;
1238         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1239
1240         return 0;
1241 }
1242
1243 static int r128_do_cleanup_pageflip(struct drm_device *dev)
1244 {
1245         drm_r128_private_t *dev_priv = dev->dev_private;
1246         DRM_DEBUG("\n");
1247
1248         R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1249         R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
1250
1251         if (dev_priv->current_page != 0) {
1252                 r128_cce_dispatch_flip(dev);
1253                 COMMIT_RING();
1254         }
1255
1256         dev_priv->page_flipping = 0;
1257         return 0;
1258 }
1259
1260 /* Swapping and flipping are different operations, need different ioctls.
1261  * They can & should be intermixed to support multiple 3d windows.
1262  */
1263
1264 static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
1265 {
1266         drm_r128_private_t *dev_priv = dev->dev_private;
1267         DRM_DEBUG("\n");
1268
1269         LOCK_TEST_WITH_RETURN(dev, file_priv);
1270
1271         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1272
1273         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1274
1275         if (!dev_priv->page_flipping)
1276                 r128_do_init_pageflip(dev);
1277
1278         r128_cce_dispatch_flip(dev);
1279
1280         COMMIT_RING();
1281         return 0;
1282 }
1283
1284 static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
1285 {
1286         drm_r128_private_t *dev_priv = dev->dev_private;
1287         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1288         DRM_DEBUG("\n");
1289
1290         LOCK_TEST_WITH_RETURN(dev, file_priv);
1291
1292         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1293
1294         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1295
1296         if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1297                 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1298
1299         r128_cce_dispatch_swap(dev);
1300         dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
1301                                         R128_UPLOAD_MASKS);
1302
1303         COMMIT_RING();
1304         return 0;
1305 }
1306
1307 static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
1308 {
1309         drm_r128_private_t *dev_priv = dev->dev_private;
1310         struct drm_device_dma *dma = dev->dma;
1311         struct drm_buf *buf;
1312         drm_r128_buf_priv_t *buf_priv;
1313         drm_r128_vertex_t *vertex = data;
1314
1315         LOCK_TEST_WITH_RETURN(dev, file_priv);
1316
1317         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1318
1319         DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
1320                   DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
1321
1322         if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
1323                 DRM_ERROR("buffer index %d (of %d max)\n",
1324                           vertex->idx, dma->buf_count - 1);
1325                 return -EINVAL;
1326         }
1327         if (vertex->prim < 0 ||
1328             vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1329                 DRM_ERROR("buffer prim %d\n", vertex->prim);
1330                 return -EINVAL;
1331         }
1332
1333         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1334         VB_AGE_TEST_WITH_RETURN(dev_priv);
1335
1336         buf = dma->buflist[vertex->idx];
1337         buf_priv = buf->dev_private;
1338
1339         if (buf->file_priv != file_priv) {
1340                 DRM_ERROR("process %d using buffer owned by %p\n",
1341                           DRM_CURRENTPID, buf->file_priv);
1342                 return -EINVAL;
1343         }
1344         if (buf->pending) {
1345                 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
1346                 return -EINVAL;
1347         }
1348
1349         buf->used = vertex->count;
1350         buf_priv->prim = vertex->prim;
1351         buf_priv->discard = vertex->discard;
1352
1353         r128_cce_dispatch_vertex(dev, buf);
1354
1355         COMMIT_RING();
1356         return 0;
1357 }
1358
1359 static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
1360 {
1361         drm_r128_private_t *dev_priv = dev->dev_private;
1362         struct drm_device_dma *dma = dev->dma;
1363         struct drm_buf *buf;
1364         drm_r128_buf_priv_t *buf_priv;
1365         drm_r128_indices_t *elts = data;
1366         int count;
1367
1368         LOCK_TEST_WITH_RETURN(dev, file_priv);
1369
1370         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1371
1372         DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
1373                   elts->idx, elts->start, elts->end, elts->discard);
1374
1375         if (elts->idx < 0 || elts->idx >= dma->buf_count) {
1376                 DRM_ERROR("buffer index %d (of %d max)\n",
1377                           elts->idx, dma->buf_count - 1);
1378                 return -EINVAL;
1379         }
1380         if (elts->prim < 0 ||
1381             elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1382                 DRM_ERROR("buffer prim %d\n", elts->prim);
1383                 return -EINVAL;
1384         }
1385
1386         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1387         VB_AGE_TEST_WITH_RETURN(dev_priv);
1388
1389         buf = dma->buflist[elts->idx];
1390         buf_priv = buf->dev_private;
1391
1392         if (buf->file_priv != file_priv) {
1393                 DRM_ERROR("process %d using buffer owned by %p\n",
1394                           DRM_CURRENTPID, buf->file_priv);
1395                 return -EINVAL;
1396         }
1397         if (buf->pending) {
1398                 DRM_ERROR("sending pending buffer %d\n", elts->idx);
1399                 return -EINVAL;
1400         }
1401
1402         count = (elts->end - elts->start) / sizeof(u16);
1403         elts->start -= R128_INDEX_PRIM_OFFSET;
1404
1405         if (elts->start & 0x7) {
1406                 DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
1407                 return -EINVAL;
1408         }
1409         if (elts->start < buf->used) {
1410                 DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
1411                 return -EINVAL;
1412         }
1413
1414         buf->used = elts->end;
1415         buf_priv->prim = elts->prim;
1416         buf_priv->discard = elts->discard;
1417
1418         r128_cce_dispatch_indices(dev, buf, elts->start, elts->end, count);
1419
1420         COMMIT_RING();
1421         return 0;
1422 }
1423
1424 static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
1425 {
1426         struct drm_device_dma *dma = dev->dma;
1427         drm_r128_private_t *dev_priv = dev->dev_private;
1428         drm_r128_blit_t *blit = data;
1429         int ret;
1430
1431         LOCK_TEST_WITH_RETURN(dev, file_priv);
1432
1433         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1434
1435         DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx);
1436
1437         if (blit->idx < 0 || blit->idx >= dma->buf_count) {
1438                 DRM_ERROR("buffer index %d (of %d max)\n",
1439                           blit->idx, dma->buf_count - 1);
1440                 return -EINVAL;
1441         }
1442
1443         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1444         VB_AGE_TEST_WITH_RETURN(dev_priv);
1445
1446         ret = r128_cce_dispatch_blit(dev, file_priv, blit);
1447
1448         COMMIT_RING();
1449         return ret;
1450 }
1451
1452 int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv)
1453 {
1454         drm_r128_private_t *dev_priv = dev->dev_private;
1455         drm_r128_depth_t *depth = data;
1456         int ret;
1457
1458         LOCK_TEST_WITH_RETURN(dev, file_priv);
1459
1460         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1461
1462         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1463
1464         ret = -EINVAL;
1465         switch (depth->func) {
1466         case R128_WRITE_SPAN:
1467                 ret = r128_cce_dispatch_write_span(dev, depth);
1468                 break;
1469         case R128_WRITE_PIXELS:
1470                 ret = r128_cce_dispatch_write_pixels(dev, depth);
1471                 break;
1472         case R128_READ_SPAN:
1473                 ret = r128_cce_dispatch_read_span(dev, depth);
1474                 break;
1475         case R128_READ_PIXELS:
1476                 ret = r128_cce_dispatch_read_pixels(dev, depth);
1477                 break;
1478         }
1479
1480         COMMIT_RING();
1481         return ret;
1482 }
1483
1484 int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
1485 {
1486         drm_r128_private_t *dev_priv = dev->dev_private;
1487         drm_r128_stipple_t *stipple = data;
1488         u32 mask[32];
1489
1490         LOCK_TEST_WITH_RETURN(dev, file_priv);
1491
1492         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1493
1494         if (copy_from_user(&mask, stipple->mask, 32 * sizeof(u32)))
1495                 return -EFAULT;
1496
1497         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1498
1499         r128_cce_dispatch_stipple(dev, mask);
1500
1501         COMMIT_RING();
1502         return 0;
1503 }
1504
1505 static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
1506 {
1507         drm_r128_private_t *dev_priv = dev->dev_private;
1508         struct drm_device_dma *dma = dev->dma;
1509         struct drm_buf *buf;
1510         drm_r128_buf_priv_t *buf_priv;
1511         drm_r128_indirect_t *indirect = data;
1512 #if 0
1513         RING_LOCALS;
1514 #endif
1515
1516         LOCK_TEST_WITH_RETURN(dev, file_priv);
1517
1518         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1519
1520         DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
1521                   indirect->idx, indirect->start, indirect->end,
1522                   indirect->discard);
1523
1524         if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
1525                 DRM_ERROR("buffer index %d (of %d max)\n",
1526                           indirect->idx, dma->buf_count - 1);
1527                 return -EINVAL;
1528         }
1529
1530         buf = dma->buflist[indirect->idx];
1531         buf_priv = buf->dev_private;
1532
1533         if (buf->file_priv != file_priv) {
1534                 DRM_ERROR("process %d using buffer owned by %p\n",
1535                           DRM_CURRENTPID, buf->file_priv);
1536                 return -EINVAL;
1537         }
1538         if (buf->pending) {
1539                 DRM_ERROR("sending pending buffer %d\n", indirect->idx);
1540                 return -EINVAL;
1541         }
1542
1543         if (indirect->start < buf->used) {
1544                 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
1545                           indirect->start, buf->used);
1546                 return -EINVAL;
1547         }
1548
1549         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1550         VB_AGE_TEST_WITH_RETURN(dev_priv);
1551
1552         buf->used = indirect->end;
1553         buf_priv->discard = indirect->discard;
1554
1555 #if 0
1556         /* Wait for the 3D stream to idle before the indirect buffer
1557          * containing 2D acceleration commands is processed.
1558          */
1559         BEGIN_RING(2);
1560         RADEON_WAIT_UNTIL_3D_IDLE();
1561         ADVANCE_RING();
1562 #endif
1563
1564         /* Dispatch the indirect buffer full of commands from the
1565          * X server.  This is insecure and is thus only available to
1566          * privileged clients.
1567          */
1568         r128_cce_dispatch_indirect(dev, buf, indirect->start, indirect->end);
1569
1570         COMMIT_RING();
1571         return 0;
1572 }
1573
1574 int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
1575 {
1576         drm_r128_private_t *dev_priv = dev->dev_private;
1577         drm_r128_getparam_t *param = data;
1578         int value;
1579
1580         DEV_INIT_TEST_WITH_RETURN(dev_priv);
1581
1582         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1583
1584         switch (param->param) {
1585         case R128_PARAM_IRQ_NR:
1586                 value = dev->pdev->irq;
1587                 break;
1588         default:
1589                 return -EINVAL;
1590         }
1591
1592         if (copy_to_user(param->value, &value, sizeof(int))) {
1593                 DRM_ERROR("copy_to_user\n");
1594                 return -EFAULT;
1595         }
1596
1597         return 0;
1598 }
1599
1600 void r128_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
1601 {
1602         if (dev->dev_private) {
1603                 drm_r128_private_t *dev_priv = dev->dev_private;
1604                 if (dev_priv->page_flipping)
1605                         r128_do_cleanup_pageflip(dev);
1606         }
1607 }
1608 void r128_driver_lastclose(struct drm_device *dev)
1609 {
1610         r128_do_cleanup_cce(dev);
1611 }
1612
1613 const struct drm_ioctl_desc r128_ioctls[] = {
1614         DRM_IOCTL_DEF_DRV(R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1615         DRM_IOCTL_DEF_DRV(R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1616         DRM_IOCTL_DEF_DRV(R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1617         DRM_IOCTL_DEF_DRV(R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1618         DRM_IOCTL_DEF_DRV(R128_CCE_IDLE, r128_cce_idle, DRM_AUTH),
1619         DRM_IOCTL_DEF_DRV(R128_RESET, r128_engine_reset, DRM_AUTH),
1620         DRM_IOCTL_DEF_DRV(R128_FULLSCREEN, r128_fullscreen, DRM_AUTH),
1621         DRM_IOCTL_DEF_DRV(R128_SWAP, r128_cce_swap, DRM_AUTH),
1622         DRM_IOCTL_DEF_DRV(R128_FLIP, r128_cce_flip, DRM_AUTH),
1623         DRM_IOCTL_DEF_DRV(R128_CLEAR, r128_cce_clear, DRM_AUTH),
1624         DRM_IOCTL_DEF_DRV(R128_VERTEX, r128_cce_vertex, DRM_AUTH),
1625         DRM_IOCTL_DEF_DRV(R128_INDICES, r128_cce_indices, DRM_AUTH),
1626         DRM_IOCTL_DEF_DRV(R128_BLIT, r128_cce_blit, DRM_AUTH),
1627         DRM_IOCTL_DEF_DRV(R128_DEPTH, r128_cce_depth, DRM_AUTH),
1628         DRM_IOCTL_DEF_DRV(R128_STIPPLE, r128_cce_stipple, DRM_AUTH),
1629         DRM_IOCTL_DEF_DRV(R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1630         DRM_IOCTL_DEF_DRV(R128_GETPARAM, r128_getparam, DRM_AUTH),
1631 };
1632
1633 int r128_max_ioctl = ARRAY_SIZE(r128_ioctls);