2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
43 * @modes: Pointer to array of fixed modes appropriate for this panel. If
44 * only one mode then this can just be the address of this the mode.
45 * NOTE: cannot be used with "timings" and also if this is specified
46 * then you cannot override the mode in the device tree.
47 * @num_modes: Number of elements in modes array.
48 * @timings: Pointer to array of display timings. NOTE: cannot be used with
49 * "modes" and also these will be used to validate a device tree
50 * override if one is present.
51 * @num_timings: Number of elements in timings array.
52 * @bpc: Bits per color.
53 * @size: Structure containing the physical size of this panel.
54 * @delay: Structure containing various delay values for this panel.
55 * @bus_format: See MEDIA_BUS_FMT_... defines.
56 * @bus_flags: See DRM_BUS_FLAG_... defines.
57 * @connector_type: LVDS, eDP, DSI, DPI, etc.
60 const struct drm_display_mode *modes;
61 unsigned int num_modes;
62 const struct display_timing *timings;
63 unsigned int num_timings;
69 * @size.width: Width (in mm) of the active display area.
74 * @size.height: Height (in mm) of the active display area.
81 * @delay.prepare: Time for the panel to become ready.
83 * The time (in milliseconds) that it takes for the panel to
84 * become ready and start receiving video data
89 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up.
91 * Add this to the prepare delay if we know Hot Plug Detect
94 unsigned int hpd_absent_delay;
97 * @delay.prepare_to_enable: Time between prepare and enable.
99 * The minimum time, in milliseconds, that needs to have passed
100 * between when prepare finished and enable may begin. If at
101 * enable time less time has passed since prepare finished,
102 * the driver waits for the remaining time.
104 * If a fixed enable delay is also specified, we'll start
105 * counting before delaying for the fixed delay.
107 * If a fixed prepare delay is also specified, we won't start
108 * counting until after the fixed delay. We can't overlap this
109 * fixed delay with the min time because the fixed delay
110 * doesn't happen at the end of the function if a HPD GPIO was
116 * // do fixed prepare delay
117 * // wait for HPD GPIO if applicable
118 * // start counting for prepare_to_enable
121 * // do fixed enable delay
122 * // enforce prepare_to_enable min time
124 unsigned int prepare_to_enable;
127 * @delay.enable: Time for the panel to display a valid frame.
129 * The time (in milliseconds) that it takes for the panel to
130 * display the first valid frame after starting to receive
136 * @delay.disable: Time for the panel to turn the display off.
138 * The time (in milliseconds) that it takes for the panel to
139 * turn the display off (no content is visible).
141 unsigned int disable;
144 * @delay.unprepare: Time to power down completely.
146 * The time (in milliseconds) that it takes for the panel
147 * to power itself down completely.
149 * This time is used to prevent a future "prepare" from
150 * starting until at least this many milliseconds has passed.
151 * If at prepare time less time has passed since unprepare
152 * finished, the driver waits for the remaining time.
154 unsigned int unprepare;
162 struct panel_simple {
163 struct drm_panel base;
167 ktime_t prepared_time;
168 ktime_t unprepared_time;
170 const struct panel_desc *desc;
172 struct regulator *supply;
173 struct i2c_adapter *ddc;
175 struct gpio_desc *enable_gpio;
176 struct gpio_desc *hpd_gpio;
178 struct drm_display_mode override_mode;
180 enum drm_panel_orientation orientation;
183 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
185 return container_of(panel, struct panel_simple, base);
188 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
189 struct drm_connector *connector)
191 struct drm_display_mode *mode;
192 unsigned int i, num = 0;
194 for (i = 0; i < panel->desc->num_timings; i++) {
195 const struct display_timing *dt = &panel->desc->timings[i];
198 videomode_from_timing(dt, &vm);
199 mode = drm_mode_create(connector->dev);
201 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
202 dt->hactive.typ, dt->vactive.typ);
206 drm_display_mode_from_videomode(&vm, mode);
208 mode->type |= DRM_MODE_TYPE_DRIVER;
210 if (panel->desc->num_timings == 1)
211 mode->type |= DRM_MODE_TYPE_PREFERRED;
213 drm_mode_probed_add(connector, mode);
220 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
221 struct drm_connector *connector)
223 struct drm_display_mode *mode;
224 unsigned int i, num = 0;
226 for (i = 0; i < panel->desc->num_modes; i++) {
227 const struct drm_display_mode *m = &panel->desc->modes[i];
229 mode = drm_mode_duplicate(connector->dev, m);
231 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
232 m->hdisplay, m->vdisplay,
233 drm_mode_vrefresh(m));
237 mode->type |= DRM_MODE_TYPE_DRIVER;
239 if (panel->desc->num_modes == 1)
240 mode->type |= DRM_MODE_TYPE_PREFERRED;
242 drm_mode_set_name(mode);
244 drm_mode_probed_add(connector, mode);
251 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
252 struct drm_connector *connector)
254 struct drm_display_mode *mode;
255 bool has_override = panel->override_mode.type;
256 unsigned int num = 0;
262 mode = drm_mode_duplicate(connector->dev,
263 &panel->override_mode);
265 drm_mode_probed_add(connector, mode);
268 dev_err(panel->base.dev, "failed to add override mode\n");
272 /* Only add timings if override was not there or failed to validate */
273 if (num == 0 && panel->desc->num_timings)
274 num = panel_simple_get_timings_modes(panel, connector);
277 * Only add fixed modes if timings/override added no mode.
279 * We should only ever have either the display timings specified
280 * or a fixed mode. Anything else is rather bogus.
282 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
284 num = panel_simple_get_display_modes(panel, connector);
286 connector->display_info.bpc = panel->desc->bpc;
287 connector->display_info.width_mm = panel->desc->size.width;
288 connector->display_info.height_mm = panel->desc->size.height;
289 if (panel->desc->bus_format)
290 drm_display_info_set_bus_formats(&connector->display_info,
291 &panel->desc->bus_format, 1);
292 connector->display_info.bus_flags = panel->desc->bus_flags;
297 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
299 ktime_t now_ktime, min_ktime;
304 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
305 now_ktime = ktime_get();
307 if (ktime_before(now_ktime, min_ktime))
308 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
311 static int panel_simple_disable(struct drm_panel *panel)
313 struct panel_simple *p = to_panel_simple(panel);
318 if (p->desc->delay.disable)
319 msleep(p->desc->delay.disable);
326 static int panel_simple_unprepare(struct drm_panel *panel)
328 struct panel_simple *p = to_panel_simple(panel);
330 if (p->prepared_time == 0)
333 gpiod_set_value_cansleep(p->enable_gpio, 0);
335 regulator_disable(p->supply);
337 p->prepared_time = 0;
338 p->unprepared_time = ktime_get();
343 static int panel_simple_get_hpd_gpio(struct device *dev,
344 struct panel_simple *p, bool from_probe)
348 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
349 if (IS_ERR(p->hpd_gpio)) {
350 err = PTR_ERR(p->hpd_gpio);
353 * If we're called from probe we won't consider '-EPROBE_DEFER'
354 * to be an error--we'll leave the error code in "hpd_gpio".
355 * When we try to use it we'll try again. This allows for
356 * circular dependencies where the component providing the
357 * hpd gpio needs the panel to init before probing.
359 if (err != -EPROBE_DEFER || !from_probe) {
360 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
368 static int panel_simple_prepare(struct drm_panel *panel)
370 struct panel_simple *p = to_panel_simple(panel);
375 if (p->prepared_time != 0)
378 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
380 err = regulator_enable(p->supply);
382 dev_err(panel->dev, "failed to enable supply: %d\n", err);
386 gpiod_set_value_cansleep(p->enable_gpio, 1);
388 delay = p->desc->delay.prepare;
390 delay += p->desc->delay.hpd_absent_delay;
395 if (IS_ERR(p->hpd_gpio)) {
396 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
401 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
402 hpd_asserted, hpd_asserted,
404 if (hpd_asserted < 0)
409 "error waiting for hpd GPIO: %d\n", err);
414 p->prepared_time = ktime_get();
419 static int panel_simple_enable(struct drm_panel *panel)
421 struct panel_simple *p = to_panel_simple(panel);
426 if (p->desc->delay.enable)
427 msleep(p->desc->delay.enable);
429 panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable);
436 static int panel_simple_get_modes(struct drm_panel *panel,
437 struct drm_connector *connector)
439 struct panel_simple *p = to_panel_simple(panel);
442 /* probe EDID if a DDC bus is available */
444 struct edid *edid = drm_get_edid(connector, p->ddc);
446 drm_connector_update_edid_property(connector, edid);
448 num += drm_add_edid_modes(connector, edid);
453 /* add hard-coded panel modes */
454 num += panel_simple_get_non_edid_modes(p, connector);
456 /* set up connector's "panel orientation" property */
457 drm_connector_set_panel_orientation(connector, p->orientation);
462 static int panel_simple_get_timings(struct drm_panel *panel,
463 unsigned int num_timings,
464 struct display_timing *timings)
466 struct panel_simple *p = to_panel_simple(panel);
469 if (p->desc->num_timings < num_timings)
470 num_timings = p->desc->num_timings;
473 for (i = 0; i < num_timings; i++)
474 timings[i] = p->desc->timings[i];
476 return p->desc->num_timings;
479 static const struct drm_panel_funcs panel_simple_funcs = {
480 .disable = panel_simple_disable,
481 .unprepare = panel_simple_unprepare,
482 .prepare = panel_simple_prepare,
483 .enable = panel_simple_enable,
484 .get_modes = panel_simple_get_modes,
485 .get_timings = panel_simple_get_timings,
488 static struct panel_desc panel_dpi;
490 static int panel_dpi_probe(struct device *dev,
491 struct panel_simple *panel)
493 struct display_timing *timing;
494 const struct device_node *np;
495 struct panel_desc *desc;
496 unsigned int bus_flags;
501 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
505 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
509 ret = of_get_display_timing(np, "panel-timing", timing);
511 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
516 desc->timings = timing;
517 desc->num_timings = 1;
519 of_property_read_u32(np, "width-mm", &desc->size.width);
520 of_property_read_u32(np, "height-mm", &desc->size.height);
522 /* Extract bus_flags from display_timing */
524 vm.flags = timing->flags;
525 drm_bus_flags_from_videomode(&vm, &bus_flags);
526 desc->bus_flags = bus_flags;
528 /* We do not know the connector for the DT node, so guess it */
529 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
536 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
537 (to_check->field.typ >= bounds->field.min && \
538 to_check->field.typ <= bounds->field.max)
539 static void panel_simple_parse_panel_timing_node(struct device *dev,
540 struct panel_simple *panel,
541 const struct display_timing *ot)
543 const struct panel_desc *desc = panel->desc;
547 if (WARN_ON(desc->num_modes)) {
548 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
551 if (WARN_ON(!desc->num_timings)) {
552 dev_err(dev, "Reject override mode: no timings specified\n");
556 for (i = 0; i < panel->desc->num_timings; i++) {
557 const struct display_timing *dt = &panel->desc->timings[i];
559 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
560 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
561 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
562 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
563 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
564 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
565 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
566 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
569 if (ot->flags != dt->flags)
572 videomode_from_timing(ot, &vm);
573 drm_display_mode_from_videomode(&vm, &panel->override_mode);
574 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
575 DRM_MODE_TYPE_PREFERRED;
579 if (WARN_ON(!panel->override_mode.type))
580 dev_err(dev, "Reject override mode: No display_timing found\n");
583 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
585 struct panel_simple *panel;
586 struct display_timing dt;
587 struct device_node *ddc;
592 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
596 panel->enabled = false;
597 panel->prepared_time = 0;
600 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
601 if (!panel->no_hpd) {
602 err = panel_simple_get_hpd_gpio(dev, panel, true);
607 panel->supply = devm_regulator_get(dev, "power");
608 if (IS_ERR(panel->supply))
609 return PTR_ERR(panel->supply);
611 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
613 if (IS_ERR(panel->enable_gpio)) {
614 err = PTR_ERR(panel->enable_gpio);
615 if (err != -EPROBE_DEFER)
616 dev_err(dev, "failed to request GPIO: %d\n", err);
620 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
622 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
626 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
628 panel->ddc = of_find_i2c_adapter_by_node(ddc);
632 return -EPROBE_DEFER;
635 if (desc == &panel_dpi) {
636 /* Handle the generic panel-dpi binding */
637 err = panel_dpi_probe(dev, panel);
641 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
642 panel_simple_parse_panel_timing_node(dev, panel, &dt);
645 connector_type = desc->connector_type;
646 /* Catch common mistakes for panels. */
647 switch (connector_type) {
649 dev_warn(dev, "Specify missing connector_type\n");
650 connector_type = DRM_MODE_CONNECTOR_DPI;
652 case DRM_MODE_CONNECTOR_LVDS:
653 WARN_ON(desc->bus_flags &
654 ~(DRM_BUS_FLAG_DE_LOW |
655 DRM_BUS_FLAG_DE_HIGH |
656 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
657 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
658 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
659 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
660 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
661 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
663 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
664 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
667 case DRM_MODE_CONNECTOR_eDP:
668 if (desc->bus_format == 0)
669 dev_warn(dev, "Specify missing bus_format\n");
670 if (desc->bpc != 6 && desc->bpc != 8)
671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
673 case DRM_MODE_CONNECTOR_DSI:
674 if (desc->bpc != 6 && desc->bpc != 8)
675 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
677 case DRM_MODE_CONNECTOR_DPI:
678 bus_flags = DRM_BUS_FLAG_DE_LOW |
679 DRM_BUS_FLAG_DE_HIGH |
680 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
681 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
682 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
683 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
684 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
685 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
686 if (desc->bus_flags & ~bus_flags)
687 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
688 if (!(desc->bus_flags & bus_flags))
689 dev_warn(dev, "Specify missing bus_flags\n");
690 if (desc->bus_format == 0)
691 dev_warn(dev, "Specify missing bus_format\n");
692 if (desc->bpc != 6 && desc->bpc != 8)
693 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
696 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
697 connector_type = DRM_MODE_CONNECTOR_DPI;
701 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
703 err = drm_panel_of_backlight(&panel->base);
707 drm_panel_add(&panel->base);
709 dev_set_drvdata(dev, panel);
715 put_device(&panel->ddc->dev);
720 static int panel_simple_remove(struct device *dev)
722 struct panel_simple *panel = dev_get_drvdata(dev);
724 drm_panel_remove(&panel->base);
725 drm_panel_disable(&panel->base);
726 drm_panel_unprepare(&panel->base);
729 put_device(&panel->ddc->dev);
734 static void panel_simple_shutdown(struct device *dev)
736 struct panel_simple *panel = dev_get_drvdata(dev);
738 drm_panel_disable(&panel->base);
739 drm_panel_unprepare(&panel->base);
742 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
745 .hsync_start = 1280 + 40,
746 .hsync_end = 1280 + 40 + 80,
747 .htotal = 1280 + 40 + 80 + 40,
749 .vsync_start = 800 + 3,
750 .vsync_end = 800 + 3 + 10,
751 .vtotal = 800 + 3 + 10 + 10,
752 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
755 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
756 .modes = &ire_am_1280800n3tzqw_t00h_mode,
763 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
764 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
765 .connector_type = DRM_MODE_CONNECTOR_LVDS,
768 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
771 .hsync_start = 480 + 2,
772 .hsync_end = 480 + 2 + 41,
773 .htotal = 480 + 2 + 41 + 2,
775 .vsync_start = 272 + 2,
776 .vsync_end = 272 + 2 + 10,
777 .vtotal = 272 + 2 + 10 + 2,
778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
781 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
782 .modes = &ire_am_480272h3tmqw_t01h_mode,
789 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
792 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
795 .hsync_start = 800 + 0,
796 .hsync_end = 800 + 0 + 255,
797 .htotal = 800 + 0 + 255 + 0,
799 .vsync_start = 480 + 2,
800 .vsync_end = 480 + 2 + 45,
801 .vtotal = 480 + 2 + 45 + 0,
802 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
805 static const struct panel_desc ampire_am800480r3tmqwa1h = {
806 .modes = &ire_am800480r3tmqwa1h_mode,
813 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
816 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
817 .pixelclock = { 26400000, 33300000, 46800000 },
818 .hactive = { 800, 800, 800 },
819 .hfront_porch = { 16, 210, 354 },
820 .hback_porch = { 45, 36, 6 },
821 .hsync_len = { 1, 10, 40 },
822 .vactive = { 480, 480, 480 },
823 .vfront_porch = { 7, 22, 147 },
824 .vback_porch = { 22, 13, 3 },
825 .vsync_len = { 1, 10, 20 },
826 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
827 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
830 static const struct panel_desc armadeus_st0700_adapt = {
831 .timings = &santek_st0700i5y_rbslw_f_timing,
838 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
839 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
842 static const struct drm_display_mode auo_b101aw03_mode = {
845 .hsync_start = 1024 + 156,
846 .hsync_end = 1024 + 156 + 8,
847 .htotal = 1024 + 156 + 8 + 156,
849 .vsync_start = 600 + 16,
850 .vsync_end = 600 + 16 + 6,
851 .vtotal = 600 + 16 + 6 + 16,
854 static const struct panel_desc auo_b101aw03 = {
855 .modes = &auo_b101aw03_mode,
862 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
863 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
864 .connector_type = DRM_MODE_CONNECTOR_LVDS,
867 static const struct display_timing auo_b101ean01_timing = {
868 .pixelclock = { 65300000, 72500000, 75000000 },
869 .hactive = { 1280, 1280, 1280 },
870 .hfront_porch = { 18, 119, 119 },
871 .hback_porch = { 21, 21, 21 },
872 .hsync_len = { 32, 32, 32 },
873 .vactive = { 800, 800, 800 },
874 .vfront_porch = { 4, 4, 4 },
875 .vback_porch = { 8, 8, 8 },
876 .vsync_len = { 18, 20, 20 },
879 static const struct panel_desc auo_b101ean01 = {
880 .timings = &auo_b101ean01_timing,
889 static const struct drm_display_mode auo_b101xtn01_mode = {
892 .hsync_start = 1366 + 20,
893 .hsync_end = 1366 + 20 + 70,
894 .htotal = 1366 + 20 + 70,
896 .vsync_start = 768 + 14,
897 .vsync_end = 768 + 14 + 42,
898 .vtotal = 768 + 14 + 42,
899 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
902 static const struct panel_desc auo_b101xtn01 = {
903 .modes = &auo_b101xtn01_mode,
912 static const struct drm_display_mode auo_b116xak01_mode = {
915 .hsync_start = 1366 + 48,
916 .hsync_end = 1366 + 48 + 32,
917 .htotal = 1366 + 48 + 32 + 10,
919 .vsync_start = 768 + 4,
920 .vsync_end = 768 + 4 + 6,
921 .vtotal = 768 + 4 + 6 + 15,
922 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
925 static const struct panel_desc auo_b116xak01 = {
926 .modes = &auo_b116xak01_mode,
934 .hpd_absent_delay = 200,
936 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
937 .connector_type = DRM_MODE_CONNECTOR_eDP,
940 static const struct drm_display_mode auo_b116xw03_mode = {
943 .hsync_start = 1366 + 40,
944 .hsync_end = 1366 + 40 + 40,
945 .htotal = 1366 + 40 + 40 + 32,
947 .vsync_start = 768 + 10,
948 .vsync_end = 768 + 10 + 12,
949 .vtotal = 768 + 10 + 12 + 6,
950 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
953 static const struct panel_desc auo_b116xw03 = {
954 .modes = &auo_b116xw03_mode,
964 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
965 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
966 .connector_type = DRM_MODE_CONNECTOR_eDP,
969 static const struct drm_display_mode auo_b133xtn01_mode = {
972 .hsync_start = 1366 + 48,
973 .hsync_end = 1366 + 48 + 32,
974 .htotal = 1366 + 48 + 32 + 20,
976 .vsync_start = 768 + 3,
977 .vsync_end = 768 + 3 + 6,
978 .vtotal = 768 + 3 + 6 + 13,
981 static const struct panel_desc auo_b133xtn01 = {
982 .modes = &auo_b133xtn01_mode,
991 static const struct drm_display_mode auo_b133htn01_mode = {
994 .hsync_start = 1920 + 172,
995 .hsync_end = 1920 + 172 + 80,
996 .htotal = 1920 + 172 + 80 + 60,
998 .vsync_start = 1080 + 25,
999 .vsync_end = 1080 + 25 + 10,
1000 .vtotal = 1080 + 25 + 10 + 10,
1003 static const struct panel_desc auo_b133htn01 = {
1004 .modes = &auo_b133htn01_mode,
1018 static const struct display_timing auo_g070vvn01_timings = {
1019 .pixelclock = { 33300000, 34209000, 45000000 },
1020 .hactive = { 800, 800, 800 },
1021 .hfront_porch = { 20, 40, 200 },
1022 .hback_porch = { 87, 40, 1 },
1023 .hsync_len = { 1, 48, 87 },
1024 .vactive = { 480, 480, 480 },
1025 .vfront_porch = { 5, 13, 200 },
1026 .vback_porch = { 31, 31, 29 },
1027 .vsync_len = { 1, 1, 3 },
1030 static const struct panel_desc auo_g070vvn01 = {
1031 .timings = &auo_g070vvn01_timings,
1046 static const struct drm_display_mode auo_g101evn010_mode = {
1049 .hsync_start = 1280 + 82,
1050 .hsync_end = 1280 + 82 + 2,
1051 .htotal = 1280 + 82 + 2 + 84,
1053 .vsync_start = 800 + 8,
1054 .vsync_end = 800 + 8 + 2,
1055 .vtotal = 800 + 8 + 2 + 6,
1058 static const struct panel_desc auo_g101evn010 = {
1059 .modes = &auo_g101evn010_mode,
1066 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1067 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1070 static const struct drm_display_mode auo_g104sn02_mode = {
1073 .hsync_start = 800 + 40,
1074 .hsync_end = 800 + 40 + 216,
1075 .htotal = 800 + 40 + 216 + 128,
1077 .vsync_start = 600 + 10,
1078 .vsync_end = 600 + 10 + 35,
1079 .vtotal = 600 + 10 + 35 + 2,
1082 static const struct panel_desc auo_g104sn02 = {
1083 .modes = &auo_g104sn02_mode,
1092 static const struct drm_display_mode auo_g121ean01_mode = {
1095 .hsync_start = 1280 + 58,
1096 .hsync_end = 1280 + 58 + 8,
1097 .htotal = 1280 + 58 + 8 + 70,
1099 .vsync_start = 800 + 6,
1100 .vsync_end = 800 + 6 + 4,
1101 .vtotal = 800 + 6 + 4 + 10,
1104 static const struct panel_desc auo_g121ean01 = {
1105 .modes = &auo_g121ean01_mode,
1112 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1113 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1116 static const struct display_timing auo_g133han01_timings = {
1117 .pixelclock = { 134000000, 141200000, 149000000 },
1118 .hactive = { 1920, 1920, 1920 },
1119 .hfront_porch = { 39, 58, 77 },
1120 .hback_porch = { 59, 88, 117 },
1121 .hsync_len = { 28, 42, 56 },
1122 .vactive = { 1080, 1080, 1080 },
1123 .vfront_porch = { 3, 8, 11 },
1124 .vback_porch = { 5, 14, 19 },
1125 .vsync_len = { 4, 14, 19 },
1128 static const struct panel_desc auo_g133han01 = {
1129 .timings = &auo_g133han01_timings,
1142 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1143 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1146 static const struct drm_display_mode auo_g156xtn01_mode = {
1149 .hsync_start = 1366 + 33,
1150 .hsync_end = 1366 + 33 + 67,
1153 .vsync_start = 768 + 4,
1154 .vsync_end = 768 + 4 + 4,
1158 static const struct panel_desc auo_g156xtn01 = {
1159 .modes = &auo_g156xtn01_mode,
1166 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1167 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1170 static const struct display_timing auo_g185han01_timings = {
1171 .pixelclock = { 120000000, 144000000, 175000000 },
1172 .hactive = { 1920, 1920, 1920 },
1173 .hfront_porch = { 36, 120, 148 },
1174 .hback_porch = { 24, 88, 108 },
1175 .hsync_len = { 20, 48, 64 },
1176 .vactive = { 1080, 1080, 1080 },
1177 .vfront_porch = { 6, 10, 40 },
1178 .vback_porch = { 2, 5, 20 },
1179 .vsync_len = { 2, 5, 20 },
1182 static const struct panel_desc auo_g185han01 = {
1183 .timings = &auo_g185han01_timings,
1196 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1197 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1200 static const struct display_timing auo_g190ean01_timings = {
1201 .pixelclock = { 90000000, 108000000, 135000000 },
1202 .hactive = { 1280, 1280, 1280 },
1203 .hfront_porch = { 126, 184, 1266 },
1204 .hback_porch = { 84, 122, 844 },
1205 .hsync_len = { 70, 102, 704 },
1206 .vactive = { 1024, 1024, 1024 },
1207 .vfront_porch = { 4, 26, 76 },
1208 .vback_porch = { 2, 8, 25 },
1209 .vsync_len = { 2, 8, 25 },
1212 static const struct panel_desc auo_g190ean01 = {
1213 .timings = &auo_g190ean01_timings,
1226 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1227 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1230 static const struct display_timing auo_p320hvn03_timings = {
1231 .pixelclock = { 106000000, 148500000, 164000000 },
1232 .hactive = { 1920, 1920, 1920 },
1233 .hfront_porch = { 25, 50, 130 },
1234 .hback_porch = { 25, 50, 130 },
1235 .hsync_len = { 20, 40, 105 },
1236 .vactive = { 1080, 1080, 1080 },
1237 .vfront_porch = { 8, 17, 150 },
1238 .vback_porch = { 8, 17, 150 },
1239 .vsync_len = { 4, 11, 100 },
1242 static const struct panel_desc auo_p320hvn03 = {
1243 .timings = &auo_p320hvn03_timings,
1255 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1256 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1259 static const struct drm_display_mode auo_t215hvn01_mode = {
1262 .hsync_start = 1920 + 88,
1263 .hsync_end = 1920 + 88 + 44,
1264 .htotal = 1920 + 88 + 44 + 148,
1266 .vsync_start = 1080 + 4,
1267 .vsync_end = 1080 + 4 + 5,
1268 .vtotal = 1080 + 4 + 5 + 36,
1271 static const struct panel_desc auo_t215hvn01 = {
1272 .modes = &auo_t215hvn01_mode,
1285 static const struct drm_display_mode avic_tm070ddh03_mode = {
1288 .hsync_start = 1024 + 160,
1289 .hsync_end = 1024 + 160 + 4,
1290 .htotal = 1024 + 160 + 4 + 156,
1292 .vsync_start = 600 + 17,
1293 .vsync_end = 600 + 17 + 1,
1294 .vtotal = 600 + 17 + 1 + 17,
1297 static const struct panel_desc avic_tm070ddh03 = {
1298 .modes = &avic_tm070ddh03_mode,
1312 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1315 .hsync_start = 800 + 40,
1316 .hsync_end = 800 + 40 + 48,
1317 .htotal = 800 + 40 + 48 + 40,
1319 .vsync_start = 480 + 13,
1320 .vsync_end = 480 + 13 + 3,
1321 .vtotal = 480 + 13 + 3 + 29,
1324 static const struct panel_desc bananapi_s070wv20_ct16 = {
1325 .modes = &bananapi_s070wv20_ct16_mode,
1334 static const struct drm_display_mode boe_hv070wsa_mode = {
1337 .hsync_start = 1024 + 30,
1338 .hsync_end = 1024 + 30 + 30,
1339 .htotal = 1024 + 30 + 30 + 30,
1341 .vsync_start = 600 + 10,
1342 .vsync_end = 600 + 10 + 10,
1343 .vtotal = 600 + 10 + 10 + 10,
1346 static const struct panel_desc boe_hv070wsa = {
1347 .modes = &boe_hv070wsa_mode,
1354 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1355 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1356 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1359 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1363 .hsync_start = 1280 + 48,
1364 .hsync_end = 1280 + 48 + 32,
1365 .htotal = 1280 + 48 + 32 + 80,
1367 .vsync_start = 800 + 3,
1368 .vsync_end = 800 + 3 + 5,
1369 .vtotal = 800 + 3 + 5 + 24,
1374 .hsync_start = 1280 + 48,
1375 .hsync_end = 1280 + 48 + 32,
1376 .htotal = 1280 + 48 + 32 + 80,
1378 .vsync_start = 800 + 3,
1379 .vsync_end = 800 + 3 + 5,
1380 .vtotal = 800 + 3 + 5 + 24,
1384 static const struct panel_desc boe_nv101wxmn51 = {
1385 .modes = boe_nv101wxmn51_modes,
1386 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1399 static const struct drm_display_mode boe_nv110wtm_n61_modes[] = {
1403 .hsync_start = 2160 + 48,
1404 .hsync_end = 2160 + 48 + 32,
1405 .htotal = 2160 + 48 + 32 + 100,
1407 .vsync_start = 1440 + 3,
1408 .vsync_end = 1440 + 3 + 6,
1409 .vtotal = 1440 + 3 + 6 + 31,
1414 .hsync_start = 2160 + 48,
1415 .hsync_end = 2160 + 48 + 32,
1416 .htotal = 2160 + 48 + 32 + 100,
1418 .vsync_start = 1440 + 3,
1419 .vsync_end = 1440 + 3 + 6,
1420 .vtotal = 1440 + 3 + 6 + 31,
1424 static const struct panel_desc boe_nv110wtm_n61 = {
1425 .modes = boe_nv110wtm_n61_modes,
1426 .num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes),
1433 .hpd_absent_delay = 200,
1434 .prepare_to_enable = 80,
1437 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1438 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1439 .connector_type = DRM_MODE_CONNECTOR_eDP,
1442 /* Also used for boe_nv133fhm_n62 */
1443 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1446 .hsync_start = 1920 + 48,
1447 .hsync_end = 1920 + 48 + 32,
1448 .htotal = 1920 + 48 + 32 + 200,
1450 .vsync_start = 1080 + 3,
1451 .vsync_end = 1080 + 3 + 6,
1452 .vtotal = 1080 + 3 + 6 + 31,
1453 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1456 /* Also used for boe_nv133fhm_n62 */
1457 static const struct panel_desc boe_nv133fhm_n61 = {
1458 .modes = &boe_nv133fhm_n61_modes,
1467 * When power is first given to the panel there's a short
1468 * spike on the HPD line. It was explained that this spike
1469 * was until the TCON data download was complete. On
1470 * one system this was measured at 8 ms. We'll put 15 ms
1471 * in the prepare delay just to be safe and take it away
1472 * from the hpd_absent_delay (which would otherwise be 200 ms)
1473 * to handle this. That means:
1474 * - If HPD isn't hooked up you still have 200 ms delay.
1475 * - If HPD is hooked up we won't try to look at it for the
1479 .hpd_absent_delay = 185,
1483 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1484 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1485 .connector_type = DRM_MODE_CONNECTOR_eDP,
1488 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1492 .hsync_start = 1920 + 48,
1493 .hsync_end = 1920 + 48 + 32,
1496 .vsync_start = 1080 + 3,
1497 .vsync_end = 1080 + 3 + 5,
1502 static const struct panel_desc boe_nv140fhmn49 = {
1503 .modes = boe_nv140fhmn49_modes,
1504 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1515 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1516 .connector_type = DRM_MODE_CONNECTOR_eDP,
1519 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1522 .hsync_start = 480 + 5,
1523 .hsync_end = 480 + 5 + 5,
1524 .htotal = 480 + 5 + 5 + 40,
1526 .vsync_start = 272 + 8,
1527 .vsync_end = 272 + 8 + 8,
1528 .vtotal = 272 + 8 + 8 + 8,
1529 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1532 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1533 .modes = &cdtech_s043wq26h_ct7_mode,
1540 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1543 /* S070PWS19HP-FC21 2017/04/22 */
1544 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1547 .hsync_start = 1024 + 160,
1548 .hsync_end = 1024 + 160 + 20,
1549 .htotal = 1024 + 160 + 20 + 140,
1551 .vsync_start = 600 + 12,
1552 .vsync_end = 600 + 12 + 3,
1553 .vtotal = 600 + 12 + 3 + 20,
1554 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1557 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1558 .modes = &cdtech_s070pws19hp_fc21_mode,
1565 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1566 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1567 .connector_type = DRM_MODE_CONNECTOR_DPI,
1570 /* S070SWV29HG-DC44 2017/09/21 */
1571 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1574 .hsync_start = 800 + 210,
1575 .hsync_end = 800 + 210 + 2,
1576 .htotal = 800 + 210 + 2 + 44,
1578 .vsync_start = 480 + 22,
1579 .vsync_end = 480 + 22 + 2,
1580 .vtotal = 480 + 22 + 2 + 21,
1581 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1584 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1585 .modes = &cdtech_s070swv29hg_dc44_mode,
1592 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1594 .connector_type = DRM_MODE_CONNECTOR_DPI,
1597 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1600 .hsync_start = 800 + 40,
1601 .hsync_end = 800 + 40 + 40,
1602 .htotal = 800 + 40 + 40 + 48,
1604 .vsync_start = 480 + 29,
1605 .vsync_end = 480 + 29 + 13,
1606 .vtotal = 480 + 29 + 13 + 3,
1607 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1610 static const struct panel_desc cdtech_s070wv95_ct16 = {
1611 .modes = &cdtech_s070wv95_ct16_mode,
1620 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1621 .pixelclock = { 68900000, 71100000, 73400000 },
1622 .hactive = { 1280, 1280, 1280 },
1623 .hfront_porch = { 65, 80, 95 },
1624 .hback_porch = { 64, 79, 94 },
1625 .hsync_len = { 1, 1, 1 },
1626 .vactive = { 800, 800, 800 },
1627 .vfront_porch = { 7, 11, 14 },
1628 .vback_porch = { 7, 11, 14 },
1629 .vsync_len = { 1, 1, 1 },
1630 .flags = DISPLAY_FLAGS_DE_HIGH,
1633 static const struct panel_desc chefree_ch101olhlwh_002 = {
1634 .timings = &chefree_ch101olhlwh_002_timing,
1645 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1646 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1647 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1650 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1653 .hsync_start = 800 + 49,
1654 .hsync_end = 800 + 49 + 33,
1655 .htotal = 800 + 49 + 33 + 17,
1657 .vsync_start = 1280 + 1,
1658 .vsync_end = 1280 + 1 + 7,
1659 .vtotal = 1280 + 1 + 7 + 15,
1660 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1663 static const struct panel_desc chunghwa_claa070wp03xg = {
1664 .modes = &chunghwa_claa070wp03xg_mode,
1671 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1672 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1673 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1676 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1679 .hsync_start = 1366 + 58,
1680 .hsync_end = 1366 + 58 + 58,
1681 .htotal = 1366 + 58 + 58 + 58,
1683 .vsync_start = 768 + 4,
1684 .vsync_end = 768 + 4 + 4,
1685 .vtotal = 768 + 4 + 4 + 4,
1688 static const struct panel_desc chunghwa_claa101wa01a = {
1689 .modes = &chunghwa_claa101wa01a_mode,
1696 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1697 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1698 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1701 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1704 .hsync_start = 1366 + 48,
1705 .hsync_end = 1366 + 48 + 32,
1706 .htotal = 1366 + 48 + 32 + 20,
1708 .vsync_start = 768 + 16,
1709 .vsync_end = 768 + 16 + 8,
1710 .vtotal = 768 + 16 + 8 + 16,
1713 static const struct panel_desc chunghwa_claa101wb01 = {
1714 .modes = &chunghwa_claa101wb01_mode,
1721 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1722 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1723 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1726 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1729 .hsync_start = 800 + 40,
1730 .hsync_end = 800 + 40 + 128,
1731 .htotal = 800 + 40 + 128 + 88,
1733 .vsync_start = 480 + 10,
1734 .vsync_end = 480 + 10 + 2,
1735 .vtotal = 480 + 10 + 2 + 33,
1736 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1739 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1740 .modes = &dataimage_scf0700c48ggu18_mode,
1747 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1748 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1751 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1752 .pixelclock = { 45000000, 51200000, 57000000 },
1753 .hactive = { 1024, 1024, 1024 },
1754 .hfront_porch = { 100, 106, 113 },
1755 .hback_porch = { 100, 106, 113 },
1756 .hsync_len = { 100, 108, 114 },
1757 .vactive = { 600, 600, 600 },
1758 .vfront_porch = { 8, 11, 15 },
1759 .vback_porch = { 8, 11, 15 },
1760 .vsync_len = { 9, 13, 15 },
1761 .flags = DISPLAY_FLAGS_DE_HIGH,
1764 static const struct panel_desc dlc_dlc0700yzg_1 = {
1765 .timings = &dlc_dlc0700yzg_1_timing,
1777 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1778 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1781 static const struct display_timing dlc_dlc1010gig_timing = {
1782 .pixelclock = { 68900000, 71100000, 73400000 },
1783 .hactive = { 1280, 1280, 1280 },
1784 .hfront_porch = { 43, 53, 63 },
1785 .hback_porch = { 43, 53, 63 },
1786 .hsync_len = { 44, 54, 64 },
1787 .vactive = { 800, 800, 800 },
1788 .vfront_porch = { 5, 8, 11 },
1789 .vback_porch = { 5, 8, 11 },
1790 .vsync_len = { 5, 7, 11 },
1791 .flags = DISPLAY_FLAGS_DE_HIGH,
1794 static const struct panel_desc dlc_dlc1010gig = {
1795 .timings = &dlc_dlc1010gig_timing,
1808 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1809 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1812 static const struct drm_display_mode edt_et035012dm6_mode = {
1815 .hsync_start = 320 + 20,
1816 .hsync_end = 320 + 20 + 30,
1817 .htotal = 320 + 20 + 68,
1819 .vsync_start = 240 + 4,
1820 .vsync_end = 240 + 4 + 4,
1821 .vtotal = 240 + 4 + 4 + 14,
1822 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1825 static const struct panel_desc edt_et035012dm6 = {
1826 .modes = &edt_et035012dm6_mode,
1833 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1834 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1837 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1840 .hsync_start = 480 + 8,
1841 .hsync_end = 480 + 8 + 4,
1842 .htotal = 480 + 8 + 4 + 41,
1845 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1850 .vsync_start = 288 + 2,
1851 .vsync_end = 288 + 2 + 4,
1852 .vtotal = 288 + 2 + 4 + 10,
1855 static const struct panel_desc edt_etm043080dh6gp = {
1856 .modes = &edt_etm043080dh6gp_mode,
1863 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1864 .connector_type = DRM_MODE_CONNECTOR_DPI,
1867 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1870 .hsync_start = 480 + 2,
1871 .hsync_end = 480 + 2 + 41,
1872 .htotal = 480 + 2 + 41 + 2,
1874 .vsync_start = 272 + 2,
1875 .vsync_end = 272 + 2 + 10,
1876 .vtotal = 272 + 2 + 10 + 2,
1877 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1880 static const struct panel_desc edt_etm0430g0dh6 = {
1881 .modes = &edt_etm0430g0dh6_mode,
1890 static const struct drm_display_mode edt_et057090dhu_mode = {
1893 .hsync_start = 640 + 16,
1894 .hsync_end = 640 + 16 + 30,
1895 .htotal = 640 + 16 + 30 + 114,
1897 .vsync_start = 480 + 10,
1898 .vsync_end = 480 + 10 + 3,
1899 .vtotal = 480 + 10 + 3 + 32,
1900 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1903 static const struct panel_desc edt_et057090dhu = {
1904 .modes = &edt_et057090dhu_mode,
1911 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1912 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1913 .connector_type = DRM_MODE_CONNECTOR_DPI,
1916 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1919 .hsync_start = 800 + 40,
1920 .hsync_end = 800 + 40 + 128,
1921 .htotal = 800 + 40 + 128 + 88,
1923 .vsync_start = 480 + 10,
1924 .vsync_end = 480 + 10 + 2,
1925 .vtotal = 480 + 10 + 2 + 33,
1926 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1929 static const struct panel_desc edt_etm0700g0dh6 = {
1930 .modes = &edt_etm0700g0dh6_mode,
1937 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1938 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1939 .connector_type = DRM_MODE_CONNECTOR_DPI,
1942 static const struct panel_desc edt_etm0700g0bdh6 = {
1943 .modes = &edt_etm0700g0dh6_mode,
1950 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1951 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1954 static const struct display_timing evervision_vgg804821_timing = {
1955 .pixelclock = { 27600000, 33300000, 50000000 },
1956 .hactive = { 800, 800, 800 },
1957 .hfront_porch = { 40, 66, 70 },
1958 .hback_porch = { 40, 67, 70 },
1959 .hsync_len = { 40, 67, 70 },
1960 .vactive = { 480, 480, 480 },
1961 .vfront_porch = { 6, 10, 10 },
1962 .vback_porch = { 7, 11, 11 },
1963 .vsync_len = { 7, 11, 11 },
1964 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1965 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1966 DISPLAY_FLAGS_SYNC_NEGEDGE,
1969 static const struct panel_desc evervision_vgg804821 = {
1970 .timings = &evervision_vgg804821_timing,
1977 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1978 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1981 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1984 .hsync_start = 800 + 168,
1985 .hsync_end = 800 + 168 + 64,
1986 .htotal = 800 + 168 + 64 + 88,
1988 .vsync_start = 480 + 37,
1989 .vsync_end = 480 + 37 + 2,
1990 .vtotal = 480 + 37 + 2 + 8,
1993 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1994 .modes = &foxlink_fl500wvr00_a0t_mode,
2001 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2004 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2008 .hsync_start = 320 + 44,
2009 .hsync_end = 320 + 44 + 16,
2010 .htotal = 320 + 44 + 16 + 20,
2012 .vsync_start = 240 + 2,
2013 .vsync_end = 240 + 2 + 6,
2014 .vtotal = 240 + 2 + 6 + 2,
2015 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2020 .hsync_start = 320 + 56,
2021 .hsync_end = 320 + 56 + 16,
2022 .htotal = 320 + 56 + 16 + 40,
2024 .vsync_start = 240 + 2,
2025 .vsync_end = 240 + 2 + 6,
2026 .vtotal = 240 + 2 + 6 + 2,
2027 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2031 static const struct panel_desc frida_frd350h54004 = {
2032 .modes = frida_frd350h54004_modes,
2033 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2039 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2040 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2041 .connector_type = DRM_MODE_CONNECTOR_DPI,
2044 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2047 .hsync_start = 800 + 20,
2048 .hsync_end = 800 + 20 + 24,
2049 .htotal = 800 + 20 + 24 + 20,
2051 .vsync_start = 1280 + 4,
2052 .vsync_end = 1280 + 4 + 8,
2053 .vtotal = 1280 + 4 + 8 + 4,
2054 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2057 static const struct panel_desc friendlyarm_hd702e = {
2058 .modes = &friendlyarm_hd702e_mode,
2066 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2069 .hsync_start = 480 + 5,
2070 .hsync_end = 480 + 5 + 1,
2071 .htotal = 480 + 5 + 1 + 40,
2073 .vsync_start = 272 + 8,
2074 .vsync_end = 272 + 8 + 1,
2075 .vtotal = 272 + 8 + 1 + 8,
2078 static const struct panel_desc giantplus_gpg482739qs5 = {
2079 .modes = &giantplus_gpg482739qs5_mode,
2086 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2089 static const struct display_timing giantplus_gpm940b0_timing = {
2090 .pixelclock = { 13500000, 27000000, 27500000 },
2091 .hactive = { 320, 320, 320 },
2092 .hfront_porch = { 14, 686, 718 },
2093 .hback_porch = { 50, 70, 255 },
2094 .hsync_len = { 1, 1, 1 },
2095 .vactive = { 240, 240, 240 },
2096 .vfront_porch = { 1, 1, 179 },
2097 .vback_porch = { 1, 21, 31 },
2098 .vsync_len = { 1, 1, 6 },
2099 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2102 static const struct panel_desc giantplus_gpm940b0 = {
2103 .timings = &giantplus_gpm940b0_timing,
2110 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2111 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2114 static const struct display_timing hannstar_hsd070pww1_timing = {
2115 .pixelclock = { 64300000, 71100000, 82000000 },
2116 .hactive = { 1280, 1280, 1280 },
2117 .hfront_porch = { 1, 1, 10 },
2118 .hback_porch = { 1, 1, 10 },
2120 * According to the data sheet, the minimum horizontal blanking interval
2121 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2122 * minimum working horizontal blanking interval to be 60 clocks.
2124 .hsync_len = { 58, 158, 661 },
2125 .vactive = { 800, 800, 800 },
2126 .vfront_porch = { 1, 1, 10 },
2127 .vback_porch = { 1, 1, 10 },
2128 .vsync_len = { 1, 21, 203 },
2129 .flags = DISPLAY_FLAGS_DE_HIGH,
2132 static const struct panel_desc hannstar_hsd070pww1 = {
2133 .timings = &hannstar_hsd070pww1_timing,
2140 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2141 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2144 static const struct display_timing hannstar_hsd100pxn1_timing = {
2145 .pixelclock = { 55000000, 65000000, 75000000 },
2146 .hactive = { 1024, 1024, 1024 },
2147 .hfront_porch = { 40, 40, 40 },
2148 .hback_porch = { 220, 220, 220 },
2149 .hsync_len = { 20, 60, 100 },
2150 .vactive = { 768, 768, 768 },
2151 .vfront_porch = { 7, 7, 7 },
2152 .vback_porch = { 21, 21, 21 },
2153 .vsync_len = { 10, 10, 10 },
2154 .flags = DISPLAY_FLAGS_DE_HIGH,
2157 static const struct panel_desc hannstar_hsd100pxn1 = {
2158 .timings = &hannstar_hsd100pxn1_timing,
2165 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2166 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2169 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2172 .hsync_start = 800 + 85,
2173 .hsync_end = 800 + 85 + 86,
2174 .htotal = 800 + 85 + 86 + 85,
2176 .vsync_start = 480 + 16,
2177 .vsync_end = 480 + 16 + 13,
2178 .vtotal = 480 + 16 + 13 + 16,
2181 static const struct panel_desc hitachi_tx23d38vm0caa = {
2182 .modes = &hitachi_tx23d38vm0caa_mode,
2195 static const struct drm_display_mode innolux_at043tn24_mode = {
2198 .hsync_start = 480 + 2,
2199 .hsync_end = 480 + 2 + 41,
2200 .htotal = 480 + 2 + 41 + 2,
2202 .vsync_start = 272 + 2,
2203 .vsync_end = 272 + 2 + 10,
2204 .vtotal = 272 + 2 + 10 + 2,
2205 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2208 static const struct panel_desc innolux_at043tn24 = {
2209 .modes = &innolux_at043tn24_mode,
2216 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2217 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2220 static const struct drm_display_mode innolux_at070tn92_mode = {
2223 .hsync_start = 800 + 210,
2224 .hsync_end = 800 + 210 + 20,
2225 .htotal = 800 + 210 + 20 + 46,
2227 .vsync_start = 480 + 22,
2228 .vsync_end = 480 + 22 + 10,
2229 .vtotal = 480 + 22 + 23 + 10,
2232 static const struct panel_desc innolux_at070tn92 = {
2233 .modes = &innolux_at070tn92_mode,
2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2242 static const struct display_timing innolux_g070y2_l01_timing = {
2243 .pixelclock = { 28000000, 29500000, 32000000 },
2244 .hactive = { 800, 800, 800 },
2245 .hfront_porch = { 61, 91, 141 },
2246 .hback_porch = { 60, 90, 140 },
2247 .hsync_len = { 12, 12, 12 },
2248 .vactive = { 480, 480, 480 },
2249 .vfront_porch = { 4, 9, 30 },
2250 .vback_porch = { 4, 8, 28 },
2251 .vsync_len = { 2, 2, 2 },
2252 .flags = DISPLAY_FLAGS_DE_HIGH,
2255 static const struct panel_desc innolux_g070y2_l01 = {
2256 .timings = &innolux_g070y2_l01_timing,
2269 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2270 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2273 static const struct display_timing innolux_g101ice_l01_timing = {
2274 .pixelclock = { 60400000, 71100000, 74700000 },
2275 .hactive = { 1280, 1280, 1280 },
2276 .hfront_porch = { 41, 80, 100 },
2277 .hback_porch = { 40, 79, 99 },
2278 .hsync_len = { 1, 1, 1 },
2279 .vactive = { 800, 800, 800 },
2280 .vfront_porch = { 5, 11, 14 },
2281 .vback_porch = { 4, 11, 14 },
2282 .vsync_len = { 1, 1, 1 },
2283 .flags = DISPLAY_FLAGS_DE_HIGH,
2286 static const struct panel_desc innolux_g101ice_l01 = {
2287 .timings = &innolux_g101ice_l01_timing,
2298 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2299 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2302 static const struct display_timing innolux_g121i1_l01_timing = {
2303 .pixelclock = { 67450000, 71000000, 74550000 },
2304 .hactive = { 1280, 1280, 1280 },
2305 .hfront_porch = { 40, 80, 160 },
2306 .hback_porch = { 39, 79, 159 },
2307 .hsync_len = { 1, 1, 1 },
2308 .vactive = { 800, 800, 800 },
2309 .vfront_porch = { 5, 11, 100 },
2310 .vback_porch = { 4, 11, 99 },
2311 .vsync_len = { 1, 1, 1 },
2314 static const struct panel_desc innolux_g121i1_l01 = {
2315 .timings = &innolux_g121i1_l01_timing,
2326 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2327 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2330 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2333 .hsync_start = 1024 + 0,
2334 .hsync_end = 1024 + 1,
2335 .htotal = 1024 + 0 + 1 + 320,
2337 .vsync_start = 768 + 38,
2338 .vsync_end = 768 + 38 + 1,
2339 .vtotal = 768 + 38 + 1 + 0,
2340 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2343 static const struct panel_desc innolux_g121x1_l03 = {
2344 .modes = &innolux_g121x1_l03_mode,
2359 * Datasheet specifies that at 60 Hz refresh rate:
2360 * - total horizontal time: { 1506, 1592, 1716 }
2361 * - total vertical time: { 788, 800, 868 }
2363 * ...but doesn't go into exactly how that should be split into a front
2364 * porch, back porch, or sync length. For now we'll leave a single setting
2365 * here which allows a bit of tweaking of the pixel clock at the expense of
2368 static const struct display_timing innolux_n116bge_timing = {
2369 .pixelclock = { 72600000, 76420000, 80240000 },
2370 .hactive = { 1366, 1366, 1366 },
2371 .hfront_porch = { 136, 136, 136 },
2372 .hback_porch = { 60, 60, 60 },
2373 .hsync_len = { 30, 30, 30 },
2374 .vactive = { 768, 768, 768 },
2375 .vfront_porch = { 8, 8, 8 },
2376 .vback_porch = { 12, 12, 12 },
2377 .vsync_len = { 12, 12, 12 },
2378 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2381 static const struct panel_desc innolux_n116bge = {
2382 .timings = &innolux_n116bge_timing,
2391 static const struct drm_display_mode innolux_n125hce_gn1_mode = {
2394 .hsync_start = 1920 + 40,
2395 .hsync_end = 1920 + 40 + 40,
2396 .htotal = 1920 + 40 + 40 + 80,
2398 .vsync_start = 1080 + 4,
2399 .vsync_end = 1080 + 4 + 4,
2400 .vtotal = 1080 + 4 + 4 + 24,
2403 static const struct panel_desc innolux_n125hce_gn1 = {
2404 .modes = &innolux_n125hce_gn1_mode,
2411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2412 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2413 .connector_type = DRM_MODE_CONNECTOR_eDP,
2416 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2419 .hsync_start = 1366 + 16,
2420 .hsync_end = 1366 + 16 + 34,
2421 .htotal = 1366 + 16 + 34 + 50,
2423 .vsync_start = 768 + 2,
2424 .vsync_end = 768 + 2 + 6,
2425 .vtotal = 768 + 2 + 6 + 12,
2428 static const struct panel_desc innolux_n156bge_l21 = {
2429 .modes = &innolux_n156bge_l21_mode,
2436 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2437 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2438 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2441 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2444 .hsync_start = 2160 + 48,
2445 .hsync_end = 2160 + 48 + 32,
2446 .htotal = 2160 + 48 + 32 + 80,
2448 .vsync_start = 1440 + 3,
2449 .vsync_end = 1440 + 3 + 10,
2450 .vtotal = 1440 + 3 + 10 + 27,
2451 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2454 static const struct panel_desc innolux_p120zdg_bf1 = {
2455 .modes = &innolux_p120zdg_bf1_mode,
2463 .hpd_absent_delay = 200,
2468 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2471 .hsync_start = 1024 + 128,
2472 .hsync_end = 1024 + 128 + 64,
2473 .htotal = 1024 + 128 + 64 + 128,
2475 .vsync_start = 600 + 16,
2476 .vsync_end = 600 + 16 + 4,
2477 .vtotal = 600 + 16 + 4 + 16,
2480 static const struct panel_desc innolux_zj070na_01p = {
2481 .modes = &innolux_zj070na_01p_mode,
2490 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2493 .hsync_start = 1920 + 24,
2494 .hsync_end = 1920 + 24 + 48,
2495 .htotal = 1920 + 24 + 48 + 88,
2497 .vsync_start = 1080 + 3,
2498 .vsync_end = 1080 + 3 + 12,
2499 .vtotal = 1080 + 3 + 12 + 17,
2500 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2503 static const struct panel_desc ivo_m133nwf4_r0 = {
2504 .modes = &ivo_m133nwf4_r0_mode,
2512 .hpd_absent_delay = 200,
2515 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2516 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2517 .connector_type = DRM_MODE_CONNECTOR_eDP,
2520 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2523 .hsync_start = 1366 + 40,
2524 .hsync_end = 1366 + 40 + 32,
2525 .htotal = 1366 + 40 + 32 + 62,
2527 .vsync_start = 768 + 5,
2528 .vsync_end = 768 + 5 + 5,
2529 .vtotal = 768 + 5 + 5 + 122,
2530 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2533 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2534 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2542 .hpd_absent_delay = 200,
2544 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2545 .connector_type = DRM_MODE_CONNECTOR_eDP,
2548 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2549 .pixelclock = { 5580000, 5850000, 6200000 },
2550 .hactive = { 320, 320, 320 },
2551 .hfront_porch = { 30, 30, 30 },
2552 .hback_porch = { 30, 30, 30 },
2553 .hsync_len = { 1, 5, 17 },
2554 .vactive = { 240, 240, 240 },
2555 .vfront_porch = { 6, 6, 6 },
2556 .vback_porch = { 5, 5, 5 },
2557 .vsync_len = { 1, 2, 11 },
2558 .flags = DISPLAY_FLAGS_DE_HIGH,
2561 static const struct panel_desc koe_tx14d24vm1bpa = {
2562 .timings = &koe_tx14d24vm1bpa_timing,
2571 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2572 .pixelclock = { 151820000, 156720000, 159780000 },
2573 .hactive = { 1920, 1920, 1920 },
2574 .hfront_porch = { 105, 130, 142 },
2575 .hback_porch = { 45, 70, 82 },
2576 .hsync_len = { 30, 30, 30 },
2577 .vactive = { 1200, 1200, 1200},
2578 .vfront_porch = { 3, 5, 10 },
2579 .vback_porch = { 2, 5, 10 },
2580 .vsync_len = { 5, 5, 5 },
2583 static const struct panel_desc koe_tx26d202vm0bwa = {
2584 .timings = &koe_tx26d202vm0bwa_timing,
2597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2598 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2599 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2602 static const struct display_timing koe_tx31d200vm0baa_timing = {
2603 .pixelclock = { 39600000, 43200000, 48000000 },
2604 .hactive = { 1280, 1280, 1280 },
2605 .hfront_porch = { 16, 36, 56 },
2606 .hback_porch = { 16, 36, 56 },
2607 .hsync_len = { 8, 8, 8 },
2608 .vactive = { 480, 480, 480 },
2609 .vfront_porch = { 6, 21, 33 },
2610 .vback_porch = { 6, 21, 33 },
2611 .vsync_len = { 8, 8, 8 },
2612 .flags = DISPLAY_FLAGS_DE_HIGH,
2615 static const struct panel_desc koe_tx31d200vm0baa = {
2616 .timings = &koe_tx31d200vm0baa_timing,
2623 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2624 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2627 static const struct display_timing kyo_tcg121xglp_timing = {
2628 .pixelclock = { 52000000, 65000000, 71000000 },
2629 .hactive = { 1024, 1024, 1024 },
2630 .hfront_porch = { 2, 2, 2 },
2631 .hback_porch = { 2, 2, 2 },
2632 .hsync_len = { 86, 124, 244 },
2633 .vactive = { 768, 768, 768 },
2634 .vfront_porch = { 2, 2, 2 },
2635 .vback_porch = { 2, 2, 2 },
2636 .vsync_len = { 6, 34, 73 },
2637 .flags = DISPLAY_FLAGS_DE_HIGH,
2640 static const struct panel_desc kyo_tcg121xglp = {
2641 .timings = &kyo_tcg121xglp_timing,
2648 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2649 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2652 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2655 .hsync_start = 320 + 20,
2656 .hsync_end = 320 + 20 + 30,
2657 .htotal = 320 + 20 + 30 + 38,
2659 .vsync_start = 240 + 4,
2660 .vsync_end = 240 + 4 + 3,
2661 .vtotal = 240 + 4 + 3 + 15,
2664 static const struct panel_desc lemaker_bl035_rgb_002 = {
2665 .modes = &lemaker_bl035_rgb_002_mode,
2671 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2672 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2675 static const struct drm_display_mode lg_lb070wv8_mode = {
2678 .hsync_start = 800 + 88,
2679 .hsync_end = 800 + 88 + 80,
2680 .htotal = 800 + 88 + 80 + 88,
2682 .vsync_start = 480 + 10,
2683 .vsync_end = 480 + 10 + 25,
2684 .vtotal = 480 + 10 + 25 + 10,
2687 static const struct panel_desc lg_lb070wv8 = {
2688 .modes = &lg_lb070wv8_mode,
2695 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2696 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2699 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2702 .hsync_start = 1536 + 12,
2703 .hsync_end = 1536 + 12 + 16,
2704 .htotal = 1536 + 12 + 16 + 48,
2706 .vsync_start = 2048 + 8,
2707 .vsync_end = 2048 + 8 + 4,
2708 .vtotal = 2048 + 8 + 4 + 8,
2709 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2712 static const struct panel_desc lg_lp079qx1_sp0v = {
2713 .modes = &lg_lp079qx1_sp0v_mode,
2721 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2724 .hsync_start = 2048 + 150,
2725 .hsync_end = 2048 + 150 + 5,
2726 .htotal = 2048 + 150 + 5 + 5,
2728 .vsync_start = 1536 + 3,
2729 .vsync_end = 1536 + 3 + 1,
2730 .vtotal = 1536 + 3 + 1 + 9,
2733 static const struct panel_desc lg_lp097qx1_spa1 = {
2734 .modes = &lg_lp097qx1_spa1_mode,
2742 static const struct drm_display_mode lg_lp120up1_mode = {
2745 .hsync_start = 1920 + 40,
2746 .hsync_end = 1920 + 40 + 40,
2747 .htotal = 1920 + 40 + 40+ 80,
2749 .vsync_start = 1280 + 4,
2750 .vsync_end = 1280 + 4 + 4,
2751 .vtotal = 1280 + 4 + 4 + 12,
2754 static const struct panel_desc lg_lp120up1 = {
2755 .modes = &lg_lp120up1_mode,
2762 .connector_type = DRM_MODE_CONNECTOR_eDP,
2765 static const struct drm_display_mode lg_lp129qe_mode = {
2768 .hsync_start = 2560 + 48,
2769 .hsync_end = 2560 + 48 + 32,
2770 .htotal = 2560 + 48 + 32 + 80,
2772 .vsync_start = 1700 + 3,
2773 .vsync_end = 1700 + 3 + 10,
2774 .vtotal = 1700 + 3 + 10 + 36,
2777 static const struct panel_desc lg_lp129qe = {
2778 .modes = &lg_lp129qe_mode,
2787 static const struct display_timing logictechno_lt161010_2nh_timing = {
2788 .pixelclock = { 26400000, 33300000, 46800000 },
2789 .hactive = { 800, 800, 800 },
2790 .hfront_porch = { 16, 210, 354 },
2791 .hback_porch = { 46, 46, 46 },
2792 .hsync_len = { 1, 20, 40 },
2793 .vactive = { 480, 480, 480 },
2794 .vfront_porch = { 7, 22, 147 },
2795 .vback_porch = { 23, 23, 23 },
2796 .vsync_len = { 1, 10, 20 },
2797 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2798 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2799 DISPLAY_FLAGS_SYNC_POSEDGE,
2802 static const struct panel_desc logictechno_lt161010_2nh = {
2803 .timings = &logictechno_lt161010_2nh_timing,
2809 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2810 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2811 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2812 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2813 .connector_type = DRM_MODE_CONNECTOR_DPI,
2816 static const struct display_timing logictechno_lt170410_2whc_timing = {
2817 .pixelclock = { 68900000, 71100000, 73400000 },
2818 .hactive = { 1280, 1280, 1280 },
2819 .hfront_porch = { 23, 60, 71 },
2820 .hback_porch = { 23, 60, 71 },
2821 .hsync_len = { 15, 40, 47 },
2822 .vactive = { 800, 800, 800 },
2823 .vfront_porch = { 5, 7, 10 },
2824 .vback_porch = { 5, 7, 10 },
2825 .vsync_len = { 6, 9, 12 },
2826 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2827 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2828 DISPLAY_FLAGS_SYNC_POSEDGE,
2831 static const struct panel_desc logictechno_lt170410_2whc = {
2832 .timings = &logictechno_lt170410_2whc_timing,
2838 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2839 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2840 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2843 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2846 .hsync_start = 800 + 0,
2847 .hsync_end = 800 + 1,
2848 .htotal = 800 + 0 + 1 + 160,
2850 .vsync_start = 480 + 0,
2851 .vsync_end = 480 + 48 + 1,
2852 .vtotal = 480 + 48 + 1 + 0,
2853 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2856 static const struct drm_display_mode logicpd_type_28_mode = {
2859 .hsync_start = 480 + 3,
2860 .hsync_end = 480 + 3 + 42,
2861 .htotal = 480 + 3 + 42 + 2,
2864 .vsync_start = 272 + 2,
2865 .vsync_end = 272 + 2 + 11,
2866 .vtotal = 272 + 2 + 11 + 3,
2867 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2870 static const struct panel_desc logicpd_type_28 = {
2871 .modes = &logicpd_type_28_mode,
2884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2885 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2886 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2887 .connector_type = DRM_MODE_CONNECTOR_DPI,
2890 static const struct panel_desc mitsubishi_aa070mc01 = {
2891 .modes = &mitsubishi_aa070mc01_mode,
2904 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2905 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2906 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2909 static const struct display_timing nec_nl12880bc20_05_timing = {
2910 .pixelclock = { 67000000, 71000000, 75000000 },
2911 .hactive = { 1280, 1280, 1280 },
2912 .hfront_porch = { 2, 30, 30 },
2913 .hback_porch = { 6, 100, 100 },
2914 .hsync_len = { 2, 30, 30 },
2915 .vactive = { 800, 800, 800 },
2916 .vfront_porch = { 5, 5, 5 },
2917 .vback_porch = { 11, 11, 11 },
2918 .vsync_len = { 7, 7, 7 },
2921 static const struct panel_desc nec_nl12880bc20_05 = {
2922 .timings = &nec_nl12880bc20_05_timing,
2933 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2934 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2937 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2940 .hsync_start = 480 + 2,
2941 .hsync_end = 480 + 2 + 41,
2942 .htotal = 480 + 2 + 41 + 2,
2944 .vsync_start = 272 + 2,
2945 .vsync_end = 272 + 2 + 4,
2946 .vtotal = 272 + 2 + 4 + 2,
2947 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2950 static const struct panel_desc nec_nl4827hc19_05b = {
2951 .modes = &nec_nl4827hc19_05b_mode,
2958 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2959 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2962 static const struct drm_display_mode netron_dy_e231732_mode = {
2965 .hsync_start = 1024 + 160,
2966 .hsync_end = 1024 + 160 + 70,
2967 .htotal = 1024 + 160 + 70 + 90,
2969 .vsync_start = 600 + 127,
2970 .vsync_end = 600 + 127 + 20,
2971 .vtotal = 600 + 127 + 20 + 3,
2974 static const struct panel_desc netron_dy_e231732 = {
2975 .modes = &netron_dy_e231732_mode,
2981 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2984 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2988 .hsync_start = 1920 + 48,
2989 .hsync_end = 1920 + 48 + 32,
2990 .htotal = 1920 + 48 + 32 + 80,
2992 .vsync_start = 1080 + 3,
2993 .vsync_end = 1080 + 3 + 5,
2994 .vtotal = 1080 + 3 + 5 + 23,
2995 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2999 .hsync_start = 1920 + 48,
3000 .hsync_end = 1920 + 48 + 32,
3001 .htotal = 1920 + 48 + 32 + 80,
3003 .vsync_start = 1080 + 3,
3004 .vsync_end = 1080 + 3 + 5,
3005 .vtotal = 1080 + 3 + 5 + 23,
3006 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3010 static const struct panel_desc neweast_wjfh116008a = {
3011 .modes = neweast_wjfh116008a_modes,
3023 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3024 .connector_type = DRM_MODE_CONNECTOR_eDP,
3027 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3030 .hsync_start = 480 + 2,
3031 .hsync_end = 480 + 2 + 41,
3032 .htotal = 480 + 2 + 41 + 2,
3034 .vsync_start = 272 + 2,
3035 .vsync_end = 272 + 2 + 10,
3036 .vtotal = 272 + 2 + 10 + 2,
3037 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3040 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3041 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3048 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3049 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3050 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3051 .connector_type = DRM_MODE_CONNECTOR_DPI,
3054 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3055 .pixelclock = { 130000000, 148350000, 163000000 },
3056 .hactive = { 1920, 1920, 1920 },
3057 .hfront_porch = { 80, 100, 100 },
3058 .hback_porch = { 100, 120, 120 },
3059 .hsync_len = { 50, 60, 60 },
3060 .vactive = { 1080, 1080, 1080 },
3061 .vfront_porch = { 12, 30, 30 },
3062 .vback_porch = { 4, 10, 10 },
3063 .vsync_len = { 4, 5, 5 },
3066 static const struct panel_desc nlt_nl192108ac18_02d = {
3067 .timings = &nlt_nl192108ac18_02d_timing,
3077 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3078 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3081 static const struct drm_display_mode nvd_9128_mode = {
3084 .hsync_start = 800 + 130,
3085 .hsync_end = 800 + 130 + 98,
3086 .htotal = 800 + 0 + 130 + 98,
3088 .vsync_start = 480 + 10,
3089 .vsync_end = 480 + 10 + 50,
3090 .vtotal = 480 + 0 + 10 + 50,
3093 static const struct panel_desc nvd_9128 = {
3094 .modes = &nvd_9128_mode,
3101 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3102 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3105 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3106 .pixelclock = { 30000000, 30000000, 40000000 },
3107 .hactive = { 800, 800, 800 },
3108 .hfront_porch = { 40, 40, 40 },
3109 .hback_porch = { 40, 40, 40 },
3110 .hsync_len = { 1, 48, 48 },
3111 .vactive = { 480, 480, 480 },
3112 .vfront_porch = { 13, 13, 13 },
3113 .vback_porch = { 29, 29, 29 },
3114 .vsync_len = { 3, 3, 3 },
3115 .flags = DISPLAY_FLAGS_DE_HIGH,
3118 static const struct panel_desc okaya_rs800480t_7x0gp = {
3119 .timings = &okaya_rs800480t_7x0gp_timing,
3132 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3135 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3138 .hsync_start = 480 + 5,
3139 .hsync_end = 480 + 5 + 30,
3140 .htotal = 480 + 5 + 30 + 10,
3142 .vsync_start = 272 + 8,
3143 .vsync_end = 272 + 8 + 5,
3144 .vtotal = 272 + 8 + 5 + 3,
3147 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3148 .modes = &olimex_lcd_olinuxino_43ts_mode,
3154 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3158 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3159 * pixel clocks, but this is the timing that was being used in the Adafruit
3160 * installation instructions.
3162 static const struct drm_display_mode ontat_yx700wv03_mode = {
3172 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3177 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3179 static const struct panel_desc ontat_yx700wv03 = {
3180 .modes = &ontat_yx700wv03_mode,
3187 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3190 static const struct drm_display_mode ortustech_com37h3m_mode = {
3193 .hsync_start = 480 + 40,
3194 .hsync_end = 480 + 40 + 10,
3195 .htotal = 480 + 40 + 10 + 40,
3197 .vsync_start = 640 + 4,
3198 .vsync_end = 640 + 4 + 2,
3199 .vtotal = 640 + 4 + 2 + 4,
3200 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3203 static const struct panel_desc ortustech_com37h3m = {
3204 .modes = &ortustech_com37h3m_mode,
3208 .width = 56, /* 56.16mm */
3209 .height = 75, /* 74.88mm */
3211 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3212 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3213 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3216 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3219 .hsync_start = 480 + 10,
3220 .hsync_end = 480 + 10 + 10,
3221 .htotal = 480 + 10 + 10 + 15,
3223 .vsync_start = 800 + 3,
3224 .vsync_end = 800 + 3 + 3,
3225 .vtotal = 800 + 3 + 3 + 3,
3228 static const struct panel_desc ortustech_com43h4m85ulc = {
3229 .modes = &ortustech_com43h4m85ulc_mode,
3236 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3237 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3238 .connector_type = DRM_MODE_CONNECTOR_DPI,
3241 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3244 .hsync_start = 800 + 210,
3245 .hsync_end = 800 + 210 + 30,
3246 .htotal = 800 + 210 + 30 + 16,
3248 .vsync_start = 480 + 22,
3249 .vsync_end = 480 + 22 + 13,
3250 .vtotal = 480 + 22 + 13 + 10,
3251 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3254 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3255 .modes = &osddisplays_osd070t1718_19ts_mode,
3262 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3263 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3264 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3265 .connector_type = DRM_MODE_CONNECTOR_DPI,
3268 static const struct drm_display_mode pda_91_00156_a0_mode = {
3271 .hsync_start = 800 + 1,
3272 .hsync_end = 800 + 1 + 64,
3273 .htotal = 800 + 1 + 64 + 64,
3275 .vsync_start = 480 + 1,
3276 .vsync_end = 480 + 1 + 23,
3277 .vtotal = 480 + 1 + 23 + 22,
3280 static const struct panel_desc pda_91_00156_a0 = {
3281 .modes = &pda_91_00156_a0_mode,
3287 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3290 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3293 .hsync_start = 800 + 54,
3294 .hsync_end = 800 + 54 + 2,
3295 .htotal = 800 + 54 + 2 + 44,
3297 .vsync_start = 480 + 49,
3298 .vsync_end = 480 + 49 + 2,
3299 .vtotal = 480 + 49 + 2 + 22,
3302 static const struct panel_desc powertip_ph800480t013_idf02 = {
3303 .modes = &powertip_ph800480t013_idf02_mode,
3309 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3310 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3311 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3312 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3313 .connector_type = DRM_MODE_CONNECTOR_DPI,
3316 static const struct drm_display_mode qd43003c0_40_mode = {
3319 .hsync_start = 480 + 8,
3320 .hsync_end = 480 + 8 + 4,
3321 .htotal = 480 + 8 + 4 + 39,
3323 .vsync_start = 272 + 4,
3324 .vsync_end = 272 + 4 + 10,
3325 .vtotal = 272 + 4 + 10 + 2,
3328 static const struct panel_desc qd43003c0_40 = {
3329 .modes = &qd43003c0_40_mode,
3336 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3339 static const struct display_timing rocktech_rk070er9427_timing = {
3340 .pixelclock = { 26400000, 33300000, 46800000 },
3341 .hactive = { 800, 800, 800 },
3342 .hfront_porch = { 16, 210, 354 },
3343 .hback_porch = { 46, 46, 46 },
3344 .hsync_len = { 1, 1, 1 },
3345 .vactive = { 480, 480, 480 },
3346 .vfront_porch = { 7, 22, 147 },
3347 .vback_porch = { 23, 23, 23 },
3348 .vsync_len = { 1, 1, 1 },
3349 .flags = DISPLAY_FLAGS_DE_HIGH,
3352 static const struct panel_desc rocktech_rk070er9427 = {
3353 .timings = &rocktech_rk070er9427_timing,
3366 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3369 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3372 .hsync_start = 1280 + 48,
3373 .hsync_end = 1280 + 48 + 32,
3374 .htotal = 1280 + 48 + 32 + 80,
3376 .vsync_start = 800 + 2,
3377 .vsync_end = 800 + 2 + 5,
3378 .vtotal = 800 + 2 + 5 + 16,
3381 static const struct panel_desc rocktech_rk101ii01d_ct = {
3382 .modes = &rocktech_rk101ii01d_ct_mode,
3392 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3393 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3394 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3397 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3400 .hsync_start = 2560 + 48,
3401 .hsync_end = 2560 + 48 + 32,
3402 .htotal = 2560 + 48 + 32 + 80,
3404 .vsync_start = 1600 + 2,
3405 .vsync_end = 1600 + 2 + 5,
3406 .vtotal = 1600 + 2 + 5 + 57,
3409 static const struct panel_desc samsung_lsn122dl01_c01 = {
3410 .modes = &samsung_lsn122dl01_c01_mode,
3418 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3421 .hsync_start = 1024 + 24,
3422 .hsync_end = 1024 + 24 + 136,
3423 .htotal = 1024 + 24 + 136 + 160,
3425 .vsync_start = 600 + 3,
3426 .vsync_end = 600 + 3 + 6,
3427 .vtotal = 600 + 3 + 6 + 61,
3430 static const struct panel_desc samsung_ltn101nt05 = {
3431 .modes = &samsung_ltn101nt05_mode,
3438 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3439 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3440 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3443 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3446 .hsync_start = 1366 + 64,
3447 .hsync_end = 1366 + 64 + 48,
3448 .htotal = 1366 + 64 + 48 + 128,
3450 .vsync_start = 768 + 2,
3451 .vsync_end = 768 + 2 + 5,
3452 .vtotal = 768 + 2 + 5 + 17,
3455 static const struct panel_desc samsung_ltn140at29_301 = {
3456 .modes = &samsung_ltn140at29_301_mode,
3465 static const struct display_timing satoz_sat050at40h12r2_timing = {
3466 .pixelclock = {33300000, 33300000, 50000000},
3467 .hactive = {800, 800, 800},
3468 .hfront_porch = {16, 210, 354},
3469 .hback_porch = {46, 46, 46},
3470 .hsync_len = {1, 1, 40},
3471 .vactive = {480, 480, 480},
3472 .vfront_porch = {7, 22, 147},
3473 .vback_porch = {23, 23, 23},
3474 .vsync_len = {1, 1, 20},
3477 static const struct panel_desc satoz_sat050at40h12r2 = {
3478 .timings = &satoz_sat050at40h12r2_timing,
3485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3486 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3489 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3492 .hsync_start = 1920 + 48,
3493 .hsync_end = 1920 + 48 + 32,
3494 .htotal = 1920 + 48 + 32 + 80,
3496 .vsync_start = 1280 + 3,
3497 .vsync_end = 1280 + 3 + 10,
3498 .vtotal = 1280 + 3 + 10 + 57,
3499 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3502 static const struct panel_desc sharp_ld_d5116z01b = {
3503 .modes = &sharp_ld_d5116z01b_mode,
3510 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3511 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3514 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3517 .hsync_start = 800 + 64,
3518 .hsync_end = 800 + 64 + 128,
3519 .htotal = 800 + 64 + 128 + 64,
3521 .vsync_start = 480 + 8,
3522 .vsync_end = 480 + 8 + 2,
3523 .vtotal = 480 + 8 + 2 + 35,
3524 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3527 static const struct panel_desc sharp_lq070y3dg3b = {
3528 .modes = &sharp_lq070y3dg3b_mode,
3532 .width = 152, /* 152.4mm */
3533 .height = 91, /* 91.4mm */
3535 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3536 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3537 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3540 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3543 .hsync_start = 240 + 16,
3544 .hsync_end = 240 + 16 + 7,
3545 .htotal = 240 + 16 + 7 + 5,
3547 .vsync_start = 320 + 9,
3548 .vsync_end = 320 + 9 + 1,
3549 .vtotal = 320 + 9 + 1 + 7,
3552 static const struct panel_desc sharp_lq035q7db03 = {
3553 .modes = &sharp_lq035q7db03_mode,
3560 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3563 static const struct display_timing sharp_lq101k1ly04_timing = {
3564 .pixelclock = { 60000000, 65000000, 80000000 },
3565 .hactive = { 1280, 1280, 1280 },
3566 .hfront_porch = { 20, 20, 20 },
3567 .hback_porch = { 20, 20, 20 },
3568 .hsync_len = { 10, 10, 10 },
3569 .vactive = { 800, 800, 800 },
3570 .vfront_porch = { 4, 4, 4 },
3571 .vback_porch = { 4, 4, 4 },
3572 .vsync_len = { 4, 4, 4 },
3573 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3576 static const struct panel_desc sharp_lq101k1ly04 = {
3577 .timings = &sharp_lq101k1ly04_timing,
3584 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3585 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3588 static const struct display_timing sharp_lq123p1jx31_timing = {
3589 .pixelclock = { 252750000, 252750000, 266604720 },
3590 .hactive = { 2400, 2400, 2400 },
3591 .hfront_porch = { 48, 48, 48 },
3592 .hback_porch = { 80, 80, 84 },
3593 .hsync_len = { 32, 32, 32 },
3594 .vactive = { 1600, 1600, 1600 },
3595 .vfront_porch = { 3, 3, 3 },
3596 .vback_porch = { 33, 33, 120 },
3597 .vsync_len = { 10, 10, 10 },
3598 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3601 static const struct panel_desc sharp_lq123p1jx31 = {
3602 .timings = &sharp_lq123p1jx31_timing,
3616 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3620 .hsync_start = 240 + 58,
3621 .hsync_end = 240 + 58 + 1,
3622 .htotal = 240 + 58 + 1 + 1,
3624 .vsync_start = 160 + 24,
3625 .vsync_end = 160 + 24 + 10,
3626 .vtotal = 160 + 24 + 10 + 6,
3627 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3632 .hsync_start = 240 + 8,
3633 .hsync_end = 240 + 8 + 1,
3634 .htotal = 240 + 8 + 1 + 1,
3636 .vsync_start = 160 + 24,
3637 .vsync_end = 160 + 24 + 10,
3638 .vtotal = 160 + 24 + 10 + 6,
3639 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3643 static const struct panel_desc sharp_ls020b1dd01d = {
3644 .modes = sharp_ls020b1dd01d_modes,
3645 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3651 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3652 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3653 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3654 | DRM_BUS_FLAG_SHARP_SIGNALS,
3657 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3660 .hsync_start = 800 + 1,
3661 .hsync_end = 800 + 1 + 64,
3662 .htotal = 800 + 1 + 64 + 64,
3664 .vsync_start = 480 + 1,
3665 .vsync_end = 480 + 1 + 23,
3666 .vtotal = 480 + 1 + 23 + 22,
3669 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3670 .modes = &shelly_sca07010_bfn_lnn_mode,
3676 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3679 static const struct drm_display_mode starry_kr070pe2t_mode = {
3682 .hsync_start = 800 + 209,
3683 .hsync_end = 800 + 209 + 1,
3684 .htotal = 800 + 209 + 1 + 45,
3686 .vsync_start = 480 + 22,
3687 .vsync_end = 480 + 22 + 1,
3688 .vtotal = 480 + 22 + 1 + 22,
3691 static const struct panel_desc starry_kr070pe2t = {
3692 .modes = &starry_kr070pe2t_mode,
3699 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3700 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3701 .connector_type = DRM_MODE_CONNECTOR_DPI,
3704 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3707 .hsync_start = 1920 + 16,
3708 .hsync_end = 1920 + 16 + 16,
3709 .htotal = 1920 + 16 + 16 + 32,
3711 .vsync_start = 1200 + 15,
3712 .vsync_end = 1200 + 15 + 2,
3713 .vtotal = 1200 + 15 + 2 + 18,
3714 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3717 static const struct panel_desc starry_kr122ea0sra = {
3718 .modes = &starry_kr122ea0sra_mode,
3725 .prepare = 10 + 200,
3727 .unprepare = 10 + 500,
3731 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3734 .hsync_start = 800 + 39,
3735 .hsync_end = 800 + 39 + 47,
3736 .htotal = 800 + 39 + 47 + 39,
3738 .vsync_start = 480 + 13,
3739 .vsync_end = 480 + 13 + 2,
3740 .vtotal = 480 + 13 + 2 + 29,
3743 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3744 .modes = &tfc_s9700rtwv43tr_01b_mode,
3751 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3752 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3755 static const struct display_timing tianma_tm070jdhg30_timing = {
3756 .pixelclock = { 62600000, 68200000, 78100000 },
3757 .hactive = { 1280, 1280, 1280 },
3758 .hfront_porch = { 15, 64, 159 },
3759 .hback_porch = { 5, 5, 5 },
3760 .hsync_len = { 1, 1, 256 },
3761 .vactive = { 800, 800, 800 },
3762 .vfront_porch = { 3, 40, 99 },
3763 .vback_porch = { 2, 2, 2 },
3764 .vsync_len = { 1, 1, 128 },
3765 .flags = DISPLAY_FLAGS_DE_HIGH,
3768 static const struct panel_desc tianma_tm070jdhg30 = {
3769 .timings = &tianma_tm070jdhg30_timing,
3776 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3777 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3780 static const struct panel_desc tianma_tm070jvhg33 = {
3781 .timings = &tianma_tm070jdhg30_timing,
3788 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3789 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3792 static const struct display_timing tianma_tm070rvhg71_timing = {
3793 .pixelclock = { 27700000, 29200000, 39600000 },
3794 .hactive = { 800, 800, 800 },
3795 .hfront_porch = { 12, 40, 212 },
3796 .hback_porch = { 88, 88, 88 },
3797 .hsync_len = { 1, 1, 40 },
3798 .vactive = { 480, 480, 480 },
3799 .vfront_porch = { 1, 13, 88 },
3800 .vback_porch = { 32, 32, 32 },
3801 .vsync_len = { 1, 1, 3 },
3802 .flags = DISPLAY_FLAGS_DE_HIGH,
3805 static const struct panel_desc tianma_tm070rvhg71 = {
3806 .timings = &tianma_tm070rvhg71_timing,
3813 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3814 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3817 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3821 .hsync_start = 320 + 50,
3822 .hsync_end = 320 + 50 + 6,
3823 .htotal = 320 + 50 + 6 + 38,
3825 .vsync_start = 240 + 3,
3826 .vsync_end = 240 + 3 + 1,
3827 .vtotal = 240 + 3 + 1 + 17,
3828 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3832 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3833 .modes = ti_nspire_cx_lcd_mode,
3840 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3841 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3844 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3848 .hsync_start = 320 + 6,
3849 .hsync_end = 320 + 6 + 6,
3850 .htotal = 320 + 6 + 6 + 6,
3852 .vsync_start = 240 + 0,
3853 .vsync_end = 240 + 0 + 1,
3854 .vtotal = 240 + 0 + 1 + 0,
3855 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3859 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3860 .modes = ti_nspire_classic_lcd_mode,
3862 /* The grayscale panel has 8 bit for the color .. Y (black) */
3868 /* This is the grayscale bus format */
3869 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3870 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3873 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3876 .hsync_start = 1280 + 192,
3877 .hsync_end = 1280 + 192 + 128,
3878 .htotal = 1280 + 192 + 128 + 64,
3880 .vsync_start = 768 + 20,
3881 .vsync_end = 768 + 20 + 7,
3882 .vtotal = 768 + 20 + 7 + 3,
3885 static const struct panel_desc toshiba_lt089ac29000 = {
3886 .modes = &toshiba_lt089ac29000_mode,
3892 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3893 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3894 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3897 static const struct drm_display_mode tpk_f07a_0102_mode = {
3900 .hsync_start = 800 + 40,
3901 .hsync_end = 800 + 40 + 128,
3902 .htotal = 800 + 40 + 128 + 88,
3904 .vsync_start = 480 + 10,
3905 .vsync_end = 480 + 10 + 2,
3906 .vtotal = 480 + 10 + 2 + 33,
3909 static const struct panel_desc tpk_f07a_0102 = {
3910 .modes = &tpk_f07a_0102_mode,
3916 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3919 static const struct drm_display_mode tpk_f10a_0102_mode = {
3922 .hsync_start = 1024 + 176,
3923 .hsync_end = 1024 + 176 + 5,
3924 .htotal = 1024 + 176 + 5 + 88,
3926 .vsync_start = 600 + 20,
3927 .vsync_end = 600 + 20 + 5,
3928 .vtotal = 600 + 20 + 5 + 25,
3931 static const struct panel_desc tpk_f10a_0102 = {
3932 .modes = &tpk_f10a_0102_mode,
3940 static const struct display_timing urt_umsh_8596md_timing = {
3941 .pixelclock = { 33260000, 33260000, 33260000 },
3942 .hactive = { 800, 800, 800 },
3943 .hfront_porch = { 41, 41, 41 },
3944 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3945 .hsync_len = { 71, 128, 128 },
3946 .vactive = { 480, 480, 480 },
3947 .vfront_porch = { 10, 10, 10 },
3948 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3949 .vsync_len = { 2, 2, 2 },
3950 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3951 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3954 static const struct panel_desc urt_umsh_8596md_lvds = {
3955 .timings = &urt_umsh_8596md_timing,
3962 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3963 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3966 static const struct panel_desc urt_umsh_8596md_parallel = {
3967 .timings = &urt_umsh_8596md_timing,
3974 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3977 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3980 .hsync_start = 800 + 210,
3981 .hsync_end = 800 + 210 + 20,
3982 .htotal = 800 + 210 + 20 + 46,
3984 .vsync_start = 480 + 22,
3985 .vsync_end = 480 + 22 + 10,
3986 .vtotal = 480 + 22 + 10 + 23,
3987 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3990 static const struct panel_desc vl050_8048nt_c01 = {
3991 .modes = &vl050_8048nt_c01_mode,
3998 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3999 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4002 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4005 .hsync_start = 320 + 20,
4006 .hsync_end = 320 + 20 + 30,
4007 .htotal = 320 + 20 + 30 + 38,
4009 .vsync_start = 240 + 4,
4010 .vsync_end = 240 + 4 + 3,
4011 .vtotal = 240 + 4 + 3 + 15,
4012 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4015 static const struct panel_desc winstar_wf35ltiacd = {
4016 .modes = &winstar_wf35ltiacd_mode,
4023 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4026 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4029 .hsync_start = 1024 + 100,
4030 .hsync_end = 1024 + 100 + 100,
4031 .htotal = 1024 + 100 + 100 + 120,
4033 .vsync_start = 600 + 10,
4034 .vsync_end = 600 + 10 + 10,
4035 .vtotal = 600 + 10 + 10 + 15,
4036 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4039 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4040 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4047 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4048 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4049 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4052 static const struct drm_display_mode arm_rtsm_mode[] = {
4056 .hsync_start = 1024 + 24,
4057 .hsync_end = 1024 + 24 + 136,
4058 .htotal = 1024 + 24 + 136 + 160,
4060 .vsync_start = 768 + 3,
4061 .vsync_end = 768 + 3 + 6,
4062 .vtotal = 768 + 3 + 6 + 29,
4063 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4067 static const struct panel_desc arm_rtsm = {
4068 .modes = arm_rtsm_mode,
4075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4078 static const struct of_device_id platform_of_match[] = {
4080 .compatible = "ampire,am-1280800n3tzqw-t00h",
4081 .data = &ire_am_1280800n3tzqw_t00h,
4083 .compatible = "ampire,am-480272h3tmqw-t01h",
4084 .data = &ire_am_480272h3tmqw_t01h,
4086 .compatible = "ampire,am800480r3tmqwa1h",
4087 .data = &ire_am800480r3tmqwa1h,
4089 .compatible = "arm,rtsm-display",
4092 .compatible = "armadeus,st0700-adapt",
4093 .data = &armadeus_st0700_adapt,
4095 .compatible = "auo,b101aw03",
4096 .data = &auo_b101aw03,
4098 .compatible = "auo,b101ean01",
4099 .data = &auo_b101ean01,
4101 .compatible = "auo,b101xtn01",
4102 .data = &auo_b101xtn01,
4104 .compatible = "auo,b116xa01",
4105 .data = &auo_b116xak01,
4107 .compatible = "auo,b116xw03",
4108 .data = &auo_b116xw03,
4110 .compatible = "auo,b133htn01",
4111 .data = &auo_b133htn01,
4113 .compatible = "auo,b133xtn01",
4114 .data = &auo_b133xtn01,
4116 .compatible = "auo,g070vvn01",
4117 .data = &auo_g070vvn01,
4119 .compatible = "auo,g101evn010",
4120 .data = &auo_g101evn010,
4122 .compatible = "auo,g104sn02",
4123 .data = &auo_g104sn02,
4125 .compatible = "auo,g121ean01",
4126 .data = &auo_g121ean01,
4128 .compatible = "auo,g133han01",
4129 .data = &auo_g133han01,
4131 .compatible = "auo,g156xtn01",
4132 .data = &auo_g156xtn01,
4134 .compatible = "auo,g185han01",
4135 .data = &auo_g185han01,
4137 .compatible = "auo,g190ean01",
4138 .data = &auo_g190ean01,
4140 .compatible = "auo,p320hvn03",
4141 .data = &auo_p320hvn03,
4143 .compatible = "auo,t215hvn01",
4144 .data = &auo_t215hvn01,
4146 .compatible = "avic,tm070ddh03",
4147 .data = &avic_tm070ddh03,
4149 .compatible = "bananapi,s070wv20-ct16",
4150 .data = &bananapi_s070wv20_ct16,
4152 .compatible = "boe,hv070wsa-100",
4153 .data = &boe_hv070wsa
4155 .compatible = "boe,nv101wxmn51",
4156 .data = &boe_nv101wxmn51,
4158 .compatible = "boe,nv110wtm-n61",
4159 .data = &boe_nv110wtm_n61,
4161 .compatible = "boe,nv133fhm-n61",
4162 .data = &boe_nv133fhm_n61,
4164 .compatible = "boe,nv133fhm-n62",
4165 .data = &boe_nv133fhm_n61,
4167 .compatible = "boe,nv140fhmn49",
4168 .data = &boe_nv140fhmn49,
4170 .compatible = "cdtech,s043wq26h-ct7",
4171 .data = &cdtech_s043wq26h_ct7,
4173 .compatible = "cdtech,s070pws19hp-fc21",
4174 .data = &cdtech_s070pws19hp_fc21,
4176 .compatible = "cdtech,s070swv29hg-dc44",
4177 .data = &cdtech_s070swv29hg_dc44,
4179 .compatible = "cdtech,s070wv95-ct16",
4180 .data = &cdtech_s070wv95_ct16,
4182 .compatible = "chefree,ch101olhlwh-002",
4183 .data = &chefree_ch101olhlwh_002,
4185 .compatible = "chunghwa,claa070wp03xg",
4186 .data = &chunghwa_claa070wp03xg,
4188 .compatible = "chunghwa,claa101wa01a",
4189 .data = &chunghwa_claa101wa01a
4191 .compatible = "chunghwa,claa101wb01",
4192 .data = &chunghwa_claa101wb01
4194 .compatible = "dataimage,scf0700c48ggu18",
4195 .data = &dataimage_scf0700c48ggu18,
4197 .compatible = "dlc,dlc0700yzg-1",
4198 .data = &dlc_dlc0700yzg_1,
4200 .compatible = "dlc,dlc1010gig",
4201 .data = &dlc_dlc1010gig,
4203 .compatible = "edt,et035012dm6",
4204 .data = &edt_et035012dm6,
4206 .compatible = "edt,etm043080dh6gp",
4207 .data = &edt_etm043080dh6gp,
4209 .compatible = "edt,etm0430g0dh6",
4210 .data = &edt_etm0430g0dh6,
4212 .compatible = "edt,et057090dhu",
4213 .data = &edt_et057090dhu,
4215 .compatible = "edt,et070080dh6",
4216 .data = &edt_etm0700g0dh6,
4218 .compatible = "edt,etm0700g0dh6",
4219 .data = &edt_etm0700g0dh6,
4221 .compatible = "edt,etm0700g0bdh6",
4222 .data = &edt_etm0700g0bdh6,
4224 .compatible = "edt,etm0700g0edh6",
4225 .data = &edt_etm0700g0bdh6,
4227 .compatible = "evervision,vgg804821",
4228 .data = &evervision_vgg804821,
4230 .compatible = "foxlink,fl500wvr00-a0t",
4231 .data = &foxlink_fl500wvr00_a0t,
4233 .compatible = "frida,frd350h54004",
4234 .data = &frida_frd350h54004,
4236 .compatible = "friendlyarm,hd702e",
4237 .data = &friendlyarm_hd702e,
4239 .compatible = "giantplus,gpg482739qs5",
4240 .data = &giantplus_gpg482739qs5
4242 .compatible = "giantplus,gpm940b0",
4243 .data = &giantplus_gpm940b0,
4245 .compatible = "hannstar,hsd070pww1",
4246 .data = &hannstar_hsd070pww1,
4248 .compatible = "hannstar,hsd100pxn1",
4249 .data = &hannstar_hsd100pxn1,
4251 .compatible = "hit,tx23d38vm0caa",
4252 .data = &hitachi_tx23d38vm0caa
4254 .compatible = "innolux,at043tn24",
4255 .data = &innolux_at043tn24,
4257 .compatible = "innolux,at070tn92",
4258 .data = &innolux_at070tn92,
4260 .compatible = "innolux,g070y2-l01",
4261 .data = &innolux_g070y2_l01,
4263 .compatible = "innolux,g101ice-l01",
4264 .data = &innolux_g101ice_l01
4266 .compatible = "innolux,g121i1-l01",
4267 .data = &innolux_g121i1_l01
4269 .compatible = "innolux,g121x1-l03",
4270 .data = &innolux_g121x1_l03,
4272 .compatible = "innolux,n116bge",
4273 .data = &innolux_n116bge,
4275 .compatible = "innolux,n125hce-gn1",
4276 .data = &innolux_n125hce_gn1,
4278 .compatible = "innolux,n156bge-l21",
4279 .data = &innolux_n156bge_l21,
4281 .compatible = "innolux,p120zdg-bf1",
4282 .data = &innolux_p120zdg_bf1,
4284 .compatible = "innolux,zj070na-01p",
4285 .data = &innolux_zj070na_01p,
4287 .compatible = "ivo,m133nwf4-r0",
4288 .data = &ivo_m133nwf4_r0,
4290 .compatible = "kingdisplay,kd116n21-30nv-a010",
4291 .data = &kingdisplay_kd116n21_30nv_a010,
4293 .compatible = "koe,tx14d24vm1bpa",
4294 .data = &koe_tx14d24vm1bpa,
4296 .compatible = "koe,tx26d202vm0bwa",
4297 .data = &koe_tx26d202vm0bwa,
4299 .compatible = "koe,tx31d200vm0baa",
4300 .data = &koe_tx31d200vm0baa,
4302 .compatible = "kyo,tcg121xglp",
4303 .data = &kyo_tcg121xglp,
4305 .compatible = "lemaker,bl035-rgb-002",
4306 .data = &lemaker_bl035_rgb_002,
4308 .compatible = "lg,lb070wv8",
4309 .data = &lg_lb070wv8,
4311 .compatible = "lg,lp079qx1-sp0v",
4312 .data = &lg_lp079qx1_sp0v,
4314 .compatible = "lg,lp097qx1-spa1",
4315 .data = &lg_lp097qx1_spa1,
4317 .compatible = "lg,lp120up1",
4318 .data = &lg_lp120up1,
4320 .compatible = "lg,lp129qe",
4321 .data = &lg_lp129qe,
4323 .compatible = "logicpd,type28",
4324 .data = &logicpd_type_28,
4326 .compatible = "logictechno,lt161010-2nhc",
4327 .data = &logictechno_lt161010_2nh,
4329 .compatible = "logictechno,lt161010-2nhr",
4330 .data = &logictechno_lt161010_2nh,
4332 .compatible = "logictechno,lt170410-2whc",
4333 .data = &logictechno_lt170410_2whc,
4335 .compatible = "mitsubishi,aa070mc01-ca1",
4336 .data = &mitsubishi_aa070mc01,
4338 .compatible = "nec,nl12880bc20-05",
4339 .data = &nec_nl12880bc20_05,
4341 .compatible = "nec,nl4827hc19-05b",
4342 .data = &nec_nl4827hc19_05b,
4344 .compatible = "netron-dy,e231732",
4345 .data = &netron_dy_e231732,
4347 .compatible = "neweast,wjfh116008a",
4348 .data = &neweast_wjfh116008a,
4350 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4351 .data = &newhaven_nhd_43_480272ef_atxl,
4353 .compatible = "nlt,nl192108ac18-02d",
4354 .data = &nlt_nl192108ac18_02d,
4356 .compatible = "nvd,9128",
4359 .compatible = "okaya,rs800480t-7x0gp",
4360 .data = &okaya_rs800480t_7x0gp,
4362 .compatible = "olimex,lcd-olinuxino-43-ts",
4363 .data = &olimex_lcd_olinuxino_43ts,
4365 .compatible = "ontat,yx700wv03",
4366 .data = &ontat_yx700wv03,
4368 .compatible = "ortustech,com37h3m05dtc",
4369 .data = &ortustech_com37h3m,
4371 .compatible = "ortustech,com37h3m99dtc",
4372 .data = &ortustech_com37h3m,
4374 .compatible = "ortustech,com43h4m85ulc",
4375 .data = &ortustech_com43h4m85ulc,
4377 .compatible = "osddisplays,osd070t1718-19ts",
4378 .data = &osddisplays_osd070t1718_19ts,
4380 .compatible = "pda,91-00156-a0",
4381 .data = &pda_91_00156_a0,
4383 .compatible = "powertip,ph800480t013-idf02",
4384 .data = &powertip_ph800480t013_idf02,
4386 .compatible = "qiaodian,qd43003c0-40",
4387 .data = &qd43003c0_40,
4389 .compatible = "rocktech,rk070er9427",
4390 .data = &rocktech_rk070er9427,
4392 .compatible = "rocktech,rk101ii01d-ct",
4393 .data = &rocktech_rk101ii01d_ct,
4395 .compatible = "samsung,lsn122dl01-c01",
4396 .data = &samsung_lsn122dl01_c01,
4398 .compatible = "samsung,ltn101nt05",
4399 .data = &samsung_ltn101nt05,
4401 .compatible = "samsung,ltn140at29-301",
4402 .data = &samsung_ltn140at29_301,
4404 .compatible = "satoz,sat050at40h12r2",
4405 .data = &satoz_sat050at40h12r2,
4407 .compatible = "sharp,ld-d5116z01b",
4408 .data = &sharp_ld_d5116z01b,
4410 .compatible = "sharp,lq035q7db03",
4411 .data = &sharp_lq035q7db03,
4413 .compatible = "sharp,lq070y3dg3b",
4414 .data = &sharp_lq070y3dg3b,
4416 .compatible = "sharp,lq101k1ly04",
4417 .data = &sharp_lq101k1ly04,
4419 .compatible = "sharp,lq123p1jx31",
4420 .data = &sharp_lq123p1jx31,
4422 .compatible = "sharp,ls020b1dd01d",
4423 .data = &sharp_ls020b1dd01d,
4425 .compatible = "shelly,sca07010-bfn-lnn",
4426 .data = &shelly_sca07010_bfn_lnn,
4428 .compatible = "starry,kr070pe2t",
4429 .data = &starry_kr070pe2t,
4431 .compatible = "starry,kr122ea0sra",
4432 .data = &starry_kr122ea0sra,
4434 .compatible = "tfc,s9700rtwv43tr-01b",
4435 .data = &tfc_s9700rtwv43tr_01b,
4437 .compatible = "tianma,tm070jdhg30",
4438 .data = &tianma_tm070jdhg30,
4440 .compatible = "tianma,tm070jvhg33",
4441 .data = &tianma_tm070jvhg33,
4443 .compatible = "tianma,tm070rvhg71",
4444 .data = &tianma_tm070rvhg71,
4446 .compatible = "ti,nspire-cx-lcd-panel",
4447 .data = &ti_nspire_cx_lcd_panel,
4449 .compatible = "ti,nspire-classic-lcd-panel",
4450 .data = &ti_nspire_classic_lcd_panel,
4452 .compatible = "toshiba,lt089ac29000",
4453 .data = &toshiba_lt089ac29000,
4455 .compatible = "tpk,f07a-0102",
4456 .data = &tpk_f07a_0102,
4458 .compatible = "tpk,f10a-0102",
4459 .data = &tpk_f10a_0102,
4461 .compatible = "urt,umsh-8596md-t",
4462 .data = &urt_umsh_8596md_parallel,
4464 .compatible = "urt,umsh-8596md-1t",
4465 .data = &urt_umsh_8596md_parallel,
4467 .compatible = "urt,umsh-8596md-7t",
4468 .data = &urt_umsh_8596md_parallel,
4470 .compatible = "urt,umsh-8596md-11t",
4471 .data = &urt_umsh_8596md_lvds,
4473 .compatible = "urt,umsh-8596md-19t",
4474 .data = &urt_umsh_8596md_lvds,
4476 .compatible = "urt,umsh-8596md-20t",
4477 .data = &urt_umsh_8596md_parallel,
4479 .compatible = "vxt,vl050-8048nt-c01",
4480 .data = &vl050_8048nt_c01,
4482 .compatible = "winstar,wf35ltiacd",
4483 .data = &winstar_wf35ltiacd,
4485 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4486 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4488 /* Must be the last entry */
4489 .compatible = "panel-dpi",
4495 MODULE_DEVICE_TABLE(of, platform_of_match);
4497 static int panel_simple_platform_probe(struct platform_device *pdev)
4499 const struct of_device_id *id;
4501 id = of_match_node(platform_of_match, pdev->dev.of_node);
4505 return panel_simple_probe(&pdev->dev, id->data);
4508 static int panel_simple_platform_remove(struct platform_device *pdev)
4510 return panel_simple_remove(&pdev->dev);
4513 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4515 panel_simple_shutdown(&pdev->dev);
4518 static struct platform_driver panel_simple_platform_driver = {
4520 .name = "panel-simple",
4521 .of_match_table = platform_of_match,
4523 .probe = panel_simple_platform_probe,
4524 .remove = panel_simple_platform_remove,
4525 .shutdown = panel_simple_platform_shutdown,
4528 struct panel_desc_dsi {
4529 struct panel_desc desc;
4531 unsigned long flags;
4532 enum mipi_dsi_pixel_format format;
4536 static const struct drm_display_mode auo_b080uan01_mode = {
4539 .hsync_start = 1200 + 62,
4540 .hsync_end = 1200 + 62 + 4,
4541 .htotal = 1200 + 62 + 4 + 62,
4543 .vsync_start = 1920 + 9,
4544 .vsync_end = 1920 + 9 + 2,
4545 .vtotal = 1920 + 9 + 2 + 8,
4548 static const struct panel_desc_dsi auo_b080uan01 = {
4550 .modes = &auo_b080uan01_mode,
4557 .connector_type = DRM_MODE_CONNECTOR_DSI,
4559 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4560 .format = MIPI_DSI_FMT_RGB888,
4564 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4567 .hsync_start = 1200 + 120,
4568 .hsync_end = 1200 + 120 + 20,
4569 .htotal = 1200 + 120 + 20 + 21,
4571 .vsync_start = 1920 + 21,
4572 .vsync_end = 1920 + 21 + 3,
4573 .vtotal = 1920 + 21 + 3 + 18,
4574 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4577 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4579 .modes = &boe_tv080wum_nl0_mode,
4585 .connector_type = DRM_MODE_CONNECTOR_DSI,
4587 .flags = MIPI_DSI_MODE_VIDEO |
4588 MIPI_DSI_MODE_VIDEO_BURST |
4589 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4590 .format = MIPI_DSI_FMT_RGB888,
4594 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4597 .hsync_start = 800 + 32,
4598 .hsync_end = 800 + 32 + 1,
4599 .htotal = 800 + 32 + 1 + 57,
4601 .vsync_start = 1280 + 28,
4602 .vsync_end = 1280 + 28 + 1,
4603 .vtotal = 1280 + 28 + 1 + 14,
4606 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4608 .modes = &lg_ld070wx3_sl01_mode,
4615 .connector_type = DRM_MODE_CONNECTOR_DSI,
4617 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4618 .format = MIPI_DSI_FMT_RGB888,
4622 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4625 .hsync_start = 720 + 12,
4626 .hsync_end = 720 + 12 + 4,
4627 .htotal = 720 + 12 + 4 + 112,
4629 .vsync_start = 1280 + 8,
4630 .vsync_end = 1280 + 8 + 4,
4631 .vtotal = 1280 + 8 + 4 + 12,
4634 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4636 .modes = &lg_lh500wx1_sd03_mode,
4643 .connector_type = DRM_MODE_CONNECTOR_DSI,
4645 .flags = MIPI_DSI_MODE_VIDEO,
4646 .format = MIPI_DSI_FMT_RGB888,
4650 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4653 .hsync_start = 1920 + 154,
4654 .hsync_end = 1920 + 154 + 16,
4655 .htotal = 1920 + 154 + 16 + 32,
4657 .vsync_start = 1200 + 17,
4658 .vsync_end = 1200 + 17 + 2,
4659 .vtotal = 1200 + 17 + 2 + 16,
4662 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4664 .modes = &panasonic_vvx10f004b00_mode,
4671 .connector_type = DRM_MODE_CONNECTOR_DSI,
4673 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4674 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4675 .format = MIPI_DSI_FMT_RGB888,
4679 static const struct drm_display_mode lg_acx467akm_7_mode = {
4682 .hsync_start = 1080 + 2,
4683 .hsync_end = 1080 + 2 + 2,
4684 .htotal = 1080 + 2 + 2 + 2,
4686 .vsync_start = 1920 + 2,
4687 .vsync_end = 1920 + 2 + 2,
4688 .vtotal = 1920 + 2 + 2 + 2,
4691 static const struct panel_desc_dsi lg_acx467akm_7 = {
4693 .modes = &lg_acx467akm_7_mode,
4700 .connector_type = DRM_MODE_CONNECTOR_DSI,
4703 .format = MIPI_DSI_FMT_RGB888,
4707 static const struct drm_display_mode osd101t2045_53ts_mode = {
4710 .hsync_start = 1920 + 112,
4711 .hsync_end = 1920 + 112 + 16,
4712 .htotal = 1920 + 112 + 16 + 32,
4714 .vsync_start = 1200 + 16,
4715 .vsync_end = 1200 + 16 + 2,
4716 .vtotal = 1200 + 16 + 2 + 16,
4717 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4720 static const struct panel_desc_dsi osd101t2045_53ts = {
4722 .modes = &osd101t2045_53ts_mode,
4729 .connector_type = DRM_MODE_CONNECTOR_DSI,
4731 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4732 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4733 MIPI_DSI_MODE_EOT_PACKET,
4734 .format = MIPI_DSI_FMT_RGB888,
4738 static const struct of_device_id dsi_of_match[] = {
4740 .compatible = "auo,b080uan01",
4741 .data = &auo_b080uan01
4743 .compatible = "boe,tv080wum-nl0",
4744 .data = &boe_tv080wum_nl0
4746 .compatible = "lg,ld070wx3-sl01",
4747 .data = &lg_ld070wx3_sl01
4749 .compatible = "lg,lh500wx1-sd03",
4750 .data = &lg_lh500wx1_sd03
4752 .compatible = "panasonic,vvx10f004b00",
4753 .data = &panasonic_vvx10f004b00
4755 .compatible = "lg,acx467akm-7",
4756 .data = &lg_acx467akm_7
4758 .compatible = "osddisplays,osd101t2045-53ts",
4759 .data = &osd101t2045_53ts
4764 MODULE_DEVICE_TABLE(of, dsi_of_match);
4766 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4768 const struct panel_desc_dsi *desc;
4769 const struct of_device_id *id;
4772 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4778 err = panel_simple_probe(&dsi->dev, &desc->desc);
4782 dsi->mode_flags = desc->flags;
4783 dsi->format = desc->format;
4784 dsi->lanes = desc->lanes;
4786 err = mipi_dsi_attach(dsi);
4788 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4790 drm_panel_remove(&panel->base);
4796 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4800 err = mipi_dsi_detach(dsi);
4802 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4804 return panel_simple_remove(&dsi->dev);
4807 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4809 panel_simple_shutdown(&dsi->dev);
4812 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4814 .name = "panel-simple-dsi",
4815 .of_match_table = dsi_of_match,
4817 .probe = panel_simple_dsi_probe,
4818 .remove = panel_simple_dsi_remove,
4819 .shutdown = panel_simple_dsi_shutdown,
4822 static int __init panel_simple_init(void)
4826 err = platform_driver_register(&panel_simple_platform_driver);
4830 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4831 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4833 platform_driver_unregister(&panel_simple_platform_driver);
4840 module_init(panel_simple_init);
4842 static void __exit panel_simple_exit(void)
4844 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4845 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4847 platform_driver_unregister(&panel_simple_platform_driver);
4849 module_exit(panel_simple_exit);
4851 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4852 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4853 MODULE_LICENSE("GPL and additional rights");