drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c

   1 /*
   2  * Toppoly TD028TTEC1 panel support
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
   6  *
   7  * Neo 1973 code (jbt6k74.c):
   8  * Copyright (C) 2006-2007 by OpenMoko, Inc.
   9  * Author: Harald Welte <laforge@openmoko.org>
  10  *
  11  * Ported and adapted from Neo 1973 U-Boot by:
  12  * H. Nikolaus Schaller <hns@goldelico.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of the GNU General Public License version 2 as published by
  16  * the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  21  * more details.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program.  If not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/delay.h>
  29 #include <linux/spi/spi.h>
  30
  31 #include "../dss/omapdss.h"
  32
  33 struct panel_drv_data {
  34         struct omap_dss_device dssdev;
  35
  36         struct videomode vm;
  37
  38         struct backlight_device *backlight;
  39
  40         struct spi_device *spi_dev;
  41 };
  42
  43 static const struct videomode td028ttec1_panel_vm = {
  44         .hactive        = 480,
  45         .vactive        = 640,
  46         .pixelclock     = 22153000,
  47         .hfront_porch   = 24,
  48         .hsync_len      = 8,
  49         .hback_porch    = 8,
  50         .vfront_porch   = 4,
  51         .vsync_len      = 2,
  52         .vback_porch    = 2,
  53
  54         .flags          = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
  55 };
  56
  57 #define JBT_COMMAND     0x000
  58 #define JBT_DATA        0x100
  59
  60 static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
  61 {
  62         int rc;
  63         u16 tx_buf = JBT_COMMAND | reg;
  64
  65         rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
  66                         1*sizeof(u16));
  67         if (rc != 0)
  68                 dev_err(&ddata->spi_dev->dev,
  69                         "jbt_ret_write_0 spi_write ret %d\n", rc);
  70
  71         return rc;
  72 }
  73
  74 static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
  75 {
  76         int rc;
  77         u16 tx_buf[2];
  78
  79         tx_buf[0] = JBT_COMMAND | reg;
  80         tx_buf[1] = JBT_DATA | data;
  81         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
  82                         2*sizeof(u16));
  83         if (rc != 0)
  84                 dev_err(&ddata->spi_dev->dev,
  85                         "jbt_reg_write_1 spi_write ret %d\n", rc);
  86
  87         return rc;
  88 }
  89
  90 static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
  91 {
  92         int rc;
  93         u16 tx_buf[3];
  94
  95         tx_buf[0] = JBT_COMMAND | reg;
  96         tx_buf[1] = JBT_DATA | (data >> 8);
  97         tx_buf[2] = JBT_DATA | (data & 0xff);
  98
  99         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
 100                         3*sizeof(u16));
 101
 102         if (rc != 0)
 103                 dev_err(&ddata->spi_dev->dev,
 104                         "jbt_reg_write_2 spi_write ret %d\n", rc);
 105
 106         return rc;
 107 }
 108
 109 enum jbt_register {
 110         JBT_REG_SLEEP_IN                = 0x10,
 111         JBT_REG_SLEEP_OUT               = 0x11,
 112
 113         JBT_REG_DISPLAY_OFF             = 0x28,
 114         JBT_REG_DISPLAY_ON              = 0x29,
 115
 116         JBT_REG_RGB_FORMAT              = 0x3a,
 117         JBT_REG_QUAD_RATE               = 0x3b,
 118
 119         JBT_REG_POWER_ON_OFF            = 0xb0,
 120         JBT_REG_BOOSTER_OP              = 0xb1,
 121         JBT_REG_BOOSTER_MODE            = 0xb2,
 122         JBT_REG_BOOSTER_FREQ            = 0xb3,
 123         JBT_REG_OPAMP_SYSCLK            = 0xb4,
 124         JBT_REG_VSC_VOLTAGE             = 0xb5,
 125         JBT_REG_VCOM_VOLTAGE            = 0xb6,
 126         JBT_REG_EXT_DISPL               = 0xb7,
 127         JBT_REG_OUTPUT_CONTROL          = 0xb8,
 128         JBT_REG_DCCLK_DCEV              = 0xb9,
 129         JBT_REG_DISPLAY_MODE1           = 0xba,
 130         JBT_REG_DISPLAY_MODE2           = 0xbb,
 131         JBT_REG_DISPLAY_MODE            = 0xbc,
 132         JBT_REG_ASW_SLEW                = 0xbd,
 133         JBT_REG_DUMMY_DISPLAY           = 0xbe,
 134         JBT_REG_DRIVE_SYSTEM            = 0xbf,
 135
 136         JBT_REG_SLEEP_OUT_FR_A          = 0xc0,
 137         JBT_REG_SLEEP_OUT_FR_B          = 0xc1,
 138         JBT_REG_SLEEP_OUT_FR_C          = 0xc2,
 139         JBT_REG_SLEEP_IN_LCCNT_D        = 0xc3,
 140         JBT_REG_SLEEP_IN_LCCNT_E        = 0xc4,
 141         JBT_REG_SLEEP_IN_LCCNT_F        = 0xc5,
 142         JBT_REG_SLEEP_IN_LCCNT_G        = 0xc6,
 143
 144         JBT_REG_GAMMA1_FINE_1           = 0xc7,
 145         JBT_REG_GAMMA1_FINE_2           = 0xc8,
 146         JBT_REG_GAMMA1_INCLINATION      = 0xc9,
 147         JBT_REG_GAMMA1_BLUE_OFFSET      = 0xca,
 148
 149         JBT_REG_BLANK_CONTROL           = 0xcf,
 150         JBT_REG_BLANK_TH_TV             = 0xd0,
 151         JBT_REG_CKV_ON_OFF              = 0xd1,
 152         JBT_REG_CKV_1_2                 = 0xd2,
 153         JBT_REG_OEV_TIMING              = 0xd3,
 154         JBT_REG_ASW_TIMING_1            = 0xd4,
 155         JBT_REG_ASW_TIMING_2            = 0xd5,
 156
 157         JBT_REG_HCLOCK_VGA              = 0xec,
 158         JBT_REG_HCLOCK_QVGA             = 0xed,
 159 };
 160
 161 #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
 162
 163 static int td028ttec1_panel_connect(struct omap_dss_device *src,
 164                                     struct omap_dss_device *dst)
 165 {
 166         return 0;
 167 }
 168
 169 static void td028ttec1_panel_disconnect(struct omap_dss_device *src,
 170                                         struct omap_dss_device *dst)
 171 {
 172 }
 173
 174 static void td028ttec1_panel_enable(struct omap_dss_device *dssdev)
 175 {
 176         struct panel_drv_data *ddata = to_panel_data(dssdev);
 177         int r = 0;
 178
 179         dev_dbg(dssdev->dev, "%s: state %d\n", __func__, dssdev->state);
 180
 181         /* three times command zero */
 182         r |= jbt_ret_write_0(ddata, 0x00);
 183         usleep_range(1000, 2000);
 184         r |= jbt_ret_write_0(ddata, 0x00);
 185         usleep_range(1000, 2000);
 186         r |= jbt_ret_write_0(ddata, 0x00);
 187         usleep_range(1000, 2000);
 188
 189         if (r) {
 190                 dev_warn(dssdev->dev, "%s: transfer error\n", __func__);
 191                 return;
 192         }
 193
 194         /* deep standby out */
 195         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
 196
 197         /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
 198         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
 199
 200         /* Quad mode off */
 201         r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
 202
 203         /* AVDD on, XVDD on */
 204         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
 205
 206         /* Output control */
 207         r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
 208
 209         /* Sleep mode off */
 210         r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
 211
 212         /* at this point we have like 50% grey */
 213
 214         /* initialize register set */
 215         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
 216         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
 217         r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
 218         r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
 219         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
 220         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
 221         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 222         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 223         r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
 224         r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
 225         r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
 226         r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
 227         r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
 228         /*
 229          * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
 230          * to avoid red / blue flicker
 231          */
 232         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
 233         r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
 234
 235         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
 236         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
 237         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
 238         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
 239         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
 240         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
 241         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
 242
 243         r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
 244         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
 245         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
 246         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
 247
 248         r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
 249         r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
 250         r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
 251
 252         r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
 253         r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
 254
 255         r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
 256         r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
 257         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
 258
 259         r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
 260
 261         if (r)
 262                 dev_err(dssdev->dev, "%s: write error\n", __func__);
 263
 264         backlight_enable(ddata->backlight);
 265 }
 266
 267 static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
 268 {
 269         struct panel_drv_data *ddata = to_panel_data(dssdev);
 270
 271         backlight_disable(ddata->backlight);
 272
 273         dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
 274
 275         jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
 276         jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
 277         jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
 278         jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
 279 }
 280
 281 static int td028ttec1_panel_get_modes(struct omap_dss_device *dssdev,
 282                                       struct drm_connector *connector)
 283 {
 284         struct panel_drv_data *ddata = to_panel_data(dssdev);
 285
 286         return omapdss_display_get_modes(connector, &ddata->vm);
 287 }
 288
 289 static const struct omap_dss_device_ops td028ttec1_ops = {
 290         .connect        = td028ttec1_panel_connect,
 291         .disconnect     = td028ttec1_panel_disconnect,
 292
 293         .enable         = td028ttec1_panel_enable,
 294         .disable        = td028ttec1_panel_disable,
 295
 296         .get_modes      = td028ttec1_panel_get_modes,
 297 };
 298
 299 static int td028ttec1_panel_probe(struct spi_device *spi)
 300 {
 301         struct panel_drv_data *ddata;
 302         struct omap_dss_device *dssdev;
 303         int r;
 304
 305         dev_dbg(&spi->dev, "%s\n", __func__);
 306
 307         spi->bits_per_word = 9;
 308         spi->mode = SPI_MODE_3;
 309
 310         r = spi_setup(spi);
 311         if (r < 0) {
 312                 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
 313                 return r;
 314         }
 315
 316         ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
 317         if (ddata == NULL)
 318                 return -ENOMEM;
 319
 320         ddata->backlight = devm_of_find_backlight(&spi->dev);
 321         if (IS_ERR(ddata->backlight))
 322                 return PTR_ERR(ddata->backlight);
 323
 324         dev_set_drvdata(&spi->dev, ddata);
 325
 326         ddata->spi_dev = spi;
 327
 328         ddata->vm = td028ttec1_panel_vm;
 329
 330         dssdev = &ddata->dssdev;
 331         dssdev->dev = &spi->dev;
 332         dssdev->ops = &td028ttec1_ops;
 333         dssdev->type = OMAP_DISPLAY_TYPE_DPI;
 334         dssdev->display = true;
 335         dssdev->owner = THIS_MODULE;
 336         dssdev->of_ports = BIT(0);
 337         dssdev->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
 338
 339         /*
 340          * Note: According to the panel documentation:
 341          * SYNC needs to be driven on the FALLING edge
 342          */
 343         dssdev->bus_flags = DRM_BUS_FLAG_DE_HIGH
 344                           | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE
 345                           | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
 346
 347         omapdss_display_init(dssdev);
 348         omapdss_device_register(dssdev);
 349
 350         return 0;
 351 }
 352
 353 static int td028ttec1_panel_remove(struct spi_device *spi)
 354 {
 355         struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
 356         struct omap_dss_device *dssdev = &ddata->dssdev;
 357
 358         dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
 359
 360         omapdss_device_unregister(dssdev);
 361
 362         td028ttec1_panel_disable(dssdev);
 363
 364         return 0;
 365 }
 366
 367 static const struct of_device_id td028ttec1_of_match[] = {
 368         { .compatible = "omapdss,tpo,td028ttec1", },
 369         /* keep to not break older DTB */
 370         { .compatible = "omapdss,toppoly,td028ttec1", },
 371         {},
 372 };
 373
 374 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
 375
 376 static const struct spi_device_id td028ttec1_ids[] = {
 377         { "toppoly,td028ttec1", 0 },
 378         { "tpo,td028ttec1", 0},
 379         { /* sentinel */ }
 380 };
 381
 382 MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
 383
 384
 385 static struct spi_driver td028ttec1_spi_driver = {
 386         .probe          = td028ttec1_panel_probe,
 387         .remove         = td028ttec1_panel_remove,
 388         .id_table       = td028ttec1_ids,
 389
 390         .driver         = {
 391                 .name   = "panel-tpo-td028ttec1",
 392                 .of_match_table = td028ttec1_of_match,
 393                 .suppress_bind_attrs = true,
 394         },
 395 };
 396
 397 module_spi_driver(td028ttec1_spi_driver);
 398
 399 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
 400 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
 401 MODULE_LICENSE("GPL");