drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "gf100.h"
  25 #include "ctxgf100.h"
  26 #include "fuc/os.h"
  27
  28 #include <core/client.h>
  29 #include <core/option.h>
  30 #include <core/firmware.h>
  31 #include <subdev/secboot.h>
  32 #include <subdev/fb.h>
  33 #include <subdev/mc.h>
  34 #include <subdev/pmu.h>
  35 #include <subdev/timer.h>
  36 #include <engine/fifo.h>
  37
  38 #include <nvif/class.h>
  39 #include <nvif/cl9097.h>
  40 #include <nvif/if900d.h>
  41 #include <nvif/unpack.h>
  42
  43 /*******************************************************************************
  44  * Zero Bandwidth Clear
  45  ******************************************************************************/
  46
  47 static void
  48 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
  49 {
  50         struct nvkm_device *device = gr->base.engine.subdev.device;
  51         if (gr->zbc_color[zbc].format) {
  52                 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);
  53                 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);
  54                 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);
  55                 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);
  56         }
  57         nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);
  58         nvkm_wr32(device, 0x405820, zbc);
  59         nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
  60 }
  61
  62 static int
  63 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
  64                        const u32 ds[4], const u32 l2[4])
  65 {
  66         struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
  67         int zbc = -ENOSPC, i;
  68
  69         for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
  70                 if (gr->zbc_color[i].format) {
  71                         if (gr->zbc_color[i].format != format)
  72                                 continue;
  73                         if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
  74                                    gr->zbc_color[i].ds)))
  75                                 continue;
  76                         if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
  77                                    gr->zbc_color[i].l2))) {
  78                                 WARN_ON(1);
  79                                 return -EINVAL;
  80                         }
  81                         return i;
  82                 } else {
  83                         zbc = (zbc < 0) ? i : zbc;
  84                 }
  85         }
  86
  87         if (zbc < 0)
  88                 return zbc;
  89
  90         memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
  91         memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
  92         gr->zbc_color[zbc].format = format;
  93         nvkm_ltc_zbc_color_get(ltc, zbc, l2);
  94         gf100_gr_zbc_clear_color(gr, zbc);
  95         return zbc;
  96 }
  97
  98 static void
  99 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
 100 {
 101         struct nvkm_device *device = gr->base.engine.subdev.device;
 102         if (gr->zbc_depth[zbc].format)
 103                 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);
 104         nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);
 105         nvkm_wr32(device, 0x405820, zbc);
 106         nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
 107 }
 108
 109 static int
 110 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
 111                        const u32 ds, const u32 l2)
 112 {
 113         struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
 114         int zbc = -ENOSPC, i;
 115
 116         for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
 117                 if (gr->zbc_depth[i].format) {
 118                         if (gr->zbc_depth[i].format != format)
 119                                 continue;
 120                         if (gr->zbc_depth[i].ds != ds)
 121                                 continue;
 122                         if (gr->zbc_depth[i].l2 != l2) {
 123                                 WARN_ON(1);
 124                                 return -EINVAL;
 125                         }
 126                         return i;
 127                 } else {
 128                         zbc = (zbc < 0) ? i : zbc;
 129                 }
 130         }
 131
 132         if (zbc < 0)
 133                 return zbc;
 134
 135         gr->zbc_depth[zbc].format = format;
 136         gr->zbc_depth[zbc].ds = ds;
 137         gr->zbc_depth[zbc].l2 = l2;
 138         nvkm_ltc_zbc_depth_get(ltc, zbc, l2);
 139         gf100_gr_zbc_clear_depth(gr, zbc);
 140         return zbc;
 141 }
 142
 143 /*******************************************************************************
 144  * Graphics object classes
 145  ******************************************************************************/
 146 #define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object)
 147
 148 struct gf100_gr_object {
 149         struct nvkm_object object;
 150         struct gf100_gr_chan *chan;
 151 };
 152
 153 static int
 154 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
 155 {
 156         struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
 157         union {
 158                 struct fermi_a_zbc_color_v0 v0;
 159         } *args = data;
 160         int ret = -ENOSYS;
 161
 162         if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
 163                 switch (args->v0.format) {
 164                 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
 165                 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
 166                 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
 167                 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
 168                 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
 169                 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
 170                 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
 171                 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
 172                 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
 173                 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
 174                 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
 175                 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
 176                 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
 177                 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
 178                 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
 179                 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
 180                 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
 181                 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
 182                 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
 183                         ret = gf100_gr_zbc_color_get(gr, args->v0.format,
 184                                                            args->v0.ds,
 185                                                            args->v0.l2);
 186                         if (ret >= 0) {
 187                                 args->v0.index = ret;
 188                                 return 0;
 189                         }
 190                         break;
 191                 default:
 192                         return -EINVAL;
 193                 }
 194         }
 195
 196         return ret;
 197 }
 198
 199 static int
 200 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
 201 {
 202         struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
 203         union {
 204                 struct fermi_a_zbc_depth_v0 v0;
 205         } *args = data;
 206         int ret = -ENOSYS;
 207
 208         if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
 209                 switch (args->v0.format) {
 210                 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
 211                         ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
 212                                                            args->v0.ds,
 213                                                            args->v0.l2);
 214                         return (ret >= 0) ? 0 : -ENOSPC;
 215                 default:
 216                         return -EINVAL;
 217                 }
 218         }
 219
 220         return ret;
 221 }
 222
 223 static int
 224 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
 225 {
 226         nvif_ioctl(object, "fermi mthd %08x\n", mthd);
 227         switch (mthd) {
 228         case FERMI_A_ZBC_COLOR:
 229                 return gf100_fermi_mthd_zbc_color(object, data, size);
 230         case FERMI_A_ZBC_DEPTH:
 231                 return gf100_fermi_mthd_zbc_depth(object, data, size);
 232         default:
 233                 break;
 234         }
 235         return -EINVAL;
 236 }
 237
 238 const struct nvkm_object_func
 239 gf100_fermi = {
 240         .mthd = gf100_fermi_mthd,
 241 };
 242
 243 static void
 244 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)
 245 {
 246         nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000);
 247         nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000);
 248 }
 249
 250 static bool
 251 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)
 252 {
 253         switch (class & 0x00ff) {
 254         case 0x97:
 255         case 0xc0:
 256                 switch (mthd) {
 257                 case 0x1528:
 258                         gf100_gr_mthd_set_shader_exceptions(device, data);
 259                         return true;
 260                 default:
 261                         break;
 262                 }
 263                 break;
 264         default:
 265                 break;
 266         }
 267         return false;
 268 }
 269
 270 static const struct nvkm_object_func
 271 gf100_gr_object_func = {
 272 };
 273
 274 static int
 275 gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
 276                     struct nvkm_object **pobject)
 277 {
 278         struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent);
 279         struct gf100_gr_object *object;
 280
 281         if (!(object = kzalloc(sizeof(*object), GFP_KERNEL)))
 282                 return -ENOMEM;
 283         *pobject = &object->object;
 284
 285         nvkm_object_ctor(oclass->base.func ? oclass->base.func :
 286                          &gf100_gr_object_func, oclass, &object->object);
 287         object->chan = chan;
 288         return 0;
 289 }
 290
 291 static int
 292 gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass)
 293 {
 294         struct gf100_gr *gr = gf100_gr(base);
 295         int c = 0;
 296
 297         while (gr->func->sclass[c].oclass) {
 298                 if (c++ == index) {
 299                         *sclass = gr->func->sclass[index];
 300                         sclass->ctor = gf100_gr_object_new;
 301                         return index;
 302                 }
 303         }
 304
 305         return c;
 306 }
 307
 308 /*******************************************************************************
 309  * PGRAPH context
 310  ******************************************************************************/
 311
 312 static int
 313 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
 314                    int align, struct nvkm_gpuobj **pgpuobj)
 315 {
 316         struct gf100_gr_chan *chan = gf100_gr_chan(object);
 317         struct gf100_gr *gr = chan->gr;
 318         int ret, i;
 319
 320         ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
 321                               align, false, parent, pgpuobj);
 322         if (ret)
 323                 return ret;
 324
 325         nvkm_kmap(*pgpuobj);
 326         for (i = 0; i < gr->size; i += 4)
 327                 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]);
 328
 329         if (!gr->firmware) {
 330                 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2);
 331                 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8);
 332         } else {
 333                 nvkm_wo32(*pgpuobj, 0xf4, 0);
 334                 nvkm_wo32(*pgpuobj, 0xf8, 0);
 335                 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2);
 336                 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr));
 337                 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr));
 338                 nvkm_wo32(*pgpuobj, 0x1c, 1);
 339                 nvkm_wo32(*pgpuobj, 0x20, 0);
 340                 nvkm_wo32(*pgpuobj, 0x28, 0);
 341                 nvkm_wo32(*pgpuobj, 0x2c, 0);
 342         }
 343         nvkm_done(*pgpuobj);
 344         return 0;
 345 }
 346
 347 static void *
 348 gf100_gr_chan_dtor(struct nvkm_object *object)
 349 {
 350         struct gf100_gr_chan *chan = gf100_gr_chan(object);
 351         int i;
 352
 353         for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
 354                 nvkm_vmm_put(chan->vmm, &chan->data[i].vma);
 355                 nvkm_memory_unref(&chan->data[i].mem);
 356         }
 357
 358         nvkm_vmm_put(chan->vmm, &chan->mmio_vma);
 359         nvkm_memory_unref(&chan->mmio);
 360         nvkm_vmm_unref(&chan->vmm);
 361         return chan;
 362 }
 363
 364 static const struct nvkm_object_func
 365 gf100_gr_chan = {
 366         .dtor = gf100_gr_chan_dtor,
 367         .bind = gf100_gr_chan_bind,
 368 };
 369
 370 static int
 371 gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
 372                   const struct nvkm_oclass *oclass,
 373                   struct nvkm_object **pobject)
 374 {
 375         struct gf100_gr *gr = gf100_gr(base);
 376         struct gf100_gr_data *data = gr->mmio_data;
 377         struct gf100_gr_mmio *mmio = gr->mmio_list;
 378         struct gf100_gr_chan *chan;
 379         struct gf100_vmm_map_v0 args = { .priv = 1 };
 380         struct nvkm_device *device = gr->base.engine.subdev.device;
 381         int ret, i;
 382
 383         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
 384                 return -ENOMEM;
 385         nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object);
 386         chan->gr = gr;
 387         chan->vmm = nvkm_vmm_ref(fifoch->vmm);
 388         *pobject = &chan->object;
 389
 390         /* allocate memory for a "mmio list" buffer that's used by the HUB
 391          * fuc to modify some per-context register settings on first load
 392          * of the context.
 393          */
 394         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,
 395                               false, &chan->mmio);
 396         if (ret)
 397                 return ret;
 398
 399         ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma);
 400         if (ret)
 401                 return ret;
 402
 403         ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm,
 404                               chan->mmio_vma, &args, sizeof(args));
 405         if (ret)
 406                 return ret;
 407
 408         /* allocate buffers referenced by mmio list */
 409         for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) {
 410                 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
 411                                       data->size, data->align, false,
 412                                       &chan->data[i].mem);
 413                 if (ret)
 414                         return ret;
 415
 416                 ret = nvkm_vmm_get(fifoch->vmm, 12,
 417                                    nvkm_memory_size(chan->data[i].mem),
 418                                    &chan->data[i].vma);
 419                 if (ret)
 420                         return ret;
 421
 422                 args.priv = data->priv;
 423
 424                 ret = nvkm_memory_map(chan->data[i].mem, 0, chan->vmm,
 425                                       chan->data[i].vma, &args, sizeof(args));
 426                 if (ret)
 427                         return ret;
 428
 429                 data++;
 430         }
 431
 432         /* finally, fill in the mmio list and point the context at it */
 433         nvkm_kmap(chan->mmio);
 434         for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
 435                 u32 addr = mmio->addr;
 436                 u32 data = mmio->data;
 437
 438                 if (mmio->buffer >= 0) {
 439                         u64 info = chan->data[mmio->buffer].vma->addr;
 440                         data |= info >> mmio->shift;
 441                 }
 442
 443                 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
 444                 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
 445                 mmio++;
 446         }
 447         nvkm_done(chan->mmio);
 448         return 0;
 449 }
 450
 451 /*******************************************************************************
 452  * PGRAPH register lists
 453  ******************************************************************************/
 454
 455 const struct gf100_gr_init
 456 gf100_gr_init_main_0[] = {
 457         { 0x400080,   1, 0x04, 0x003083c2 },
 458         { 0x400088,   1, 0x04, 0x00006fe7 },
 459         { 0x40008c,   1, 0x04, 0x00000000 },
 460         { 0x400090,   1, 0x04, 0x00000030 },
 461         { 0x40013c,   1, 0x04, 0x013901f7 },
 462         { 0x400140,   1, 0x04, 0x00000100 },
 463         { 0x400144,   1, 0x04, 0x00000000 },
 464         { 0x400148,   1, 0x04, 0x00000110 },
 465         { 0x400138,   1, 0x04, 0x00000000 },
 466         { 0x400130,   2, 0x04, 0x00000000 },
 467         { 0x400124,   1, 0x04, 0x00000002 },
 468         {}
 469 };
 470
 471 const struct gf100_gr_init
 472 gf100_gr_init_fe_0[] = {
 473         { 0x40415c,   1, 0x04, 0x00000000 },
 474         { 0x404170,   1, 0x04, 0x00000000 },
 475         {}
 476 };
 477
 478 const struct gf100_gr_init
 479 gf100_gr_init_pri_0[] = {
 480         { 0x404488,   2, 0x04, 0x00000000 },
 481         {}
 482 };
 483
 484 const struct gf100_gr_init
 485 gf100_gr_init_rstr2d_0[] = {
 486         { 0x407808,   1, 0x04, 0x00000000 },
 487         {}
 488 };
 489
 490 const struct gf100_gr_init
 491 gf100_gr_init_pd_0[] = {
 492         { 0x406024,   1, 0x04, 0x00000000 },
 493         {}
 494 };
 495
 496 const struct gf100_gr_init
 497 gf100_gr_init_ds_0[] = {
 498         { 0x405844,   1, 0x04, 0x00ffffff },
 499         { 0x405850,   1, 0x04, 0x00000000 },
 500         { 0x405908,   1, 0x04, 0x00000000 },
 501         {}
 502 };
 503
 504 const struct gf100_gr_init
 505 gf100_gr_init_scc_0[] = {
 506         { 0x40803c,   1, 0x04, 0x00000000 },
 507         {}
 508 };
 509
 510 const struct gf100_gr_init
 511 gf100_gr_init_prop_0[] = {
 512         { 0x4184a0,   1, 0x04, 0x00000000 },
 513         {}
 514 };
 515
 516 const struct gf100_gr_init
 517 gf100_gr_init_gpc_unk_0[] = {
 518         { 0x418604,   1, 0x04, 0x00000000 },
 519         { 0x418680,   1, 0x04, 0x00000000 },
 520         { 0x418714,   1, 0x04, 0x80000000 },
 521         { 0x418384,   1, 0x04, 0x00000000 },
 522         {}
 523 };
 524
 525 const struct gf100_gr_init
 526 gf100_gr_init_setup_0[] = {
 527         { 0x418814,   3, 0x04, 0x00000000 },
 528         {}
 529 };
 530
 531 const struct gf100_gr_init
 532 gf100_gr_init_crstr_0[] = {
 533         { 0x418b04,   1, 0x04, 0x00000000 },
 534         {}
 535 };
 536
 537 const struct gf100_gr_init
 538 gf100_gr_init_setup_1[] = {
 539         { 0x4188c8,   1, 0x04, 0x80000000 },
 540         { 0x4188cc,   1, 0x04, 0x00000000 },
 541         { 0x4188d0,   1, 0x04, 0x00010000 },
 542         { 0x4188d4,   1, 0x04, 0x00000001 },
 543         {}
 544 };
 545
 546 const struct gf100_gr_init
 547 gf100_gr_init_zcull_0[] = {
 548         { 0x418910,   1, 0x04, 0x00010001 },
 549         { 0x418914,   1, 0x04, 0x00000301 },
 550         { 0x418918,   1, 0x04, 0x00800000 },
 551         { 0x418980,   1, 0x04, 0x77777770 },
 552         { 0x418984,   3, 0x04, 0x77777777 },
 553         {}
 554 };
 555
 556 const struct gf100_gr_init
 557 gf100_gr_init_gpm_0[] = {
 558         { 0x418c04,   1, 0x04, 0x00000000 },
 559         { 0x418c88,   1, 0x04, 0x00000000 },
 560         {}
 561 };
 562
 563 const struct gf100_gr_init
 564 gf100_gr_init_gpc_unk_1[] = {
 565         { 0x418d00,   1, 0x04, 0x00000000 },
 566         { 0x418f08,   1, 0x04, 0x00000000 },
 567         { 0x418e00,   1, 0x04, 0x00000050 },
 568         { 0x418e08,   1, 0x04, 0x00000000 },
 569         {}
 570 };
 571
 572 const struct gf100_gr_init
 573 gf100_gr_init_gcc_0[] = {
 574         { 0x41900c,   1, 0x04, 0x00000000 },
 575         { 0x419018,   1, 0x04, 0x00000000 },
 576         {}
 577 };
 578
 579 const struct gf100_gr_init
 580 gf100_gr_init_tpccs_0[] = {
 581         { 0x419d08,   2, 0x04, 0x00000000 },
 582         { 0x419d10,   1, 0x04, 0x00000014 },
 583         {}
 584 };
 585
 586 const struct gf100_gr_init
 587 gf100_gr_init_tex_0[] = {
 588         { 0x419ab0,   1, 0x04, 0x00000000 },
 589         { 0x419ab8,   1, 0x04, 0x000000e7 },
 590         { 0x419abc,   2, 0x04, 0x00000000 },
 591         {}
 592 };
 593
 594 const struct gf100_gr_init
 595 gf100_gr_init_pe_0[] = {
 596         { 0x41980c,   3, 0x04, 0x00000000 },
 597         { 0x419844,   1, 0x04, 0x00000000 },
 598         { 0x41984c,   1, 0x04, 0x00005bc5 },
 599         { 0x419850,   4, 0x04, 0x00000000 },
 600         {}
 601 };
 602
 603 const struct gf100_gr_init
 604 gf100_gr_init_l1c_0[] = {
 605         { 0x419c98,   1, 0x04, 0x00000000 },
 606         { 0x419ca8,   1, 0x04, 0x80000000 },
 607         { 0x419cb4,   1, 0x04, 0x00000000 },
 608         { 0x419cb8,   1, 0x04, 0x00008bf4 },
 609         { 0x419cbc,   1, 0x04, 0x28137606 },
 610         { 0x419cc0,   2, 0x04, 0x00000000 },
 611         {}
 612 };
 613
 614 const struct gf100_gr_init
 615 gf100_gr_init_wwdx_0[] = {
 616         { 0x419bd4,   1, 0x04, 0x00800000 },
 617         { 0x419bdc,   1, 0x04, 0x00000000 },
 618         {}
 619 };
 620
 621 const struct gf100_gr_init
 622 gf100_gr_init_tpccs_1[] = {
 623         { 0x419d2c,   1, 0x04, 0x00000000 },
 624         {}
 625 };
 626
 627 const struct gf100_gr_init
 628 gf100_gr_init_mpc_0[] = {
 629         { 0x419c0c,   1, 0x04, 0x00000000 },
 630         {}
 631 };
 632
 633 static const struct gf100_gr_init
 634 gf100_gr_init_sm_0[] = {
 635         { 0x419e00,   1, 0x04, 0x00000000 },
 636         { 0x419ea0,   1, 0x04, 0x00000000 },
 637         { 0x419ea4,   1, 0x04, 0x00000100 },
 638         { 0x419ea8,   1, 0x04, 0x00001100 },
 639         { 0x419eac,   1, 0x04, 0x11100702 },
 640         { 0x419eb0,   1, 0x04, 0x00000003 },
 641         { 0x419eb4,   4, 0x04, 0x00000000 },
 642         { 0x419ec8,   1, 0x04, 0x06060618 },
 643         { 0x419ed0,   1, 0x04, 0x0eff0e38 },
 644         { 0x419ed4,   1, 0x04, 0x011104f1 },
 645         { 0x419edc,   1, 0x04, 0x00000000 },
 646         { 0x419f00,   1, 0x04, 0x00000000 },
 647         { 0x419f2c,   1, 0x04, 0x00000000 },
 648         {}
 649 };
 650
 651 const struct gf100_gr_init
 652 gf100_gr_init_be_0[] = {
 653         { 0x40880c,   1, 0x04, 0x00000000 },
 654         { 0x408910,   9, 0x04, 0x00000000 },
 655         { 0x408950,   1, 0x04, 0x00000000 },
 656         { 0x408954,   1, 0x04, 0x0000ffff },
 657         { 0x408984,   1, 0x04, 0x00000000 },
 658         { 0x408988,   1, 0x04, 0x08040201 },
 659         { 0x40898c,   1, 0x04, 0x80402010 },
 660         {}
 661 };
 662
 663 const struct gf100_gr_init
 664 gf100_gr_init_fe_1[] = {
 665         { 0x4040f0,   1, 0x04, 0x00000000 },
 666         {}
 667 };
 668
 669 const struct gf100_gr_init
 670 gf100_gr_init_pe_1[] = {
 671         { 0x419880,   1, 0x04, 0x00000002 },
 672         {}
 673 };
 674
 675 static const struct gf100_gr_pack
 676 gf100_gr_pack_mmio[] = {
 677         { gf100_gr_init_main_0 },
 678         { gf100_gr_init_fe_0 },
 679         { gf100_gr_init_pri_0 },
 680         { gf100_gr_init_rstr2d_0 },
 681         { gf100_gr_init_pd_0 },
 682         { gf100_gr_init_ds_0 },
 683         { gf100_gr_init_scc_0 },
 684         { gf100_gr_init_prop_0 },
 685         { gf100_gr_init_gpc_unk_0 },
 686         { gf100_gr_init_setup_0 },
 687         { gf100_gr_init_crstr_0 },
 688         { gf100_gr_init_setup_1 },
 689         { gf100_gr_init_zcull_0 },
 690         { gf100_gr_init_gpm_0 },
 691         { gf100_gr_init_gpc_unk_1 },
 692         { gf100_gr_init_gcc_0 },
 693         { gf100_gr_init_tpccs_0 },
 694         { gf100_gr_init_tex_0 },
 695         { gf100_gr_init_pe_0 },
 696         { gf100_gr_init_l1c_0 },
 697         { gf100_gr_init_wwdx_0 },
 698         { gf100_gr_init_tpccs_1 },
 699         { gf100_gr_init_mpc_0 },
 700         { gf100_gr_init_sm_0 },
 701         { gf100_gr_init_be_0 },
 702         { gf100_gr_init_fe_1 },
 703         { gf100_gr_init_pe_1 },
 704         {}
 705 };
 706
 707 /*******************************************************************************
 708  * PGRAPH engine/subdev functions
 709  ******************************************************************************/
 710
 711 static bool
 712 gf100_gr_chsw_load(struct nvkm_gr *base)
 713 {
 714         struct gf100_gr *gr = gf100_gr(base);
 715         if (!gr->firmware) {
 716                 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c);
 717                 if (trace & 0x00000040)
 718                         return true;
 719         } else {
 720                 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808);
 721                 if (mthd & 0x00080000)
 722                         return true;
 723         }
 724         return false;
 725 }
 726
 727 int
 728 gf100_gr_rops(struct gf100_gr *gr)
 729 {
 730         struct nvkm_device *device = gr->base.engine.subdev.device;
 731         return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;
 732 }
 733
 734 void
 735 gf100_gr_zbc_init(struct gf100_gr *gr)
 736 {
 737         const u32  zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 738                               0x00000000, 0x00000000, 0x00000000, 0x00000000 };
 739         const u32   one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
 740                               0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
 741         const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 742                               0x00000000, 0x00000000, 0x00000000, 0x00000000 };
 743         const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
 744                               0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
 745         struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
 746         int index;
 747
 748         if (!gr->zbc_color[0].format) {
 749                 gf100_gr_zbc_color_get(gr, 1,  & zero[0],   &zero[4]);
 750                 gf100_gr_zbc_color_get(gr, 2,  &  one[0],    &one[4]);
 751                 gf100_gr_zbc_color_get(gr, 4,  &f32_0[0],  &f32_0[4]);
 752                 gf100_gr_zbc_color_get(gr, 4,  &f32_1[0],  &f32_1[4]);
 753                 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000);
 754                 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000);
 755         }
 756
 757         for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
 758                 gf100_gr_zbc_clear_color(gr, index);
 759         for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
 760                 gf100_gr_zbc_clear_depth(gr, index);
 761 }
 762
 763 /**
 764  * Wait until GR goes idle. GR is considered idle if it is disabled by the
 765  * MC (0x200) register, or GR is not busy and a context switch is not in
 766  * progress.
 767  */
 768 int
 769 gf100_gr_wait_idle(struct gf100_gr *gr)
 770 {
 771         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
 772         struct nvkm_device *device = subdev->device;
 773         unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
 774         bool gr_enabled, ctxsw_active, gr_busy;
 775
 776         do {
 777                 /*
 778                  * required to make sure FIFO_ENGINE_STATUS (0x2640) is
 779                  * up-to-date
 780                  */
 781                 nvkm_rd32(device, 0x400700);
 782
 783                 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
 784                 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000;
 785                 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
 786
 787                 if (!gr_enabled || (!gr_busy && !ctxsw_active))
 788                         return 0;
 789         } while (time_before(jiffies, end_jiffies));
 790
 791         nvkm_error(subdev,
 792                    "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
 793                    gr_enabled, ctxsw_active, gr_busy);
 794         return -EAGAIN;
 795 }
 796
 797 void
 798 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
 799 {
 800         struct nvkm_device *device = gr->base.engine.subdev.device;
 801         const struct gf100_gr_pack *pack;
 802         const struct gf100_gr_init *init;
 803
 804         pack_for_each_init(init, pack, p) {
 805                 u32 next = init->addr + init->count * init->pitch;
 806                 u32 addr = init->addr;
 807                 while (addr < next) {
 808                         nvkm_wr32(device, addr, init->data);
 809                         addr += init->pitch;
 810                 }
 811         }
 812 }
 813
 814 void
 815 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
 816 {
 817         struct nvkm_device *device = gr->base.engine.subdev.device;
 818         const struct gf100_gr_pack *pack;
 819         const struct gf100_gr_init *init;
 820         u32 data = 0;
 821
 822         nvkm_wr32(device, 0x400208, 0x80000000);
 823
 824         pack_for_each_init(init, pack, p) {
 825                 u32 next = init->addr + init->count * init->pitch;
 826                 u32 addr = init->addr;
 827
 828                 if ((pack == p && init == p->init) || data != init->data) {
 829                         nvkm_wr32(device, 0x400204, init->data);
 830                         data = init->data;
 831                 }
 832
 833                 while (addr < next) {
 834                         nvkm_wr32(device, 0x400200, addr);
 835                         /**
 836                          * Wait for GR to go idle after submitting a
 837                          * GO_IDLE bundle
 838                          */
 839                         if ((addr & 0xffff) == 0xe100)
 840                                 gf100_gr_wait_idle(gr);
 841                         nvkm_msec(device, 2000,
 842                                 if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
 843                                         break;
 844                         );
 845                         addr += init->pitch;
 846                 }
 847         }
 848
 849         nvkm_wr32(device, 0x400208, 0x00000000);
 850 }
 851
 852 void
 853 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
 854 {
 855         struct nvkm_device *device = gr->base.engine.subdev.device;
 856         const struct gf100_gr_pack *pack;
 857         const struct gf100_gr_init *init;
 858         u32 data = 0;
 859
 860         pack_for_each_init(init, pack, p) {
 861                 u32 ctrl = 0x80000000 | pack->type;
 862                 u32 next = init->addr + init->count * init->pitch;
 863                 u32 addr = init->addr;
 864
 865                 if ((pack == p && init == p->init) || data != init->data) {
 866                         nvkm_wr32(device, 0x40448c, init->data);
 867                         data = init->data;
 868                 }
 869
 870                 while (addr < next) {
 871                         nvkm_wr32(device, 0x404488, ctrl | (addr << 14));
 872                         addr += init->pitch;
 873                 }
 874         }
 875 }
 876
 877 u64
 878 gf100_gr_units(struct nvkm_gr *base)
 879 {
 880         struct gf100_gr *gr = gf100_gr(base);
 881         u64 cfg;
 882
 883         cfg  = (u32)gr->gpc_nr;
 884         cfg |= (u32)gr->tpc_total << 8;
 885         cfg |= (u64)gr->rop_nr << 32;
 886
 887         return cfg;
 888 }
 889
 890 static const struct nvkm_bitfield gf100_dispatch_error[] = {
 891         { 0x00000001, "INJECTED_BUNDLE_ERROR" },
 892         { 0x00000002, "CLASS_SUBCH_MISMATCH" },
 893         { 0x00000004, "SUBCHSW_DURING_NOTIFY" },
 894         {}
 895 };
 896
 897 static const struct nvkm_bitfield gf100_m2mf_error[] = {
 898         { 0x00000001, "PUSH_TOO_MUCH_DATA" },
 899         { 0x00000002, "PUSH_NOT_ENOUGH_DATA" },
 900         {}
 901 };
 902
 903 static const struct nvkm_bitfield gf100_unk6_error[] = {
 904         { 0x00000001, "TEMP_TOO_SMALL" },
 905         {}
 906 };
 907
 908 static const struct nvkm_bitfield gf100_ccache_error[] = {
 909         { 0x00000001, "INTR" },
 910         { 0x00000002, "LDCONST_OOB" },
 911         {}
 912 };
 913
 914 static const struct nvkm_bitfield gf100_macro_error[] = {
 915         { 0x00000001, "TOO_FEW_PARAMS" },
 916         { 0x00000002, "TOO_MANY_PARAMS" },
 917         { 0x00000004, "ILLEGAL_OPCODE" },
 918         { 0x00000008, "DOUBLE_BRANCH" },
 919         { 0x00000010, "WATCHDOG" },
 920         {}
 921 };
 922
 923 static const struct nvkm_bitfield gk104_sked_error[] = {
 924         { 0x00000040, "CTA_RESUME" },
 925         { 0x00000080, "CONSTANT_BUFFER_SIZE" },
 926         { 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
 927         { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
 928         { 0x00000800, "WARP_CSTACK_SIZE" },
 929         { 0x00001000, "TOTAL_TEMP_SIZE" },
 930         { 0x00002000, "REGISTER_COUNT" },
 931         { 0x00040000, "TOTAL_THREADS" },
 932         { 0x00100000, "PROGRAM_OFFSET" },
 933         { 0x00200000, "SHARED_MEMORY_SIZE" },
 934         { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" },
 935         { 0x01000000, "MEMORY_WINDOW_OVERLAP" },
 936         { 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
 937         { 0x04000000, "TOTAL_REGISTER_COUNT" },
 938         {}
 939 };
 940
 941 static const struct nvkm_bitfield gf100_gpc_rop_error[] = {
 942         { 0x00000002, "RT_PITCH_OVERRUN" },
 943         { 0x00000010, "RT_WIDTH_OVERRUN" },
 944         { 0x00000020, "RT_HEIGHT_OVERRUN" },
 945         { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
 946         { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
 947         { 0x00000400, "RT_LINEAR_MISMATCH" },
 948         {}
 949 };
 950
 951 static void
 952 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
 953 {
 954         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
 955         struct nvkm_device *device = subdev->device;
 956         char error[128];
 957         u32 trap[4];
 958
 959         trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
 960         trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
 961         trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
 962         trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
 963
 964         nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]);
 965
 966         nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
 967                            "format = %x, storage type = %x\n",
 968                    gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
 969                    (trap[2] >> 8) & 0x3f, trap[3] & 0xff);
 970         nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 971 }
 972
 973 static const struct nvkm_enum gf100_mp_warp_error[] = {
 974         { 0x01, "STACK_ERROR" },
 975         { 0x02, "API_STACK_ERROR" },
 976         { 0x03, "RET_EMPTY_STACK_ERROR" },
 977         { 0x04, "PC_WRAP" },
 978         { 0x05, "MISALIGNED_PC" },
 979         { 0x06, "PC_OVERFLOW" },
 980         { 0x07, "MISALIGNED_IMMC_ADDR" },
 981         { 0x08, "MISALIGNED_REG" },
 982         { 0x09, "ILLEGAL_INSTR_ENCODING" },
 983         { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
 984         { 0x0b, "ILLEGAL_INSTR_PARAM" },
 985         { 0x0c, "INVALID_CONST_ADDR" },
 986         { 0x0d, "OOR_REG" },
 987         { 0x0e, "OOR_ADDR" },
 988         { 0x0f, "MISALIGNED_ADDR" },
 989         { 0x10, "INVALID_ADDR_SPACE" },
 990         { 0x11, "ILLEGAL_INSTR_PARAM2" },
 991         { 0x12, "INVALID_CONST_ADDR_LDC" },
 992         { 0x13, "GEOMETRY_SM_ERROR" },
 993         { 0x14, "DIVERGENT" },
 994         { 0x15, "WARP_EXIT" },
 995         {}
 996 };
 997
 998 static const struct nvkm_bitfield gf100_mp_global_error[] = {
 999         { 0x00000001, "SM_TO_SM_FAULT" },
1000         { 0x00000002, "L1_ERROR" },
1001         { 0x00000004, "MULTIPLE_WARP_ERRORS" },
1002         { 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
1003         { 0x00000010, "BPT_INT" },
1004         { 0x00000020, "BPT_PAUSE" },
1005         { 0x00000040, "SINGLE_STEP_COMPLETE" },
1006         { 0x20000000, "ECC_SEC_ERROR" },
1007         { 0x40000000, "ECC_DED_ERROR" },
1008         { 0x80000000, "TIMEOUT" },
1009         {}
1010 };
1011
1012 static void
1013 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
1014 {
1015         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1016         struct nvkm_device *device = subdev->device;
1017         u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
1018         u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
1019         const struct nvkm_enum *warp;
1020         char glob[128];
1021
1022         nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
1023         warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
1024
1025         nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
1026                            "global %08x [%s] warp %04x [%s]\n",
1027                    gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
1028
1029         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
1030         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
1031 }
1032
1033 static void
1034 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
1035 {
1036         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1037         struct nvkm_device *device = subdev->device;
1038         u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
1039
1040         if (stat & 0x00000001) {
1041                 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
1042                 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap);
1043                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
1044                 stat &= ~0x00000001;
1045         }
1046
1047         if (stat & 0x00000002) {
1048                 gf100_gr_trap_mp(gr, gpc, tpc);
1049                 stat &= ~0x00000002;
1050         }
1051
1052         if (stat & 0x00000004) {
1053                 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
1054                 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap);
1055                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
1056                 stat &= ~0x00000004;
1057         }
1058
1059         if (stat & 0x00000008) {
1060                 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
1061                 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap);
1062                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
1063                 stat &= ~0x00000008;
1064         }
1065
1066         if (stat & 0x00000010) {
1067                 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430));
1068                 nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap);
1069                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000);
1070                 stat &= ~0x00000010;
1071         }
1072
1073         if (stat) {
1074                 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
1075         }
1076 }
1077
1078 static void
1079 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
1080 {
1081         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1082         struct nvkm_device *device = subdev->device;
1083         u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
1084         int tpc;
1085
1086         if (stat & 0x00000001) {
1087                 gf100_gr_trap_gpc_rop(gr, gpc);
1088                 stat &= ~0x00000001;
1089         }
1090
1091         if (stat & 0x00000002) {
1092                 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
1093                 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap);
1094                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1095                 stat &= ~0x00000002;
1096         }
1097
1098         if (stat & 0x00000004) {
1099                 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
1100                 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap);
1101                 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1102                 stat &= ~0x00000004;
1103         }
1104
1105         if (stat & 0x00000008) {
1106                 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
1107                 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap);
1108                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
1109                 stat &= ~0x00000009;
1110         }
1111
1112         for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
1113                 u32 mask = 0x00010000 << tpc;
1114                 if (stat & mask) {
1115                         gf100_gr_trap_tpc(gr, gpc, tpc);
1116                         nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);
1117                         stat &= ~mask;
1118                 }
1119         }
1120
1121         if (stat) {
1122                 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat);
1123         }
1124 }
1125
1126 static void
1127 gf100_gr_trap_intr(struct gf100_gr *gr)
1128 {
1129         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1130         struct nvkm_device *device = subdev->device;
1131         char error[128];
1132         u32 trap = nvkm_rd32(device, 0x400108);
1133         int rop, gpc;
1134
1135         if (trap & 0x00000001) {
1136                 u32 stat = nvkm_rd32(device, 0x404000);
1137
1138                 nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error,
1139                                stat & 0x3fffffff);
1140                 nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error);
1141                 nvkm_wr32(device, 0x404000, 0xc0000000);
1142                 nvkm_wr32(device, 0x400108, 0x00000001);
1143                 trap &= ~0x00000001;
1144         }
1145
1146         if (trap & 0x00000002) {
1147                 u32 stat = nvkm_rd32(device, 0x404600);
1148
1149                 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error,
1150                                stat & 0x3fffffff);
1151                 nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error);
1152
1153                 nvkm_wr32(device, 0x404600, 0xc0000000);
1154                 nvkm_wr32(device, 0x400108, 0x00000002);
1155                 trap &= ~0x00000002;
1156         }
1157
1158         if (trap & 0x00000008) {
1159                 u32 stat = nvkm_rd32(device, 0x408030);
1160
1161                 nvkm_snprintbf(error, sizeof(error), gf100_ccache_error,
1162                                stat & 0x3fffffff);
1163                 nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error);
1164                 nvkm_wr32(device, 0x408030, 0xc0000000);
1165                 nvkm_wr32(device, 0x400108, 0x00000008);
1166                 trap &= ~0x00000008;
1167         }
1168
1169         if (trap & 0x00000010) {
1170                 u32 stat = nvkm_rd32(device, 0x405840);
1171                 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n",
1172                            stat, stat & 0xffffff, (stat >> 24) & 0x3f);
1173                 nvkm_wr32(device, 0x405840, 0xc0000000);
1174                 nvkm_wr32(device, 0x400108, 0x00000010);
1175                 trap &= ~0x00000010;
1176         }
1177
1178         if (trap & 0x00000040) {
1179                 u32 stat = nvkm_rd32(device, 0x40601c);
1180
1181                 nvkm_snprintbf(error, sizeof(error), gf100_unk6_error,
1182                                stat & 0x3fffffff);
1183                 nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error);
1184
1185                 nvkm_wr32(device, 0x40601c, 0xc0000000);
1186                 nvkm_wr32(device, 0x400108, 0x00000040);
1187                 trap &= ~0x00000040;
1188         }
1189
1190         if (trap & 0x00000080) {
1191                 u32 stat = nvkm_rd32(device, 0x404490);
1192                 u32 pc = nvkm_rd32(device, 0x404494);
1193                 u32 op = nvkm_rd32(device, 0x40449c);
1194
1195                 nvkm_snprintbf(error, sizeof(error), gf100_macro_error,
1196                                stat & 0x1fffffff);
1197                 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n",
1198                            stat, error, pc & 0x7ff,
1199                            (pc & 0x10000000) ? "" : " (invalid)",
1200                            op);
1201
1202                 nvkm_wr32(device, 0x404490, 0xc0000000);
1203                 nvkm_wr32(device, 0x400108, 0x00000080);
1204                 trap &= ~0x00000080;
1205         }
1206
1207         if (trap & 0x00000100) {
1208                 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
1209
1210                 nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat);
1211                 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error);
1212
1213                 if (stat)
1214                         nvkm_wr32(device, 0x407020, 0x40000000);
1215                 nvkm_wr32(device, 0x400108, 0x00000100);
1216                 trap &= ~0x00000100;
1217         }
1218
1219         if (trap & 0x01000000) {
1220                 u32 stat = nvkm_rd32(device, 0x400118);
1221                 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
1222                         u32 mask = 0x00000001 << gpc;
1223                         if (stat & mask) {
1224                                 gf100_gr_trap_gpc(gr, gpc);
1225                                 nvkm_wr32(device, 0x400118, mask);
1226                                 stat &= ~mask;
1227                         }
1228                 }
1229                 nvkm_wr32(device, 0x400108, 0x01000000);
1230                 trap &= ~0x01000000;
1231         }
1232
1233         if (trap & 0x02000000) {
1234                 for (rop = 0; rop < gr->rop_nr; rop++) {
1235                         u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
1236                         u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
1237                         nvkm_error(subdev, "ROP%d %08x %08x\n",
1238                                  rop, statz, statc);
1239                         nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
1240                         nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
1241                 }
1242                 nvkm_wr32(device, 0x400108, 0x02000000);
1243                 trap &= ~0x02000000;
1244         }
1245
1246         if (trap) {
1247                 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap);
1248                 nvkm_wr32(device, 0x400108, trap);
1249         }
1250 }
1251
1252 static void
1253 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
1254 {
1255         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1256         struct nvkm_device *device = subdev->device;
1257         nvkm_error(subdev, "%06x - done %08x\n", base,
1258                    nvkm_rd32(device, base + 0x400));
1259         nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1260                    nvkm_rd32(device, base + 0x800),
1261                    nvkm_rd32(device, base + 0x804),
1262                    nvkm_rd32(device, base + 0x808),
1263                    nvkm_rd32(device, base + 0x80c));
1264         nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1265                    nvkm_rd32(device, base + 0x810),
1266                    nvkm_rd32(device, base + 0x814),
1267                    nvkm_rd32(device, base + 0x818),
1268                    nvkm_rd32(device, base + 0x81c));
1269 }
1270
1271 void
1272 gf100_gr_ctxctl_debug(struct gf100_gr *gr)
1273 {
1274         struct nvkm_device *device = gr->base.engine.subdev.device;
1275         u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;
1276         u32 gpc;
1277
1278         gf100_gr_ctxctl_debug_unit(gr, 0x409000);
1279         for (gpc = 0; gpc < gpcnr; gpc++)
1280                 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
1281 }
1282
1283 static void
1284 gf100_gr_ctxctl_isr(struct gf100_gr *gr)
1285 {
1286         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1287         struct nvkm_device *device = subdev->device;
1288         u32 stat = nvkm_rd32(device, 0x409c18);
1289
1290         if (!gr->firmware && (stat & 0x00000001)) {
1291                 u32 code = nvkm_rd32(device, 0x409814);
1292                 if (code == E_BAD_FWMTHD) {
1293                         u32 class = nvkm_rd32(device, 0x409808);
1294                         u32  addr = nvkm_rd32(device, 0x40980c);
1295                         u32  subc = (addr & 0x00070000) >> 16;
1296                         u32  mthd = (addr & 0x00003ffc);
1297                         u32  data = nvkm_rd32(device, 0x409810);
1298
1299                         nvkm_error(subdev, "FECS MTHD subc %d class %04x "
1300                                            "mthd %04x data %08x\n",
1301                                    subc, class, mthd, data);
1302                 } else {
1303                         nvkm_error(subdev, "FECS ucode error %d\n", code);
1304                 }
1305                 nvkm_wr32(device, 0x409c20, 0x00000001);
1306                 stat &= ~0x00000001;
1307         }
1308
1309         if (!gr->firmware && (stat & 0x00080000)) {
1310                 nvkm_error(subdev, "FECS watchdog timeout\n");
1311                 gf100_gr_ctxctl_debug(gr);
1312                 nvkm_wr32(device, 0x409c20, 0x00080000);
1313                 stat &= ~0x00080000;
1314         }
1315
1316         if (stat) {
1317                 nvkm_error(subdev, "FECS %08x\n", stat);
1318                 gf100_gr_ctxctl_debug(gr);
1319                 nvkm_wr32(device, 0x409c20, stat);
1320         }
1321 }
1322
1323 static void
1324 gf100_gr_intr(struct nvkm_gr *base)
1325 {
1326         struct gf100_gr *gr = gf100_gr(base);
1327         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1328         struct nvkm_device *device = subdev->device;
1329         struct nvkm_fifo_chan *chan;
1330         unsigned long flags;
1331         u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
1332         u32 stat = nvkm_rd32(device, 0x400100);
1333         u32 addr = nvkm_rd32(device, 0x400704);
1334         u32 mthd = (addr & 0x00003ffc);
1335         u32 subc = (addr & 0x00070000) >> 16;
1336         u32 data = nvkm_rd32(device, 0x400708);
1337         u32 code = nvkm_rd32(device, 0x400110);
1338         u32 class;
1339         const char *name = "unknown";
1340         int chid = -1;
1341
1342         chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags);
1343         if (chan) {
1344                 name = chan->object.client->name;
1345                 chid = chan->chid;
1346         }
1347
1348         if (device->card_type < NV_E0 || subc < 4)
1349                 class = nvkm_rd32(device, 0x404200 + (subc * 4));
1350         else
1351                 class = 0x0000;
1352
1353         if (stat & 0x00000001) {
1354                 /*
1355                  * notifier interrupt, only needed for cyclestats
1356                  * can be safely ignored
1357                  */
1358                 nvkm_wr32(device, 0x400100, 0x00000001);
1359                 stat &= ~0x00000001;
1360         }
1361
1362         if (stat & 0x00000010) {
1363                 if (!gf100_gr_mthd_sw(device, class, mthd, data)) {
1364                         nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] "
1365                                    "subc %d class %04x mthd %04x data %08x\n",
1366                                    chid, inst << 12, name, subc,
1367                                    class, mthd, data);
1368                 }
1369                 nvkm_wr32(device, 0x400100, 0x00000010);
1370                 stat &= ~0x00000010;
1371         }
1372
1373         if (stat & 0x00000020) {
1374                 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] "
1375                            "subc %d class %04x mthd %04x data %08x\n",
1376                            chid, inst << 12, name, subc, class, mthd, data);
1377                 nvkm_wr32(device, 0x400100, 0x00000020);
1378                 stat &= ~0x00000020;
1379         }
1380
1381         if (stat & 0x00100000) {
1382                 const struct nvkm_enum *en =
1383                         nvkm_enum_find(nv50_data_error_names, code);
1384                 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] "
1385                                    "subc %d class %04x mthd %04x data %08x\n",
1386                            code, en ? en->name : "", chid, inst << 12,
1387                            name, subc, class, mthd, data);
1388                 nvkm_wr32(device, 0x400100, 0x00100000);
1389                 stat &= ~0x00100000;
1390         }
1391
1392         if (stat & 0x00200000) {
1393                 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n",
1394                            chid, inst << 12, name);
1395                 gf100_gr_trap_intr(gr);
1396                 nvkm_wr32(device, 0x400100, 0x00200000);
1397                 stat &= ~0x00200000;
1398         }
1399
1400         if (stat & 0x00080000) {
1401                 gf100_gr_ctxctl_isr(gr);
1402                 nvkm_wr32(device, 0x400100, 0x00080000);
1403                 stat &= ~0x00080000;
1404         }
1405
1406         if (stat) {
1407                 nvkm_error(subdev, "intr %08x\n", stat);
1408                 nvkm_wr32(device, 0x400100, stat);
1409         }
1410
1411         nvkm_wr32(device, 0x400500, 0x00010001);
1412         nvkm_fifo_chan_put(device->fifo, flags, &chan);
1413 }
1414
1415 static void
1416 gf100_gr_init_fw(struct nvkm_falcon *falcon,
1417                  struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
1418 {
1419         nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0);
1420         nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false);
1421 }
1422
1423 static void
1424 gf100_gr_init_csdata(struct gf100_gr *gr,
1425                      const struct gf100_gr_pack *pack,
1426                      u32 falcon, u32 starstar, u32 base)
1427 {
1428         struct nvkm_device *device = gr->base.engine.subdev.device;
1429         const struct gf100_gr_pack *iter;
1430         const struct gf100_gr_init *init;
1431         u32 addr = ~0, prev = ~0, xfer = 0;
1432         u32 star, temp;
1433
1434         nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);
1435         star = nvkm_rd32(device, falcon + 0x01c4);
1436         temp = nvkm_rd32(device, falcon + 0x01c4);
1437         if (temp > star)
1438                 star = temp;
1439         nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);
1440
1441         pack_for_each_init(init, iter, pack) {
1442                 u32 head = init->addr - base;
1443                 u32 tail = head + init->count * init->pitch;
1444                 while (head < tail) {
1445                         if (head != prev + 4 || xfer >= 32) {
1446                                 if (xfer) {
1447                                         u32 data = ((--xfer << 26) | addr);
1448                                         nvkm_wr32(device, falcon + 0x01c4, data);
1449                                         star += 4;
1450                                 }
1451                                 addr = head;
1452                                 xfer = 0;
1453                         }
1454                         prev = head;
1455                         xfer = xfer + 1;
1456                         head = head + init->pitch;
1457                 }
1458         }
1459
1460         nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);
1461         nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);
1462         nvkm_wr32(device, falcon + 0x01c4, star + 4);
1463 }
1464
1465 /* Initialize context from an external (secure or not) firmware */
1466 static int
1467 gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
1468 {
1469         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1470         struct nvkm_device *device = subdev->device;
1471         struct nvkm_secboot *sb = device->secboot;
1472         u32 secboot_mask = 0;
1473
1474         /* load fuc microcode */
1475         nvkm_mc_unk260(device, 0);
1476
1477         /* securely-managed falcons must be reset using secure boot */
1478         if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
1479                 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_FECS);
1480         else
1481                 gf100_gr_init_fw(gr->fecs, &gr->fuc409c, &gr->fuc409d);
1482
1483         if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
1484                 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_GPCCS);
1485         else
1486                 gf100_gr_init_fw(gr->gpccs, &gr->fuc41ac, &gr->fuc41ad);
1487
1488         if (secboot_mask != 0) {
1489                 int ret = nvkm_secboot_reset(sb, secboot_mask);
1490                 if (ret)
1491                         return ret;
1492         }
1493
1494         nvkm_mc_unk260(device, 1);
1495
1496         /* start both of them running */
1497         nvkm_wr32(device, 0x409840, 0xffffffff);
1498         nvkm_wr32(device, 0x41a10c, 0x00000000);
1499         nvkm_wr32(device, 0x40910c, 0x00000000);
1500
1501         nvkm_falcon_start(gr->gpccs);
1502         nvkm_falcon_start(gr->fecs);
1503
1504         if (nvkm_msec(device, 2000,
1505                 if (nvkm_rd32(device, 0x409800) & 0x00000001)
1506                         break;
1507         ) < 0)
1508                 return -EBUSY;
1509
1510         nvkm_wr32(device, 0x409840, 0xffffffff);
1511         nvkm_wr32(device, 0x409500, 0x7fffffff);
1512         nvkm_wr32(device, 0x409504, 0x00000021);
1513
1514         nvkm_wr32(device, 0x409840, 0xffffffff);
1515         nvkm_wr32(device, 0x409500, 0x00000000);
1516         nvkm_wr32(device, 0x409504, 0x00000010);
1517         if (nvkm_msec(device, 2000,
1518                 if ((gr->size = nvkm_rd32(device, 0x409800)))
1519                         break;
1520         ) < 0)
1521                 return -EBUSY;
1522
1523         nvkm_wr32(device, 0x409840, 0xffffffff);
1524         nvkm_wr32(device, 0x409500, 0x00000000);
1525         nvkm_wr32(device, 0x409504, 0x00000016);
1526         if (nvkm_msec(device, 2000,
1527                 if (nvkm_rd32(device, 0x409800))
1528                         break;
1529         ) < 0)
1530                 return -EBUSY;
1531
1532         nvkm_wr32(device, 0x409840, 0xffffffff);
1533         nvkm_wr32(device, 0x409500, 0x00000000);
1534         nvkm_wr32(device, 0x409504, 0x00000025);
1535         if (nvkm_msec(device, 2000,
1536                 if (nvkm_rd32(device, 0x409800))
1537                         break;
1538         ) < 0)
1539                 return -EBUSY;
1540
1541         if (device->chipset >= 0xe0) {
1542                 nvkm_wr32(device, 0x409800, 0x00000000);
1543                 nvkm_wr32(device, 0x409500, 0x00000001);
1544                 nvkm_wr32(device, 0x409504, 0x00000030);
1545                 if (nvkm_msec(device, 2000,
1546                         if (nvkm_rd32(device, 0x409800))
1547                                 break;
1548                 ) < 0)
1549                         return -EBUSY;
1550
1551                 nvkm_wr32(device, 0x409810, 0xb00095c8);
1552                 nvkm_wr32(device, 0x409800, 0x00000000);
1553                 nvkm_wr32(device, 0x409500, 0x00000001);
1554                 nvkm_wr32(device, 0x409504, 0x00000031);
1555                 if (nvkm_msec(device, 2000,
1556                         if (nvkm_rd32(device, 0x409800))
1557                                 break;
1558                 ) < 0)
1559                         return -EBUSY;
1560
1561                 nvkm_wr32(device, 0x409810, 0x00080420);
1562                 nvkm_wr32(device, 0x409800, 0x00000000);
1563                 nvkm_wr32(device, 0x409500, 0x00000001);
1564                 nvkm_wr32(device, 0x409504, 0x00000032);
1565                 if (nvkm_msec(device, 2000,
1566                         if (nvkm_rd32(device, 0x409800))
1567                                 break;
1568                 ) < 0)
1569                         return -EBUSY;
1570
1571                 nvkm_wr32(device, 0x409614, 0x00000070);
1572                 nvkm_wr32(device, 0x409614, 0x00000770);
1573                 nvkm_wr32(device, 0x40802c, 0x00000001);
1574         }
1575
1576         if (gr->data == NULL) {
1577                 int ret = gf100_grctx_generate(gr);
1578                 if (ret) {
1579                         nvkm_error(subdev, "failed to construct context\n");
1580                         return ret;
1581                 }
1582         }
1583
1584         return 0;
1585 }
1586
1587 static int
1588 gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
1589 {
1590         const struct gf100_grctx_func *grctx = gr->func->grctx;
1591         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1592         struct nvkm_device *device = subdev->device;
1593
1594         if (!gr->func->fecs.ucode) {
1595                 return -ENOSYS;
1596         }
1597
1598         /* load HUB microcode */
1599         nvkm_mc_unk260(device, 0);
1600         nvkm_falcon_load_dmem(gr->fecs, gr->func->fecs.ucode->data.data, 0x0,
1601                               gr->func->fecs.ucode->data.size, 0);
1602         nvkm_falcon_load_imem(gr->fecs, gr->func->fecs.ucode->code.data, 0x0,
1603                               gr->func->fecs.ucode->code.size, 0, 0, false);
1604
1605         /* load GPC microcode */
1606         nvkm_falcon_load_dmem(gr->gpccs, gr->func->gpccs.ucode->data.data, 0x0,
1607                               gr->func->gpccs.ucode->data.size, 0);
1608         nvkm_falcon_load_imem(gr->gpccs, gr->func->gpccs.ucode->code.data, 0x0,
1609                               gr->func->gpccs.ucode->code.size, 0, 0, false);
1610         nvkm_mc_unk260(device, 1);
1611
1612         /* load register lists */
1613         gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000);
1614         gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000);
1615         gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800);
1616         gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00);
1617
1618         /* start HUB ucode running, it'll init the GPCs */
1619         nvkm_wr32(device, 0x40910c, 0x00000000);
1620         nvkm_wr32(device, 0x409100, 0x00000002);
1621         if (nvkm_msec(device, 2000,
1622                 if (nvkm_rd32(device, 0x409800) & 0x80000000)
1623                         break;
1624         ) < 0) {
1625                 gf100_gr_ctxctl_debug(gr);
1626                 return -EBUSY;
1627         }
1628
1629         gr->size = nvkm_rd32(device, 0x409804);
1630         if (gr->data == NULL) {
1631                 int ret = gf100_grctx_generate(gr);
1632                 if (ret) {
1633                         nvkm_error(subdev, "failed to construct context\n");
1634                         return ret;
1635                 }
1636         }
1637
1638         return 0;
1639 }
1640
1641 int
1642 gf100_gr_init_ctxctl(struct gf100_gr *gr)
1643 {
1644         int ret;
1645
1646         if (gr->firmware)
1647                 ret = gf100_gr_init_ctxctl_ext(gr);
1648         else
1649                 ret = gf100_gr_init_ctxctl_int(gr);
1650
1651         return ret;
1652 }
1653
1654 static int
1655 gf100_gr_oneinit(struct nvkm_gr *base)
1656 {
1657         struct gf100_gr *gr = gf100_gr(base);
1658         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1659         struct nvkm_device *device = subdev->device;
1660         int i, j;
1661         int ret;
1662
1663         ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs);
1664         if (ret)
1665                 return ret;
1666
1667         ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs);
1668         if (ret)
1669                 return ret;
1670
1671         nvkm_pmu_pgob(device->pmu, false);
1672
1673         gr->rop_nr = gr->func->rops(gr);
1674         gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
1675         for (i = 0; i < gr->gpc_nr; i++) {
1676                 gr->tpc_nr[i]  = nvkm_rd32(device, GPC_UNIT(i, 0x2608));
1677                 gr->tpc_total += gr->tpc_nr[i];
1678                 gr->ppc_nr[i]  = gr->func->ppc_nr;
1679                 for (j = 0; j < gr->ppc_nr[i]; j++) {
1680                         u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
1681                         if (mask)
1682                                 gr->ppc_mask[i] |= (1 << j);
1683                         gr->ppc_tpc_nr[i][j] = hweight8(mask);
1684                 }
1685         }
1686
1687         /*XXX: these need figuring out... though it might not even matter */
1688         switch (device->chipset) {
1689         case 0xc0:
1690                 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
1691                         gr->screen_tile_row_offset = 0x07;
1692                 } else
1693                 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
1694                         gr->screen_tile_row_offset = 0x05;
1695                 } else
1696                 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
1697                         gr->screen_tile_row_offset = 0x06;
1698                 }
1699                 break;
1700         case 0xc3: /* 450, 4/0/0/0, 2 */
1701                 gr->screen_tile_row_offset = 0x03;
1702                 break;
1703         case 0xc4: /* 460, 3/4/0/0, 4 */
1704                 gr->screen_tile_row_offset = 0x01;
1705                 break;
1706         case 0xc1: /* 2/0/0/0, 1 */
1707                 gr->screen_tile_row_offset = 0x01;
1708                 break;
1709         case 0xc8: /* 4/4/3/4, 5 */
1710                 gr->screen_tile_row_offset = 0x06;
1711                 break;
1712         case 0xce: /* 4/4/0/0, 4 */
1713                 gr->screen_tile_row_offset = 0x03;
1714                 break;
1715         case 0xcf: /* 4/0/0/0, 3 */
1716                 gr->screen_tile_row_offset = 0x03;
1717                 break;
1718         case 0xd7:
1719         case 0xd9: /* 1/0/0/0, 1 */
1720         case 0xea: /* gk20a */
1721         case 0x12b: /* gm20b */
1722                 gr->screen_tile_row_offset = 0x01;
1723                 break;
1724         }
1725
1726         return 0;
1727 }
1728
1729 static int
1730 gf100_gr_init_(struct nvkm_gr *base)
1731 {
1732         struct gf100_gr *gr = gf100_gr(base);
1733         struct nvkm_subdev *subdev = &base->engine.subdev;
1734         u32 ret;
1735
1736         nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
1737
1738         ret = nvkm_falcon_get(gr->fecs, subdev);
1739         if (ret)
1740                 return ret;
1741
1742         ret = nvkm_falcon_get(gr->gpccs, subdev);
1743         if (ret)
1744                 return ret;
1745
1746         return gr->func->init(gr);
1747 }
1748
1749 static int
1750 gf100_gr_fini_(struct nvkm_gr *base, bool suspend)
1751 {
1752         struct gf100_gr *gr = gf100_gr(base);
1753         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1754         nvkm_falcon_put(gr->gpccs, subdev);
1755         nvkm_falcon_put(gr->fecs, subdev);
1756         return 0;
1757 }
1758
1759 void
1760 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
1761 {
1762         kfree(fuc->data);
1763         fuc->data = NULL;
1764 }
1765
1766 static void
1767 gf100_gr_dtor_init(struct gf100_gr_pack *pack)
1768 {
1769         vfree(pack);
1770 }
1771
1772 void *
1773 gf100_gr_dtor(struct nvkm_gr *base)
1774 {
1775         struct gf100_gr *gr = gf100_gr(base);
1776
1777         if (gr->func->dtor)
1778                 gr->func->dtor(gr);
1779         kfree(gr->data);
1780
1781         nvkm_falcon_del(&gr->gpccs);
1782         nvkm_falcon_del(&gr->fecs);
1783
1784         gf100_gr_dtor_fw(&gr->fuc409c);
1785         gf100_gr_dtor_fw(&gr->fuc409d);
1786         gf100_gr_dtor_fw(&gr->fuc41ac);
1787         gf100_gr_dtor_fw(&gr->fuc41ad);
1788
1789         gf100_gr_dtor_init(gr->fuc_bundle);
1790         gf100_gr_dtor_init(gr->fuc_method);
1791         gf100_gr_dtor_init(gr->fuc_sw_ctx);
1792         gf100_gr_dtor_init(gr->fuc_sw_nonctx);
1793
1794         return gr;
1795 }
1796
1797 static const struct nvkm_gr_func
1798 gf100_gr_ = {
1799         .dtor = gf100_gr_dtor,
1800         .oneinit = gf100_gr_oneinit,
1801         .init = gf100_gr_init_,
1802         .fini = gf100_gr_fini_,
1803         .intr = gf100_gr_intr,
1804         .units = gf100_gr_units,
1805         .chan_new = gf100_gr_chan_new,
1806         .object_get = gf100_gr_object_get,
1807         .chsw_load = gf100_gr_chsw_load,
1808 };
1809
1810 int
1811 gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname,
1812                         struct gf100_gr_fuc *fuc, int ret)
1813 {
1814         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1815         struct nvkm_device *device = subdev->device;
1816         const struct firmware *fw;
1817         char f[32];
1818
1819         /* see if this firmware has a legacy path */
1820         if (!strcmp(fwname, "fecs_inst"))
1821                 fwname = "fuc409c";
1822         else if (!strcmp(fwname, "fecs_data"))
1823                 fwname = "fuc409d";
1824         else if (!strcmp(fwname, "gpccs_inst"))
1825                 fwname = "fuc41ac";
1826         else if (!strcmp(fwname, "gpccs_data"))
1827                 fwname = "fuc41ad";
1828         else {
1829                 /* nope, let's just return the error we got */
1830                 nvkm_error(subdev, "failed to load %s\n", fwname);
1831                 return ret;
1832         }
1833
1834         /* yes, try to load from the legacy path */
1835         nvkm_debug(subdev, "%s: falling back to legacy path\n", fwname);
1836
1837         snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
1838         ret = request_firmware(&fw, f, device->dev);
1839         if (ret) {
1840                 snprintf(f, sizeof(f), "nouveau/%s", fwname);
1841                 ret = request_firmware(&fw, f, device->dev);
1842                 if (ret) {
1843                         nvkm_error(subdev, "failed to load %s\n", fwname);
1844                         return ret;
1845                 }
1846         }
1847
1848         fuc->size = fw->size;
1849         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1850         release_firmware(fw);
1851         return (fuc->data != NULL) ? 0 : -ENOMEM;
1852 }
1853
1854 int
1855 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
1856                  struct gf100_gr_fuc *fuc)
1857 {
1858         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1859         struct nvkm_device *device = subdev->device;
1860         const struct firmware *fw;
1861         int ret;
1862
1863         ret = nvkm_firmware_get(device, fwname, &fw);
1864         if (ret) {
1865                 ret = gf100_gr_ctor_fw_legacy(gr, fwname, fuc, ret);
1866                 if (ret)
1867                         return -ENODEV;
1868                 return 0;
1869         }
1870
1871         fuc->size = fw->size;
1872         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1873         nvkm_firmware_put(fw);
1874         return (fuc->data != NULL) ? 0 : -ENOMEM;
1875 }
1876
1877 int
1878 gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device,
1879               int index, struct gf100_gr *gr)
1880 {
1881         gr->func = func;
1882         gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW",
1883                                     func->fecs.ucode == NULL);
1884
1885         return nvkm_gr_ctor(&gf100_gr_, device, index,
1886                             gr->firmware || func->fecs.ucode != NULL,
1887                             &gr->base);
1888 }
1889
1890 int
1891 gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
1892               int index, struct nvkm_gr **pgr)
1893 {
1894         struct gf100_gr *gr;
1895         int ret;
1896
1897         if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
1898                 return -ENOMEM;
1899         *pgr = &gr->base;
1900
1901         ret = gf100_gr_ctor(func, device, index, gr);
1902         if (ret)
1903                 return ret;
1904
1905         if (gr->firmware) {
1906                 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
1907                     gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
1908                     gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
1909                     gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
1910                         return -ENODEV;
1911         }
1912
1913         return 0;
1914 }
1915
1916 void
1917 gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
1918 {
1919         struct nvkm_device *device = gr->base.engine.subdev.device;
1920         struct nvkm_fb *fb = device->fb;
1921
1922         nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001);
1923         nvkm_wr32(device, 0x4188a4, 0x00000000);
1924         nvkm_wr32(device, 0x418888, 0x00000000);
1925         nvkm_wr32(device, 0x41888c, 0x00000000);
1926         nvkm_wr32(device, 0x418890, 0x00000000);
1927         nvkm_wr32(device, 0x418894, 0x00000000);
1928         nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8);
1929         nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8);
1930 }
1931
1932 int
1933 gf100_gr_init(struct gf100_gr *gr)
1934 {
1935         struct nvkm_device *device = gr->base.engine.subdev.device;
1936         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
1937         u32 data[TPC_MAX / 8] = {};
1938         u8  tpcnr[GPC_MAX];
1939         int gpc, tpc, rop;
1940         int i;
1941
1942         gr->func->init_gpc_mmu(gr);
1943
1944         gf100_gr_mmio(gr, gr->func->mmio);
1945
1946         nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);
1947
1948         memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
1949         for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
1950                 do {
1951                         gpc = (gpc + 1) % gr->gpc_nr;
1952                 } while (!tpcnr[gpc]);
1953                 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
1954
1955                 data[i / 8] |= tpc << ((i % 8) * 4);
1956         }
1957
1958         nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
1959         nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
1960         nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
1961         nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
1962
1963         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1964                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
1965                           gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
1966                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
1967                                                          gr->tpc_total);
1968                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
1969         }
1970
1971         if (device->chipset != 0xd7)
1972                 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
1973         else
1974                 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
1975
1976         nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
1977
1978         nvkm_wr32(device, 0x400500, 0x00010001);
1979
1980         nvkm_wr32(device, 0x400100, 0xffffffff);
1981         nvkm_wr32(device, 0x40013c, 0xffffffff);
1982
1983         nvkm_wr32(device, 0x409c24, 0x000f0000);
1984         nvkm_wr32(device, 0x404000, 0xc0000000);
1985         nvkm_wr32(device, 0x404600, 0xc0000000);
1986         nvkm_wr32(device, 0x408030, 0xc0000000);
1987         nvkm_wr32(device, 0x40601c, 0xc0000000);
1988         nvkm_wr32(device, 0x404490, 0xc0000000);
1989         nvkm_wr32(device, 0x406018, 0xc0000000);
1990         nvkm_wr32(device, 0x405840, 0xc0000000);
1991         nvkm_wr32(device, 0x405844, 0x00ffffff);
1992         nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
1993         nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
1994
1995         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1996                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1997                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1998                 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1999                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
2000                 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
2001                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
2002                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
2003                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
2004                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
2005                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
2006                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
2007                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
2008                 }
2009                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
2010                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
2011         }
2012
2013         for (rop = 0; rop < gr->rop_nr; rop++) {
2014                 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
2015                 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
2016                 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
2017                 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
2018         }
2019
2020         nvkm_wr32(device, 0x400108, 0xffffffff);
2021         nvkm_wr32(device, 0x400138, 0xffffffff);
2022         nvkm_wr32(device, 0x400118, 0xffffffff);
2023         nvkm_wr32(device, 0x400130, 0xffffffff);
2024         nvkm_wr32(device, 0x40011c, 0xffffffff);
2025         nvkm_wr32(device, 0x400134, 0xffffffff);
2026
2027         nvkm_wr32(device, 0x400054, 0x34ce3464);
2028
2029         gf100_gr_zbc_init(gr);
2030
2031         return gf100_gr_init_ctxctl(gr);
2032 }
2033
2034 #include "fuc/hubgf100.fuc3.h"
2035
2036 struct gf100_gr_ucode
2037 gf100_gr_fecs_ucode = {
2038         .code.data = gf100_grhub_code,
2039         .code.size = sizeof(gf100_grhub_code),
2040         .data.data = gf100_grhub_data,
2041         .data.size = sizeof(gf100_grhub_data),
2042 };
2043
2044 #include "fuc/gpcgf100.fuc3.h"
2045
2046 struct gf100_gr_ucode
2047 gf100_gr_gpccs_ucode = {
2048         .code.data = gf100_grgpc_code,
2049         .code.size = sizeof(gf100_grgpc_code),
2050         .data.data = gf100_grgpc_data,
2051         .data.size = sizeof(gf100_grgpc_data),
2052 };
2053
2054 static const struct gf100_gr_func
2055 gf100_gr = {
2056         .init = gf100_gr_init,
2057         .init_gpc_mmu = gf100_gr_init_gpc_mmu,
2058         .mmio = gf100_gr_pack_mmio,
2059         .fecs.ucode = &gf100_gr_fecs_ucode,
2060         .gpccs.ucode = &gf100_gr_gpccs_ucode,
2061         .rops = gf100_gr_rops,
2062         .grctx = &gf100_grctx,
2063         .sclass = {
2064                 { -1, -1, FERMI_TWOD_A },
2065                 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
2066                 { -1, -1, FERMI_A, &gf100_fermi },
2067                 { -1, -1, FERMI_COMPUTE_A },
2068                 {}
2069         }
2070 };
2071
2072 int
2073 gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
2074 {
2075         return gf100_gr_new_(&gf100_gr, device, index, pgr);
2076 }