2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
30 #include <linux/dma-mapping.h>
31 #include <drm/ttm/ttm_tt.h>
33 #include "nouveau_drv.h"
34 #include "nouveau_chan.h"
35 #include "nouveau_fence.h"
37 #include "nouveau_bo.h"
38 #include "nouveau_ttm.h"
39 #include "nouveau_gem.h"
40 #include "nouveau_mem.h"
41 #include "nouveau_vmm.h"
43 #include <nvif/class.h>
44 #include <nvif/if500b.h>
45 #include <nvif/if900b.h>
47 static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
48 struct ttm_resource *reg);
49 static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
52 * NV10-NV40 tiling helpers
56 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
57 u32 addr, u32 size, u32 pitch, u32 flags)
59 struct nouveau_drm *drm = nouveau_drm(dev);
60 int i = reg - drm->tile.reg;
61 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
62 struct nvkm_fb_tile *tile = &fb->tile.region[i];
64 nouveau_fence_unref(®->fence);
67 nvkm_fb_tile_fini(fb, i, tile);
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
72 nvkm_fb_tile_prog(fb, i, tile);
75 static struct nouveau_drm_tile *
76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
81 spin_lock(&drm->tile.lock);
84 (!tile->fence || nouveau_fence_done(tile->fence)))
89 spin_unlock(&drm->tile.lock);
94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct dma_fence *fence)
97 struct nouveau_drm *drm = nouveau_drm(dev);
100 spin_lock(&drm->tile.lock);
101 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
103 spin_unlock(&drm->tile.lock);
107 static struct nouveau_drm_tile *
108 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
109 u32 size, u32 pitch, u32 zeta)
111 struct nouveau_drm *drm = nouveau_drm(dev);
112 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
113 struct nouveau_drm_tile *tile, *found = NULL;
116 for (i = 0; i < fb->tile.regions; i++) {
117 tile = nv10_bo_get_tile_region(dev, i);
119 if (pitch && !found) {
123 } else if (tile && fb->tile.region[i].pitch) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
128 nv10_bo_put_tile_region(dev, tile, NULL);
132 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
137 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
139 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
140 struct drm_device *dev = drm->dev;
141 struct nouveau_bo *nvbo = nouveau_bo(bo);
143 WARN_ON(nvbo->bo.pin_count > 0);
144 nouveau_bo_del_io_reserve_lru(bo);
145 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
148 * If nouveau_bo_new() allocated this buffer, the GEM object was never
149 * initialized, so don't attempt to release it.
152 drm_gem_object_release(&bo->base);
154 dma_resv_fini(&bo->base._resv);
160 roundup_64(u64 x, u32 y)
168 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
170 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
171 struct nvif_device *device = &drm->client.device;
173 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
175 if (device->info.chipset >= 0x40) {
177 *size = roundup_64(*size, 64 * nvbo->mode);
179 } else if (device->info.chipset >= 0x30) {
181 *size = roundup_64(*size, 64 * nvbo->mode);
183 } else if (device->info.chipset >= 0x20) {
185 *size = roundup_64(*size, 64 * nvbo->mode);
187 } else if (device->info.chipset >= 0x10) {
189 *size = roundup_64(*size, 32 * nvbo->mode);
193 *size = roundup_64(*size, (1 << nvbo->page));
194 *align = max((1 << nvbo->page), *align);
197 *size = roundup_64(*size, PAGE_SIZE);
201 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
202 u32 tile_mode, u32 tile_flags, bool internal)
204 struct nouveau_drm *drm = cli->drm;
205 struct nouveau_bo *nvbo;
206 struct nvif_mmu *mmu = &cli->mmu;
207 struct nvif_vmm *vmm = &nouveau_cli_vmm(cli)->vmm;
211 NV_WARN(drm, "skipped size %016llx\n", *size);
212 return ERR_PTR(-EINVAL);
215 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
217 return ERR_PTR(-ENOMEM);
219 INIT_LIST_HEAD(&nvbo->head);
220 INIT_LIST_HEAD(&nvbo->entry);
221 INIT_LIST_HEAD(&nvbo->vma_list);
222 nvbo->bo.bdev = &drm->ttm.bdev;
224 /* This is confusing, and doesn't actually mean we want an uncached
225 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
226 * into in nouveau_gem_new().
228 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
229 /* Determine if we can get a cache-coherent map, forcing
230 * uncached mapping if we can't.
232 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
233 nvbo->force_coherent = true;
236 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
237 if (!nouveau_cli_uvmm(cli) || internal) {
238 /* for BO noVM allocs, don't assign kinds */
239 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
240 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
241 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
243 return ERR_PTR(-EINVAL);
246 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
247 } else if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
248 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
249 nvbo->comp = (tile_flags & 0x00030000) >> 16;
250 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
252 return ERR_PTR(-EINVAL);
255 nvbo->zeta = (tile_flags & 0x00000007);
257 nvbo->mode = tile_mode;
259 /* Determine the desirable target GPU page size for the buffer. */
260 for (i = 0; i < vmm->page_nr; i++) {
261 /* Because we cannot currently allow VMM maps to fail
262 * during buffer migration, we need to determine page
263 * size for the buffer up-front, and pre-allocate its
266 * Skip page sizes that can't support needed domains.
268 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
269 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
271 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
272 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
275 /* Select this page size if it's the first that supports
276 * the potential memory domains, or when it's compatible
277 * with the requested compression settings.
279 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
282 /* Stop once the buffer is larger than the current page size. */
283 if (*size >= 1ULL << vmm->page[i].shift)
287 if (WARN_ON(pi < 0)) {
289 return ERR_PTR(-EINVAL);
292 /* Disable compression if suitable settings couldn't be found. */
293 if (nvbo->comp && !vmm->page[pi].comp) {
294 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
295 nvbo->kind = mmu->kind[nvbo->kind];
298 nvbo->page = vmm->page[pi].shift;
300 /* reject other tile flags when in VM mode. */
302 return ERR_PTR(-EINVAL);
303 if (tile_flags & ~NOUVEAU_GEM_TILE_NONCONTIG)
304 return ERR_PTR(-EINVAL);
306 /* Determine the desirable target GPU page size for the buffer. */
307 for (i = 0; i < vmm->page_nr; i++) {
308 /* Because we cannot currently allow VMM maps to fail
309 * during buffer migration, we need to determine page
310 * size for the buffer up-front, and pre-allocate its
313 * Skip page sizes that can't support needed domains.
315 if ((domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
317 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
318 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
323 /* Stop once the buffer is larger than the current page size. */
324 if (*size >= 1ULL << vmm->page[i].shift)
327 if (WARN_ON(pi < 0)) {
329 return ERR_PTR(-EINVAL);
331 nvbo->page = vmm->page[pi].shift;
334 nouveau_bo_fixup_align(nvbo, align, size);
340 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
341 struct sg_table *sg, struct dma_resv *robj)
343 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
345 struct ttm_operation_ctx ctx = {
346 .interruptible = false,
347 .no_wait_gpu = false,
351 nouveau_bo_placement_set(nvbo, domain, 0);
352 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
354 ret = ttm_bo_init_reserved(nvbo->bo.bdev, &nvbo->bo, type,
355 &nvbo->placement, align >> PAGE_SHIFT, &ctx,
356 sg, robj, nouveau_bo_del_ttm);
358 /* ttm will call nouveau_bo_del_ttm if it fails.. */
363 ttm_bo_unreserve(&nvbo->bo);
369 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
370 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
371 struct sg_table *sg, struct dma_resv *robj,
372 struct nouveau_bo **pnvbo)
374 struct nouveau_bo *nvbo;
377 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
380 return PTR_ERR(nvbo);
382 nvbo->bo.base.size = size;
383 dma_resv_init(&nvbo->bo.base._resv);
384 drm_vma_node_reset(&nvbo->bo.base.vma_node);
386 /* This must be called before ttm_bo_init_reserved(). Subsequent
387 * bo_move() callbacks might already iterate the GEMs GPUVA list.
389 drm_gem_gpuva_init(&nvbo->bo.base);
391 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
400 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
404 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
405 pl[*n].mem_type = TTM_PL_VRAM;
409 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
410 pl[*n].mem_type = TTM_PL_TT;
414 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
415 pl[*n].mem_type = TTM_PL_SYSTEM;
416 pl[(*n)++].flags = 0;
421 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
423 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
424 u64 vram_size = drm->client.device.info.ram_size;
425 unsigned i, fpfn, lpfn;
427 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
428 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
429 nvbo->bo.base.size < vram_size / 4) {
431 * Make sure that the color and depth buffers are handled
432 * by independent memory controller units. Up to a 9x
433 * speed up when alpha-blending and depth-test are enabled
437 fpfn = (vram_size / 2) >> PAGE_SHIFT;
441 lpfn = (vram_size / 2) >> PAGE_SHIFT;
443 for (i = 0; i < nvbo->placement.num_placement; ++i) {
444 nvbo->placements[i].fpfn = fpfn;
445 nvbo->placements[i].lpfn = lpfn;
447 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
448 nvbo->busy_placements[i].fpfn = fpfn;
449 nvbo->busy_placements[i].lpfn = lpfn;
455 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
458 struct ttm_placement *pl = &nvbo->placement;
460 pl->placement = nvbo->placements;
461 set_placement_list(nvbo->placements, &pl->num_placement, domain);
463 pl->busy_placement = nvbo->busy_placements;
464 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
467 set_placement_range(nvbo, domain);
471 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
473 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
474 struct ttm_buffer_object *bo = &nvbo->bo;
475 bool force = false, evict = false;
478 ret = ttm_bo_reserve(bo, false, false, NULL);
482 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
483 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
491 if (nvbo->bo.pin_count) {
494 switch (bo->resource->mem_type) {
496 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
499 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
506 NV_ERROR(drm, "bo %p pinned elsewhere: "
507 "0x%08x vs 0x%08x\n", bo,
508 bo->resource->mem_type, domain);
511 ttm_bo_pin(&nvbo->bo);
516 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
517 ret = nouveau_bo_validate(nvbo, false, false);
522 nouveau_bo_placement_set(nvbo, domain, 0);
523 ret = nouveau_bo_validate(nvbo, false, false);
527 ttm_bo_pin(&nvbo->bo);
529 switch (bo->resource->mem_type) {
531 drm->gem.vram_available -= bo->base.size;
534 drm->gem.gart_available -= bo->base.size;
542 nvbo->contig = false;
543 ttm_bo_unreserve(bo);
548 nouveau_bo_unpin(struct nouveau_bo *nvbo)
550 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
551 struct ttm_buffer_object *bo = &nvbo->bo;
554 ret = ttm_bo_reserve(bo, false, false, NULL);
558 ttm_bo_unpin(&nvbo->bo);
559 if (!nvbo->bo.pin_count) {
560 switch (bo->resource->mem_type) {
562 drm->gem.vram_available += bo->base.size;
565 drm->gem.gart_available += bo->base.size;
572 ttm_bo_unreserve(bo);
577 nouveau_bo_map(struct nouveau_bo *nvbo)
581 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
585 ret = ttm_bo_kmap(&nvbo->bo, 0, PFN_UP(nvbo->bo.base.size), &nvbo->kmap);
587 ttm_bo_unreserve(&nvbo->bo);
592 nouveau_bo_unmap(struct nouveau_bo *nvbo)
597 ttm_bo_kunmap(&nvbo->kmap);
601 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
603 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
604 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
607 if (!ttm_dma || !ttm_dma->dma_address)
609 if (!ttm_dma->pages) {
610 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
614 /* Don't waste time looping if the object is coherent */
615 if (nvbo->force_coherent)
619 while (i < ttm_dma->num_pages) {
620 struct page *p = ttm_dma->pages[i];
621 size_t num_pages = 1;
623 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
624 if (++p != ttm_dma->pages[j])
629 dma_sync_single_for_device(drm->dev->dev,
630 ttm_dma->dma_address[i],
631 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
637 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
639 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
640 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
643 if (!ttm_dma || !ttm_dma->dma_address)
645 if (!ttm_dma->pages) {
646 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
650 /* Don't waste time looping if the object is coherent */
651 if (nvbo->force_coherent)
655 while (i < ttm_dma->num_pages) {
656 struct page *p = ttm_dma->pages[i];
657 size_t num_pages = 1;
659 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
660 if (++p != ttm_dma->pages[j])
666 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
667 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
672 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
674 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
675 struct nouveau_bo *nvbo = nouveau_bo(bo);
677 mutex_lock(&drm->ttm.io_reserve_mutex);
678 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
679 mutex_unlock(&drm->ttm.io_reserve_mutex);
682 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
684 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
685 struct nouveau_bo *nvbo = nouveau_bo(bo);
687 mutex_lock(&drm->ttm.io_reserve_mutex);
688 list_del_init(&nvbo->io_reserve_lru);
689 mutex_unlock(&drm->ttm.io_reserve_mutex);
693 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
696 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
699 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
703 nouveau_bo_sync_for_device(nvbo);
709 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
712 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
717 iowrite16_native(val, (void __force __iomem *)mem);
723 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
726 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
731 return ioread32_native((void __force __iomem *)mem);
737 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
740 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
745 iowrite32_native(val, (void __force __iomem *)mem);
750 static struct ttm_tt *
751 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
753 #if IS_ENABLED(CONFIG_AGP)
754 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
756 if (drm->agp.bridge) {
757 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
761 return nouveau_sgdma_create_ttm(bo, page_flags);
765 nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
766 struct ttm_resource *reg)
768 #if IS_ENABLED(CONFIG_AGP)
769 struct nouveau_drm *drm = nouveau_bdev(bdev);
773 #if IS_ENABLED(CONFIG_AGP)
775 return ttm_agp_bind(ttm, reg);
777 return nouveau_sgdma_bind(bdev, ttm, reg);
781 nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
783 #if IS_ENABLED(CONFIG_AGP)
784 struct nouveau_drm *drm = nouveau_bdev(bdev);
786 if (drm->agp.bridge) {
791 nouveau_sgdma_unbind(bdev, ttm);
795 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
797 struct nouveau_bo *nvbo = nouveau_bo(bo);
799 switch (bo->resource->mem_type) {
801 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
802 NOUVEAU_GEM_DOMAIN_CPU);
805 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
809 *pl = nvbo->placement;
813 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
814 struct ttm_resource *reg)
816 struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
817 struct nouveau_mem *new_mem = nouveau_mem(reg);
818 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
821 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
822 old_mem->mem.size, &old_mem->vma[0]);
826 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
827 new_mem->mem.size, &old_mem->vma[1]);
831 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
835 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
838 nvif_vmm_put(vmm, &old_mem->vma[1]);
839 nvif_vmm_put(vmm, &old_mem->vma[0]);
845 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
846 struct ttm_operation_ctx *ctx,
847 struct ttm_resource *new_reg)
849 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
850 struct nouveau_channel *chan = drm->ttm.chan;
851 struct nouveau_cli *cli = (void *)chan->user.client;
852 struct nouveau_fence *fence;
855 /* create temporary vmas for the transfer and attach them to the
856 * old nvkm_mem node, these will get cleaned up after ttm has
857 * destroyed the ttm_resource
859 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
860 ret = nouveau_bo_move_prep(drm, bo, new_reg);
865 if (drm_drv_uses_atomic_modeset(drm->dev))
866 mutex_lock(&cli->mutex);
868 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
870 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
874 ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
878 ret = nouveau_fence_new(&fence);
882 ret = nouveau_fence_emit(fence, chan);
884 nouveau_fence_unref(&fence);
888 /* TODO: figure out a better solution here
890 * wait on the fence here explicitly as going through
891 * ttm_bo_move_accel_cleanup somehow doesn't seem to do it.
893 * Without this the operation can timeout and we'll fallback to a
894 * software copy, which might take several minutes to finish.
896 nouveau_fence_wait(fence, false, false);
897 ret = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false,
899 nouveau_fence_unref(&fence);
902 mutex_unlock(&cli->mutex);
907 nouveau_bo_move_init(struct nouveau_drm *drm)
909 static const struct _method_table {
913 int (*exec)(struct nouveau_channel *,
914 struct ttm_buffer_object *,
915 struct ttm_resource *, struct ttm_resource *);
916 int (*init)(struct nouveau_channel *, u32 handle);
918 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
919 { "GRCE", 0, 0xc7b5, nve0_bo_move_copy, nvc0_bo_move_init },
920 { "COPY", 4, 0xc6b5, nve0_bo_move_copy, nve0_bo_move_init },
921 { "GRCE", 0, 0xc6b5, nve0_bo_move_copy, nvc0_bo_move_init },
922 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
923 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
924 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
925 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
926 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
927 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
928 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
929 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
930 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
931 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
932 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
933 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
934 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
935 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
936 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
937 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
938 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
939 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
940 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
943 const struct _method_table *mthd = _methods;
944 const char *name = "CPU";
948 struct nouveau_channel *chan;
957 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
958 mthd->oclass | (mthd->engine << 16),
959 mthd->oclass, NULL, 0,
962 ret = mthd->init(chan, drm->ttm.copy.handle);
964 nvif_object_dtor(&drm->ttm.copy);
968 drm->ttm.move = mthd->exec;
969 drm->ttm.chan = chan;
973 } while ((++mthd)->exec);
975 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
978 static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
979 struct ttm_resource *new_reg)
981 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
982 struct nouveau_bo *nvbo = nouveau_bo(bo);
983 struct nouveau_vma *vma;
986 /* ttm can now (stupidly) pass the driver bos it didn't create... */
987 if (bo->destroy != nouveau_bo_del_ttm)
990 nouveau_bo_del_io_reserve_lru(bo);
992 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
993 mem->mem.page == nvbo->page) {
994 list_for_each_entry(vma, &nvbo->vma_list, head) {
995 nouveau_vma_map(vma, mem);
997 nouveau_uvmm_bo_map_all(nvbo, mem);
999 list_for_each_entry(vma, &nvbo->vma_list, head) {
1000 ret = dma_resv_wait_timeout(bo->base.resv,
1001 DMA_RESV_USAGE_BOOKKEEP,
1004 nouveau_vma_unmap(vma);
1006 nouveau_uvmm_bo_unmap_all(nvbo);
1010 nvbo->offset = (new_reg->start << PAGE_SHIFT);
1015 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1016 struct nouveau_drm_tile **new_tile)
1018 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1019 struct drm_device *dev = drm->dev;
1020 struct nouveau_bo *nvbo = nouveau_bo(bo);
1021 u64 offset = new_reg->start << PAGE_SHIFT;
1024 if (new_reg->mem_type != TTM_PL_VRAM)
1027 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1028 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
1029 nvbo->mode, nvbo->zeta);
1036 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1037 struct nouveau_drm_tile *new_tile,
1038 struct nouveau_drm_tile **old_tile)
1040 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1041 struct drm_device *dev = drm->dev;
1042 struct dma_fence *fence;
1045 ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE,
1048 dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE,
1049 false, MAX_SCHEDULE_TIMEOUT);
1051 nv10_bo_put_tile_region(dev, *old_tile, fence);
1052 *old_tile = new_tile;
1056 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1057 struct ttm_operation_ctx *ctx,
1058 struct ttm_resource *new_reg,
1059 struct ttm_place *hop)
1061 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1062 struct nouveau_bo *nvbo = nouveau_bo(bo);
1063 struct ttm_resource *old_reg = bo->resource;
1064 struct nouveau_drm_tile *new_tile = NULL;
1068 if (new_reg->mem_type == TTM_PL_TT) {
1069 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
1074 nouveau_bo_move_ntfy(bo, new_reg);
1075 ret = ttm_bo_wait_ctx(bo, ctx);
1079 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1080 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1086 if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
1088 ttm_bo_move_null(bo, new_reg);
1092 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1093 new_reg->mem_type == TTM_PL_TT) {
1094 ttm_bo_move_null(bo, new_reg);
1098 if (old_reg->mem_type == TTM_PL_TT &&
1099 new_reg->mem_type == TTM_PL_SYSTEM) {
1100 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1101 ttm_resource_free(bo, &bo->resource);
1102 ttm_bo_assign_mem(bo, new_reg);
1106 /* Hardware assisted copy. */
1107 if (drm->ttm.move) {
1108 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1109 new_reg->mem_type == TTM_PL_VRAM) ||
1110 (old_reg->mem_type == TTM_PL_VRAM &&
1111 new_reg->mem_type == TTM_PL_SYSTEM)) {
1114 hop->mem_type = TTM_PL_TT;
1118 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1124 /* Fallback to software copy. */
1125 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1129 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1131 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1133 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1137 nouveau_bo_move_ntfy(bo, bo->resource);
1143 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1144 struct ttm_resource *reg)
1146 struct nouveau_mem *mem = nouveau_mem(reg);
1148 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1149 switch (reg->mem_type) {
1152 nvif_object_unmap_handle(&mem->mem.object);
1155 nvif_object_unmap_handle(&mem->mem.object);
1164 nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1166 struct nouveau_drm *drm = nouveau_bdev(bdev);
1167 struct nvkm_device *device = nvxx_device(&drm->client.device);
1168 struct nouveau_mem *mem = nouveau_mem(reg);
1169 struct nvif_mmu *mmu = &drm->client.mmu;
1172 mutex_lock(&drm->ttm.io_reserve_mutex);
1174 switch (reg->mem_type) {
1180 #if IS_ENABLED(CONFIG_AGP)
1181 if (drm->agp.bridge) {
1182 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1184 reg->bus.is_iomem = !drm->agp.cma;
1185 reg->bus.caching = ttm_write_combined;
1188 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1194 fallthrough; /* tiled memory */
1196 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1197 device->func->resource_addr(device, 1);
1198 reg->bus.is_iomem = true;
1200 /* Some BARs do not support being ioremapped WC */
1201 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1202 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1203 reg->bus.caching = ttm_uncached;
1205 reg->bus.caching = ttm_write_combined;
1207 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1209 struct nv50_mem_map_v0 nv50;
1210 struct gf100_mem_map_v0 gf100;
1215 switch (mem->mem.object.oclass) {
1216 case NVIF_CLASS_MEM_NV50:
1217 args.nv50.version = 0;
1219 args.nv50.kind = mem->kind;
1220 args.nv50.comp = mem->comp;
1221 argc = sizeof(args.nv50);
1223 case NVIF_CLASS_MEM_GF100:
1224 args.gf100.version = 0;
1226 args.gf100.kind = mem->kind;
1227 argc = sizeof(args.gf100);
1234 ret = nvif_object_map_handle(&mem->mem.object,
1238 if (WARN_ON(ret == 0))
1243 reg->bus.offset = handle;
1252 if (ret == -ENOSPC) {
1253 struct nouveau_bo *nvbo;
1255 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1259 list_del_init(&nvbo->io_reserve_lru);
1260 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1262 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1267 mutex_unlock(&drm->ttm.io_reserve_mutex);
1272 nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1274 struct nouveau_drm *drm = nouveau_bdev(bdev);
1276 mutex_lock(&drm->ttm.io_reserve_mutex);
1277 nouveau_ttm_io_mem_free_locked(drm, reg);
1278 mutex_unlock(&drm->ttm.io_reserve_mutex);
1281 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1283 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1284 struct nouveau_bo *nvbo = nouveau_bo(bo);
1285 struct nvkm_device *device = nvxx_device(&drm->client.device);
1286 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1289 /* as long as the bo isn't in vram, and isn't tiled, we've got
1290 * nothing to do here.
1292 if (bo->resource->mem_type != TTM_PL_VRAM) {
1293 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1297 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1300 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1303 /* make sure bo is in mappable vram */
1304 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1305 bo->resource->start + PFN_UP(bo->resource->size) < mappable)
1308 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1309 nvbo->placements[i].fpfn = 0;
1310 nvbo->placements[i].lpfn = mappable;
1313 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1314 nvbo->busy_placements[i].fpfn = 0;
1315 nvbo->busy_placements[i].lpfn = mappable;
1318 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1321 ret = nouveau_bo_validate(nvbo, false, false);
1322 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1323 return VM_FAULT_NOPAGE;
1324 else if (unlikely(ret))
1325 return VM_FAULT_SIGBUS;
1327 ttm_bo_move_to_lru_tail_unlocked(bo);
1332 nouveau_ttm_tt_populate(struct ttm_device *bdev,
1333 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1335 struct ttm_tt *ttm_dma = (void *)ttm;
1336 struct nouveau_drm *drm;
1337 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1339 if (ttm_tt_is_populated(ttm))
1342 if (slave && ttm->sg) {
1343 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1348 drm = nouveau_bdev(bdev);
1350 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1354 nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1357 struct nouveau_drm *drm;
1358 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1363 nouveau_ttm_tt_unbind(bdev, ttm);
1365 drm = nouveau_bdev(bdev);
1367 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1371 nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1374 #if IS_ENABLED(CONFIG_AGP)
1375 struct nouveau_drm *drm = nouveau_bdev(bdev);
1376 if (drm->agp.bridge) {
1377 ttm_agp_destroy(ttm);
1381 nouveau_sgdma_destroy(bdev, ttm);
1385 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1387 struct dma_resv *resv = nvbo->bo.base.resv;
1392 dma_resv_add_fence(resv, &fence->base, exclusive ?
1393 DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ);
1397 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1399 nouveau_bo_move_ntfy(bo, NULL);
1402 struct ttm_device_funcs nouveau_bo_driver = {
1403 .ttm_tt_create = &nouveau_ttm_tt_create,
1404 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1405 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1406 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1407 .eviction_valuable = ttm_bo_eviction_valuable,
1408 .evict_flags = nouveau_bo_evict_flags,
1409 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1410 .move = nouveau_bo_move,
1411 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1412 .io_mem_free = &nouveau_ttm_io_mem_free,