4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00)
14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00)
15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11)
16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57)
21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00)
23 Copyright (C) 2013-2015 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
26 Permission is hereby granted, free of charge, to any person obtaining
27 a copy of this software and associated documentation files (the
28 "Software"), to deal in the Software without restriction, including
29 without limitation the rights to use, copy, modify, merge, publish,
30 distribute, sublicense, and/or sell copies of the Software, and to
31 permit persons to whom the Software is furnished to do so, subject to
32 the following conditions:
34 The above copyright notice and this permission notice (including the
35 next paragraph) shall be included in all copies or substantial
36 portions of the Software.
38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
86 PACK_3D_FRAME_INT = 0,
87 PACK_3D_H_ROW_INT = 1,
88 PACK_3D_V_ROW_INT = 2,
92 enum mdp5_scale_filter {
93 SCALE_FILTER_NEAREST = 0,
95 SCALE_FILTER_PCMN = 2,
105 enum mdp5_client_id {
132 enum mdp5_cursor_format {
133 CURSOR_FMT_ARGB8888 = 0,
134 CURSOR_FMT_ARGB1555 = 2,
135 CURSOR_FMT_ARGB4444 = 4,
138 enum mdp5_cursor_alpha {
139 CURSOR_ALPHA_CONST = 0,
140 CURSOR_ALPHA_PER_PIXEL = 2,
150 enum mdp5_data_format {
155 #define MDP5_IRQ_INTF0_WB_ROT_COMP 0x00000001
156 #define MDP5_IRQ_INTF1_WB_ROT_COMP 0x00000002
157 #define MDP5_IRQ_INTF2_WB_ROT_COMP 0x00000004
158 #define MDP5_IRQ_INTF3_WB_ROT_COMP 0x00000008
159 #define MDP5_IRQ_INTF0_WB_WFD 0x00000010
160 #define MDP5_IRQ_INTF1_WB_WFD 0x00000020
161 #define MDP5_IRQ_INTF2_WB_WFD 0x00000040
162 #define MDP5_IRQ_INTF3_WB_WFD 0x00000080
163 #define MDP5_IRQ_INTF0_PING_PONG_COMP 0x00000100
164 #define MDP5_IRQ_INTF1_PING_PONG_COMP 0x00000200
165 #define MDP5_IRQ_INTF2_PING_PONG_COMP 0x00000400
166 #define MDP5_IRQ_INTF3_PING_PONG_COMP 0x00000800
167 #define MDP5_IRQ_INTF0_PING_PONG_RD_PTR 0x00001000
168 #define MDP5_IRQ_INTF1_PING_PONG_RD_PTR 0x00002000
169 #define MDP5_IRQ_INTF2_PING_PONG_RD_PTR 0x00004000
170 #define MDP5_IRQ_INTF3_PING_PONG_RD_PTR 0x00008000
171 #define MDP5_IRQ_INTF0_PING_PONG_WR_PTR 0x00010000
172 #define MDP5_IRQ_INTF1_PING_PONG_WR_PTR 0x00020000
173 #define MDP5_IRQ_INTF2_PING_PONG_WR_PTR 0x00040000
174 #define MDP5_IRQ_INTF3_PING_PONG_WR_PTR 0x00080000
175 #define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF 0x00100000
176 #define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF 0x00200000
177 #define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF 0x00400000
178 #define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF 0x00800000
179 #define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
180 #define MDP5_IRQ_INTF0_VSYNC 0x02000000
181 #define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
182 #define MDP5_IRQ_INTF1_VSYNC 0x08000000
183 #define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
184 #define MDP5_IRQ_INTF2_VSYNC 0x20000000
185 #define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
186 #define MDP5_IRQ_INTF3_VSYNC 0x80000000
187 #define REG_MDP5_HW_VERSION 0x00000000
189 #define REG_MDP5_HW_INTR_STATUS 0x00000010
190 #define MDP5_HW_INTR_STATUS_INTR_MDP 0x00000001
191 #define MDP5_HW_INTR_STATUS_INTR_DSI0 0x00000010
192 #define MDP5_HW_INTR_STATUS_INTR_DSI1 0x00000020
193 #define MDP5_HW_INTR_STATUS_INTR_HDMI 0x00000100
194 #define MDP5_HW_INTR_STATUS_INTR_EDP 0x00001000
196 #define REG_MDP5_MDP_VERSION 0x00000100
197 #define MDP5_MDP_VERSION_MINOR__MASK 0x00ff0000
198 #define MDP5_MDP_VERSION_MINOR__SHIFT 16
199 static inline uint32_t MDP5_MDP_VERSION_MINOR(uint32_t val)
201 return ((val) << MDP5_MDP_VERSION_MINOR__SHIFT) & MDP5_MDP_VERSION_MINOR__MASK;
203 #define MDP5_MDP_VERSION_MAJOR__MASK 0xf0000000
204 #define MDP5_MDP_VERSION_MAJOR__SHIFT 28
205 static inline uint32_t MDP5_MDP_VERSION_MAJOR(uint32_t val)
207 return ((val) << MDP5_MDP_VERSION_MAJOR__SHIFT) & MDP5_MDP_VERSION_MAJOR__MASK;
210 #define REG_MDP5_DISP_INTF_SEL 0x00000104
211 #define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
212 #define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
213 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf val)
215 return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
217 #define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
218 #define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
219 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf val)
221 return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
223 #define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
224 #define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
225 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf val)
227 return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
229 #define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
230 #define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
231 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf val)
233 return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
236 #define REG_MDP5_INTR_EN 0x00000110
238 #define REG_MDP5_INTR_STATUS 0x00000114
240 #define REG_MDP5_INTR_CLEAR 0x00000118
242 #define REG_MDP5_HIST_INTR_EN 0x0000011c
244 #define REG_MDP5_HIST_INTR_STATUS 0x00000120
246 #define REG_MDP5_HIST_INTR_CLEAR 0x00000124
248 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000180 + 0x4*i0; }
250 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000180 + 0x4*i0; }
251 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
252 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
253 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id val)
255 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
257 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
258 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
259 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id val)
261 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
263 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
264 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
265 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id val)
267 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
270 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000230 + 0x4*i0; }
272 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000230 + 0x4*i0; }
273 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
274 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
275 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id val)
277 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
279 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
280 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
281 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id val)
283 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
285 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
286 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
287 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id val)
289 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
292 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
295 case IGC_VIG: return 0x00000300;
296 case IGC_RGB: return 0x00000310;
297 case IGC_DMA: return 0x00000320;
298 case IGC_DSPP: return 0x00000400;
299 default: return INVALID_IDX(idx);
302 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
304 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
306 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
307 #define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
308 #define MDP5_IGC_LUT_REG_VAL__SHIFT 0
309 static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
311 return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
313 #define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
314 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
315 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
316 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
318 static inline uint32_t __offset_CTL(uint32_t idx)
321 case 0: return (mdp5_cfg->ctl.base[0]);
322 case 1: return (mdp5_cfg->ctl.base[1]);
323 case 2: return (mdp5_cfg->ctl.base[2]);
324 case 3: return (mdp5_cfg->ctl.base[3]);
325 case 4: return (mdp5_cfg->ctl.base[4]);
326 default: return INVALID_IDX(idx);
329 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
331 static inline uint32_t __offset_LAYER(uint32_t idx)
334 case 0: return 0x00000000;
335 case 1: return 0x00000004;
336 case 2: return 0x00000008;
337 case 3: return 0x0000000c;
338 case 4: return 0x00000010;
339 case 5: return 0x00000024;
340 default: return INVALID_IDX(idx);
343 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
345 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
346 #define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
347 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
348 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)
350 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
352 #define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
353 #define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
354 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)
356 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
358 #define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
359 #define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
360 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)
362 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
364 #define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
365 #define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
366 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)
368 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
370 #define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
371 #define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
372 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)
374 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
376 #define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
377 #define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
378 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)
380 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
382 #define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
383 #define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
384 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)
386 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
388 #define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
389 #define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
390 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
392 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
394 #define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
395 #define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
396 #define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
397 #define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
398 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val)
400 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
402 #define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
403 #define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
404 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val)
406 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
409 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
410 #define MDP5_CTL_OP_MODE__MASK 0x0000000f
411 #define MDP5_CTL_OP_MODE__SHIFT 0
412 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
414 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
416 #define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
417 #define MDP5_CTL_OP_INTF_NUM__SHIFT 4
418 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
420 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
422 #define MDP5_CTL_OP_CMD_MODE 0x00020000
423 #define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
424 #define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
425 #define MDP5_CTL_OP_PACK_3D__SHIFT 20
426 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
428 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
431 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
432 #define MDP5_CTL_FLUSH_VIG0 0x00000001
433 #define MDP5_CTL_FLUSH_VIG1 0x00000002
434 #define MDP5_CTL_FLUSH_VIG2 0x00000004
435 #define MDP5_CTL_FLUSH_RGB0 0x00000008
436 #define MDP5_CTL_FLUSH_RGB1 0x00000010
437 #define MDP5_CTL_FLUSH_RGB2 0x00000020
438 #define MDP5_CTL_FLUSH_LM0 0x00000040
439 #define MDP5_CTL_FLUSH_LM1 0x00000080
440 #define MDP5_CTL_FLUSH_LM2 0x00000100
441 #define MDP5_CTL_FLUSH_LM3 0x00000200
442 #define MDP5_CTL_FLUSH_LM4 0x00000400
443 #define MDP5_CTL_FLUSH_DMA0 0x00000800
444 #define MDP5_CTL_FLUSH_DMA1 0x00001000
445 #define MDP5_CTL_FLUSH_DSPP0 0x00002000
446 #define MDP5_CTL_FLUSH_DSPP1 0x00004000
447 #define MDP5_CTL_FLUSH_DSPP2 0x00008000
448 #define MDP5_CTL_FLUSH_CTL 0x00020000
449 #define MDP5_CTL_FLUSH_VIG3 0x00040000
450 #define MDP5_CTL_FLUSH_RGB3 0x00080000
451 #define MDP5_CTL_FLUSH_LM5 0x00100000
452 #define MDP5_CTL_FLUSH_DSPP3 0x00200000
454 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
456 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
458 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
461 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
462 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
463 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
464 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
465 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
466 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
467 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
468 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
469 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
470 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
471 default: return INVALID_IDX(idx);
474 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
476 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
477 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
478 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
479 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
481 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
483 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
484 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
485 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
487 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
489 #define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
491 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
493 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
495 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
497 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
498 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
499 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
500 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
502 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
504 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
505 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
506 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
508 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
511 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
512 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
513 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
514 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
516 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
518 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
519 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
520 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
522 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
525 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
526 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
527 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
528 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
530 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
532 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
533 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
534 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
536 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
539 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
540 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
541 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
542 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
544 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
546 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
547 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
548 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
550 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
553 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
554 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
555 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
556 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
558 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
561 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
563 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
564 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
565 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
566 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
568 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
570 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
571 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
572 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
574 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
577 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
579 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
580 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
581 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
582 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
584 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
586 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
587 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
588 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
590 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
593 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
595 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
596 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
597 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
598 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
600 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
603 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
605 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
606 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
607 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
608 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
610 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
613 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
614 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
615 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
616 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
618 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
620 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
621 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
622 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
624 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
627 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
628 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
629 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
630 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
632 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
634 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
635 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
636 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
638 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
641 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
642 #define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
643 #define MDP5_PIPE_SRC_XY_Y__SHIFT 16
644 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
646 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
648 #define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
649 #define MDP5_PIPE_SRC_XY_X__SHIFT 0
650 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
652 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
655 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
656 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
657 #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
658 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
660 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
662 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
663 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
664 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
666 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
669 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
670 #define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
671 #define MDP5_PIPE_OUT_XY_Y__SHIFT 16
672 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
674 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
676 #define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
677 #define MDP5_PIPE_OUT_XY_X__SHIFT 0
678 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
680 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
683 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
685 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
687 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
689 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
691 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
692 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
693 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
694 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
696 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
698 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
699 #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
700 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
702 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
705 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
706 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
707 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
708 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
710 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
712 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
713 #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
714 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
716 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
719 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
721 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
722 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
723 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
724 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
726 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
728 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
729 #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
730 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
732 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
734 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
735 #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
736 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
738 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
740 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
741 #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
742 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
744 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
746 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
747 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
748 #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
749 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
751 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
753 #define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
754 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
755 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
756 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
758 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
760 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
761 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
762 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00180000
763 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19
764 static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val)
766 return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
768 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
769 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
770 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
772 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
775 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
776 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
777 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
778 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
780 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
782 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
783 #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
784 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
786 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
788 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
789 #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
790 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
792 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
794 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
795 #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
796 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
798 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
801 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
802 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
803 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
804 #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
805 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
807 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
809 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
810 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
811 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
812 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
813 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
814 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
815 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
817 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
819 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
821 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
823 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
825 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
827 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
829 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
831 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
833 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
835 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
837 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
839 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
840 #define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
841 #define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
842 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
844 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
846 #define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
847 #define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
848 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
850 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
853 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
854 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
855 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
856 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300
857 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT 8
858 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)
860 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK;
862 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK 0x00000c00
863 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT 10
864 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)
866 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK;
868 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK 0x00003000
869 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT 12
870 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)
872 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK;
874 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK 0x0000c000
875 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT 14
876 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)
878 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK;
880 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK 0x00030000
881 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT 16
882 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)
884 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK;
886 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK 0x000c0000
887 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT 18
888 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)
890 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK;
893 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
895 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
897 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
899 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
901 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
903 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
905 static inline uint32_t __offset_LM(uint32_t idx)
908 case 0: return (mdp5_cfg->lm.base[0]);
909 case 1: return (mdp5_cfg->lm.base[1]);
910 case 2: return (mdp5_cfg->lm.base[2]);
911 case 3: return (mdp5_cfg->lm.base[3]);
912 case 4: return (mdp5_cfg->lm.base[4]);
913 default: return INVALID_IDX(idx);
916 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
918 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
919 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
920 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
921 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
922 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
924 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
925 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
926 #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
927 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
929 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
931 #define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
932 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
933 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
935 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
938 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
940 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
942 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
944 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
945 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
946 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
947 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
949 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
951 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
952 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
953 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
954 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
955 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
956 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
957 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
959 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
961 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
962 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
963 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
964 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
966 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + 0x30*i1; }
968 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + 0x30*i1; }
970 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000002c + __offset_LM(i0) + 0x30*i1; }
972 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000030 + __offset_LM(i0) + 0x30*i1; }
974 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000034 + __offset_LM(i0) + 0x30*i1; }
976 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000038 + __offset_LM(i0) + 0x30*i1; }
978 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000003c + __offset_LM(i0) + 0x30*i1; }
980 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000040 + __offset_LM(i0) + 0x30*i1; }
982 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000044 + __offset_LM(i0) + 0x30*i1; }
984 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_LM(i0) + 0x30*i1; }
986 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
987 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
988 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
989 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
991 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
993 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
994 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
995 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
997 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1000 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1001 #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
1002 #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
1003 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1005 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1007 #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1008 #define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
1009 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1011 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1014 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1015 #define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1016 #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
1017 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1019 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1021 #define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1022 #define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
1023 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1025 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1028 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1029 #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1030 #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
1031 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1033 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1036 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1037 #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1038 #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
1039 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1041 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1044 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1046 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1047 #define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1048 #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
1049 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1051 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1053 #define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1054 #define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
1055 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1057 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1060 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1061 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1062 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1063 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
1064 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1066 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1068 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
1070 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1072 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1074 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1076 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1078 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1080 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1082 static inline uint32_t __offset_DSPP(uint32_t idx)
1085 case 0: return (mdp5_cfg->dspp.base[0]);
1086 case 1: return (mdp5_cfg->dspp.base[1]);
1087 case 2: return (mdp5_cfg->dspp.base[2]);
1088 case 3: return (mdp5_cfg->dspp.base[3]);
1089 default: return INVALID_IDX(idx);
1092 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1094 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1095 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1096 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1097 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
1098 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1100 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1102 #define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1103 #define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1104 #define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1105 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1106 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1107 #define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1108 #define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1109 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1111 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1113 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1115 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1117 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1119 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1121 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1123 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1125 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1127 static inline uint32_t __offset_INTF(uint32_t idx)
1130 case 0: return (mdp5_cfg->intf.base[0]);
1131 case 1: return (mdp5_cfg->intf.base[1]);
1132 case 2: return (mdp5_cfg->intf.base[2]);
1133 case 3: return (mdp5_cfg->intf.base[3]);
1134 case 4: return (mdp5_cfg->intf.base[4]);
1135 default: return INVALID_IDX(idx);
1138 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1140 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1142 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1144 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1145 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1146 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
1147 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1149 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1151 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1152 #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
1153 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1155 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1158 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1160 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1162 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1164 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1166 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1168 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1170 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1172 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1174 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1175 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1176 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
1177 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1179 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1181 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1183 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1184 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1185 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
1186 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1188 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1191 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1193 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1195 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1196 #define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1197 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
1198 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1200 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1202 #define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1203 #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
1204 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1206 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1209 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1210 #define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1211 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
1212 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1214 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1216 #define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1217 #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
1218 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1220 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1222 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1224 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1226 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1228 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1230 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1231 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1232 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1233 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1235 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1237 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1239 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1241 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1243 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1245 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1247 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1249 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1251 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1253 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1255 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1257 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1259 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1261 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1263 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1265 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1267 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1269 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1271 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1273 static inline uint32_t __offset_AD(uint32_t idx)
1276 case 0: return (mdp5_cfg->ad.base[0]);
1277 case 1: return (mdp5_cfg->ad.base[1]);
1278 default: return INVALID_IDX(idx);
1281 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1283 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1285 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1287 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1289 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1291 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1293 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1295 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1297 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1299 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1301 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1303 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1305 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1307 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1309 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1311 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1313 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1315 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1317 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1319 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1321 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1323 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1325 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1327 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1329 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1331 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1333 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1335 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1337 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1339 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1341 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1343 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1345 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1347 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1349 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1352 #endif /* MDP5_XML */