2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <drm/drm_mode.h>
22 #include "drm_crtc_helper.h"
23 #include "drm_flip_work.h"
28 struct drm_plane *plane;
29 struct drm_plane *planes[8];
35 /* which mixer/encoder we route output to: */
41 uint32_t width, height;
44 /* next cursor to scan-out: */
46 struct drm_gem_object *next_bo;
48 /* current cursor being scanned out: */
49 struct drm_gem_object *scanout_bo;
53 /* if there is a pending flip, these will be non-null: */
54 struct drm_pending_vblank_event *event;
55 struct msm_fence_cb pageflip_cb;
57 #define PENDING_CURSOR 0x1
58 #define PENDING_FLIP 0x2
61 /* the fb that we logically (from PoV of KMS API) hold a ref
62 * to. Which we may not yet be scanning out (we may still
63 * be scanning out previous in case of page_flip while waiting
64 * for gpu rendering to complete:
66 struct drm_framebuffer *fb;
68 /* the fb that we currently hold a scanout ref to: */
69 struct drm_framebuffer *scanout_fb;
71 /* for unref'ing framebuffers after scanout completes: */
72 struct drm_flip_work unref_fb_work;
74 /* for unref'ing cursor bo's after scanout completes: */
75 struct drm_flip_work unref_cursor_work;
77 struct mdp_irq vblank;
80 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
82 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
84 struct msm_drm_private *priv = crtc->dev->dev_private;
85 return to_mdp4_kms(to_mdp_kms(priv->kms));
88 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
90 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
92 atomic_or(pending, &mdp4_crtc->pending);
93 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
96 static void crtc_flush(struct drm_crtc *crtc)
98 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
99 struct mdp4_kms *mdp4_kms = get_kms(crtc);
100 uint32_t i, flush = 0;
102 for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
103 struct drm_plane *plane = mdp4_crtc->planes[i];
105 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
106 flush |= pipe2flush(pipe_id);
109 flush |= ovlp2flush(mdp4_crtc->ovlp);
111 DBG("%s: flush=%08x", mdp4_crtc->name, flush);
113 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
116 static void update_fb(struct drm_crtc *crtc, struct drm_framebuffer *new_fb)
118 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
119 struct drm_framebuffer *old_fb = mdp4_crtc->fb;
121 /* grab reference to incoming scanout fb: */
122 drm_framebuffer_reference(new_fb);
123 mdp4_crtc->base.primary->fb = new_fb;
124 mdp4_crtc->fb = new_fb;
127 drm_flip_work_queue(&mdp4_crtc->unref_fb_work, old_fb);
130 /* unlike update_fb(), take a ref to the new scanout fb *before* updating
131 * plane, then call this. Needed to ensure we don't unref the buffer that
132 * is actually still being scanned out.
134 * Note that this whole thing goes away with atomic.. since we can defer
135 * calling into driver until rendering is done.
137 static void update_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
139 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
141 /* flush updates, to make sure hw is updated to new scanout fb,
142 * so that we can safely queue unref to current fb (ie. next
143 * vblank we know hw is done w/ previous scanout_fb).
147 if (mdp4_crtc->scanout_fb)
148 drm_flip_work_queue(&mdp4_crtc->unref_fb_work,
149 mdp4_crtc->scanout_fb);
151 mdp4_crtc->scanout_fb = fb;
153 /* enable vblank to complete flip: */
154 request_pending(crtc, PENDING_FLIP);
157 /* if file!=NULL, this is preclose potential cancel-flip path */
158 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
160 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
161 struct drm_device *dev = crtc->dev;
162 struct drm_pending_vblank_event *event;
165 spin_lock_irqsave(&dev->event_lock, flags);
166 event = mdp4_crtc->event;
168 /* if regular vblank case (!file) or if cancel-flip from
169 * preclose on file that requested flip, then send the
172 if (!file || (event->base.file_priv == file)) {
173 mdp4_crtc->event = NULL;
174 drm_send_vblank_event(dev, mdp4_crtc->id, event);
177 spin_unlock_irqrestore(&dev->event_lock, flags);
180 static void pageflip_cb(struct msm_fence_cb *cb)
182 struct mdp4_crtc *mdp4_crtc =
183 container_of(cb, struct mdp4_crtc, pageflip_cb);
184 struct drm_crtc *crtc = &mdp4_crtc->base;
185 struct drm_framebuffer *fb = crtc->primary->fb;
190 drm_framebuffer_reference(fb);
191 mdp4_plane_set_scanout(mdp4_crtc->plane, fb);
192 update_scanout(crtc, fb);
195 static void unref_fb_worker(struct drm_flip_work *work, void *val)
197 struct mdp4_crtc *mdp4_crtc =
198 container_of(work, struct mdp4_crtc, unref_fb_work);
199 struct drm_device *dev = mdp4_crtc->base.dev;
201 mutex_lock(&dev->mode_config.mutex);
202 drm_framebuffer_unreference(val);
203 mutex_unlock(&dev->mode_config.mutex);
206 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
208 struct mdp4_crtc *mdp4_crtc =
209 container_of(work, struct mdp4_crtc, unref_cursor_work);
210 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
212 msm_gem_put_iova(val, mdp4_kms->id);
213 drm_gem_object_unreference_unlocked(val);
216 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
218 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
220 drm_crtc_cleanup(crtc);
221 drm_flip_work_cleanup(&mdp4_crtc->unref_fb_work);
222 drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
227 static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
229 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
230 struct mdp4_kms *mdp4_kms = get_kms(crtc);
231 bool enabled = (mode == DRM_MODE_DPMS_ON);
233 DBG("%s: mode=%d", mdp4_crtc->name, mode);
235 if (enabled != mdp4_crtc->enabled) {
237 mdp4_enable(mdp4_kms);
238 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
240 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
241 mdp4_disable(mdp4_kms);
243 mdp4_crtc->enabled = enabled;
247 static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
248 const struct drm_display_mode *mode,
249 struct drm_display_mode *adjusted_mode)
254 static void blend_setup(struct drm_crtc *crtc)
256 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
257 struct mdp4_kms *mdp4_kms = get_kms(crtc);
258 int i, ovlp = mdp4_crtc->ovlp;
259 uint32_t mixer_cfg = 0;
260 static const enum mdp_mixer_stage_id stages[] = {
261 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
263 /* statically (for now) map planes to mixer stage (z-order): */
264 static const int idxs[] = {
274 bool alpha[4]= { false, false, false, false };
276 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
277 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
278 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
279 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
281 /* TODO single register for all CRTCs, so this won't work properly
282 * when multiple CRTCs are active..
284 for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
285 struct drm_plane *plane = mdp4_crtc->planes[i];
287 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
288 int idx = idxs[pipe_id];
290 const struct mdp_format *format =
291 to_mdp_format(msm_framebuffer_format(plane->fb));
292 alpha[idx-1] = format->alpha_enable;
294 mixer_cfg |= mixercfg(mdp4_crtc->mixer, pipe_id, stages[idx]);
298 /* this shouldn't happen.. and seems to cause underflow: */
301 for (i = 0; i < 4; i++) {
305 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
306 MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
307 MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
309 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
310 MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
313 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
314 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
315 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
316 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
317 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
318 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
319 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
320 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
323 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
326 static int mdp4_crtc_mode_set(struct drm_crtc *crtc,
327 struct drm_display_mode *mode,
328 struct drm_display_mode *adjusted_mode,
330 struct drm_framebuffer *old_fb)
332 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
333 struct mdp4_kms *mdp4_kms = get_kms(crtc);
334 enum mdp4_dma dma = mdp4_crtc->dma;
335 int ret, ovlp = mdp4_crtc->ovlp;
337 mode = adjusted_mode;
339 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
340 mdp4_crtc->name, mode->base.id, mode->name,
341 mode->vrefresh, mode->clock,
342 mode->hdisplay, mode->hsync_start,
343 mode->hsync_end, mode->htotal,
344 mode->vdisplay, mode->vsync_start,
345 mode->vsync_end, mode->vtotal,
346 mode->type, mode->flags);
348 /* grab extra ref for update_scanout() */
349 drm_framebuffer_reference(crtc->primary->fb);
351 ret = mdp4_plane_mode_set(mdp4_crtc->plane, crtc, crtc->primary->fb,
352 0, 0, mode->hdisplay, mode->vdisplay,
354 mode->hdisplay << 16, mode->vdisplay << 16);
356 drm_framebuffer_unreference(crtc->primary->fb);
357 dev_err(crtc->dev->dev, "%s: failed to set mode on plane: %d\n",
358 mdp4_crtc->name, ret);
362 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
363 MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
364 MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
366 /* take data from pipe: */
367 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
368 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma),
369 crtc->primary->fb->pitches[0]);
370 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
371 MDP4_DMA_DST_SIZE_WIDTH(0) |
372 MDP4_DMA_DST_SIZE_HEIGHT(0));
374 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
375 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
376 MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
377 MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
378 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp),
379 crtc->primary->fb->pitches[0]);
381 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
384 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
385 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
386 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
389 update_fb(crtc, crtc->primary->fb);
390 update_scanout(crtc, crtc->primary->fb);
395 static void mdp4_crtc_prepare(struct drm_crtc *crtc)
397 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
398 DBG("%s", mdp4_crtc->name);
399 /* make sure we hold a ref to mdp clks while setting up mode: */
400 mdp4_enable(get_kms(crtc));
401 mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
404 static void mdp4_crtc_commit(struct drm_crtc *crtc)
406 mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
408 /* drop the ref to mdp clk's that we got in prepare: */
409 mdp4_disable(get_kms(crtc));
412 static int mdp4_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
413 struct drm_framebuffer *old_fb)
415 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
416 struct drm_plane *plane = mdp4_crtc->plane;
417 struct drm_display_mode *mode = &crtc->mode;
420 /* grab extra ref for update_scanout() */
421 drm_framebuffer_reference(crtc->primary->fb);
423 ret = mdp4_plane_mode_set(plane, crtc, crtc->primary->fb,
424 0, 0, mode->hdisplay, mode->vdisplay,
426 mode->hdisplay << 16, mode->vdisplay << 16);
428 drm_framebuffer_unreference(crtc->primary->fb);
432 update_fb(crtc, crtc->primary->fb);
433 update_scanout(crtc, crtc->primary->fb);
438 static void mdp4_crtc_load_lut(struct drm_crtc *crtc)
442 static int mdp4_crtc_page_flip(struct drm_crtc *crtc,
443 struct drm_framebuffer *new_fb,
444 struct drm_pending_vblank_event *event,
445 uint32_t page_flip_flags)
447 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
448 struct drm_device *dev = crtc->dev;
449 struct drm_gem_object *obj;
452 if (mdp4_crtc->event) {
453 dev_err(dev->dev, "already pending flip!\n");
457 obj = msm_framebuffer_bo(new_fb, 0);
459 spin_lock_irqsave(&dev->event_lock, flags);
460 mdp4_crtc->event = event;
461 spin_unlock_irqrestore(&dev->event_lock, flags);
463 update_fb(crtc, new_fb);
465 return msm_gem_queue_inactive_cb(obj, &mdp4_crtc->pageflip_cb);
468 static int mdp4_crtc_set_property(struct drm_crtc *crtc,
469 struct drm_property *property, uint64_t val)
475 #define CURSOR_WIDTH 64
476 #define CURSOR_HEIGHT 64
478 /* called from IRQ to update cursor related registers (if needed). The
479 * cursor registers, other than x/y position, appear not to be double
480 * buffered, and changing them other than from vblank seems to trigger
483 static void update_cursor(struct drm_crtc *crtc)
485 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
486 struct mdp4_kms *mdp4_kms = get_kms(crtc);
487 enum mdp4_dma dma = mdp4_crtc->dma;
490 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
491 if (mdp4_crtc->cursor.stale) {
492 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
493 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
494 uint32_t iova = mdp4_crtc->cursor.next_iova;
497 /* take a obj ref + iova ref when we start scanning out: */
498 drm_gem_object_reference(next_bo);
499 msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
502 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
503 MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
504 MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
505 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
506 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
507 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
508 MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
510 /* disable cursor: */
511 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
512 mdp4_kms->blank_cursor_iova);
515 /* and drop the iova ref + obj rev when done scanning out: */
517 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
519 mdp4_crtc->cursor.scanout_bo = next_bo;
520 mdp4_crtc->cursor.stale = false;
523 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
524 MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
525 MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
527 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
530 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
531 struct drm_file *file_priv, uint32_t handle,
532 uint32_t width, uint32_t height)
534 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
535 struct mdp4_kms *mdp4_kms = get_kms(crtc);
536 struct drm_device *dev = crtc->dev;
537 struct drm_gem_object *cursor_bo, *old_bo;
542 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
543 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
548 cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
556 ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
563 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
564 old_bo = mdp4_crtc->cursor.next_bo;
565 mdp4_crtc->cursor.next_bo = cursor_bo;
566 mdp4_crtc->cursor.next_iova = iova;
567 mdp4_crtc->cursor.width = width;
568 mdp4_crtc->cursor.height = height;
569 mdp4_crtc->cursor.stale = true;
570 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
573 /* drop our previous reference: */
574 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
577 request_pending(crtc, PENDING_CURSOR);
582 drm_gem_object_unreference_unlocked(cursor_bo);
586 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
588 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
591 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
592 mdp4_crtc->cursor.x = x;
593 mdp4_crtc->cursor.y = y;
594 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
597 request_pending(crtc, PENDING_CURSOR);
602 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
603 .set_config = drm_crtc_helper_set_config,
604 .destroy = mdp4_crtc_destroy,
605 .page_flip = mdp4_crtc_page_flip,
606 .set_property = mdp4_crtc_set_property,
607 .cursor_set = mdp4_crtc_cursor_set,
608 .cursor_move = mdp4_crtc_cursor_move,
611 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
612 .dpms = mdp4_crtc_dpms,
613 .mode_fixup = mdp4_crtc_mode_fixup,
614 .mode_set = mdp4_crtc_mode_set,
615 .prepare = mdp4_crtc_prepare,
616 .commit = mdp4_crtc_commit,
617 .mode_set_base = mdp4_crtc_mode_set_base,
618 .load_lut = mdp4_crtc_load_lut,
621 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
623 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
624 struct drm_crtc *crtc = &mdp4_crtc->base;
625 struct msm_drm_private *priv = crtc->dev->dev_private;
628 mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
630 pending = atomic_xchg(&mdp4_crtc->pending, 0);
632 if (pending & PENDING_FLIP) {
633 complete_flip(crtc, NULL);
634 drm_flip_work_commit(&mdp4_crtc->unref_fb_work, priv->wq);
637 if (pending & PENDING_CURSOR) {
639 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
643 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
645 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
646 struct drm_crtc *crtc = &mdp4_crtc->base;
647 DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
651 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
653 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
654 return mdp4_crtc->vblank.irqmask;
657 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
659 DBG("cancel: %p", file);
660 complete_flip(crtc, file);
663 /* set dma config, ie. the format the encoder wants. */
664 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
666 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
667 struct mdp4_kms *mdp4_kms = get_kms(crtc);
669 mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
672 /* set interface for routing crtc->encoder: */
673 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf)
675 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
676 struct mdp4_kms *mdp4_kms = get_kms(crtc);
679 intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
681 switch (mdp4_crtc->dma) {
683 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
684 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
687 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
688 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
691 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
692 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
696 if (intf == INTF_DSI_VIDEO) {
697 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
698 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
699 mdp4_crtc->mixer = 0;
700 } else if (intf == INTF_DSI_CMD) {
701 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
702 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
703 mdp4_crtc->mixer = 0;
704 } else if (intf == INTF_LCDC_DTV){
705 mdp4_crtc->mixer = 1;
710 DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
712 mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
715 static void set_attach(struct drm_crtc *crtc, enum mdp4_pipe pipe_id,
716 struct drm_plane *plane)
718 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
720 BUG_ON(pipe_id >= ARRAY_SIZE(mdp4_crtc->planes));
722 if (mdp4_crtc->planes[pipe_id] == plane)
725 mdp4_crtc->planes[pipe_id] = plane;
727 if (mdp4_crtc->enabled && (plane != mdp4_crtc->plane))
731 void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane)
733 set_attach(crtc, mdp4_plane_pipe(plane), plane);
736 void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane)
738 /* don't actually detatch our primary plane: */
739 if (to_mdp4_crtc(crtc)->plane == plane)
741 set_attach(crtc, mdp4_plane_pipe(plane), NULL);
744 static const char *dma_names[] = {
745 "DMA_P", "DMA_S", "DMA_E",
748 /* initialize crtc */
749 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
750 struct drm_plane *plane, int id, int ovlp_id,
751 enum mdp4_dma dma_id)
753 struct drm_crtc *crtc = NULL;
754 struct mdp4_crtc *mdp4_crtc;
757 mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
763 crtc = &mdp4_crtc->base;
765 mdp4_crtc->plane = plane;
768 mdp4_crtc->ovlp = ovlp_id;
769 mdp4_crtc->dma = dma_id;
771 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
772 mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
774 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
775 mdp4_crtc->err.irq = mdp4_crtc_err_irq;
777 snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
778 dma_names[dma_id], ovlp_id);
780 spin_lock_init(&mdp4_crtc->cursor.lock);
782 ret = drm_flip_work_init(&mdp4_crtc->unref_fb_work, 16,
783 "unref fb", unref_fb_worker);
787 ret = drm_flip_work_init(&mdp4_crtc->unref_cursor_work, 64,
788 "unref cursor", unref_cursor_worker);
790 INIT_FENCE_CB(&mdp4_crtc->pageflip_cb, pageflip_cb);
792 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs);
793 drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
795 mdp4_plane_install_properties(mdp4_crtc->plane, &crtc->base);
801 mdp4_crtc_destroy(crtc);