1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
8 #include "adreno_gpu.h"
13 extern bool hang_debug;
16 struct adreno_gpu base;
18 struct drm_gem_object *sqe_bo;
21 struct msm_ringbuffer *cur_ring;
22 struct msm_file_private *cur_ctx;
26 struct drm_gem_object *shadow_bo;
32 void __iomem *llc_mmio;
37 struct opp_table *opp_table;
40 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
43 * Given a register and a count, return a value to program into
44 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
45 * registers starting at _reg.
47 #define A6XX_PROTECT_NORDWR(_reg, _len) \
49 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
52 * Same as above, but allow reads over the range. For areas of mixed use (such
53 * as performance counters) this allows us to protect a much larger range with a
56 #define A6XX_PROTECT_RDONLY(_reg, _len) \
57 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
59 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
61 if(adreno_is_a630(gpu))
67 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
68 ((_ring)->id * sizeof(uint32_t)))
70 int a6xx_gmu_resume(struct a6xx_gpu *gpu);
71 int a6xx_gmu_stop(struct a6xx_gpu *gpu);
73 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
75 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
77 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
78 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
80 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
81 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
83 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp);
84 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
86 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
87 struct drm_printer *p);
89 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
90 int a6xx_gpu_state_put(struct msm_gpu_state *state);
92 #endif /* __A6XX_GPU_H__ */