drivers/gpu/drm/i915/intel_uc.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_uc.h"
  26 #include "intel_guc_submission.h"
  27 #include "intel_guc.h"
  28 #include "i915_drv.h"
  29 #include "i915_reset.h"
  30
  31 static void guc_free_load_err_log(struct intel_guc *guc);
  32
  33 /* Reset GuC providing us with fresh state for both GuC and HuC.
  34  */
  35 static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
  36 {
  37         int ret;
  38         u32 guc_status;
  39
  40         ret = intel_reset_guc(dev_priv);
  41         if (ret) {
  42                 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
  43                 return ret;
  44         }
  45
  46         guc_status = I915_READ(GUC_STATUS);
  47         WARN(!(guc_status & GS_MIA_IN_RESET),
  48              "GuC status: 0x%x, MIA core expected to be in reset\n",
  49              guc_status);
  50
  51         return ret;
  52 }
  53
  54 static int __get_platform_enable_guc(struct drm_i915_private *i915)
  55 {
  56         struct intel_uc_fw *guc_fw = &i915->guc.fw;
  57         struct intel_uc_fw *huc_fw = &i915->huc.fw;
  58         int enable_guc = 0;
  59
  60         /* Default is to enable GuC/HuC if we know their firmwares */
  61         if (intel_uc_fw_is_selected(guc_fw))
  62                 enable_guc |= ENABLE_GUC_SUBMISSION;
  63         if (intel_uc_fw_is_selected(huc_fw))
  64                 enable_guc |= ENABLE_GUC_LOAD_HUC;
  65
  66         /* Any platform specific fine-tuning can be done here */
  67
  68         return enable_guc;
  69 }
  70
  71 static int __get_default_guc_log_level(struct drm_i915_private *i915)
  72 {
  73         int guc_log_level;
  74
  75         if (!HAS_GUC(i915) || !intel_uc_is_using_guc(i915))
  76                 guc_log_level = GUC_LOG_LEVEL_DISABLED;
  77         else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
  78                  IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
  79                 guc_log_level = GUC_LOG_LEVEL_MAX;
  80         else
  81                 guc_log_level = GUC_LOG_LEVEL_NON_VERBOSE;
  82
  83         /* Any platform specific fine-tuning can be done here */
  84
  85         return guc_log_level;
  86 }
  87
  88 /**
  89  * sanitize_options_early - sanitize uC related modparam options
  90  * @i915: device private
  91  *
  92  * In case of "enable_guc" option this function will attempt to modify
  93  * it only if it was initially set to "auto(-1)". Default value for this
  94  * modparam varies between platforms and it is hardcoded in driver code.
  95  * Any other modparam value is only monitored against availability of the
  96  * related hardware or firmware definitions.
  97  *
  98  * In case of "guc_log_level" option this function will attempt to modify
  99  * it only if it was initially set to "auto(-1)" or if initial value was
 100  * "enable(1..4)" on platforms without the GuC. Default value for this
 101  * modparam varies between platforms and is usually set to "disable(0)"
 102  * unless GuC is enabled on given platform and the driver is compiled with
 103  * debug config when this modparam will default to "enable(1..4)".
 104  */
 105 static void sanitize_options_early(struct drm_i915_private *i915)
 106 {
 107         struct intel_uc_fw *guc_fw = &i915->guc.fw;
 108         struct intel_uc_fw *huc_fw = &i915->huc.fw;
 109
 110         /* A negative value means "use platform default" */
 111         if (i915_modparams.enable_guc < 0)
 112                 i915_modparams.enable_guc = __get_platform_enable_guc(i915);
 113
 114         DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
 115                          i915_modparams.enable_guc,
 116                          yesno(intel_uc_is_using_guc_submission(i915)),
 117                          yesno(intel_uc_is_using_huc(i915)));
 118
 119         /* Verify GuC firmware availability */
 120         if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
 121                 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 122                          "enable_guc", i915_modparams.enable_guc,
 123                          !HAS_GUC(i915) ? "no GuC hardware" :
 124                                           "no GuC firmware");
 125         }
 126
 127         /* Verify HuC firmware availability */
 128         if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
 129                 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 130                          "enable_guc", i915_modparams.enable_guc,
 131                          !HAS_HUC(i915) ? "no HuC hardware" :
 132                                           "no HuC firmware");
 133         }
 134
 135         /* A negative value means "use platform/config default" */
 136         if (i915_modparams.guc_log_level < 0)
 137                 i915_modparams.guc_log_level =
 138                         __get_default_guc_log_level(i915);
 139
 140         if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
 141                 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 142                          "guc_log_level", i915_modparams.guc_log_level,
 143                          !HAS_GUC(i915) ? "no GuC hardware" :
 144                                           "GuC not enabled");
 145                 i915_modparams.guc_log_level = 0;
 146         }
 147
 148         if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
 149                 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 150                          "guc_log_level", i915_modparams.guc_log_level,
 151                          "verbosity too high");
 152                 i915_modparams.guc_log_level = GUC_LOG_LEVEL_MAX;
 153         }
 154
 155         DRM_DEBUG_DRIVER("guc_log_level=%d (enabled:%s, verbose:%s, verbosity:%d)\n",
 156                          i915_modparams.guc_log_level,
 157                          yesno(i915_modparams.guc_log_level),
 158                          yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915_modparams.guc_log_level)),
 159                          GUC_LOG_LEVEL_TO_VERBOSITY(i915_modparams.guc_log_level));
 160
 161         /* Make sure that sanitization was done */
 162         GEM_BUG_ON(i915_modparams.enable_guc < 0);
 163         GEM_BUG_ON(i915_modparams.guc_log_level < 0);
 164 }
 165
 166 void intel_uc_init_early(struct drm_i915_private *i915)
 167 {
 168         struct intel_guc *guc = &i915->guc;
 169         struct intel_huc *huc = &i915->huc;
 170
 171         intel_guc_init_early(guc);
 172         intel_huc_init_early(huc);
 173
 174         sanitize_options_early(i915);
 175 }
 176
 177 void intel_uc_cleanup_early(struct drm_i915_private *i915)
 178 {
 179         struct intel_guc *guc = &i915->guc;
 180
 181         guc_free_load_err_log(guc);
 182 }
 183
 184 /**
 185  * intel_uc_init_mmio - setup uC MMIO access
 186  * @i915: device private
 187  *
 188  * Setup minimal state necessary for MMIO accesses later in the
 189  * initialization sequence.
 190  */
 191 void intel_uc_init_mmio(struct drm_i915_private *i915)
 192 {
 193         intel_guc_init_send_regs(&i915->guc);
 194 }
 195
 196 static void guc_capture_load_err_log(struct intel_guc *guc)
 197 {
 198         if (!guc->log.vma || !intel_guc_log_get_level(&guc->log))
 199                 return;
 200
 201         if (!guc->load_err_log)
 202                 guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
 203
 204         return;
 205 }
 206
 207 static void guc_free_load_err_log(struct intel_guc *guc)
 208 {
 209         if (guc->load_err_log)
 210                 i915_gem_object_put(guc->load_err_log);
 211 }
 212
 213 static int guc_enable_communication(struct intel_guc *guc)
 214 {
 215         struct drm_i915_private *i915 = guc_to_i915(guc);
 216
 217         gen9_enable_guc_interrupts(i915);
 218
 219         if (HAS_GUC_CT(i915))
 220                 return intel_guc_ct_enable(&guc->ct);
 221
 222         guc->send = intel_guc_send_mmio;
 223         guc->handler = intel_guc_to_host_event_handler_mmio;
 224         return 0;
 225 }
 226
 227 static void guc_disable_communication(struct intel_guc *guc)
 228 {
 229         struct drm_i915_private *i915 = guc_to_i915(guc);
 230
 231         if (HAS_GUC_CT(i915))
 232                 intel_guc_ct_disable(&guc->ct);
 233
 234         gen9_disable_guc_interrupts(i915);
 235
 236         guc->send = intel_guc_send_nop;
 237         guc->handler = intel_guc_to_host_event_handler_nop;
 238 }
 239
 240 int intel_uc_init_misc(struct drm_i915_private *i915)
 241 {
 242         struct intel_guc *guc = &i915->guc;
 243         struct intel_huc *huc = &i915->huc;
 244         int ret;
 245
 246         if (!USES_GUC(i915))
 247                 return 0;
 248
 249         ret = intel_guc_init_misc(guc);
 250         if (ret)
 251                 return ret;
 252
 253         if (USES_HUC(i915)) {
 254                 ret = intel_huc_init_misc(huc);
 255                 if (ret)
 256                         goto err_guc;
 257         }
 258
 259         return 0;
 260
 261 err_guc:
 262         intel_guc_fini_misc(guc);
 263         return ret;
 264 }
 265
 266 void intel_uc_fini_misc(struct drm_i915_private *i915)
 267 {
 268         struct intel_guc *guc = &i915->guc;
 269         struct intel_huc *huc = &i915->huc;
 270
 271         if (!USES_GUC(i915))
 272                 return;
 273
 274         if (USES_HUC(i915))
 275                 intel_huc_fini_misc(huc);
 276
 277         intel_guc_fini_misc(guc);
 278 }
 279
 280 int intel_uc_init(struct drm_i915_private *i915)
 281 {
 282         struct intel_guc *guc = &i915->guc;
 283         int ret;
 284
 285         if (!USES_GUC(i915))
 286                 return 0;
 287
 288         if (!HAS_GUC(i915))
 289                 return -ENODEV;
 290
 291         ret = intel_guc_init(guc);
 292         if (ret)
 293                 return ret;
 294
 295         if (USES_GUC_SUBMISSION(i915)) {
 296                 /*
 297                  * This is stuff we need to have available at fw load time
 298                  * if we are planning to enable submission later
 299                  */
 300                 ret = intel_guc_submission_init(guc);
 301                 if (ret) {
 302                         intel_guc_fini(guc);
 303                         return ret;
 304                 }
 305         }
 306
 307         return 0;
 308 }
 309
 310 void intel_uc_fini(struct drm_i915_private *i915)
 311 {
 312         struct intel_guc *guc = &i915->guc;
 313
 314         if (!USES_GUC(i915))
 315                 return;
 316
 317         GEM_BUG_ON(!HAS_GUC(i915));
 318
 319         if (USES_GUC_SUBMISSION(i915))
 320                 intel_guc_submission_fini(guc);
 321
 322         intel_guc_fini(guc);
 323 }
 324
 325 void intel_uc_sanitize(struct drm_i915_private *i915)
 326 {
 327         struct intel_guc *guc = &i915->guc;
 328         struct intel_huc *huc = &i915->huc;
 329
 330         if (!USES_GUC(i915))
 331                 return;
 332
 333         GEM_BUG_ON(!HAS_GUC(i915));
 334
 335         guc_disable_communication(guc);
 336
 337         intel_huc_sanitize(huc);
 338         intel_guc_sanitize(guc);
 339
 340         __intel_uc_reset_hw(i915);
 341 }
 342
 343 int intel_uc_init_hw(struct drm_i915_private *i915)
 344 {
 345         struct intel_guc *guc = &i915->guc;
 346         struct intel_huc *huc = &i915->huc;
 347         int ret, attempts;
 348
 349         if (!USES_GUC(i915))
 350                 return 0;
 351
 352         GEM_BUG_ON(!HAS_GUC(i915));
 353
 354         gen9_reset_guc_interrupts(i915);
 355
 356         /* WaEnableuKernelHeaderValidFix:skl */
 357         /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
 358         if (IS_GEN(i915, 9))
 359                 attempts = 3;
 360         else
 361                 attempts = 1;
 362
 363         while (attempts--) {
 364                 /*
 365                  * Always reset the GuC just before (re)loading, so
 366                  * that the state and timing are fairly predictable
 367                  */
 368                 ret = __intel_uc_reset_hw(i915);
 369                 if (ret)
 370                         goto err_out;
 371
 372                 if (USES_HUC(i915)) {
 373                         ret = intel_huc_fw_upload(huc);
 374                         if (ret)
 375                                 goto err_out;
 376                 }
 377
 378                 intel_guc_init_params(guc);
 379                 ret = intel_guc_fw_upload(guc);
 380                 if (ret == 0 || ret != -ETIMEDOUT)
 381                         break;
 382
 383                 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
 384                                  "retry %d more time(s)\n", ret, attempts);
 385         }
 386
 387         /* Did we succeded or run out of retries? */
 388         if (ret)
 389                 goto err_log_capture;
 390
 391         ret = guc_enable_communication(guc);
 392         if (ret)
 393                 goto err_log_capture;
 394
 395         if (USES_HUC(i915)) {
 396                 ret = intel_huc_auth(huc);
 397                 if (ret)
 398                         goto err_communication;
 399         }
 400
 401         if (USES_GUC_SUBMISSION(i915)) {
 402                 ret = intel_guc_submission_enable(guc);
 403                 if (ret)
 404                         goto err_communication;
 405         } else if (INTEL_GEN(i915) < 11) {
 406                 ret = intel_guc_sample_forcewake(guc);
 407                 if (ret)
 408                         goto err_communication;
 409         }
 410
 411         dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
 412                  guc->fw.major_ver_found, guc->fw.minor_ver_found);
 413         dev_info(i915->drm.dev, "GuC submission %s\n",
 414                  enableddisabled(USES_GUC_SUBMISSION(i915)));
 415         dev_info(i915->drm.dev, "HuC %s\n",
 416                  enableddisabled(USES_HUC(i915)));
 417
 418         return 0;
 419
 420         /*
 421          * We've failed to load the firmware :(
 422          */
 423 err_communication:
 424         guc_disable_communication(guc);
 425 err_log_capture:
 426         guc_capture_load_err_log(guc);
 427 err_out:
 428         /*
 429          * Note that there is no fallback as either user explicitly asked for
 430          * the GuC or driver default option was to run with the GuC enabled.
 431          */
 432         if (GEM_WARN_ON(ret == -EIO))
 433                 ret = -EINVAL;
 434
 435         dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
 436         return ret;
 437 }
 438
 439 void intel_uc_fini_hw(struct drm_i915_private *i915)
 440 {
 441         struct intel_guc *guc = &i915->guc;
 442
 443         if (!USES_GUC(i915))
 444                 return;
 445
 446         GEM_BUG_ON(!HAS_GUC(i915));
 447
 448         if (USES_GUC_SUBMISSION(i915))
 449                 intel_guc_submission_disable(guc);
 450
 451         guc_disable_communication(guc);
 452 }
 453
 454 int intel_uc_suspend(struct drm_i915_private *i915)
 455 {
 456         struct intel_guc *guc = &i915->guc;
 457         int err;
 458
 459         if (!USES_GUC(i915))
 460                 return 0;
 461
 462         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 463                 return 0;
 464
 465         err = intel_guc_suspend(guc);
 466         if (err) {
 467                 DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
 468                 return err;
 469         }
 470
 471         gen9_disable_guc_interrupts(i915);
 472
 473         return 0;
 474 }
 475
 476 int intel_uc_resume(struct drm_i915_private *i915)
 477 {
 478         struct intel_guc *guc = &i915->guc;
 479         int err;
 480
 481         if (!USES_GUC(i915))
 482                 return 0;
 483
 484         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 485                 return 0;
 486
 487         gen9_enable_guc_interrupts(i915);
 488
 489         err = intel_guc_resume(guc);
 490         if (err) {
 491                 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
 492                 return err;
 493         }
 494
 495         return 0;
 496 }