drivers/gpu/drm/i915/intel_uc.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_uc.h"
  26 #include "intel_guc_submission.h"
  27 #include "intel_guc.h"
  28 #include "i915_drv.h"
  29
  30 static void guc_free_load_err_log(struct intel_guc *guc);
  31
  32 /* Reset GuC providing us with fresh state for both GuC and HuC.
  33  */
  34 static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
  35 {
  36         int ret;
  37         u32 guc_status;
  38
  39         ret = intel_reset_guc(dev_priv);
  40         if (ret) {
  41                 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
  42                 return ret;
  43         }
  44
  45         guc_status = I915_READ(GUC_STATUS);
  46         WARN(!(guc_status & GS_MIA_IN_RESET),
  47              "GuC status: 0x%x, MIA core expected to be in reset\n",
  48              guc_status);
  49
  50         return ret;
  51 }
  52
  53 static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
  54 {
  55         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
  56         struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
  57         int enable_guc = 0;
  58
  59         /* Default is to enable GuC/HuC if we know their firmwares */
  60         if (intel_uc_fw_is_selected(guc_fw))
  61                 enable_guc |= ENABLE_GUC_SUBMISSION;
  62         if (intel_uc_fw_is_selected(huc_fw))
  63                 enable_guc |= ENABLE_GUC_LOAD_HUC;
  64
  65         /* Any platform specific fine-tuning can be done here */
  66
  67         return enable_guc;
  68 }
  69
  70 static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
  71 {
  72         int guc_log_level;
  73
  74         if (!HAS_GUC(dev_priv) || !intel_uc_is_using_guc())
  75                 guc_log_level = GUC_LOG_LEVEL_DISABLED;
  76         else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
  77                  IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
  78                 guc_log_level = GUC_LOG_LEVEL_MAX;
  79         else
  80                 guc_log_level = GUC_LOG_LEVEL_NON_VERBOSE;
  81
  82         /* Any platform specific fine-tuning can be done here */
  83
  84         return guc_log_level;
  85 }
  86
  87 /**
  88  * sanitize_options_early - sanitize uC related modparam options
  89  * @dev_priv: device private
  90  *
  91  * In case of "enable_guc" option this function will attempt to modify
  92  * it only if it was initially set to "auto(-1)". Default value for this
  93  * modparam varies between platforms and it is hardcoded in driver code.
  94  * Any other modparam value is only monitored against availability of the
  95  * related hardware or firmware definitions.
  96  *
  97  * In case of "guc_log_level" option this function will attempt to modify
  98  * it only if it was initially set to "auto(-1)" or if initial value was
  99  * "enable(1..4)" on platforms without the GuC. Default value for this
 100  * modparam varies between platforms and is usually set to "disable(0)"
 101  * unless GuC is enabled on given platform and the driver is compiled with
 102  * debug config when this modparam will default to "enable(1..4)".
 103  */
 104 static void sanitize_options_early(struct drm_i915_private *dev_priv)
 105 {
 106         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 107         struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
 108
 109         /* A negative value means "use platform default" */
 110         if (i915_modparams.enable_guc < 0)
 111                 i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv);
 112
 113         DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
 114                          i915_modparams.enable_guc,
 115                          yesno(intel_uc_is_using_guc_submission()),
 116                          yesno(intel_uc_is_using_huc()));
 117
 118         /* Verify GuC firmware availability */
 119         if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
 120                 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 121                          "enable_guc", i915_modparams.enable_guc,
 122                          !HAS_GUC(dev_priv) ? "no GuC hardware" :
 123                                               "no GuC firmware");
 124         }
 125
 126         /* Verify HuC firmware availability */
 127         if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
 128                 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 129                          "enable_guc", i915_modparams.enable_guc,
 130                          !HAS_HUC(dev_priv) ? "no HuC hardware" :
 131                                               "no HuC firmware");
 132         }
 133
 134         /* A negative value means "use platform/config default" */
 135         if (i915_modparams.guc_log_level < 0)
 136                 i915_modparams.guc_log_level =
 137                         __get_default_guc_log_level(dev_priv);
 138
 139         if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc()) {
 140                 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 141                          "guc_log_level", i915_modparams.guc_log_level,
 142                          !HAS_GUC(dev_priv) ? "no GuC hardware" :
 143                                               "GuC not enabled");
 144                 i915_modparams.guc_log_level = 0;
 145         }
 146
 147         if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
 148                 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 149                          "guc_log_level", i915_modparams.guc_log_level,
 150                          "verbosity too high");
 151                 i915_modparams.guc_log_level = GUC_LOG_LEVEL_MAX;
 152         }
 153
 154         DRM_DEBUG_DRIVER("guc_log_level=%d (enabled:%s, verbose:%s, verbosity:%d)\n",
 155                          i915_modparams.guc_log_level,
 156                          yesno(i915_modparams.guc_log_level),
 157                          yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915_modparams.guc_log_level)),
 158                          GUC_LOG_LEVEL_TO_VERBOSITY(i915_modparams.guc_log_level));
 159
 160         /* Make sure that sanitization was done */
 161         GEM_BUG_ON(i915_modparams.enable_guc < 0);
 162         GEM_BUG_ON(i915_modparams.guc_log_level < 0);
 163 }
 164
 165 void intel_uc_init_early(struct drm_i915_private *i915)
 166 {
 167         struct intel_guc *guc = &i915->guc;
 168         struct intel_huc *huc = &i915->huc;
 169
 170         intel_guc_init_early(guc);
 171         intel_huc_init_early(huc);
 172
 173         sanitize_options_early(i915);
 174
 175         if (USES_GUC(i915))
 176                 intel_uc_fw_fetch(i915, &guc->fw);
 177
 178         if (USES_HUC(i915))
 179                 intel_uc_fw_fetch(i915, &huc->fw);
 180 }
 181
 182 void intel_uc_cleanup_early(struct drm_i915_private *i915)
 183 {
 184         struct intel_guc *guc = &i915->guc;
 185         struct intel_huc *huc = &i915->huc;
 186
 187         if (USES_HUC(i915))
 188                 intel_uc_fw_fini(&huc->fw);
 189
 190         if (USES_GUC(i915))
 191                 intel_uc_fw_fini(&guc->fw);
 192
 193         guc_free_load_err_log(guc);
 194 }
 195
 196 /**
 197  * intel_uc_init_mmio - setup uC MMIO access
 198  *
 199  * @dev_priv: device private
 200  *
 201  * Setup minimal state necessary for MMIO accesses later in the
 202  * initialization sequence.
 203  */
 204 void intel_uc_init_mmio(struct drm_i915_private *dev_priv)
 205 {
 206         intel_guc_init_send_regs(&dev_priv->guc);
 207 }
 208
 209 static void guc_capture_load_err_log(struct intel_guc *guc)
 210 {
 211         if (!guc->log.vma || !i915_modparams.guc_log_level)
 212                 return;
 213
 214         if (!guc->load_err_log)
 215                 guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
 216
 217         return;
 218 }
 219
 220 static void guc_free_load_err_log(struct intel_guc *guc)
 221 {
 222         if (guc->load_err_log)
 223                 i915_gem_object_put(guc->load_err_log);
 224 }
 225
 226 static int guc_enable_communication(struct intel_guc *guc)
 227 {
 228         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 229
 230         gen9_enable_guc_interrupts(dev_priv);
 231
 232         if (HAS_GUC_CT(dev_priv))
 233                 return intel_guc_ct_enable(&guc->ct);
 234
 235         guc->send = intel_guc_send_mmio;
 236         guc->handler = intel_guc_to_host_event_handler_mmio;
 237         return 0;
 238 }
 239
 240 static void guc_disable_communication(struct intel_guc *guc)
 241 {
 242         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 243
 244         if (HAS_GUC_CT(dev_priv))
 245                 intel_guc_ct_disable(&guc->ct);
 246
 247         gen9_disable_guc_interrupts(dev_priv);
 248
 249         guc->send = intel_guc_send_nop;
 250         guc->handler = intel_guc_to_host_event_handler_nop;
 251 }
 252
 253 int intel_uc_init_misc(struct drm_i915_private *dev_priv)
 254 {
 255         struct intel_guc *guc = &dev_priv->guc;
 256         int ret;
 257
 258         if (!USES_GUC(dev_priv))
 259                 return 0;
 260
 261         intel_guc_init_ggtt_pin_bias(guc);
 262
 263         ret = intel_guc_init_wq(guc);
 264         if (ret)
 265                 return ret;
 266
 267         return 0;
 268 }
 269
 270 void intel_uc_fini_misc(struct drm_i915_private *dev_priv)
 271 {
 272         struct intel_guc *guc = &dev_priv->guc;
 273
 274         if (!USES_GUC(dev_priv))
 275                 return;
 276
 277         intel_guc_fini_wq(guc);
 278 }
 279
 280 int intel_uc_init(struct drm_i915_private *dev_priv)
 281 {
 282         struct intel_guc *guc = &dev_priv->guc;
 283         int ret;
 284
 285         if (!USES_GUC(dev_priv))
 286                 return 0;
 287
 288         if (!HAS_GUC(dev_priv))
 289                 return -ENODEV;
 290
 291         ret = intel_guc_init(guc);
 292         if (ret)
 293                 return ret;
 294
 295         if (USES_GUC_SUBMISSION(dev_priv)) {
 296                 /*
 297                  * This is stuff we need to have available at fw load time
 298                  * if we are planning to enable submission later
 299                  */
 300                 ret = intel_guc_submission_init(guc);
 301                 if (ret) {
 302                         intel_guc_fini(guc);
 303                         return ret;
 304                 }
 305         }
 306
 307         return 0;
 308 }
 309
 310 void intel_uc_fini(struct drm_i915_private *dev_priv)
 311 {
 312         struct intel_guc *guc = &dev_priv->guc;
 313
 314         if (!USES_GUC(dev_priv))
 315                 return;
 316
 317         GEM_BUG_ON(!HAS_GUC(dev_priv));
 318
 319         if (USES_GUC_SUBMISSION(dev_priv))
 320                 intel_guc_submission_fini(guc);
 321
 322         intel_guc_fini(guc);
 323 }
 324
 325 void intel_uc_sanitize(struct drm_i915_private *i915)
 326 {
 327         struct intel_guc *guc = &i915->guc;
 328         struct intel_huc *huc = &i915->huc;
 329
 330         if (!USES_GUC(i915))
 331                 return;
 332
 333         GEM_BUG_ON(!HAS_GUC(i915));
 334
 335         guc_disable_communication(guc);
 336
 337         intel_huc_sanitize(huc);
 338         intel_guc_sanitize(guc);
 339
 340         __intel_uc_reset_hw(i915);
 341 }
 342
 343 int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 344 {
 345         struct intel_guc *guc = &dev_priv->guc;
 346         struct intel_huc *huc = &dev_priv->huc;
 347         int ret, attempts;
 348
 349         if (!USES_GUC(dev_priv))
 350                 return 0;
 351
 352         GEM_BUG_ON(!HAS_GUC(dev_priv));
 353
 354         gen9_reset_guc_interrupts(dev_priv);
 355
 356         /* WaEnableuKernelHeaderValidFix:skl */
 357         /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
 358         if (IS_GEN9(dev_priv))
 359                 attempts = 3;
 360         else
 361                 attempts = 1;
 362
 363         while (attempts--) {
 364                 /*
 365                  * Always reset the GuC just before (re)loading, so
 366                  * that the state and timing are fairly predictable
 367                  */
 368                 ret = __intel_uc_reset_hw(dev_priv);
 369                 if (ret)
 370                         goto err_out;
 371
 372                 if (USES_HUC(dev_priv)) {
 373                         ret = intel_huc_fw_upload(huc);
 374                         if (ret)
 375                                 goto err_out;
 376                 }
 377
 378                 intel_guc_init_params(guc);
 379                 ret = intel_guc_fw_upload(guc);
 380                 if (ret == 0 || ret != -EAGAIN)
 381                         break;
 382
 383                 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
 384                                  "retry %d more time(s)\n", ret, attempts);
 385         }
 386
 387         /* Did we succeded or run out of retries? */
 388         if (ret)
 389                 goto err_log_capture;
 390
 391         ret = guc_enable_communication(guc);
 392         if (ret)
 393                 goto err_log_capture;
 394
 395         if (USES_HUC(dev_priv)) {
 396                 ret = intel_huc_auth(huc);
 397                 if (ret)
 398                         goto err_communication;
 399         }
 400
 401         if (USES_GUC_SUBMISSION(dev_priv)) {
 402                 ret = intel_guc_submission_enable(guc);
 403                 if (ret)
 404                         goto err_communication;
 405         }
 406
 407         dev_info(dev_priv->drm.dev, "GuC firmware version %u.%u\n",
 408                  guc->fw.major_ver_found, guc->fw.minor_ver_found);
 409         dev_info(dev_priv->drm.dev, "GuC submission %s\n",
 410                  enableddisabled(USES_GUC_SUBMISSION(dev_priv)));
 411         dev_info(dev_priv->drm.dev, "HuC %s\n",
 412                  enableddisabled(USES_HUC(dev_priv)));
 413
 414         return 0;
 415
 416         /*
 417          * We've failed to load the firmware :(
 418          */
 419 err_communication:
 420         guc_disable_communication(guc);
 421 err_log_capture:
 422         guc_capture_load_err_log(guc);
 423 err_out:
 424         /*
 425          * Note that there is no fallback as either user explicitly asked for
 426          * the GuC or driver default option was to run with the GuC enabled.
 427          */
 428         if (GEM_WARN_ON(ret == -EIO))
 429                 ret = -EINVAL;
 430
 431         dev_err(dev_priv->drm.dev, "GuC initialization failed %d\n", ret);
 432         return ret;
 433 }
 434
 435 void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 436 {
 437         struct intel_guc *guc = &dev_priv->guc;
 438
 439         if (!USES_GUC(dev_priv))
 440                 return;
 441
 442         GEM_BUG_ON(!HAS_GUC(dev_priv));
 443
 444         if (USES_GUC_SUBMISSION(dev_priv))
 445                 intel_guc_submission_disable(guc);
 446
 447         guc_disable_communication(guc);
 448 }
 449
 450 int intel_uc_suspend(struct drm_i915_private *i915)
 451 {
 452         struct intel_guc *guc = &i915->guc;
 453         int err;
 454
 455         if (!USES_GUC(i915))
 456                 return 0;
 457
 458         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 459                 return 0;
 460
 461         err = intel_guc_suspend(guc);
 462         if (err) {
 463                 DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
 464                 return err;
 465         }
 466
 467         gen9_disable_guc_interrupts(i915);
 468
 469         return 0;
 470 }
 471
 472 int intel_uc_resume(struct drm_i915_private *i915)
 473 {
 474         struct intel_guc *guc = &i915->guc;
 475         int err;
 476
 477         if (!USES_GUC(i915))
 478                 return 0;
 479
 480         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 481                 return 0;
 482
 483         gen9_enable_guc_interrupts(i915);
 484
 485         err = intel_guc_resume(guc);
 486         if (err) {
 487                 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
 488                 return err;
 489         }
 490
 491         return 0;
 492 }