drivers/gpu/drm/i915/intel_uc.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "i915_drv.h"
  26 #include "intel_uc.h"
  27 #include <linux/firmware.h>
  28
  29 /* Cleans up uC firmware by releasing the firmware GEM obj.
  30  */
  31 static void __intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
  32 {
  33         struct drm_i915_gem_object *obj;
  34
  35         obj = fetch_and_zero(&uc_fw->obj);
  36         if (obj)
  37                 i915_gem_object_put(obj);
  38
  39         uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
  40 }
  41
  42 /* Reset GuC providing us with fresh state for both GuC and HuC.
  43  */
  44 static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
  45 {
  46         int ret;
  47         u32 guc_status;
  48
  49         ret = intel_guc_reset(dev_priv);
  50         if (ret) {
  51                 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
  52                 return ret;
  53         }
  54
  55         guc_status = I915_READ(GUC_STATUS);
  56         WARN(!(guc_status & GS_MIA_IN_RESET),
  57              "GuC status: 0x%x, MIA core expected to be in reset\n",
  58              guc_status);
  59
  60         return ret;
  61 }
  62
  63 void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
  64 {
  65         if (!HAS_GUC(dev_priv)) {
  66                 if (i915.enable_guc_loading > 0 ||
  67                     i915.enable_guc_submission > 0)
  68                         DRM_INFO("Ignoring GuC options, no hardware\n");
  69
  70                 i915.enable_guc_loading = 0;
  71                 i915.enable_guc_submission = 0;
  72                 return;
  73         }
  74
  75         /* A negative value means "use platform default" */
  76         if (i915.enable_guc_loading < 0)
  77                 i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
  78
  79         /* Verify firmware version */
  80         if (i915.enable_guc_loading) {
  81                 if (HAS_HUC_UCODE(dev_priv))
  82                         intel_huc_select_fw(&dev_priv->huc);
  83
  84                 if (intel_guc_select_fw(&dev_priv->guc))
  85                         i915.enable_guc_loading = 0;
  86         }
  87
  88         /* Can't enable guc submission without guc loaded */
  89         if (!i915.enable_guc_loading)
  90                 i915.enable_guc_submission = 0;
  91
  92         /* A negative value means "use platform default" */
  93         if (i915.enable_guc_submission < 0)
  94                 i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
  95 }
  96
  97 static void gen8_guc_raise_irq(struct intel_guc *guc)
  98 {
  99         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 100
 101         I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
 102 }
 103
 104 void intel_uc_init_early(struct drm_i915_private *dev_priv)
 105 {
 106         struct intel_guc *guc = &dev_priv->guc;
 107
 108         intel_guc_ct_init_early(&guc->ct);
 109
 110         mutex_init(&guc->send_mutex);
 111         guc->send = intel_guc_send_nop;
 112         guc->notify = gen8_guc_raise_irq;
 113 }
 114
 115 static void fetch_uc_fw(struct drm_i915_private *dev_priv,
 116                         struct intel_uc_fw *uc_fw)
 117 {
 118         struct pci_dev *pdev = dev_priv->drm.pdev;
 119         struct drm_i915_gem_object *obj;
 120         const struct firmware *fw = NULL;
 121         struct uc_css_header *css;
 122         size_t size;
 123         int err;
 124
 125         if (!uc_fw->path)
 126                 return;
 127
 128         uc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
 129
 130         DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
 131                          intel_uc_fw_status_repr(uc_fw->fetch_status));
 132
 133         err = request_firmware(&fw, uc_fw->path, &pdev->dev);
 134         if (err)
 135                 goto fail;
 136         if (!fw)
 137                 goto fail;
 138
 139         DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
 140                          uc_fw->path, fw);
 141
 142         /* Check the size of the blob before examining buffer contents */
 143         if (fw->size < sizeof(struct uc_css_header)) {
 144                 DRM_NOTE("Firmware header is missing\n");
 145                 goto fail;
 146         }
 147
 148         css = (struct uc_css_header *)fw->data;
 149
 150         /* Firmware bits always start from header */
 151         uc_fw->header_offset = 0;
 152         uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 153                               css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 154
 155         if (uc_fw->header_size != sizeof(struct uc_css_header)) {
 156                 DRM_NOTE("CSS header definition mismatch\n");
 157                 goto fail;
 158         }
 159
 160         /* then, uCode */
 161         uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
 162         uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 163
 164         /* now RSA */
 165         if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 166                 DRM_NOTE("RSA key size is bad\n");
 167                 goto fail;
 168         }
 169         uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
 170         uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 171
 172         /* At least, it should have header, uCode and RSA. Size of all three. */
 173         size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
 174         if (fw->size < size) {
 175                 DRM_NOTE("Missing firmware components\n");
 176                 goto fail;
 177         }
 178
 179         /*
 180          * The GuC firmware image has the version number embedded at a
 181          * well-known offset within the firmware blob; note that major / minor
 182          * version are TWO bytes each (i.e. u16), although all pointers and
 183          * offsets are defined in terms of bytes (u8).
 184          */
 185         switch (uc_fw->type) {
 186         case INTEL_UC_FW_TYPE_GUC:
 187                 /* Header and uCode will be loaded to WOPCM. Size of the two. */
 188                 size = uc_fw->header_size + uc_fw->ucode_size;
 189
 190                 /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
 191                 if (size > intel_guc_wopcm_size(dev_priv)) {
 192                         DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 193                         goto fail;
 194                 }
 195                 uc_fw->major_ver_found = css->guc.sw_version >> 16;
 196                 uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
 197                 break;
 198
 199         case INTEL_UC_FW_TYPE_HUC:
 200                 uc_fw->major_ver_found = css->huc.sw_version >> 16;
 201                 uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
 202                 break;
 203
 204         default:
 205                 DRM_ERROR("Unknown firmware type %d\n", uc_fw->type);
 206                 err = -ENOEXEC;
 207                 goto fail;
 208         }
 209
 210         if (uc_fw->major_ver_wanted == 0 && uc_fw->minor_ver_wanted == 0) {
 211                 DRM_NOTE("Skipping %s firmware version check\n",
 212                          intel_uc_fw_type_repr(uc_fw->type));
 213         } else if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
 214                    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
 215                 DRM_NOTE("%s firmware version %d.%d, required %d.%d\n",
 216                          intel_uc_fw_type_repr(uc_fw->type),
 217                          uc_fw->major_ver_found, uc_fw->minor_ver_found,
 218                          uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 219                 err = -ENOEXEC;
 220                 goto fail;
 221         }
 222
 223         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 224                          uc_fw->major_ver_found, uc_fw->minor_ver_found,
 225                          uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 226
 227         obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
 228         if (IS_ERR(obj)) {
 229                 err = PTR_ERR(obj);
 230                 goto fail;
 231         }
 232
 233         uc_fw->obj = obj;
 234         uc_fw->size = fw->size;
 235
 236         DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
 237                          uc_fw->obj);
 238
 239         release_firmware(fw);
 240         uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
 241         return;
 242
 243 fail:
 244         DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
 245                  uc_fw->path, err);
 246         DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 247                          err, fw, uc_fw->obj);
 248
 249         release_firmware(fw);           /* OK even if fw is NULL */
 250         uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL;
 251 }
 252
 253 void intel_uc_init_fw(struct drm_i915_private *dev_priv)
 254 {
 255         fetch_uc_fw(dev_priv, &dev_priv->huc.fw);
 256         fetch_uc_fw(dev_priv, &dev_priv->guc.fw);
 257 }
 258
 259 void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
 260 {
 261         __intel_uc_fw_fini(&dev_priv->guc.fw);
 262         __intel_uc_fw_fini(&dev_priv->huc.fw);
 263 }
 264
 265 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
 266 {
 267         GEM_BUG_ON(!guc->send_regs.base);
 268         GEM_BUG_ON(!guc->send_regs.count);
 269         GEM_BUG_ON(i >= guc->send_regs.count);
 270
 271         return _MMIO(guc->send_regs.base + 4 * i);
 272 }
 273
 274 static void guc_init_send_regs(struct intel_guc *guc)
 275 {
 276         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 277         enum forcewake_domains fw_domains = 0;
 278         unsigned int i;
 279
 280         guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
 281         guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
 282
 283         for (i = 0; i < guc->send_regs.count; i++) {
 284                 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
 285                                         guc_send_reg(guc, i),
 286                                         FW_REG_READ | FW_REG_WRITE);
 287         }
 288         guc->send_regs.fw_domains = fw_domains;
 289 }
 290
 291 static void guc_capture_load_err_log(struct intel_guc *guc)
 292 {
 293         if (!guc->log.vma || i915.guc_log_level < 0)
 294                 return;
 295
 296         if (!guc->load_err_log)
 297                 guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
 298
 299         return;
 300 }
 301
 302 static void guc_free_load_err_log(struct intel_guc *guc)
 303 {
 304         if (guc->load_err_log)
 305                 i915_gem_object_put(guc->load_err_log);
 306 }
 307
 308 static int guc_enable_communication(struct intel_guc *guc)
 309 {
 310         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 311
 312         guc_init_send_regs(guc);
 313
 314         if (HAS_GUC_CT(dev_priv))
 315                 return intel_guc_enable_ct(guc);
 316
 317         guc->send = intel_guc_send_mmio;
 318         return 0;
 319 }
 320
 321 static void guc_disable_communication(struct intel_guc *guc)
 322 {
 323         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 324
 325         if (HAS_GUC_CT(dev_priv))
 326                 intel_guc_disable_ct(guc);
 327
 328         guc->send = intel_guc_send_nop;
 329 }
 330
 331 int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 332 {
 333         struct intel_guc *guc = &dev_priv->guc;
 334         int ret, attempts;
 335
 336         if (!i915.enable_guc_loading)
 337                 return 0;
 338
 339         guc_disable_communication(guc);
 340         gen9_reset_guc_interrupts(dev_priv);
 341
 342         /* We need to notify the guc whenever we change the GGTT */
 343         i915_ggtt_enable_guc(dev_priv);
 344
 345         if (i915.enable_guc_submission) {
 346                 /*
 347                  * This is stuff we need to have available at fw load time
 348                  * if we are planning to enable submission later
 349                  */
 350                 ret = i915_guc_submission_init(dev_priv);
 351                 if (ret)
 352                         goto err_guc;
 353         }
 354
 355         /* init WOPCM */
 356         I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
 357         I915_WRITE(DMA_GUC_WOPCM_OFFSET,
 358                    GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
 359
 360         /* WaEnableuKernelHeaderValidFix:skl */
 361         /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
 362         if (IS_GEN9(dev_priv))
 363                 attempts = 3;
 364         else
 365                 attempts = 1;
 366
 367         while (attempts--) {
 368                 /*
 369                  * Always reset the GuC just before (re)loading, so
 370                  * that the state and timing are fairly predictable
 371                  */
 372                 ret = __intel_uc_reset_hw(dev_priv);
 373                 if (ret)
 374                         goto err_submission;
 375
 376                 intel_huc_init_hw(&dev_priv->huc);
 377                 ret = intel_guc_init_hw(&dev_priv->guc);
 378                 if (ret == 0 || ret != -EAGAIN)
 379                         break;
 380
 381                 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
 382                                  "retry %d more time(s)\n", ret, attempts);
 383         }
 384
 385         /* Did we succeded or run out of retries? */
 386         if (ret)
 387                 goto err_log_capture;
 388
 389         ret = guc_enable_communication(guc);
 390         if (ret)
 391                 goto err_log_capture;
 392
 393         intel_guc_auth_huc(dev_priv);
 394         if (i915.enable_guc_submission) {
 395                 if (i915.guc_log_level >= 0)
 396                         gen9_enable_guc_interrupts(dev_priv);
 397
 398                 ret = i915_guc_submission_enable(dev_priv);
 399                 if (ret)
 400                         goto err_interrupts;
 401         }
 402
 403         return 0;
 404
 405         /*
 406          * We've failed to load the firmware :(
 407          *
 408          * Decide whether to disable GuC submission and fall back to
 409          * execlist mode, and whether to hide the error by returning
 410          * zero or to return -EIO, which the caller will treat as a
 411          * nonfatal error (i.e. it doesn't prevent driver load, but
 412          * marks the GPU as wedged until reset).
 413          */
 414 err_interrupts:
 415         guc_disable_communication(guc);
 416         gen9_disable_guc_interrupts(dev_priv);
 417 err_log_capture:
 418         guc_capture_load_err_log(guc);
 419 err_submission:
 420         if (i915.enable_guc_submission)
 421                 i915_guc_submission_fini(dev_priv);
 422 err_guc:
 423         i915_ggtt_disable_guc(dev_priv);
 424
 425         DRM_ERROR("GuC init failed\n");
 426         if (i915.enable_guc_loading > 1 || i915.enable_guc_submission > 1)
 427                 ret = -EIO;
 428         else
 429                 ret = 0;
 430
 431         if (i915.enable_guc_submission) {
 432                 i915.enable_guc_submission = 0;
 433                 DRM_NOTE("Falling back from GuC submission to execlist mode\n");
 434         }
 435
 436         i915.enable_guc_loading = 0;
 437         DRM_NOTE("GuC firmware loading disabled\n");
 438
 439         return ret;
 440 }
 441
 442 void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 443 {
 444         guc_free_load_err_log(&dev_priv->guc);
 445
 446         if (!i915.enable_guc_loading)
 447                 return;
 448
 449         if (i915.enable_guc_submission)
 450                 i915_guc_submission_disable(dev_priv);
 451
 452         guc_disable_communication(&dev_priv->guc);
 453
 454         if (i915.enable_guc_submission) {
 455                 gen9_disable_guc_interrupts(dev_priv);
 456                 i915_guc_submission_fini(dev_priv);
 457         }
 458
 459         i915_ggtt_disable_guc(dev_priv);
 460 }
 461
 462 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
 463 {
 464         WARN(1, "Unexpected send: action=%#x\n", *action);
 465         return -ENODEV;
 466 }
 467
 468 /*
 469  * This function implements the MMIO based host to GuC interface.
 470  */
 471 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
 472 {
 473         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 474         u32 status;
 475         int i;
 476         int ret;
 477
 478         GEM_BUG_ON(!len);
 479         GEM_BUG_ON(len > guc->send_regs.count);
 480
 481         /* If CT is available, we expect to use MMIO only during init/fini */
 482         GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
 483                 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
 484                 *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
 485
 486         mutex_lock(&guc->send_mutex);
 487         intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
 488
 489         for (i = 0; i < len; i++)
 490                 I915_WRITE(guc_send_reg(guc, i), action[i]);
 491
 492         POSTING_READ(guc_send_reg(guc, i - 1));
 493
 494         intel_guc_notify(guc);
 495
 496         /*
 497          * No GuC command should ever take longer than 10ms.
 498          * Fast commands should still complete in 10us.
 499          */
 500         ret = __intel_wait_for_register_fw(dev_priv,
 501                                            guc_send_reg(guc, 0),
 502                                            INTEL_GUC_RECV_MASK,
 503                                            INTEL_GUC_RECV_MASK,
 504                                            10, 10, &status);
 505         if (status != INTEL_GUC_STATUS_SUCCESS) {
 506                 /*
 507                  * Either the GuC explicitly returned an error (which
 508                  * we convert to -EIO here) or no response at all was
 509                  * received within the timeout limit (-ETIMEDOUT)
 510                  */
 511                 if (ret != -ETIMEDOUT)
 512                         ret = -EIO;
 513
 514                 DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
 515                          " ret=%d status=0x%08X response=0x%08X\n",
 516                          action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
 517         }
 518
 519         intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
 520         mutex_unlock(&guc->send_mutex);
 521
 522         return ret;
 523 }
 524
 525 int intel_guc_sample_forcewake(struct intel_guc *guc)
 526 {
 527         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 528         u32 action[2];
 529
 530         action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
 531         /* WaRsDisableCoarsePowerGating:skl,bxt */
 532         if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
 533                 action[1] = 0;
 534         else
 535                 /* bit 0 and 1 are for Render and Media domain separately */
 536                 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 537
 538         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 539 }