1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
6 #include "i915_gem_request.h"
7 #include "i915_gem_timeline.h"
9 #include "i915_selftest.h"
13 #define I915_CMD_HASH_ORDER 9
15 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
16 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
17 * to give some inclination as to some of the magic values used in the various
20 #define CACHELINE_BYTES 64
21 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
23 struct intel_hw_status_page {
29 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
30 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
32 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
33 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
35 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
36 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
38 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
39 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
41 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
42 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
44 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
45 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
47 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
48 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
50 enum intel_engine_hangcheck_action {
55 ENGINE_ACTIVE_SUBUNITS,
60 static inline const char *
61 hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
68 case ENGINE_ACTIVE_SEQNO:
69 return "active seqno";
70 case ENGINE_ACTIVE_HEAD:
72 case ENGINE_ACTIVE_SUBUNITS:
73 return "active subunits";
74 case ENGINE_WAIT_KICK:
83 #define I915_MAX_SLICES 3
84 #define I915_MAX_SUBSLICES 3
86 #define instdone_slice_mask(dev_priv__) \
87 (INTEL_GEN(dev_priv__) == 7 ? \
88 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
90 #define instdone_subslice_mask(dev_priv__) \
91 (INTEL_GEN(dev_priv__) == 7 ? \
92 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
94 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
95 for ((slice__) = 0, (subslice__) = 0; \
96 (slice__) < I915_MAX_SLICES; \
97 (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
98 (slice__) += ((subslice__) == 0)) \
99 for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
100 (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
102 struct intel_instdone {
104 /* The following exist only in the RCS engine */
106 u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
107 u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
110 struct intel_engine_hangcheck {
113 enum intel_engine_hangcheck_action action;
114 unsigned long action_timestamp;
116 struct intel_instdone instdone;
117 struct drm_i915_gem_request *active_request;
122 struct i915_vma *vma;
125 struct list_head request_list;
136 struct i915_gem_context;
137 struct drm_i915_reg_table;
140 * we use a single page to load ctx workarounds so all of these
141 * values are referred in terms of dwords
143 * struct i915_wa_ctx_bb:
144 * offset: specifies batch starting position, also helpful in case
145 * if we want to have multiple batches at different offsets based on
146 * some criteria. It is not a requirement at the moment but provides
147 * an option for future use.
148 * size: size of the batch in DWORDS
150 struct i915_ctx_workarounds {
151 struct i915_wa_ctx_bb {
154 } indirect_ctx, per_ctx;
155 struct i915_vma *vma;
158 struct drm_i915_gem_request;
161 * Engine IDs definitions.
162 * Keep instances of the same type engine together.
164 enum intel_engine_id {
169 #define _VCS(n) (VCS + (n))
173 struct i915_priolist {
175 struct list_head requests;
180 * struct intel_engine_execlists - execlist submission queue and port state
182 * The struct intel_engine_execlists represents the combined logical state of
183 * driver and the hardware state for execlist mode of submission.
185 struct intel_engine_execlists {
187 * @tasklet: softirq tasklet for bottom handler
189 struct tasklet_struct tasklet;
192 * @default_priolist: priority list for I915_PRIORITY_NORMAL
194 struct i915_priolist default_priolist;
197 * @no_priolist: priority lists disabled
202 * @port: execlist port states
204 * For each hardware ELSP (ExecList Submission Port) we keep
205 * track of the last request and the number of times we submitted
206 * that port to hw. We then count the number of times the hw reports
207 * a context completion or preemption. As only one context can
208 * be active on hw, we limit resubmission of context to port[0]. This
209 * is called Lite Restore, of the context.
211 struct execlist_port {
213 * @request_count: combined request and submission count
215 struct drm_i915_gem_request *request_count;
216 #define EXECLIST_COUNT_BITS 2
217 #define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
218 #define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
219 #define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
220 #define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
221 #define port_set(p, packed) ((p)->request_count = (packed))
222 #define port_isset(p) ((p)->request_count)
223 #define port_index(p, execlists) ((p) - (execlists)->port)
226 * @context_id: context ID for port
228 GEM_DEBUG_DECL(u32 context_id);
230 #define EXECLIST_MAX_PORTS 2
231 } port[EXECLIST_MAX_PORTS];
234 * @active: is the HW active? We consider the HW as active after
235 * submitting any context for execution and until we have seen the
236 * last context completion event. After that, we do not expect any
237 * more events until we submit, and so can park the HW.
239 * As we have a small number of different sources from which we feed
240 * the HW, we track the state of each inside a single bitfield.
243 #define EXECLISTS_ACTIVE_USER 0
244 #define EXECLISTS_ACTIVE_PREEMPT 1
245 #define EXECLISTS_ACTIVE_HWACK 2
248 * @port_mask: number of execlist ports - 1
250 unsigned int port_mask;
253 * @queue: queue of requests, in priority lists
255 struct rb_root queue;
258 * @first: leftmost level in priority @queue
260 struct rb_node *first;
263 * @fw_domains: forcewake domains for irq tasklet
265 unsigned int fw_domains;
268 * @csb_head: context status buffer head
270 unsigned int csb_head;
273 * @csb_use_mmio: access csb through mmio, instead of hwsp
278 #define INTEL_ENGINE_CS_MAX_NAME 8
280 struct intel_engine_cs {
281 struct drm_i915_private *i915;
282 char name[INTEL_ENGINE_CS_MAX_NAME];
284 enum intel_engine_id id;
295 unsigned int irq_shift;
297 struct intel_ring *buffer;
298 struct intel_timeline *timeline;
300 struct drm_i915_gem_object *default_state;
303 unsigned long irq_posted;
304 #define ENGINE_IRQ_BREADCRUMB 0
305 #define ENGINE_IRQ_EXECLIST 1
307 /* Rather than have every client wait upon all user interrupts,
308 * with the herd waking after every interrupt and each doing the
309 * heavyweight seqno dance, we delegate the task (of being the
310 * bottom-half of the user interrupt) to the first client. After
311 * every interrupt, we wake up one client, who does the heavyweight
312 * coherent seqno read and either goes back to sleep (if incomplete),
313 * or wakes up all the completed clients in parallel, before then
314 * transferring the bottom-half status to the next client in the queue.
316 * Compared to walking the entire list of waiters in a single dedicated
317 * bottom-half, we reduce the latency of the first waiter by avoiding
318 * a context switch, but incur additional coherent seqno reads when
319 * following the chain of request breadcrumbs. Since it is most likely
320 * that we have a single client waiting on each seqno, then reducing
321 * the overhead of waking that client is much preferred.
323 struct intel_breadcrumbs {
324 spinlock_t irq_lock; /* protects irq_*; irqsafe */
325 struct intel_wait *irq_wait; /* oldest waiter by retirement */
327 spinlock_t rb_lock; /* protects the rb and wraps irq_lock */
328 struct rb_root waiters; /* sorted by retirement, priority */
329 struct rb_root signals; /* sorted by retirement */
330 struct task_struct *signaler; /* used for fence signalling */
331 struct drm_i915_gem_request __rcu *first_signal;
332 struct timer_list fake_irq; /* used after a missed interrupt */
333 struct timer_list hangcheck; /* detect missed interrupts */
335 unsigned int hangcheck_interrupts;
336 unsigned int irq_enabled;
339 I915_SELFTEST_DECLARE(bool mock : 1);
344 * @enable: Bitmask of enable sample events on this engine.
346 * Bits correspond to sample event types, for instance
347 * I915_SAMPLE_QUEUED is bit 0 etc.
351 * @enable_count: Reference count for the enabled samplers.
353 * Index number corresponds to the bit number from @enable.
355 unsigned int enable_count[I915_PMU_SAMPLE_BITS];
357 * @sample: Counter values for sampling events.
359 * Our internal timer stores the current counters in this field.
361 #define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1)
362 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
364 * @busy_stats: Has enablement of engine stats tracking been
369 * @disable_busy_stats: Work item for busy stats disabling.
371 * Same as with @enable_busy_stats action, with the difference
372 * that we delay it in case there are rapid enable-disable
373 * actions, which can happen during tool startup (like perf
376 struct delayed_work disable_busy_stats;
380 * A pool of objects to use as shadow copies of client batch buffers
381 * when the command parser is enabled. Prevents the client from
382 * modifying the batch contents after software parsing.
384 struct i915_gem_batch_pool batch_pool;
386 struct intel_hw_status_page status_page;
387 struct i915_ctx_workarounds wa_ctx;
388 struct i915_vma *scratch;
390 u32 irq_keep_mask; /* always keep these interrupts */
391 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
392 void (*irq_enable)(struct intel_engine_cs *engine);
393 void (*irq_disable)(struct intel_engine_cs *engine);
395 int (*init_hw)(struct intel_engine_cs *engine);
396 void (*reset_hw)(struct intel_engine_cs *engine,
397 struct drm_i915_gem_request *req);
399 void (*park)(struct intel_engine_cs *engine);
400 void (*unpark)(struct intel_engine_cs *engine);
402 void (*set_default_submission)(struct intel_engine_cs *engine);
404 struct intel_ring *(*context_pin)(struct intel_engine_cs *engine,
405 struct i915_gem_context *ctx);
406 void (*context_unpin)(struct intel_engine_cs *engine,
407 struct i915_gem_context *ctx);
408 int (*request_alloc)(struct drm_i915_gem_request *req);
409 int (*init_context)(struct drm_i915_gem_request *req);
411 int (*emit_flush)(struct drm_i915_gem_request *request,
413 #define EMIT_INVALIDATE BIT(0)
414 #define EMIT_FLUSH BIT(1)
415 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
416 int (*emit_bb_start)(struct drm_i915_gem_request *req,
417 u64 offset, u32 length,
418 unsigned int dispatch_flags);
419 #define I915_DISPATCH_SECURE BIT(0)
420 #define I915_DISPATCH_PINNED BIT(1)
421 #define I915_DISPATCH_RS BIT(2)
422 void (*emit_breadcrumb)(struct drm_i915_gem_request *req,
424 int emit_breadcrumb_sz;
426 /* Pass the request to the hardware queue (e.g. directly into
427 * the legacy ringbuffer or to the end of an execlist).
429 * This is called from an atomic context with irqs disabled; must
432 void (*submit_request)(struct drm_i915_gem_request *req);
434 /* Call when the priority on a request has changed and it and its
435 * dependencies may need rescheduling. Note the request itself may
436 * not be ready to run!
438 * Called under the struct_mutex.
440 void (*schedule)(struct drm_i915_gem_request *request,
444 * Cancel all requests on the hardware, or queued for execution.
445 * This should only cancel the ready requests that have been
446 * submitted to the engine (via the engine->submit_request callback).
447 * This is called when marking the device as wedged.
449 void (*cancel_requests)(struct intel_engine_cs *engine);
451 /* Some chipsets are not quite as coherent as advertised and need
452 * an expensive kick to force a true read of the up-to-date seqno.
453 * However, the up-to-date seqno is not always required and the last
454 * seen value is good enough. Note that the seqno will always be
455 * monotonic, even if not coherent.
457 void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
458 void (*cleanup)(struct intel_engine_cs *engine);
460 /* GEN8 signal/wait table - never trust comments!
461 * signal to signal to signal to signal to signal to
462 * RCS VCS BCS VECS VCS2
463 * --------------------------------------------------------------------
464 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
465 * |-------------------------------------------------------------------
466 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
467 * |-------------------------------------------------------------------
468 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
469 * |-------------------------------------------------------------------
470 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
471 * |-------------------------------------------------------------------
472 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
473 * |-------------------------------------------------------------------
476 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
477 * ie. transpose of g(x, y)
479 * sync from sync from sync from sync from sync from
480 * RCS VCS BCS VECS VCS2
481 * --------------------------------------------------------------------
482 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
483 * |-------------------------------------------------------------------
484 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
485 * |-------------------------------------------------------------------
486 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
487 * |-------------------------------------------------------------------
488 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
489 * |-------------------------------------------------------------------
490 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
491 * |-------------------------------------------------------------------
494 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
495 * ie. transpose of f(x, y)
498 #define GEN6_SEMAPHORE_LAST VECS_HW
499 #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
500 #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
502 /* our mbox written by others */
503 u32 wait[GEN6_NUM_SEMAPHORES];
504 /* mboxes this ring signals to */
505 i915_reg_t signal[GEN6_NUM_SEMAPHORES];
509 int (*sync_to)(struct drm_i915_gem_request *req,
510 struct drm_i915_gem_request *signal);
511 u32 *(*signal)(struct drm_i915_gem_request *req, u32 *cs);
514 struct intel_engine_execlists execlists;
516 /* Contexts are pinned whilst they are active on the GPU. The last
517 * context executed remains active whilst the GPU is idle - the
518 * switch away and write to the context object only occurs on the
519 * next execution. Contexts are only unpinned on retirement of the
520 * following request ensuring that we can always write to the object
521 * on the context switch even after idling. Across suspend, we switch
522 * to the kernel context and trash it as the save may not happen
523 * before the hardware is powered down.
525 struct i915_gem_context *last_retired_context;
527 /* We track the current MI_SET_CONTEXT in order to eliminate
528 * redudant context switches. This presumes that requests are not
529 * reordered! Or when they are the tracking is updated along with
530 * the emission of individual requests into the legacy command
533 struct i915_gem_context *legacy_active_context;
534 struct i915_hw_ppgtt *legacy_active_ppgtt;
536 /* status_notifier: list of callbacks for context-switch changes */
537 struct atomic_notifier_head context_status_notifier;
539 struct intel_engine_hangcheck hangcheck;
541 #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
545 * Table of commands the command parser needs to know about
548 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
551 * Table of registers allowed in commands that read/write registers.
553 const struct drm_i915_reg_table *reg_tables;
557 * Returns the bitmask for the length field of the specified command.
558 * Return 0 for an unrecognized/invalid command.
560 * If the command parser finds an entry for a command in the engine's
561 * cmd_tables, it gets the command's length based on the table entry.
562 * If not, it calls this function to determine the per-engine length
563 * field encoding for the command (i.e. different opcode ranges use
564 * certain bits to encode the command length in the header).
566 u32 (*get_cmd_length_mask)(u32 cmd_header);
570 * @lock: Lock protecting the below fields.
574 * @enabled: Reference count indicating number of listeners.
576 unsigned int enabled;
578 * @active: Number of contexts currently scheduled in.
582 * @enabled_at: Timestamp when busy stats were enabled.
586 * @start: Timestamp of the last idle to active transition.
588 * Idle is defined as active == 0, active is active > 0.
592 * @total: Total time this engine was busy.
594 * Accumulated time not counting the most recent block in cases
595 * where engine is currently busy (active > 0).
601 static inline bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine)
603 return engine->flags & I915_ENGINE_NEEDS_CMD_PARSER;
607 execlists_set_active(struct intel_engine_execlists *execlists,
610 __set_bit(bit, (unsigned long *)&execlists->active);
614 execlists_clear_active(struct intel_engine_execlists *execlists,
617 __clear_bit(bit, (unsigned long *)&execlists->active);
621 execlists_is_active(const struct intel_engine_execlists *execlists,
624 return test_bit(bit, (unsigned long *)&execlists->active);
628 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists);
631 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
633 static inline unsigned int
634 execlists_num_ports(const struct intel_engine_execlists * const execlists)
636 return execlists->port_mask + 1;
640 execlists_port_complete(struct intel_engine_execlists * const execlists,
641 struct execlist_port * const port)
643 const unsigned int m = execlists->port_mask;
645 GEM_BUG_ON(port_index(port, execlists) != 0);
646 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
648 memmove(port, port + 1, m * sizeof(struct execlist_port));
649 memset(port + m, 0, sizeof(struct execlist_port));
652 static inline unsigned int
653 intel_engine_flag(const struct intel_engine_cs *engine)
655 return BIT(engine->id);
659 intel_read_status_page(struct intel_engine_cs *engine, int reg)
661 /* Ensure that the compiler doesn't optimize away the load. */
662 return READ_ONCE(engine->status_page.page_addr[reg]);
666 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
668 /* Writing into the status page should be done sparingly. Since
669 * we do when we are uncertain of the device state, we take a bit
670 * of extra paranoia to try and ensure that the HWS takes the value
671 * we give and that it doesn't end up trapped inside the CPU!
673 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
675 clflush(&engine->status_page.page_addr[reg]);
676 engine->status_page.page_addr[reg] = value;
677 clflush(&engine->status_page.page_addr[reg]);
680 WRITE_ONCE(engine->status_page.page_addr[reg], value);
685 * Reads a dword out of the status page, which is written to from the command
686 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
689 * The following dwords have a reserved meaning:
690 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
691 * 0x04: ring 0 head pointer
692 * 0x05: ring 1 head pointer (915-class)
693 * 0x06: ring 2 head pointer (915-class)
694 * 0x10-0x1b: Context status DWords (GM45)
695 * 0x1f: Last written status offset. (GM45)
696 * 0x20-0x2f: Reserved (Gen6+)
698 * The area from dword 0x30 to 0x3ff is available for driver usage.
700 #define I915_GEM_HWS_INDEX 0x30
701 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
702 #define I915_GEM_HWS_PREEMPT_INDEX 0x32
703 #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
704 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
705 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
707 #define I915_HWS_CSB_BUF0_INDEX 0x10
708 #define I915_HWS_CSB_WRITE_INDEX 0x1f
709 #define CNL_HWS_CSB_WRITE_INDEX 0x2f
712 intel_engine_create_ring(struct intel_engine_cs *engine, int size);
713 int intel_ring_pin(struct intel_ring *ring,
714 struct drm_i915_private *i915,
715 unsigned int offset_bias);
716 void intel_ring_reset(struct intel_ring *ring, u32 tail);
717 unsigned int intel_ring_update_space(struct intel_ring *ring);
718 void intel_ring_unpin(struct intel_ring *ring);
719 void intel_ring_free(struct intel_ring *ring);
721 void intel_engine_stop(struct intel_engine_cs *engine);
722 void intel_engine_cleanup(struct intel_engine_cs *engine);
724 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
726 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
728 int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes);
729 u32 __must_check *intel_ring_begin(struct drm_i915_gem_request *req,
733 intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs)
737 * This serves as a placeholder in the code so that the reader
738 * can compare against the preceding intel_ring_begin() and
739 * check that the number of dwords emitted matches the space
740 * reserved for the command packet (i.e. the value passed to
741 * intel_ring_begin()).
743 GEM_BUG_ON((req->ring->vaddr + req->ring->emit) != cs);
747 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
749 return pos & (ring->size - 1);
753 intel_ring_offset(const struct drm_i915_gem_request *req, void *addr)
755 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
756 u32 offset = addr - req->ring->vaddr;
757 GEM_BUG_ON(offset > req->ring->size);
758 return intel_ring_wrap(req->ring, offset);
762 assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
764 /* We could combine these into a single tail operation, but keeping
765 * them as seperate tests will help identify the cause should one
768 GEM_BUG_ON(!IS_ALIGNED(tail, 8));
769 GEM_BUG_ON(tail >= ring->size);
773 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6
774 * Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
775 * Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
776 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
777 * same cacheline, the Head Pointer must not be greater than the Tail
780 * We use ring->head as the last known location of the actual RING_HEAD,
781 * it may have advanced but in the worst case it is equally the same
782 * as ring->head and so we should never program RING_TAIL to advance
783 * into the same cacheline as ring->head.
785 #define cacheline(a) round_down(a, CACHELINE_BYTES)
786 GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) &&
791 static inline unsigned int
792 intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
794 /* Whilst writes to the tail are strictly order, there is no
795 * serialisation between readers and the writers. The tail may be
796 * read by i915_gem_request_retire() just as it is being updated
797 * by execlists, as although the breadcrumb is complete, the context
798 * switch hasn't been seen.
800 assert_ring_tail_valid(ring, tail);
805 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
807 void intel_engine_setup_common(struct intel_engine_cs *engine);
808 int intel_engine_init_common(struct intel_engine_cs *engine);
809 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
810 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
812 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
813 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
814 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
815 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
817 u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
818 u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine);
820 static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
822 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
825 static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
827 /* We are only peeking at the tail of the submit queue (and not the
828 * queue itself) in order to gain a hint as to the current active
829 * state of the engine. Callers are not expected to be taking
830 * engine->timeline->lock, nor are they expected to be concerned
831 * wtih serialising this hint with anything, so document it as
832 * a hint and nothing more.
834 return READ_ONCE(engine->timeline->seqno);
837 int init_workarounds_ring(struct intel_engine_cs *engine);
838 int intel_ring_workarounds_emit(struct drm_i915_gem_request *req);
840 void intel_engine_get_instdone(struct intel_engine_cs *engine,
841 struct intel_instdone *instdone);
844 * Arbitrary size for largest possible 'add request' sequence. The code paths
845 * are complex and variable. Empirical measurement shows that the worst case
846 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
847 * we need to allocate double the largest single packet within that emission
848 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
850 #define MIN_SPACE_FOR_ADD_REQUEST 336
852 static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
854 return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
857 static inline u32 intel_hws_preempt_done_address(struct intel_engine_cs *engine)
859 return engine->status_page.ggtt_offset + I915_GEM_HWS_PREEMPT_ADDR;
862 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
863 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
865 static inline void intel_wait_init(struct intel_wait *wait,
866 struct drm_i915_gem_request *rq)
872 static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno)
878 static inline bool intel_wait_has_seqno(const struct intel_wait *wait)
884 intel_wait_update_seqno(struct intel_wait *wait, u32 seqno)
887 return intel_wait_has_seqno(wait);
891 intel_wait_update_request(struct intel_wait *wait,
892 const struct drm_i915_gem_request *rq)
894 return intel_wait_update_seqno(wait, i915_gem_request_global_seqno(rq));
898 intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno)
900 return wait->seqno == seqno;
904 intel_wait_check_request(const struct intel_wait *wait,
905 const struct drm_i915_gem_request *rq)
907 return intel_wait_check_seqno(wait, i915_gem_request_global_seqno(rq));
910 static inline bool intel_wait_complete(const struct intel_wait *wait)
912 return RB_EMPTY_NODE(&wait->node);
915 bool intel_engine_add_wait(struct intel_engine_cs *engine,
916 struct intel_wait *wait);
917 void intel_engine_remove_wait(struct intel_engine_cs *engine,
918 struct intel_wait *wait);
919 void intel_engine_enable_signaling(struct drm_i915_gem_request *request,
921 void intel_engine_cancel_signaling(struct drm_i915_gem_request *request);
923 static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
925 return READ_ONCE(engine->breadcrumbs.irq_wait);
928 unsigned int intel_engine_wakeup(struct intel_engine_cs *engine);
929 #define ENGINE_WAKEUP_WAITER BIT(0)
930 #define ENGINE_WAKEUP_ASLEEP BIT(1)
932 void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine);
933 void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine);
935 void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
936 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
938 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
939 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
940 bool intel_breadcrumbs_busy(struct intel_engine_cs *engine);
942 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
944 memset(batch, 0, 6 * sizeof(u32));
946 batch[0] = GFX_OP_PIPE_CONTROL(6);
954 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset)
956 /* We're using qword write, offset should be aligned to 8 bytes. */
957 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
959 /* w/a for post sync ops following a GPGPU operation we
960 * need a prior CS_STALL, which is emitted by the flush
961 * following the batch.
963 *cs++ = GFX_OP_PIPE_CONTROL(6);
964 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
965 PIPE_CONTROL_QW_WRITE;
969 /* We're thrashing one dword of HWS. */
976 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset)
978 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
979 GEM_BUG_ON(gtt_offset & (1 << 5));
980 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
981 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
983 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
984 *cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
991 bool intel_engine_is_idle(struct intel_engine_cs *engine);
992 bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
994 bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine);
996 void intel_engines_park(struct drm_i915_private *i915);
997 void intel_engines_unpark(struct drm_i915_private *i915);
999 void intel_engines_reset_default_submission(struct drm_i915_private *i915);
1000 unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915);
1002 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
1004 void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p);
1006 struct intel_engine_cs *
1007 intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance);
1009 static inline void intel_engine_context_in(struct intel_engine_cs *engine)
1011 unsigned long flags;
1013 if (READ_ONCE(engine->stats.enabled) == 0)
1016 spin_lock_irqsave(&engine->stats.lock, flags);
1018 if (engine->stats.enabled > 0) {
1019 if (engine->stats.active++ == 0)
1020 engine->stats.start = ktime_get();
1021 GEM_BUG_ON(engine->stats.active == 0);
1024 spin_unlock_irqrestore(&engine->stats.lock, flags);
1027 static inline void intel_engine_context_out(struct intel_engine_cs *engine)
1029 unsigned long flags;
1031 if (READ_ONCE(engine->stats.enabled) == 0)
1034 spin_lock_irqsave(&engine->stats.lock, flags);
1036 if (engine->stats.enabled > 0) {
1039 if (engine->stats.active && --engine->stats.active == 0) {
1041 * Decrement the active context count and in case GPU
1042 * is now idle add up to the running total.
1044 last = ktime_sub(ktime_get(), engine->stats.start);
1046 engine->stats.total = ktime_add(engine->stats.total,
1048 } else if (engine->stats.active == 0) {
1050 * After turning on engine stats, context out might be
1051 * the first event in which case we account from the
1052 * time stats gathering was turned on.
1054 last = ktime_sub(ktime_get(), engine->stats.enabled_at);
1056 engine->stats.total = ktime_add(engine->stats.total,
1061 spin_unlock_irqrestore(&engine->stats.lock, flags);
1064 int intel_enable_engine_stats(struct intel_engine_cs *engine);
1065 void intel_disable_engine_stats(struct intel_engine_cs *engine);
1067 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
1069 #endif /* _INTEL_RINGBUFFER_H_ */