drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->primary->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112
 113         /* Clear old tags */
 114         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 115                 I915_WRITE(FBC_TAG + (i * 4), 0);
 116
 117         if (IS_GEN4(dev)) {
 118                 u32 fbc_ctl2;
 119
 120                 /* Set it up... */
 121                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 122                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 123                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 124                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 125         }
 126
 127         /* enable it... */
 128         fbc_ctl = I915_READ(FBC_CONTROL);
 129         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 130         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 131         if (IS_I945GM(dev))
 132                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 133         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 134         fbc_ctl |= obj->fence_reg;
 135         I915_WRITE(FBC_CONTROL, fbc_ctl);
 136
 137         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 138                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 139 }
 140
 141 static bool i8xx_fbc_enabled(struct drm_device *dev)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144
 145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 146 }
 147
 148 static void g4x_enable_fbc(struct drm_crtc *crtc)
 149 {
 150         struct drm_device *dev = crtc->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         struct drm_framebuffer *fb = crtc->primary->fb;
 153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 154         struct drm_i915_gem_object *obj = intel_fb->obj;
 155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 156         u32 dpfc_ctl;
 157
 158         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 159         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 160                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 161         else
 162                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 163         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 164
 165         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 166
 167         /* enable it... */
 168         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 169
 170         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 171 }
 172
 173 static void g4x_disable_fbc(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         u32 dpfc_ctl;
 177
 178         /* Disable compression */
 179         dpfc_ctl = I915_READ(DPFC_CONTROL);
 180         if (dpfc_ctl & DPFC_CTL_EN) {
 181                 dpfc_ctl &= ~DPFC_CTL_EN;
 182                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 183
 184                 DRM_DEBUG_KMS("disabled FBC\n");
 185         }
 186 }
 187
 188 static bool g4x_fbc_enabled(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 193 }
 194
 195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         u32 blt_ecoskpd;
 199
 200         /* Make sure blitter notifies FBC of writes */
 201
 202         /* Blitter is part of Media powerwell on VLV. No impact of
 203          * his param in other platforms for now */
 204         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 205
 206         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 207         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 208                 GEN6_BLITTER_LOCK_SHIFT;
 209         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 210         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 211         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 212         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 213                          GEN6_BLITTER_LOCK_SHIFT);
 214         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 215         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 216
 217         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 218 }
 219
 220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 221 {
 222         struct drm_device *dev = crtc->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_framebuffer *fb = crtc->primary->fb;
 225         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 226         struct drm_i915_gem_object *obj = intel_fb->obj;
 227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 231         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 232                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 233         else
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238
 239         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 240         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 241         /* enable it... */
 242         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 243
 244         if (IS_GEN6(dev)) {
 245                 I915_WRITE(SNB_DPFC_CTL_SA,
 246                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 247                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 248                 sandybridge_blit_fbc_update(dev);
 249         }
 250
 251         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 252 }
 253
 254 static void ironlake_disable_fbc(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         u32 dpfc_ctl;
 258
 259         /* Disable compression */
 260         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 261         if (dpfc_ctl & DPFC_CTL_EN) {
 262                 dpfc_ctl &= ~DPFC_CTL_EN;
 263                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 264
 265                 DRM_DEBUG_KMS("disabled FBC\n");
 266         }
 267 }
 268
 269 static bool ironlake_fbc_enabled(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 274 }
 275
 276 static void gen7_enable_fbc(struct drm_crtc *crtc)
 277 {
 278         struct drm_device *dev = crtc->dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         struct drm_framebuffer *fb = crtc->primary->fb;
 281         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 282         struct drm_i915_gem_object *obj = intel_fb->obj;
 283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 284         u32 dpfc_ctl;
 285
 286         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 287         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 288                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 289         else
 290                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 291         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 292
 293         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 294
 295         if (IS_IVYBRIDGE(dev)) {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 297                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 298                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 299                            ILK_FBCQ_DIS);
 300         } else {
 301                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 302                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 303                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 304                            HSW_FBCQ_DIS);
 305         }
 306
 307         I915_WRITE(SNB_DPFC_CTL_SA,
 308                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 309         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 310
 311         sandybridge_blit_fbc_update(dev);
 312
 313         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 314 }
 315
 316 bool intel_fbc_enabled(struct drm_device *dev)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         if (!dev_priv->display.fbc_enabled)
 321                 return false;
 322
 323         return dev_priv->display.fbc_enabled(dev);
 324 }
 325
 326 static void intel_fbc_work_fn(struct work_struct *__work)
 327 {
 328         struct intel_fbc_work *work =
 329                 container_of(to_delayed_work(__work),
 330                              struct intel_fbc_work, work);
 331         struct drm_device *dev = work->crtc->dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333
 334         mutex_lock(&dev->struct_mutex);
 335         if (work == dev_priv->fbc.fbc_work) {
 336                 /* Double check that we haven't switched fb without cancelling
 337                  * the prior work.
 338                  */
 339                 if (work->crtc->primary->fb == work->fb) {
 340                         dev_priv->display.enable_fbc(work->crtc);
 341
 342                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 343                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 344                         dev_priv->fbc.y = work->crtc->y;
 345                 }
 346
 347                 dev_priv->fbc.fbc_work = NULL;
 348         }
 349         mutex_unlock(&dev->struct_mutex);
 350
 351         kfree(work);
 352 }
 353
 354 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 355 {
 356         if (dev_priv->fbc.fbc_work == NULL)
 357                 return;
 358
 359         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 360
 361         /* Synchronisation is provided by struct_mutex and checking of
 362          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 363          * entirely asynchronously.
 364          */
 365         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 366                 /* tasklet was killed before being run, clean up */
 367                 kfree(dev_priv->fbc.fbc_work);
 368
 369         /* Mark the work as no longer wanted so that if it does
 370          * wake-up (because the work was already running and waiting
 371          * for our mutex), it will discover that is no longer
 372          * necessary to run.
 373          */
 374         dev_priv->fbc.fbc_work = NULL;
 375 }
 376
 377 static void intel_enable_fbc(struct drm_crtc *crtc)
 378 {
 379         struct intel_fbc_work *work;
 380         struct drm_device *dev = crtc->dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         if (!dev_priv->display.enable_fbc)
 384                 return;
 385
 386         intel_cancel_fbc_work(dev_priv);
 387
 388         work = kzalloc(sizeof(*work), GFP_KERNEL);
 389         if (work == NULL) {
 390                 DRM_ERROR("Failed to allocate FBC work structure\n");
 391                 dev_priv->display.enable_fbc(crtc);
 392                 return;
 393         }
 394
 395         work->crtc = crtc;
 396         work->fb = crtc->primary->fb;
 397         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 398
 399         dev_priv->fbc.fbc_work = work;
 400
 401         /* Delay the actual enabling to let pageflipping cease and the
 402          * display to settle before starting the compression. Note that
 403          * this delay also serves a second purpose: it allows for a
 404          * vblank to pass after disabling the FBC before we attempt
 405          * to modify the control registers.
 406          *
 407          * A more complicated solution would involve tracking vblanks
 408          * following the termination of the page-flipping sequence
 409          * and indeed performing the enable as a co-routine and not
 410          * waiting synchronously upon the vblank.
 411          *
 412          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 413          */
 414         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 415 }
 416
 417 void intel_disable_fbc(struct drm_device *dev)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420
 421         intel_cancel_fbc_work(dev_priv);
 422
 423         if (!dev_priv->display.disable_fbc)
 424                 return;
 425
 426         dev_priv->display.disable_fbc(dev);
 427         dev_priv->fbc.plane = -1;
 428 }
 429
 430 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 431                               enum no_fbc_reason reason)
 432 {
 433         if (dev_priv->fbc.no_fbc_reason == reason)
 434                 return false;
 435
 436         dev_priv->fbc.no_fbc_reason = reason;
 437         return true;
 438 }
 439
 440 /**
 441  * intel_update_fbc - enable/disable FBC as needed
 442  * @dev: the drm_device
 443  *
 444  * Set up the framebuffer compression hardware at mode set time.  We
 445  * enable it if possible:
 446  *   - plane A only (on pre-965)
 447  *   - no pixel mulitply/line duplication
 448  *   - no alpha buffer discard
 449  *   - no dual wide
 450  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 451  *
 452  * We can't assume that any compression will take place (worst case),
 453  * so the compressed buffer has to be the same size as the uncompressed
 454  * one.  It also must reside (along with the line length buffer) in
 455  * stolen memory.
 456  *
 457  * We need to enable/disable FBC on a global basis.
 458  */
 459 void intel_update_fbc(struct drm_device *dev)
 460 {
 461         struct drm_i915_private *dev_priv = dev->dev_private;
 462         struct drm_crtc *crtc = NULL, *tmp_crtc;
 463         struct intel_crtc *intel_crtc;
 464         struct drm_framebuffer *fb;
 465         struct intel_framebuffer *intel_fb;
 466         struct drm_i915_gem_object *obj;
 467         const struct drm_display_mode *adjusted_mode;
 468         unsigned int max_width, max_height;
 469
 470         if (!HAS_FBC(dev)) {
 471                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 472                 return;
 473         }
 474
 475         if (!i915.powersave) {
 476                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 477                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 478                 return;
 479         }
 480
 481         /*
 482          * If FBC is already on, we just have to verify that we can
 483          * keep it that way...
 484          * Need to disable if:
 485          *   - more than one pipe is active
 486          *   - changing FBC params (stride, fence, mode)
 487          *   - new fb is too large to fit in compressed buffer
 488          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 489          */
 490         for_each_crtc(dev, tmp_crtc) {
 491                 if (intel_crtc_active(tmp_crtc) &&
 492                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 493                         if (crtc) {
 494                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 495                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 496                                 goto out_disable;
 497                         }
 498                         crtc = tmp_crtc;
 499                 }
 500         }
 501
 502         if (!crtc || crtc->primary->fb == NULL) {
 503                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 504                         DRM_DEBUG_KMS("no output, disabling\n");
 505                 goto out_disable;
 506         }
 507
 508         intel_crtc = to_intel_crtc(crtc);
 509         fb = crtc->primary->fb;
 510         intel_fb = to_intel_framebuffer(fb);
 511         obj = intel_fb->obj;
 512         adjusted_mode = &intel_crtc->config.adjusted_mode;
 513
 514         if (i915.enable_fbc < 0) {
 515                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 516                         DRM_DEBUG_KMS("disabled per chip default\n");
 517                 goto out_disable;
 518         }
 519         if (!i915.enable_fbc) {
 520                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 521                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 522                 goto out_disable;
 523         }
 524         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 525             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 526                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 527                         DRM_DEBUG_KMS("mode incompatible with compression, "
 528                                       "disabling\n");
 529                 goto out_disable;
 530         }
 531
 532         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 533                 max_width = 4096;
 534                 max_height = 2048;
 535         } else {
 536                 max_width = 2048;
 537                 max_height = 1536;
 538         }
 539         if (intel_crtc->config.pipe_src_w > max_width ||
 540             intel_crtc->config.pipe_src_h > max_height) {
 541                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 542                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 543                 goto out_disable;
 544         }
 545         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 546             intel_crtc->plane != PLANE_A) {
 547                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 548                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 549                 goto out_disable;
 550         }
 551
 552         /* The use of a CPU fence is mandatory in order to detect writes
 553          * by the CPU to the scanout and trigger updates to the FBC.
 554          */
 555         if (obj->tiling_mode != I915_TILING_X ||
 556             obj->fence_reg == I915_FENCE_REG_NONE) {
 557                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 558                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 559                 goto out_disable;
 560         }
 561
 562         /* If the kernel debugger is active, always disable compression */
 563         if (in_dbg_master())
 564                 goto out_disable;
 565
 566         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 567                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 568                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 569                 goto out_disable;
 570         }
 571
 572         /* If the scanout has not changed, don't modify the FBC settings.
 573          * Note that we make the fundamental assumption that the fb->obj
 574          * cannot be unpinned (and have its GTT offset and fence revoked)
 575          * without first being decoupled from the scanout and FBC disabled.
 576          */
 577         if (dev_priv->fbc.plane == intel_crtc->plane &&
 578             dev_priv->fbc.fb_id == fb->base.id &&
 579             dev_priv->fbc.y == crtc->y)
 580                 return;
 581
 582         if (intel_fbc_enabled(dev)) {
 583                 /* We update FBC along two paths, after changing fb/crtc
 584                  * configuration (modeswitching) and after page-flipping
 585                  * finishes. For the latter, we know that not only did
 586                  * we disable the FBC at the start of the page-flip
 587                  * sequence, but also more than one vblank has passed.
 588                  *
 589                  * For the former case of modeswitching, it is possible
 590                  * to switch between two FBC valid configurations
 591                  * instantaneously so we do need to disable the FBC
 592                  * before we can modify its control registers. We also
 593                  * have to wait for the next vblank for that to take
 594                  * effect. However, since we delay enabling FBC we can
 595                  * assume that a vblank has passed since disabling and
 596                  * that we can safely alter the registers in the deferred
 597                  * callback.
 598                  *
 599                  * In the scenario that we go from a valid to invalid
 600                  * and then back to valid FBC configuration we have
 601                  * no strict enforcement that a vblank occurred since
 602                  * disabling the FBC. However, along all current pipe
 603                  * disabling paths we do need to wait for a vblank at
 604                  * some point. And we wait before enabling FBC anyway.
 605                  */
 606                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 607                 intel_disable_fbc(dev);
 608         }
 609
 610         intel_enable_fbc(crtc);
 611         dev_priv->fbc.no_fbc_reason = FBC_OK;
 612         return;
 613
 614 out_disable:
 615         /* Multiple disables should be harmless */
 616         if (intel_fbc_enabled(dev)) {
 617                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 618                 intel_disable_fbc(dev);
 619         }
 620         i915_gem_stolen_cleanup_compression(dev);
 621 }
 622
 623 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 624 {
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626         u32 tmp;
 627
 628         tmp = I915_READ(CLKCFG);
 629
 630         switch (tmp & CLKCFG_FSB_MASK) {
 631         case CLKCFG_FSB_533:
 632                 dev_priv->fsb_freq = 533; /* 133*4 */
 633                 break;
 634         case CLKCFG_FSB_800:
 635                 dev_priv->fsb_freq = 800; /* 200*4 */
 636                 break;
 637         case CLKCFG_FSB_667:
 638                 dev_priv->fsb_freq =  667; /* 167*4 */
 639                 break;
 640         case CLKCFG_FSB_400:
 641                 dev_priv->fsb_freq = 400; /* 100*4 */
 642                 break;
 643         }
 644
 645         switch (tmp & CLKCFG_MEM_MASK) {
 646         case CLKCFG_MEM_533:
 647                 dev_priv->mem_freq = 533;
 648                 break;
 649         case CLKCFG_MEM_667:
 650                 dev_priv->mem_freq = 667;
 651                 break;
 652         case CLKCFG_MEM_800:
 653                 dev_priv->mem_freq = 800;
 654                 break;
 655         }
 656
 657         /* detect pineview DDR3 setting */
 658         tmp = I915_READ(CSHRDDR3CTL);
 659         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 660 }
 661
 662 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 663 {
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         u16 ddrpll, csipll;
 666
 667         ddrpll = I915_READ16(DDRMPLL1);
 668         csipll = I915_READ16(CSIPLL0);
 669
 670         switch (ddrpll & 0xff) {
 671         case 0xc:
 672                 dev_priv->mem_freq = 800;
 673                 break;
 674         case 0x10:
 675                 dev_priv->mem_freq = 1066;
 676                 break;
 677         case 0x14:
 678                 dev_priv->mem_freq = 1333;
 679                 break;
 680         case 0x18:
 681                 dev_priv->mem_freq = 1600;
 682                 break;
 683         default:
 684                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 685                                  ddrpll & 0xff);
 686                 dev_priv->mem_freq = 0;
 687                 break;
 688         }
 689
 690         dev_priv->ips.r_t = dev_priv->mem_freq;
 691
 692         switch (csipll & 0x3ff) {
 693         case 0x00c:
 694                 dev_priv->fsb_freq = 3200;
 695                 break;
 696         case 0x00e:
 697                 dev_priv->fsb_freq = 3733;
 698                 break;
 699         case 0x010:
 700                 dev_priv->fsb_freq = 4266;
 701                 break;
 702         case 0x012:
 703                 dev_priv->fsb_freq = 4800;
 704                 break;
 705         case 0x014:
 706                 dev_priv->fsb_freq = 5333;
 707                 break;
 708         case 0x016:
 709                 dev_priv->fsb_freq = 5866;
 710                 break;
 711         case 0x018:
 712                 dev_priv->fsb_freq = 6400;
 713                 break;
 714         default:
 715                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 716                                  csipll & 0x3ff);
 717                 dev_priv->fsb_freq = 0;
 718                 break;
 719         }
 720
 721         if (dev_priv->fsb_freq == 3200) {
 722                 dev_priv->ips.c_m = 0;
 723         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 724                 dev_priv->ips.c_m = 1;
 725         } else {
 726                 dev_priv->ips.c_m = 2;
 727         }
 728 }
 729
 730 static const struct cxsr_latency cxsr_latency_table[] = {
 731         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 732         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 733         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 734         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 735         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 736
 737         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 738         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 739         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 740         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 741         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 742
 743         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 744         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 745         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 746         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 747         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 748
 749         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 750         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 751         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 752         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 753         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 754
 755         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 756         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 757         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 758         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 759         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 760
 761         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 762         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 763         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 764         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 765         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 766 };
 767
 768 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 769                                                          int is_ddr3,
 770                                                          int fsb,
 771                                                          int mem)
 772 {
 773         const struct cxsr_latency *latency;
 774         int i;
 775
 776         if (fsb == 0 || mem == 0)
 777                 return NULL;
 778
 779         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 780                 latency = &cxsr_latency_table[i];
 781                 if (is_desktop == latency->is_desktop &&
 782                     is_ddr3 == latency->is_ddr3 &&
 783                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 784                         return latency;
 785         }
 786
 787         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 788
 789         return NULL;
 790 }
 791
 792 static void pineview_disable_cxsr(struct drm_device *dev)
 793 {
 794         struct drm_i915_private *dev_priv = dev->dev_private;
 795
 796         /* deactivate cxsr */
 797         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 798 }
 799
 800 /*
 801  * Latency for FIFO fetches is dependent on several factors:
 802  *   - memory configuration (speed, channels)
 803  *   - chipset
 804  *   - current MCH state
 805  * It can be fairly high in some situations, so here we assume a fairly
 806  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 807  * set this value too high, the FIFO will fetch frequently to stay full)
 808  * and power consumption (set it too low to save power and we might see
 809  * FIFO underruns and display "flicker").
 810  *
 811  * A value of 5us seems to be a good balance; safe for very low end
 812  * platforms but not overly aggressive on lower latency configs.
 813  */
 814 static const int latency_ns = 5000;
 815
 816 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 817 {
 818         struct drm_i915_private *dev_priv = dev->dev_private;
 819         uint32_t dsparb = I915_READ(DSPARB);
 820         int size;
 821
 822         size = dsparb & 0x7f;
 823         if (plane)
 824                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 825
 826         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 827                       plane ? "B" : "A", size);
 828
 829         return size;
 830 }
 831
 832 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 833 {
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835         uint32_t dsparb = I915_READ(DSPARB);
 836         int size;
 837
 838         size = dsparb & 0x1ff;
 839         if (plane)
 840                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 841         size >>= 1; /* Convert to cachelines */
 842
 843         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 844                       plane ? "B" : "A", size);
 845
 846         return size;
 847 }
 848
 849 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 850 {
 851         struct drm_i915_private *dev_priv = dev->dev_private;
 852         uint32_t dsparb = I915_READ(DSPARB);
 853         int size;
 854
 855         size = dsparb & 0x7f;
 856         size >>= 2; /* Convert to cachelines */
 857
 858         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 859                       plane ? "B" : "A",
 860                       size);
 861
 862         return size;
 863 }
 864
 865 /* Pineview has different values for various configs */
 866 static const struct intel_watermark_params pineview_display_wm = {
 867         PINEVIEW_DISPLAY_FIFO,
 868         PINEVIEW_MAX_WM,
 869         PINEVIEW_DFT_WM,
 870         PINEVIEW_GUARD_WM,
 871         PINEVIEW_FIFO_LINE_SIZE
 872 };
 873 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 874         PINEVIEW_DISPLAY_FIFO,
 875         PINEVIEW_MAX_WM,
 876         PINEVIEW_DFT_HPLLOFF_WM,
 877         PINEVIEW_GUARD_WM,
 878         PINEVIEW_FIFO_LINE_SIZE
 879 };
 880 static const struct intel_watermark_params pineview_cursor_wm = {
 881         PINEVIEW_CURSOR_FIFO,
 882         PINEVIEW_CURSOR_MAX_WM,
 883         PINEVIEW_CURSOR_DFT_WM,
 884         PINEVIEW_CURSOR_GUARD_WM,
 885         PINEVIEW_FIFO_LINE_SIZE,
 886 };
 887 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 888         PINEVIEW_CURSOR_FIFO,
 889         PINEVIEW_CURSOR_MAX_WM,
 890         PINEVIEW_CURSOR_DFT_WM,
 891         PINEVIEW_CURSOR_GUARD_WM,
 892         PINEVIEW_FIFO_LINE_SIZE
 893 };
 894 static const struct intel_watermark_params g4x_wm_info = {
 895         G4X_FIFO_SIZE,
 896         G4X_MAX_WM,
 897         G4X_MAX_WM,
 898         2,
 899         G4X_FIFO_LINE_SIZE,
 900 };
 901 static const struct intel_watermark_params g4x_cursor_wm_info = {
 902         I965_CURSOR_FIFO,
 903         I965_CURSOR_MAX_WM,
 904         I965_CURSOR_DFT_WM,
 905         2,
 906         G4X_FIFO_LINE_SIZE,
 907 };
 908 static const struct intel_watermark_params valleyview_wm_info = {
 909         VALLEYVIEW_FIFO_SIZE,
 910         VALLEYVIEW_MAX_WM,
 911         VALLEYVIEW_MAX_WM,
 912         2,
 913         G4X_FIFO_LINE_SIZE,
 914 };
 915 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 916         I965_CURSOR_FIFO,
 917         VALLEYVIEW_CURSOR_MAX_WM,
 918         I965_CURSOR_DFT_WM,
 919         2,
 920         G4X_FIFO_LINE_SIZE,
 921 };
 922 static const struct intel_watermark_params i965_cursor_wm_info = {
 923         I965_CURSOR_FIFO,
 924         I965_CURSOR_MAX_WM,
 925         I965_CURSOR_DFT_WM,
 926         2,
 927         I915_FIFO_LINE_SIZE,
 928 };
 929 static const struct intel_watermark_params i945_wm_info = {
 930         I945_FIFO_SIZE,
 931         I915_MAX_WM,
 932         1,
 933         2,
 934         I915_FIFO_LINE_SIZE
 935 };
 936 static const struct intel_watermark_params i915_wm_info = {
 937         I915_FIFO_SIZE,
 938         I915_MAX_WM,
 939         1,
 940         2,
 941         I915_FIFO_LINE_SIZE
 942 };
 943 static const struct intel_watermark_params i830_wm_info = {
 944         I855GM_FIFO_SIZE,
 945         I915_MAX_WM,
 946         1,
 947         2,
 948         I830_FIFO_LINE_SIZE
 949 };
 950 static const struct intel_watermark_params i845_wm_info = {
 951         I830_FIFO_SIZE,
 952         I915_MAX_WM,
 953         1,
 954         2,
 955         I830_FIFO_LINE_SIZE
 956 };
 957
 958 /**
 959  * intel_calculate_wm - calculate watermark level
 960  * @clock_in_khz: pixel clock
 961  * @wm: chip FIFO params
 962  * @pixel_size: display pixel size
 963  * @latency_ns: memory latency for the platform
 964  *
 965  * Calculate the watermark level (the level at which the display plane will
 966  * start fetching from memory again).  Each chip has a different display
 967  * FIFO size and allocation, so the caller needs to figure that out and pass
 968  * in the correct intel_watermark_params structure.
 969  *
 970  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 971  * on the pixel size.  When it reaches the watermark level, it'll start
 972  * fetching FIFO line sized based chunks from memory until the FIFO fills
 973  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 974  * will occur, and a display engine hang could result.
 975  */
 976 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 977                                         const struct intel_watermark_params *wm,
 978                                         int fifo_size,
 979                                         int pixel_size,
 980                                         unsigned long latency_ns)
 981 {
 982         long entries_required, wm_size;
 983
 984         /*
 985          * Note: we need to make sure we don't overflow for various clock &
 986          * latency values.
 987          * clocks go from a few thousand to several hundred thousand.
 988          * latency is usually a few thousand
 989          */
 990         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 991                 1000;
 992         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 993
 994         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 995
 996         wm_size = fifo_size - (entries_required + wm->guard_size);
 997
 998         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 999
1000         /* Don't promote wm_size to unsigned... */
1001         if (wm_size > (long)wm->max_wm)
1002                 wm_size = wm->max_wm;
1003         if (wm_size <= 0)
1004                 wm_size = wm->default_wm;
1005         return wm_size;
1006 }
1007
1008 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1009 {
1010         struct drm_crtc *crtc, *enabled = NULL;
1011
1012         for_each_crtc(dev, crtc) {
1013                 if (intel_crtc_active(crtc)) {
1014                         if (enabled)
1015                                 return NULL;
1016                         enabled = crtc;
1017                 }
1018         }
1019
1020         return enabled;
1021 }
1022
1023 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1024 {
1025         struct drm_device *dev = unused_crtc->dev;
1026         struct drm_i915_private *dev_priv = dev->dev_private;
1027         struct drm_crtc *crtc;
1028         const struct cxsr_latency *latency;
1029         u32 reg;
1030         unsigned long wm;
1031
1032         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1033                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1034         if (!latency) {
1035                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1036                 pineview_disable_cxsr(dev);
1037                 return;
1038         }
1039
1040         crtc = single_enabled_crtc(dev);
1041         if (crtc) {
1042                 const struct drm_display_mode *adjusted_mode;
1043                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1044                 int clock;
1045
1046                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1047                 clock = adjusted_mode->crtc_clock;
1048
1049                 /* Display SR */
1050                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1051                                         pineview_display_wm.fifo_size,
1052                                         pixel_size, latency->display_sr);
1053                 reg = I915_READ(DSPFW1);
1054                 reg &= ~DSPFW_SR_MASK;
1055                 reg |= wm << DSPFW_SR_SHIFT;
1056                 I915_WRITE(DSPFW1, reg);
1057                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1058
1059                 /* cursor SR */
1060                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1061                                         pineview_display_wm.fifo_size,
1062                                         pixel_size, latency->cursor_sr);
1063                 reg = I915_READ(DSPFW3);
1064                 reg &= ~DSPFW_CURSOR_SR_MASK;
1065                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1066                 I915_WRITE(DSPFW3, reg);
1067
1068                 /* Display HPLL off SR */
1069                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1070                                         pineview_display_hplloff_wm.fifo_size,
1071                                         pixel_size, latency->display_hpll_disable);
1072                 reg = I915_READ(DSPFW3);
1073                 reg &= ~DSPFW_HPLL_SR_MASK;
1074                 reg |= wm & DSPFW_HPLL_SR_MASK;
1075                 I915_WRITE(DSPFW3, reg);
1076
1077                 /* cursor HPLL off SR */
1078                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1079                                         pineview_display_hplloff_wm.fifo_size,
1080                                         pixel_size, latency->cursor_hpll_disable);
1081                 reg = I915_READ(DSPFW3);
1082                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1083                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1084                 I915_WRITE(DSPFW3, reg);
1085                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1086
1087                 /* activate cxsr */
1088                 I915_WRITE(DSPFW3,
1089                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1090                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1091         } else {
1092                 pineview_disable_cxsr(dev);
1093                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1094         }
1095 }
1096
1097 static bool g4x_compute_wm0(struct drm_device *dev,
1098                             int plane,
1099                             const struct intel_watermark_params *display,
1100                             int display_latency_ns,
1101                             const struct intel_watermark_params *cursor,
1102                             int cursor_latency_ns,
1103                             int *plane_wm,
1104                             int *cursor_wm)
1105 {
1106         struct drm_crtc *crtc;
1107         const struct drm_display_mode *adjusted_mode;
1108         int htotal, hdisplay, clock, pixel_size;
1109         int line_time_us, line_count;
1110         int entries, tlb_miss;
1111
1112         crtc = intel_get_crtc_for_plane(dev, plane);
1113         if (!intel_crtc_active(crtc)) {
1114                 *cursor_wm = cursor->guard_size;
1115                 *plane_wm = display->guard_size;
1116                 return false;
1117         }
1118
1119         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1120         clock = adjusted_mode->crtc_clock;
1121         htotal = adjusted_mode->crtc_htotal;
1122         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1123         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1124
1125         /* Use the small buffer method to calculate plane watermark */
1126         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1127         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1128         if (tlb_miss > 0)
1129                 entries += tlb_miss;
1130         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1131         *plane_wm = entries + display->guard_size;
1132         if (*plane_wm > (int)display->max_wm)
1133                 *plane_wm = display->max_wm;
1134
1135         /* Use the large buffer method to calculate cursor watermark */
1136         line_time_us = max(htotal * 1000 / clock, 1);
1137         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1138         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1139         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1140         if (tlb_miss > 0)
1141                 entries += tlb_miss;
1142         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1143         *cursor_wm = entries + cursor->guard_size;
1144         if (*cursor_wm > (int)cursor->max_wm)
1145                 *cursor_wm = (int)cursor->max_wm;
1146
1147         return true;
1148 }
1149
1150 /*
1151  * Check the wm result.
1152  *
1153  * If any calculated watermark values is larger than the maximum value that
1154  * can be programmed into the associated watermark register, that watermark
1155  * must be disabled.
1156  */
1157 static bool g4x_check_srwm(struct drm_device *dev,
1158                            int display_wm, int cursor_wm,
1159                            const struct intel_watermark_params *display,
1160                            const struct intel_watermark_params *cursor)
1161 {
1162         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1163                       display_wm, cursor_wm);
1164
1165         if (display_wm > display->max_wm) {
1166                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1167                               display_wm, display->max_wm);
1168                 return false;
1169         }
1170
1171         if (cursor_wm > cursor->max_wm) {
1172                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1173                               cursor_wm, cursor->max_wm);
1174                 return false;
1175         }
1176
1177         if (!(display_wm || cursor_wm)) {
1178                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1179                 return false;
1180         }
1181
1182         return true;
1183 }
1184
1185 static bool g4x_compute_srwm(struct drm_device *dev,
1186                              int plane,
1187                              int latency_ns,
1188                              const struct intel_watermark_params *display,
1189                              const struct intel_watermark_params *cursor,
1190                              int *display_wm, int *cursor_wm)
1191 {
1192         struct drm_crtc *crtc;
1193         const struct drm_display_mode *adjusted_mode;
1194         int hdisplay, htotal, pixel_size, clock;
1195         unsigned long line_time_us;
1196         int line_count, line_size;
1197         int small, large;
1198         int entries;
1199
1200         if (!latency_ns) {
1201                 *display_wm = *cursor_wm = 0;
1202                 return false;
1203         }
1204
1205         crtc = intel_get_crtc_for_plane(dev, plane);
1206         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1207         clock = adjusted_mode->crtc_clock;
1208         htotal = adjusted_mode->crtc_htotal;
1209         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1210         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1211
1212         line_time_us = max(htotal * 1000 / clock, 1);
1213         line_count = (latency_ns / line_time_us + 1000) / 1000;
1214         line_size = hdisplay * pixel_size;
1215
1216         /* Use the minimum of the small and large buffer method for primary */
1217         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1218         large = line_count * line_size;
1219
1220         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1221         *display_wm = entries + display->guard_size;
1222
1223         /* calculate the self-refresh watermark for display cursor */
1224         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1225         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1226         *cursor_wm = entries + cursor->guard_size;
1227
1228         return g4x_check_srwm(dev,
1229                               *display_wm, *cursor_wm,
1230                               display, cursor);
1231 }
1232
1233 static bool vlv_compute_drain_latency(struct drm_device *dev,
1234                                      int plane,
1235                                      int *plane_prec_mult,
1236                                      int *plane_dl,
1237                                      int *cursor_prec_mult,
1238                                      int *cursor_dl)
1239 {
1240         struct drm_crtc *crtc;
1241         int clock, pixel_size;
1242         int entries;
1243
1244         crtc = intel_get_crtc_for_plane(dev, plane);
1245         if (!intel_crtc_active(crtc))
1246                 return false;
1247
1248         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1249         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
1250
1251         entries = (clock / 1000) * pixel_size;
1252         *plane_prec_mult = (entries > 256) ?
1253                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1254         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1255                                                      pixel_size);
1256
1257         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1258         *cursor_prec_mult = (entries > 256) ?
1259                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1260         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1261
1262         return true;
1263 }
1264
1265 /*
1266  * Update drain latency registers of memory arbiter
1267  *
1268  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1269  * to be programmed. Each plane has a drain latency multiplier and a drain
1270  * latency value.
1271  */
1272
1273 static void vlv_update_drain_latency(struct drm_device *dev)
1274 {
1275         struct drm_i915_private *dev_priv = dev->dev_private;
1276         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1277         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1278         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1279                                                         either 16 or 32 */
1280
1281         /* For plane A, Cursor A */
1282         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1283                                       &cursor_prec_mult, &cursora_dl)) {
1284                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1285                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1286                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1287                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1288
1289                 I915_WRITE(VLV_DDL1, cursora_prec |
1290                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1291                                 planea_prec | planea_dl);
1292         }
1293
1294         /* For plane B, Cursor B */
1295         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1296                                       &cursor_prec_mult, &cursorb_dl)) {
1297                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1298                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1299                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1300                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1301
1302                 I915_WRITE(VLV_DDL2, cursorb_prec |
1303                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1304                                 planeb_prec | planeb_dl);
1305         }
1306 }
1307
1308 #define single_plane_enabled(mask) is_power_of_2(mask)
1309
1310 static void valleyview_update_wm(struct drm_crtc *crtc)
1311 {
1312         struct drm_device *dev = crtc->dev;
1313         static const int sr_latency_ns = 12000;
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1316         int plane_sr, cursor_sr;
1317         int ignore_plane_sr, ignore_cursor_sr;
1318         unsigned int enabled = 0;
1319
1320         vlv_update_drain_latency(dev);
1321
1322         if (g4x_compute_wm0(dev, PIPE_A,
1323                             &valleyview_wm_info, latency_ns,
1324                             &valleyview_cursor_wm_info, latency_ns,
1325                             &planea_wm, &cursora_wm))
1326                 enabled |= 1 << PIPE_A;
1327
1328         if (g4x_compute_wm0(dev, PIPE_B,
1329                             &valleyview_wm_info, latency_ns,
1330                             &valleyview_cursor_wm_info, latency_ns,
1331                             &planeb_wm, &cursorb_wm))
1332                 enabled |= 1 << PIPE_B;
1333
1334         if (single_plane_enabled(enabled) &&
1335             g4x_compute_srwm(dev, ffs(enabled) - 1,
1336                              sr_latency_ns,
1337                              &valleyview_wm_info,
1338                              &valleyview_cursor_wm_info,
1339                              &plane_sr, &ignore_cursor_sr) &&
1340             g4x_compute_srwm(dev, ffs(enabled) - 1,
1341                              2*sr_latency_ns,
1342                              &valleyview_wm_info,
1343                              &valleyview_cursor_wm_info,
1344                              &ignore_plane_sr, &cursor_sr)) {
1345                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1346         } else {
1347                 I915_WRITE(FW_BLC_SELF_VLV,
1348                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1349                 plane_sr = cursor_sr = 0;
1350         }
1351
1352         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1353                       planea_wm, cursora_wm,
1354                       planeb_wm, cursorb_wm,
1355                       plane_sr, cursor_sr);
1356
1357         I915_WRITE(DSPFW1,
1358                    (plane_sr << DSPFW_SR_SHIFT) |
1359                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1360                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1361                    planea_wm);
1362         I915_WRITE(DSPFW2,
1363                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1364                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1365         I915_WRITE(DSPFW3,
1366                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1367                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1368 }
1369
1370 static void g4x_update_wm(struct drm_crtc *crtc)
1371 {
1372         struct drm_device *dev = crtc->dev;
1373         static const int sr_latency_ns = 12000;
1374         struct drm_i915_private *dev_priv = dev->dev_private;
1375         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1376         int plane_sr, cursor_sr;
1377         unsigned int enabled = 0;
1378
1379         if (g4x_compute_wm0(dev, PIPE_A,
1380                             &g4x_wm_info, latency_ns,
1381                             &g4x_cursor_wm_info, latency_ns,
1382                             &planea_wm, &cursora_wm))
1383                 enabled |= 1 << PIPE_A;
1384
1385         if (g4x_compute_wm0(dev, PIPE_B,
1386                             &g4x_wm_info, latency_ns,
1387                             &g4x_cursor_wm_info, latency_ns,
1388                             &planeb_wm, &cursorb_wm))
1389                 enabled |= 1 << PIPE_B;
1390
1391         if (single_plane_enabled(enabled) &&
1392             g4x_compute_srwm(dev, ffs(enabled) - 1,
1393                              sr_latency_ns,
1394                              &g4x_wm_info,
1395                              &g4x_cursor_wm_info,
1396                              &plane_sr, &cursor_sr)) {
1397                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1398         } else {
1399                 I915_WRITE(FW_BLC_SELF,
1400                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1401                 plane_sr = cursor_sr = 0;
1402         }
1403
1404         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1405                       planea_wm, cursora_wm,
1406                       planeb_wm, cursorb_wm,
1407                       plane_sr, cursor_sr);
1408
1409         I915_WRITE(DSPFW1,
1410                    (plane_sr << DSPFW_SR_SHIFT) |
1411                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1412                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1413                    planea_wm);
1414         I915_WRITE(DSPFW2,
1415                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1416                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1417         /* HPLL off in SR has some issues on G4x... disable it */
1418         I915_WRITE(DSPFW3,
1419                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1420                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1421 }
1422
1423 static void i965_update_wm(struct drm_crtc *unused_crtc)
1424 {
1425         struct drm_device *dev = unused_crtc->dev;
1426         struct drm_i915_private *dev_priv = dev->dev_private;
1427         struct drm_crtc *crtc;
1428         int srwm = 1;
1429         int cursor_sr = 16;
1430
1431         /* Calc sr entries for one plane configs */
1432         crtc = single_enabled_crtc(dev);
1433         if (crtc) {
1434                 /* self-refresh has much higher latency */
1435                 static const int sr_latency_ns = 12000;
1436                 const struct drm_display_mode *adjusted_mode =
1437                         &to_intel_crtc(crtc)->config.adjusted_mode;
1438                 int clock = adjusted_mode->crtc_clock;
1439                 int htotal = adjusted_mode->crtc_htotal;
1440                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1441                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1442                 unsigned long line_time_us;
1443                 int entries;
1444
1445                 line_time_us = max(htotal * 1000 / clock, 1);
1446
1447                 /* Use ns/us then divide to preserve precision */
1448                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1449                         pixel_size * hdisplay;
1450                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451                 srwm = I965_FIFO_SIZE - entries;
1452                 if (srwm < 0)
1453                         srwm = 1;
1454                 srwm &= 0x1ff;
1455                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1456                               entries, srwm);
1457
1458                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1460                 entries = DIV_ROUND_UP(entries,
1461                                           i965_cursor_wm_info.cacheline_size);
1462                 cursor_sr = i965_cursor_wm_info.fifo_size -
1463                         (entries + i965_cursor_wm_info.guard_size);
1464
1465                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466                         cursor_sr = i965_cursor_wm_info.max_wm;
1467
1468                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469                               "cursor %d\n", srwm, cursor_sr);
1470
1471                 if (IS_CRESTLINE(dev))
1472                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1473         } else {
1474                 /* Turn off self refresh if both pipes are enabled */
1475                 if (IS_CRESTLINE(dev))
1476                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1477                                    & ~FW_BLC_SELF_EN);
1478         }
1479
1480         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1481                       srwm);
1482
1483         /* 965 has limitations... */
1484         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1485                    (8 << 16) | (8 << 8) | (8 << 0));
1486         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1487         /* update cursor SR watermark */
1488         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1489 }
1490
1491 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1492 {
1493         struct drm_device *dev = unused_crtc->dev;
1494         struct drm_i915_private *dev_priv = dev->dev_private;
1495         const struct intel_watermark_params *wm_info;
1496         uint32_t fwater_lo;
1497         uint32_t fwater_hi;
1498         int cwm, srwm = 1;
1499         int fifo_size;
1500         int planea_wm, planeb_wm;
1501         struct drm_crtc *crtc, *enabled = NULL;
1502
1503         if (IS_I945GM(dev))
1504                 wm_info = &i945_wm_info;
1505         else if (!IS_GEN2(dev))
1506                 wm_info = &i915_wm_info;
1507         else
1508                 wm_info = &i830_wm_info;
1509
1510         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1511         crtc = intel_get_crtc_for_plane(dev, 0);
1512         if (intel_crtc_active(crtc)) {
1513                 const struct drm_display_mode *adjusted_mode;
1514                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1515                 if (IS_GEN2(dev))
1516                         cpp = 4;
1517
1518                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1519                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1520                                                wm_info, fifo_size, cpp,
1521                                                latency_ns);
1522                 enabled = crtc;
1523         } else
1524                 planea_wm = fifo_size - wm_info->guard_size;
1525
1526         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1527         crtc = intel_get_crtc_for_plane(dev, 1);
1528         if (intel_crtc_active(crtc)) {
1529                 const struct drm_display_mode *adjusted_mode;
1530                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1531                 if (IS_GEN2(dev))
1532                         cpp = 4;
1533
1534                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1535                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1536                                                wm_info, fifo_size, cpp,
1537                                                latency_ns);
1538                 if (enabled == NULL)
1539                         enabled = crtc;
1540                 else
1541                         enabled = NULL;
1542         } else
1543                 planeb_wm = fifo_size - wm_info->guard_size;
1544
1545         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1546
1547         if (IS_I915GM(dev) && enabled) {
1548                 struct intel_framebuffer *fb;
1549
1550                 fb = to_intel_framebuffer(enabled->primary->fb);
1551
1552                 /* self-refresh seems busted with untiled */
1553                 if (fb->obj->tiling_mode == I915_TILING_NONE)
1554                         enabled = NULL;
1555         }
1556
1557         /*
1558          * Overlay gets an aggressive default since video jitter is bad.
1559          */
1560         cwm = 2;
1561
1562         /* Play safe and disable self-refresh before adjusting watermarks. */
1563         if (IS_I945G(dev) || IS_I945GM(dev))
1564                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1565         else if (IS_I915GM(dev))
1566                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1567
1568         /* Calc sr entries for one plane configs */
1569         if (HAS_FW_BLC(dev) && enabled) {
1570                 /* self-refresh has much higher latency */
1571                 static const int sr_latency_ns = 6000;
1572                 const struct drm_display_mode *adjusted_mode =
1573                         &to_intel_crtc(enabled)->config.adjusted_mode;
1574                 int clock = adjusted_mode->crtc_clock;
1575                 int htotal = adjusted_mode->crtc_htotal;
1576                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1577                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1578                 unsigned long line_time_us;
1579                 int entries;
1580
1581                 line_time_us = max(htotal * 1000 / clock, 1);
1582
1583                 /* Use ns/us then divide to preserve precision */
1584                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1585                         pixel_size * hdisplay;
1586                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1587                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1588                 srwm = wm_info->fifo_size - entries;
1589                 if (srwm < 0)
1590                         srwm = 1;
1591
1592                 if (IS_I945G(dev) || IS_I945GM(dev))
1593                         I915_WRITE(FW_BLC_SELF,
1594                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1595                 else if (IS_I915GM(dev))
1596                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1597         }
1598
1599         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1600                       planea_wm, planeb_wm, cwm, srwm);
1601
1602         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1603         fwater_hi = (cwm & 0x1f);
1604
1605         /* Set request length to 8 cachelines per fetch */
1606         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1607         fwater_hi = fwater_hi | (1 << 8);
1608
1609         I915_WRITE(FW_BLC, fwater_lo);
1610         I915_WRITE(FW_BLC2, fwater_hi);
1611
1612         if (HAS_FW_BLC(dev)) {
1613                 if (enabled) {
1614                         if (IS_I945G(dev) || IS_I945GM(dev))
1615                                 I915_WRITE(FW_BLC_SELF,
1616                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1617                         else if (IS_I915GM(dev))
1618                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1619                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1620                 } else
1621                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1622         }
1623 }
1624
1625 static void i845_update_wm(struct drm_crtc *unused_crtc)
1626 {
1627         struct drm_device *dev = unused_crtc->dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629         struct drm_crtc *crtc;
1630         const struct drm_display_mode *adjusted_mode;
1631         uint32_t fwater_lo;
1632         int planea_wm;
1633
1634         crtc = single_enabled_crtc(dev);
1635         if (crtc == NULL)
1636                 return;
1637
1638         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1639         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1640                                        &i845_wm_info,
1641                                        dev_priv->display.get_fifo_size(dev, 0),
1642                                        4, latency_ns);
1643         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1644         fwater_lo |= (3<<8) | planea_wm;
1645
1646         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1647
1648         I915_WRITE(FW_BLC, fwater_lo);
1649 }
1650
1651 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1652                                     struct drm_crtc *crtc)
1653 {
1654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1655         uint32_t pixel_rate;
1656
1657         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1658
1659         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660          * adjust the pixel_rate here. */
1661
1662         if (intel_crtc->config.pch_pfit.enabled) {
1663                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1664                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1665
1666                 pipe_w = intel_crtc->config.pipe_src_w;
1667                 pipe_h = intel_crtc->config.pipe_src_h;
1668                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669                 pfit_h = pfit_size & 0xFFFF;
1670                 if (pipe_w < pfit_w)
1671                         pipe_w = pfit_w;
1672                 if (pipe_h < pfit_h)
1673                         pipe_h = pfit_h;
1674
1675                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1676                                      pfit_w * pfit_h);
1677         }
1678
1679         return pixel_rate;
1680 }
1681
1682 /* latency must be in 0.1us units. */
1683 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1684                                uint32_t latency)
1685 {
1686         uint64_t ret;
1687
1688         if (WARN(latency == 0, "Latency value missing\n"))
1689                 return UINT_MAX;
1690
1691         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1692         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1693
1694         return ret;
1695 }
1696
1697 /* latency must be in 0.1us units. */
1698 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1699                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1700                                uint32_t latency)
1701 {
1702         uint32_t ret;
1703
1704         if (WARN(latency == 0, "Latency value missing\n"))
1705                 return UINT_MAX;
1706
1707         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1708         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1709         ret = DIV_ROUND_UP(ret, 64) + 2;
1710         return ret;
1711 }
1712
1713 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1714                            uint8_t bytes_per_pixel)
1715 {
1716         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1717 }
1718
1719 struct ilk_pipe_wm_parameters {
1720         bool active;
1721         uint32_t pipe_htotal;
1722         uint32_t pixel_rate;
1723         struct intel_plane_wm_parameters pri;
1724         struct intel_plane_wm_parameters spr;
1725         struct intel_plane_wm_parameters cur;
1726 };
1727
1728 struct ilk_wm_maximums {
1729         uint16_t pri;
1730         uint16_t spr;
1731         uint16_t cur;
1732         uint16_t fbc;
1733 };
1734
1735 /* used in computing the new watermarks state */
1736 struct intel_wm_config {
1737         unsigned int num_pipes_active;
1738         bool sprites_enabled;
1739         bool sprites_scaled;
1740 };
1741
1742 /*
1743  * For both WM_PIPE and WM_LP.
1744  * mem_value must be in 0.1us units.
1745  */
1746 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1747                                    uint32_t mem_value,
1748                                    bool is_lp)
1749 {
1750         uint32_t method1, method2;
1751
1752         if (!params->active || !params->pri.enabled)
1753                 return 0;
1754
1755         method1 = ilk_wm_method1(params->pixel_rate,
1756                                  params->pri.bytes_per_pixel,
1757                                  mem_value);
1758
1759         if (!is_lp)
1760                 return method1;
1761
1762         method2 = ilk_wm_method2(params->pixel_rate,
1763                                  params->pipe_htotal,
1764                                  params->pri.horiz_pixels,
1765                                  params->pri.bytes_per_pixel,
1766                                  mem_value);
1767
1768         return min(method1, method2);
1769 }
1770
1771 /*
1772  * For both WM_PIPE and WM_LP.
1773  * mem_value must be in 0.1us units.
1774  */
1775 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1776                                    uint32_t mem_value)
1777 {
1778         uint32_t method1, method2;
1779
1780         if (!params->active || !params->spr.enabled)
1781                 return 0;
1782
1783         method1 = ilk_wm_method1(params->pixel_rate,
1784                                  params->spr.bytes_per_pixel,
1785                                  mem_value);
1786         method2 = ilk_wm_method2(params->pixel_rate,
1787                                  params->pipe_htotal,
1788                                  params->spr.horiz_pixels,
1789                                  params->spr.bytes_per_pixel,
1790                                  mem_value);
1791         return min(method1, method2);
1792 }
1793
1794 /*
1795  * For both WM_PIPE and WM_LP.
1796  * mem_value must be in 0.1us units.
1797  */
1798 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1799                                    uint32_t mem_value)
1800 {
1801         if (!params->active || !params->cur.enabled)
1802                 return 0;
1803
1804         return ilk_wm_method2(params->pixel_rate,
1805                               params->pipe_htotal,
1806                               params->cur.horiz_pixels,
1807                               params->cur.bytes_per_pixel,
1808                               mem_value);
1809 }
1810
1811 /* Only for WM_LP. */
1812 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1813                                    uint32_t pri_val)
1814 {
1815         if (!params->active || !params->pri.enabled)
1816                 return 0;
1817
1818         return ilk_wm_fbc(pri_val,
1819                           params->pri.horiz_pixels,
1820                           params->pri.bytes_per_pixel);
1821 }
1822
1823 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1824 {
1825         if (INTEL_INFO(dev)->gen >= 8)
1826                 return 3072;
1827         else if (INTEL_INFO(dev)->gen >= 7)
1828                 return 768;
1829         else
1830                 return 512;
1831 }
1832
1833 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1834                                          int level, bool is_sprite)
1835 {
1836         if (INTEL_INFO(dev)->gen >= 8)
1837                 /* BDW primary/sprite plane watermarks */
1838                 return level == 0 ? 255 : 2047;
1839         else if (INTEL_INFO(dev)->gen >= 7)
1840                 /* IVB/HSW primary/sprite plane watermarks */
1841                 return level == 0 ? 127 : 1023;
1842         else if (!is_sprite)
1843                 /* ILK/SNB primary plane watermarks */
1844                 return level == 0 ? 127 : 511;
1845         else
1846                 /* ILK/SNB sprite plane watermarks */
1847                 return level == 0 ? 63 : 255;
1848 }
1849
1850 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1851                                           int level)
1852 {
1853         if (INTEL_INFO(dev)->gen >= 7)
1854                 return level == 0 ? 63 : 255;
1855         else
1856                 return level == 0 ? 31 : 63;
1857 }
1858
1859 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1860 {
1861         if (INTEL_INFO(dev)->gen >= 8)
1862                 return 31;
1863         else
1864                 return 15;
1865 }
1866
1867 /* Calculate the maximum primary/sprite plane watermark */
1868 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1869                                      int level,
1870                                      const struct intel_wm_config *config,
1871                                      enum intel_ddb_partitioning ddb_partitioning,
1872                                      bool is_sprite)
1873 {
1874         unsigned int fifo_size = ilk_display_fifo_size(dev);
1875
1876         /* if sprites aren't enabled, sprites get nothing */
1877         if (is_sprite && !config->sprites_enabled)
1878                 return 0;
1879
1880         /* HSW allows LP1+ watermarks even with multiple pipes */
1881         if (level == 0 || config->num_pipes_active > 1) {
1882                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1883
1884                 /*
1885                  * For some reason the non self refresh
1886                  * FIFO size is only half of the self
1887                  * refresh FIFO size on ILK/SNB.
1888                  */
1889                 if (INTEL_INFO(dev)->gen <= 6)
1890                         fifo_size /= 2;
1891         }
1892
1893         if (config->sprites_enabled) {
1894                 /* level 0 is always calculated with 1:1 split */
1895                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1896                         if (is_sprite)
1897                                 fifo_size *= 5;
1898                         fifo_size /= 6;
1899                 } else {
1900                         fifo_size /= 2;
1901                 }
1902         }
1903
1904         /* clamp to max that the registers can hold */
1905         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1906 }
1907
1908 /* Calculate the maximum cursor plane watermark */
1909 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1910                                       int level,
1911                                       const struct intel_wm_config *config)
1912 {
1913         /* HSW LP1+ watermarks w/ multiple pipes */
1914         if (level > 0 && config->num_pipes_active > 1)
1915                 return 64;
1916
1917         /* otherwise just report max that registers can hold */
1918         return ilk_cursor_wm_reg_max(dev, level);
1919 }
1920
1921 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1922                                     int level,
1923                                     const struct intel_wm_config *config,
1924                                     enum intel_ddb_partitioning ddb_partitioning,
1925                                     struct ilk_wm_maximums *max)
1926 {
1927         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1928         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1929         max->cur = ilk_cursor_wm_max(dev, level, config);
1930         max->fbc = ilk_fbc_wm_reg_max(dev);
1931 }
1932
1933 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1934                                         int level,
1935                                         struct ilk_wm_maximums *max)
1936 {
1937         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1938         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1939         max->cur = ilk_cursor_wm_reg_max(dev, level);
1940         max->fbc = ilk_fbc_wm_reg_max(dev);
1941 }
1942
1943 static bool ilk_validate_wm_level(int level,
1944                                   const struct ilk_wm_maximums *max,
1945                                   struct intel_wm_level *result)
1946 {
1947         bool ret;
1948
1949         /* already determined to be invalid? */
1950         if (!result->enable)
1951                 return false;
1952
1953         result->enable = result->pri_val <= max->pri &&
1954                          result->spr_val <= max->spr &&
1955                          result->cur_val <= max->cur;
1956
1957         ret = result->enable;
1958
1959         /*
1960          * HACK until we can pre-compute everything,
1961          * and thus fail gracefully if LP0 watermarks
1962          * are exceeded...
1963          */
1964         if (level == 0 && !result->enable) {
1965                 if (result->pri_val > max->pri)
1966                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1967                                       level, result->pri_val, max->pri);
1968                 if (result->spr_val > max->spr)
1969                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1970                                       level, result->spr_val, max->spr);
1971                 if (result->cur_val > max->cur)
1972                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1973                                       level, result->cur_val, max->cur);
1974
1975                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1976                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1977                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1978                 result->enable = true;
1979         }
1980
1981         return ret;
1982 }
1983
1984 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1985                                  int level,
1986                                  const struct ilk_pipe_wm_parameters *p,
1987                                  struct intel_wm_level *result)
1988 {
1989         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1990         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1991         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1992
1993         /* WM1+ latency values stored in 0.5us units */
1994         if (level > 0) {
1995                 pri_latency *= 5;
1996                 spr_latency *= 5;
1997                 cur_latency *= 5;
1998         }
1999
2000         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2001         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2002         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2003         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2004         result->enable = true;
2005 }
2006
2007 static uint32_t
2008 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2009 {
2010         struct drm_i915_private *dev_priv = dev->dev_private;
2011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2012         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2013         u32 linetime, ips_linetime;
2014
2015         if (!intel_crtc_active(crtc))
2016                 return 0;
2017
2018         /* The WM are computed with base on how long it takes to fill a single
2019          * row at the given clock rate, multiplied by 8.
2020          * */
2021         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2022                                      mode->crtc_clock);
2023         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2024                                          intel_ddi_get_cdclk_freq(dev_priv));
2025
2026         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2027                PIPE_WM_LINETIME_TIME(linetime);
2028 }
2029
2030 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2031 {
2032         struct drm_i915_private *dev_priv = dev->dev_private;
2033
2034         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2035                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2036
2037                 wm[0] = (sskpd >> 56) & 0xFF;
2038                 if (wm[0] == 0)
2039                         wm[0] = sskpd & 0xF;
2040                 wm[1] = (sskpd >> 4) & 0xFF;
2041                 wm[2] = (sskpd >> 12) & 0xFF;
2042                 wm[3] = (sskpd >> 20) & 0x1FF;
2043                 wm[4] = (sskpd >> 32) & 0x1FF;
2044         } else if (INTEL_INFO(dev)->gen >= 6) {
2045                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2046
2047                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2048                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2049                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2050                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2051         } else if (INTEL_INFO(dev)->gen >= 5) {
2052                 uint32_t mltr = I915_READ(MLTR_ILK);
2053
2054                 /* ILK primary LP0 latency is 700 ns */
2055                 wm[0] = 7;
2056                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2057                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2058         }
2059 }
2060
2061 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2062 {
2063         /* ILK sprite LP0 latency is 1300 ns */
2064         if (INTEL_INFO(dev)->gen == 5)
2065                 wm[0] = 13;
2066 }
2067
2068 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2069 {
2070         /* ILK cursor LP0 latency is 1300 ns */
2071         if (INTEL_INFO(dev)->gen == 5)
2072                 wm[0] = 13;
2073
2074         /* WaDoubleCursorLP3Latency:ivb */
2075         if (IS_IVYBRIDGE(dev))
2076                 wm[3] *= 2;
2077 }
2078
2079 int ilk_wm_max_level(const struct drm_device *dev)
2080 {
2081         /* how many WM levels are we expecting */
2082         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2083                 return 4;
2084         else if (INTEL_INFO(dev)->gen >= 6)
2085                 return 3;
2086         else
2087                 return 2;
2088 }
2089
2090 static void intel_print_wm_latency(struct drm_device *dev,
2091                                    const char *name,
2092                                    const uint16_t wm[5])
2093 {
2094         int level, max_level = ilk_wm_max_level(dev);
2095
2096         for (level = 0; level <= max_level; level++) {
2097                 unsigned int latency = wm[level];
2098
2099                 if (latency == 0) {
2100                         DRM_ERROR("%s WM%d latency not provided\n",
2101                                   name, level);
2102                         continue;
2103                 }
2104
2105                 /* WM1+ latency values in 0.5us units */
2106                 if (level > 0)
2107                         latency *= 5;
2108
2109                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2110                               name, level, wm[level],
2111                               latency / 10, latency % 10);
2112         }
2113 }
2114
2115 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2116                                     uint16_t wm[5], uint16_t min)
2117 {
2118         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2119
2120         if (wm[0] >= min)
2121                 return false;
2122
2123         wm[0] = max(wm[0], min);
2124         for (level = 1; level <= max_level; level++)
2125                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2126
2127         return true;
2128 }
2129
2130 static void snb_wm_latency_quirk(struct drm_device *dev)
2131 {
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         bool changed;
2134
2135         /*
2136          * The BIOS provided WM memory latency values are often
2137          * inadequate for high resolution displays. Adjust them.
2138          */
2139         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2140                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2141                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2142
2143         if (!changed)
2144                 return;
2145
2146         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2147         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2148         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2149         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2150 }
2151
2152 static void ilk_setup_wm_latency(struct drm_device *dev)
2153 {
2154         struct drm_i915_private *dev_priv = dev->dev_private;
2155
2156         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2157
2158         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2159                sizeof(dev_priv->wm.pri_latency));
2160         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2161                sizeof(dev_priv->wm.pri_latency));
2162
2163         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2164         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2165
2166         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2167         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2168         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2169
2170         if (IS_GEN6(dev))
2171                 snb_wm_latency_quirk(dev);
2172 }
2173
2174 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2175                                       struct ilk_pipe_wm_parameters *p)
2176 {
2177         struct drm_device *dev = crtc->dev;
2178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2179         enum pipe pipe = intel_crtc->pipe;
2180         struct drm_plane *plane;
2181
2182         if (!intel_crtc_active(crtc))
2183                 return;
2184
2185         p->active = true;
2186         p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2187         p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2188         p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2189         p->cur.bytes_per_pixel = 4;
2190         p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2191         p->cur.horiz_pixels = intel_crtc->cursor_width;
2192         /* TODO: for now, assume primary and cursor planes are always enabled. */
2193         p->pri.enabled = true;
2194         p->cur.enabled = true;
2195
2196         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2197                 struct intel_plane *intel_plane = to_intel_plane(plane);
2198
2199                 if (intel_plane->pipe == pipe) {
2200                         p->spr = intel_plane->wm;
2201                         break;
2202                 }
2203         }
2204 }
2205
2206 static void ilk_compute_wm_config(struct drm_device *dev,
2207                                   struct intel_wm_config *config)
2208 {
2209         struct intel_crtc *intel_crtc;
2210
2211         /* Compute the currently _active_ config */
2212         for_each_intel_crtc(dev, intel_crtc) {
2213                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2214
2215                 if (!wm->pipe_enabled)
2216                         continue;
2217
2218                 config->sprites_enabled |= wm->sprites_enabled;
2219                 config->sprites_scaled |= wm->sprites_scaled;
2220                 config->num_pipes_active++;
2221         }
2222 }
2223
2224 /* Compute new watermarks for the pipe */
2225 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2226                                   const struct ilk_pipe_wm_parameters *params,
2227                                   struct intel_pipe_wm *pipe_wm)
2228 {
2229         struct drm_device *dev = crtc->dev;
2230         const struct drm_i915_private *dev_priv = dev->dev_private;
2231         int level, max_level = ilk_wm_max_level(dev);
2232         /* LP0 watermark maximums depend on this pipe alone */
2233         struct intel_wm_config config = {
2234                 .num_pipes_active = 1,
2235                 .sprites_enabled = params->spr.enabled,
2236                 .sprites_scaled = params->spr.scaled,
2237         };
2238         struct ilk_wm_maximums max;
2239
2240         pipe_wm->pipe_enabled = params->active;
2241         pipe_wm->sprites_enabled = params->spr.enabled;
2242         pipe_wm->sprites_scaled = params->spr.scaled;
2243
2244         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2245         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2246                 max_level = 1;
2247
2248         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2249         if (params->spr.scaled)
2250                 max_level = 0;
2251
2252         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2253
2254         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2255                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2256
2257         /* LP0 watermarks always use 1/2 DDB partitioning */
2258         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2259
2260         /* At least LP0 must be valid */
2261         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2262                 return false;
2263
2264         ilk_compute_wm_reg_maximums(dev, 1, &max);
2265
2266         for (level = 1; level <= max_level; level++) {
2267                 struct intel_wm_level wm = {};
2268
2269                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2270
2271                 /*
2272                  * Disable any watermark level that exceeds the
2273                  * register maximums since such watermarks are
2274                  * always invalid.
2275                  */
2276                 if (!ilk_validate_wm_level(level, &max, &wm))
2277                         break;
2278
2279                 pipe_wm->wm[level] = wm;
2280         }
2281
2282         return true;
2283 }
2284
2285 /*
2286  * Merge the watermarks from all active pipes for a specific level.
2287  */
2288 static void ilk_merge_wm_level(struct drm_device *dev,
2289                                int level,
2290                                struct intel_wm_level *ret_wm)
2291 {
2292         const struct intel_crtc *intel_crtc;
2293
2294         ret_wm->enable = true;
2295
2296         for_each_intel_crtc(dev, intel_crtc) {
2297                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2298                 const struct intel_wm_level *wm = &active->wm[level];
2299
2300                 if (!active->pipe_enabled)
2301                         continue;
2302
2303                 /*
2304                  * The watermark values may have been used in the past,
2305                  * so we must maintain them in the registers for some
2306                  * time even if the level is now disabled.
2307                  */
2308                 if (!wm->enable)
2309                         ret_wm->enable = false;
2310
2311                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2312                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2313                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2314                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2315         }
2316 }
2317
2318 /*
2319  * Merge all low power watermarks for all active pipes.
2320  */
2321 static void ilk_wm_merge(struct drm_device *dev,
2322                          const struct intel_wm_config *config,
2323                          const struct ilk_wm_maximums *max,
2324                          struct intel_pipe_wm *merged)
2325 {
2326         int level, max_level = ilk_wm_max_level(dev);
2327         int last_enabled_level = max_level;
2328
2329         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2330         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2331             config->num_pipes_active > 1)
2332                 return;
2333
2334         /* ILK: FBC WM must be disabled always */
2335         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2336
2337         /* merge each WM1+ level */
2338         for (level = 1; level <= max_level; level++) {
2339                 struct intel_wm_level *wm = &merged->wm[level];
2340
2341                 ilk_merge_wm_level(dev, level, wm);
2342
2343                 if (level > last_enabled_level)
2344                         wm->enable = false;
2345                 else if (!ilk_validate_wm_level(level, max, wm))
2346                         /* make sure all following levels get disabled */
2347                         last_enabled_level = level - 1;
2348
2349                 /*
2350                  * The spec says it is preferred to disable
2351                  * FBC WMs instead of disabling a WM level.
2352                  */
2353                 if (wm->fbc_val > max->fbc) {
2354                         if (wm->enable)
2355                                 merged->fbc_wm_enabled = false;
2356                         wm->fbc_val = 0;
2357                 }
2358         }
2359
2360         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2361         /*
2362          * FIXME this is racy. FBC might get enabled later.
2363          * What we should check here is whether FBC can be
2364          * enabled sometime later.
2365          */
2366         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2367                 for (level = 2; level <= max_level; level++) {
2368                         struct intel_wm_level *wm = &merged->wm[level];
2369
2370                         wm->enable = false;
2371                 }
2372         }
2373 }
2374
2375 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2376 {
2377         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2378         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2379 }
2380
2381 /* The value we need to program into the WM_LPx latency field */
2382 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2383 {
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385
2386         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2387                 return 2 * level;
2388         else
2389                 return dev_priv->wm.pri_latency[level];
2390 }
2391
2392 static void ilk_compute_wm_results(struct drm_device *dev,
2393                                    const struct intel_pipe_wm *merged,
2394                                    enum intel_ddb_partitioning partitioning,
2395                                    struct ilk_wm_values *results)
2396 {
2397         struct intel_crtc *intel_crtc;
2398         int level, wm_lp;
2399
2400         results->enable_fbc_wm = merged->fbc_wm_enabled;
2401         results->partitioning = partitioning;
2402
2403         /* LP1+ register values */
2404         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2405                 const struct intel_wm_level *r;
2406
2407                 level = ilk_wm_lp_to_level(wm_lp, merged);
2408
2409                 r = &merged->wm[level];
2410
2411                 /*
2412                  * Maintain the watermark values even if the level is
2413                  * disabled. Doing otherwise could cause underruns.
2414                  */
2415                 results->wm_lp[wm_lp - 1] =
2416                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2417                         (r->pri_val << WM1_LP_SR_SHIFT) |
2418                         r->cur_val;
2419
2420                 if (r->enable)
2421                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2422
2423                 if (INTEL_INFO(dev)->gen >= 8)
2424                         results->wm_lp[wm_lp - 1] |=
2425                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2426                 else
2427                         results->wm_lp[wm_lp - 1] |=
2428                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2429
2430                 /*
2431                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2432                  * level is disabled. Doing otherwise could cause underruns.
2433                  */
2434                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2435                         WARN_ON(wm_lp != 1);
2436                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2437                 } else
2438                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2439         }
2440
2441         /* LP0 register values */
2442         for_each_intel_crtc(dev, intel_crtc) {
2443                 enum pipe pipe = intel_crtc->pipe;
2444                 const struct intel_wm_level *r =
2445                         &intel_crtc->wm.active.wm[0];
2446
2447                 if (WARN_ON(!r->enable))
2448                         continue;
2449
2450                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2451
2452                 results->wm_pipe[pipe] =
2453                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2454                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2455                         r->cur_val;
2456         }
2457 }
2458
2459 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2460  * case both are at the same level. Prefer r1 in case they're the same. */
2461 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2462                                                   struct intel_pipe_wm *r1,
2463                                                   struct intel_pipe_wm *r2)
2464 {
2465         int level, max_level = ilk_wm_max_level(dev);
2466         int level1 = 0, level2 = 0;
2467
2468         for (level = 1; level <= max_level; level++) {
2469                 if (r1->wm[level].enable)
2470                         level1 = level;
2471                 if (r2->wm[level].enable)
2472                         level2 = level;
2473         }
2474
2475         if (level1 == level2) {
2476                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2477                         return r2;
2478                 else
2479                         return r1;
2480         } else if (level1 > level2) {
2481                 return r1;
2482         } else {
2483                 return r2;
2484         }
2485 }
2486
2487 /* dirty bits used to track which watermarks need changes */
2488 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2489 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2490 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2491 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2492 #define WM_DIRTY_FBC (1 << 24)
2493 #define WM_DIRTY_DDB (1 << 25)
2494
2495 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2496                                          const struct ilk_wm_values *old,
2497                                          const struct ilk_wm_values *new)
2498 {
2499         unsigned int dirty = 0;
2500         enum pipe pipe;
2501         int wm_lp;
2502
2503         for_each_pipe(pipe) {
2504                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2505                         dirty |= WM_DIRTY_LINETIME(pipe);
2506                         /* Must disable LP1+ watermarks too */
2507                         dirty |= WM_DIRTY_LP_ALL;
2508                 }
2509
2510                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2511                         dirty |= WM_DIRTY_PIPE(pipe);
2512                         /* Must disable LP1+ watermarks too */
2513                         dirty |= WM_DIRTY_LP_ALL;
2514                 }
2515         }
2516
2517         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2518                 dirty |= WM_DIRTY_FBC;
2519                 /* Must disable LP1+ watermarks too */
2520                 dirty |= WM_DIRTY_LP_ALL;
2521         }
2522
2523         if (old->partitioning != new->partitioning) {
2524                 dirty |= WM_DIRTY_DDB;
2525                 /* Must disable LP1+ watermarks too */
2526                 dirty |= WM_DIRTY_LP_ALL;
2527         }
2528
2529         /* LP1+ watermarks already deemed dirty, no need to continue */
2530         if (dirty & WM_DIRTY_LP_ALL)
2531                 return dirty;
2532
2533         /* Find the lowest numbered LP1+ watermark in need of an update... */
2534         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2535                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2536                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2537                         break;
2538         }
2539
2540         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2541         for (; wm_lp <= 3; wm_lp++)
2542                 dirty |= WM_DIRTY_LP(wm_lp);
2543
2544         return dirty;
2545 }
2546
2547 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2548                                unsigned int dirty)
2549 {
2550         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2551         bool changed = false;
2552
2553         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2554                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2555                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2556                 changed = true;
2557         }
2558         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2559                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2560                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2561                 changed = true;
2562         }
2563         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2564                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2565                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2566                 changed = true;
2567         }
2568
2569         /*
2570          * Don't touch WM1S_LP_EN here.
2571          * Doing so could cause underruns.
2572          */
2573
2574         return changed;
2575 }
2576
2577 /*
2578  * The spec says we shouldn't write when we don't need, because every write
2579  * causes WMs to be re-evaluated, expending some power.
2580  */
2581 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2582                                 struct ilk_wm_values *results)
2583 {
2584         struct drm_device *dev = dev_priv->dev;
2585         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2586         unsigned int dirty;
2587         uint32_t val;
2588
2589         dirty = ilk_compute_wm_dirty(dev, previous, results);
2590         if (!dirty)
2591                 return;
2592
2593         _ilk_disable_lp_wm(dev_priv, dirty);
2594
2595         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2596                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2597         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2598                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2599         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2600                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2601
2602         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2603                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2604         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2605                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2606         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2607                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2608
2609         if (dirty & WM_DIRTY_DDB) {
2610                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2611                         val = I915_READ(WM_MISC);
2612                         if (results->partitioning == INTEL_DDB_PART_1_2)
2613                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2614                         else
2615                                 val |= WM_MISC_DATA_PARTITION_5_6;
2616                         I915_WRITE(WM_MISC, val);
2617                 } else {
2618                         val = I915_READ(DISP_ARB_CTL2);
2619                         if (results->partitioning == INTEL_DDB_PART_1_2)
2620                                 val &= ~DISP_DATA_PARTITION_5_6;
2621                         else
2622                                 val |= DISP_DATA_PARTITION_5_6;
2623                         I915_WRITE(DISP_ARB_CTL2, val);
2624                 }
2625         }
2626
2627         if (dirty & WM_DIRTY_FBC) {
2628                 val = I915_READ(DISP_ARB_CTL);
2629                 if (results->enable_fbc_wm)
2630                         val &= ~DISP_FBC_WM_DIS;
2631                 else
2632                         val |= DISP_FBC_WM_DIS;
2633                 I915_WRITE(DISP_ARB_CTL, val);
2634         }
2635
2636         if (dirty & WM_DIRTY_LP(1) &&
2637             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2638                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2639
2640         if (INTEL_INFO(dev)->gen >= 7) {
2641                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2642                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2643                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2644                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2645         }
2646
2647         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2648                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2649         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2650                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2651         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2652                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2653
2654         dev_priv->wm.hw = *results;
2655 }
2656
2657 static bool ilk_disable_lp_wm(struct drm_device *dev)
2658 {
2659         struct drm_i915_private *dev_priv = dev->dev_private;
2660
2661         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2662 }
2663
2664 static void ilk_update_wm(struct drm_crtc *crtc)
2665 {
2666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667         struct drm_device *dev = crtc->dev;
2668         struct drm_i915_private *dev_priv = dev->dev_private;
2669         struct ilk_wm_maximums max;
2670         struct ilk_pipe_wm_parameters params = {};
2671         struct ilk_wm_values results = {};
2672         enum intel_ddb_partitioning partitioning;
2673         struct intel_pipe_wm pipe_wm = {};
2674         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2675         struct intel_wm_config config = {};
2676
2677         ilk_compute_wm_parameters(crtc, &params);
2678
2679         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2680
2681         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2682                 return;
2683
2684         intel_crtc->wm.active = pipe_wm;
2685
2686         ilk_compute_wm_config(dev, &config);
2687
2688         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2689         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2690
2691         /* 5/6 split only in single pipe config on IVB+ */
2692         if (INTEL_INFO(dev)->gen >= 7 &&
2693             config.num_pipes_active == 1 && config.sprites_enabled) {
2694                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2695                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2696
2697                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2698         } else {
2699                 best_lp_wm = &lp_wm_1_2;
2700         }
2701
2702         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2703                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2704
2705         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2706
2707         ilk_write_wm_values(dev_priv, &results);
2708 }
2709
2710 static void ilk_update_sprite_wm(struct drm_plane *plane,
2711                                      struct drm_crtc *crtc,
2712                                      uint32_t sprite_width, int pixel_size,
2713                                      bool enabled, bool scaled)
2714 {
2715         struct drm_device *dev = plane->dev;
2716         struct intel_plane *intel_plane = to_intel_plane(plane);
2717
2718         intel_plane->wm.enabled = enabled;
2719         intel_plane->wm.scaled = scaled;
2720         intel_plane->wm.horiz_pixels = sprite_width;
2721         intel_plane->wm.bytes_per_pixel = pixel_size;
2722
2723         /*
2724          * IVB workaround: must disable low power watermarks for at least
2725          * one frame before enabling scaling.  LP watermarks can be re-enabled
2726          * when scaling is disabled.
2727          *
2728          * WaCxSRDisabledForSpriteScaling:ivb
2729          */
2730         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2731                 intel_wait_for_vblank(dev, intel_plane->pipe);
2732
2733         ilk_update_wm(crtc);
2734 }
2735
2736 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2737 {
2738         struct drm_device *dev = crtc->dev;
2739         struct drm_i915_private *dev_priv = dev->dev_private;
2740         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2743         enum pipe pipe = intel_crtc->pipe;
2744         static const unsigned int wm0_pipe_reg[] = {
2745                 [PIPE_A] = WM0_PIPEA_ILK,
2746                 [PIPE_B] = WM0_PIPEB_ILK,
2747                 [PIPE_C] = WM0_PIPEC_IVB,
2748         };
2749
2750         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2751         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2752                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2753
2754         active->pipe_enabled = intel_crtc_active(crtc);
2755
2756         if (active->pipe_enabled) {
2757                 u32 tmp = hw->wm_pipe[pipe];
2758
2759                 /*
2760                  * For active pipes LP0 watermark is marked as
2761                  * enabled, and LP1+ watermaks as disabled since
2762                  * we can't really reverse compute them in case
2763                  * multiple pipes are active.
2764                  */
2765                 active->wm[0].enable = true;
2766                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2767                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2768                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2769                 active->linetime = hw->wm_linetime[pipe];
2770         } else {
2771                 int level, max_level = ilk_wm_max_level(dev);
2772
2773                 /*
2774                  * For inactive pipes, all watermark levels
2775                  * should be marked as enabled but zeroed,
2776                  * which is what we'd compute them to.
2777                  */
2778                 for (level = 0; level <= max_level; level++)
2779                         active->wm[level].enable = true;
2780         }
2781 }
2782
2783 void ilk_wm_get_hw_state(struct drm_device *dev)
2784 {
2785         struct drm_i915_private *dev_priv = dev->dev_private;
2786         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2787         struct drm_crtc *crtc;
2788
2789         for_each_crtc(dev, crtc)
2790                 ilk_pipe_wm_get_hw_state(crtc);
2791
2792         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2793         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2794         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2795
2796         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2797         if (INTEL_INFO(dev)->gen >= 7) {
2798                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2799                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2800         }
2801
2802         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2803                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2804                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2805         else if (IS_IVYBRIDGE(dev))
2806                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2807                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2808
2809         hw->enable_fbc_wm =
2810                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2811 }
2812
2813 /**
2814  * intel_update_watermarks - update FIFO watermark values based on current modes
2815  *
2816  * Calculate watermark values for the various WM regs based on current mode
2817  * and plane configuration.
2818  *
2819  * There are several cases to deal with here:
2820  *   - normal (i.e. non-self-refresh)
2821  *   - self-refresh (SR) mode
2822  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2823  *   - lines are small relative to FIFO size (buffer can hold more than 2
2824  *     lines), so need to account for TLB latency
2825  *
2826  *   The normal calculation is:
2827  *     watermark = dotclock * bytes per pixel * latency
2828  *   where latency is platform & configuration dependent (we assume pessimal
2829  *   values here).
2830  *
2831  *   The SR calculation is:
2832  *     watermark = (trunc(latency/line time)+1) * surface width *
2833  *       bytes per pixel
2834  *   where
2835  *     line time = htotal / dotclock
2836  *     surface width = hdisplay for normal plane and 64 for cursor
2837  *   and latency is assumed to be high, as above.
2838  *
2839  * The final value programmed to the register should always be rounded up,
2840  * and include an extra 2 entries to account for clock crossings.
2841  *
2842  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2843  * to set the non-SR watermarks to 8.
2844  */
2845 void intel_update_watermarks(struct drm_crtc *crtc)
2846 {
2847         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2848
2849         if (dev_priv->display.update_wm)
2850                 dev_priv->display.update_wm(crtc);
2851 }
2852
2853 void intel_update_sprite_watermarks(struct drm_plane *plane,
2854                                     struct drm_crtc *crtc,
2855                                     uint32_t sprite_width, int pixel_size,
2856                                     bool enabled, bool scaled)
2857 {
2858         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2859
2860         if (dev_priv->display.update_sprite_wm)
2861                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2862                                                    pixel_size, enabled, scaled);
2863 }
2864
2865 static struct drm_i915_gem_object *
2866 intel_alloc_context_page(struct drm_device *dev)
2867 {
2868         struct drm_i915_gem_object *ctx;
2869         int ret;
2870
2871         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2872
2873         ctx = i915_gem_alloc_object(dev, 4096);
2874         if (!ctx) {
2875                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2876                 return NULL;
2877         }
2878
2879         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2880         if (ret) {
2881                 DRM_ERROR("failed to pin power context: %d\n", ret);
2882                 goto err_unref;
2883         }
2884
2885         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2886         if (ret) {
2887                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2888                 goto err_unpin;
2889         }
2890
2891         return ctx;
2892
2893 err_unpin:
2894         i915_gem_object_ggtt_unpin(ctx);
2895 err_unref:
2896         drm_gem_object_unreference(&ctx->base);
2897         return NULL;
2898 }
2899
2900 /**
2901  * Lock protecting IPS related data structures
2902  */
2903 DEFINE_SPINLOCK(mchdev_lock);
2904
2905 /* Global for IPS driver to get at the current i915 device. Protected by
2906  * mchdev_lock. */
2907 static struct drm_i915_private *i915_mch_dev;
2908
2909 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2910 {
2911         struct drm_i915_private *dev_priv = dev->dev_private;
2912         u16 rgvswctl;
2913
2914         assert_spin_locked(&mchdev_lock);
2915
2916         rgvswctl = I915_READ16(MEMSWCTL);
2917         if (rgvswctl & MEMCTL_CMD_STS) {
2918                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2919                 return false; /* still busy with another command */
2920         }
2921
2922         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2923                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2924         I915_WRITE16(MEMSWCTL, rgvswctl);
2925         POSTING_READ16(MEMSWCTL);
2926
2927         rgvswctl |= MEMCTL_CMD_STS;
2928         I915_WRITE16(MEMSWCTL, rgvswctl);
2929
2930         return true;
2931 }
2932
2933 static void ironlake_enable_drps(struct drm_device *dev)
2934 {
2935         struct drm_i915_private *dev_priv = dev->dev_private;
2936         u32 rgvmodectl = I915_READ(MEMMODECTL);
2937         u8 fmax, fmin, fstart, vstart;
2938
2939         spin_lock_irq(&mchdev_lock);
2940
2941         /* Enable temp reporting */
2942         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2943         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2944
2945         /* 100ms RC evaluation intervals */
2946         I915_WRITE(RCUPEI, 100000);
2947         I915_WRITE(RCDNEI, 100000);
2948
2949         /* Set max/min thresholds to 90ms and 80ms respectively */
2950         I915_WRITE(RCBMAXAVG, 90000);
2951         I915_WRITE(RCBMINAVG, 80000);
2952
2953         I915_WRITE(MEMIHYST, 1);
2954
2955         /* Set up min, max, and cur for interrupt handling */
2956         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2957         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2958         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2959                 MEMMODE_FSTART_SHIFT;
2960
2961         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2962                 PXVFREQ_PX_SHIFT;
2963
2964         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2965         dev_priv->ips.fstart = fstart;
2966
2967         dev_priv->ips.max_delay = fstart;
2968         dev_priv->ips.min_delay = fmin;
2969         dev_priv->ips.cur_delay = fstart;
2970
2971         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2972                          fmax, fmin, fstart);
2973
2974         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2975
2976         /*
2977          * Interrupts will be enabled in ironlake_irq_postinstall
2978          */
2979
2980         I915_WRITE(VIDSTART, vstart);
2981         POSTING_READ(VIDSTART);
2982
2983         rgvmodectl |= MEMMODE_SWMODE_EN;
2984         I915_WRITE(MEMMODECTL, rgvmodectl);
2985
2986         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2987                 DRM_ERROR("stuck trying to change perf mode\n");
2988         mdelay(1);
2989
2990         ironlake_set_drps(dev, fstart);
2991
2992         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2993                 I915_READ(0x112e0);
2994         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2995         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2996         getrawmonotonic(&dev_priv->ips.last_time2);
2997
2998         spin_unlock_irq(&mchdev_lock);
2999 }
3000
3001 static void ironlake_disable_drps(struct drm_device *dev)
3002 {
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         u16 rgvswctl;
3005
3006         spin_lock_irq(&mchdev_lock);
3007
3008         rgvswctl = I915_READ16(MEMSWCTL);
3009
3010         /* Ack interrupts, disable EFC interrupt */
3011         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3012         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3013         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3014         I915_WRITE(DEIIR, DE_PCU_EVENT);
3015         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3016
3017         /* Go back to the starting frequency */
3018         ironlake_set_drps(dev, dev_priv->ips.fstart);
3019         mdelay(1);
3020         rgvswctl |= MEMCTL_CMD_STS;
3021         I915_WRITE(MEMSWCTL, rgvswctl);
3022         mdelay(1);
3023
3024         spin_unlock_irq(&mchdev_lock);
3025 }
3026
3027 /* There's a funny hw issue where the hw returns all 0 when reading from
3028  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3029  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3030  * all limits and the gpu stuck at whatever frequency it is at atm).
3031  */
3032 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3033 {
3034         u32 limits;
3035
3036         /* Only set the down limit when we've reached the lowest level to avoid
3037          * getting more interrupts, otherwise leave this clear. This prevents a
3038          * race in the hw when coming out of rc6: There's a tiny window where
3039          * the hw runs at the minimal clock before selecting the desired
3040          * frequency, if the down threshold expires in that window we will not
3041          * receive a down interrupt. */
3042         limits = dev_priv->rps.max_freq_softlimit << 24;
3043         if (val <= dev_priv->rps.min_freq_softlimit)
3044                 limits |= dev_priv->rps.min_freq_softlimit << 16;
3045
3046         return limits;
3047 }
3048
3049 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3050 {
3051         int new_power;
3052
3053         new_power = dev_priv->rps.power;
3054         switch (dev_priv->rps.power) {
3055         case LOW_POWER:
3056                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3057                         new_power = BETWEEN;
3058                 break;
3059
3060         case BETWEEN:
3061                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3062                         new_power = LOW_POWER;
3063                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3064                         new_power = HIGH_POWER;
3065                 break;
3066
3067         case HIGH_POWER:
3068                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3069                         new_power = BETWEEN;
3070                 break;
3071         }
3072         /* Max/min bins are special */
3073         if (val == dev_priv->rps.min_freq_softlimit)
3074                 new_power = LOW_POWER;
3075         if (val == dev_priv->rps.max_freq_softlimit)
3076                 new_power = HIGH_POWER;
3077         if (new_power == dev_priv->rps.power)
3078                 return;
3079
3080         /* Note the units here are not exactly 1us, but 1280ns. */
3081         switch (new_power) {
3082         case LOW_POWER:
3083                 /* Upclock if more than 95% busy over 16ms */
3084                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3085                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3086
3087                 /* Downclock if less than 85% busy over 32ms */
3088                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3089                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3090
3091                 I915_WRITE(GEN6_RP_CONTROL,
3092                            GEN6_RP_MEDIA_TURBO |
3093                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3094                            GEN6_RP_MEDIA_IS_GFX |
3095                            GEN6_RP_ENABLE |
3096                            GEN6_RP_UP_BUSY_AVG |
3097                            GEN6_RP_DOWN_IDLE_AVG);
3098                 break;
3099
3100         case BETWEEN:
3101                 /* Upclock if more than 90% busy over 13ms */
3102                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3103                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3104
3105                 /* Downclock if less than 75% busy over 32ms */
3106                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3107                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3108
3109                 I915_WRITE(GEN6_RP_CONTROL,
3110                            GEN6_RP_MEDIA_TURBO |
3111                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3112                            GEN6_RP_MEDIA_IS_GFX |
3113                            GEN6_RP_ENABLE |
3114                            GEN6_RP_UP_BUSY_AVG |
3115                            GEN6_RP_DOWN_IDLE_AVG);
3116                 break;
3117
3118         case HIGH_POWER:
3119                 /* Upclock if more than 85% busy over 10ms */
3120                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3121                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3122
3123                 /* Downclock if less than 60% busy over 32ms */
3124                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3125                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3126
3127                 I915_WRITE(GEN6_RP_CONTROL,
3128                            GEN6_RP_MEDIA_TURBO |
3129                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3130                            GEN6_RP_MEDIA_IS_GFX |
3131                            GEN6_RP_ENABLE |
3132                            GEN6_RP_UP_BUSY_AVG |
3133                            GEN6_RP_DOWN_IDLE_AVG);
3134                 break;
3135         }
3136
3137         dev_priv->rps.power = new_power;
3138         dev_priv->rps.last_adj = 0;
3139 }
3140
3141 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3142 {
3143         u32 mask = 0;
3144
3145         if (val > dev_priv->rps.min_freq_softlimit)
3146                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3147         if (val < dev_priv->rps.max_freq_softlimit)
3148                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3149
3150         /* IVB and SNB hard hangs on looping batchbuffer
3151          * if GEN6_PM_UP_EI_EXPIRED is masked.
3152          */
3153         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3154                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3155
3156         if (IS_GEN8(dev_priv->dev))
3157                 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3158
3159         return ~mask;
3160 }
3161
3162 /* gen6_set_rps is called to update the frequency request, but should also be
3163  * called when the range (min_delay and max_delay) is modified so that we can
3164  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3165 void gen6_set_rps(struct drm_device *dev, u8 val)
3166 {
3167         struct drm_i915_private *dev_priv = dev->dev_private;
3168
3169         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3170         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3171         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3172
3173         /* min/max delay may still have been modified so be sure to
3174          * write the limits value.
3175          */
3176         if (val != dev_priv->rps.cur_freq) {
3177                 gen6_set_rps_thresholds(dev_priv, val);
3178
3179                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3180                         I915_WRITE(GEN6_RPNSWREQ,
3181                                    HSW_FREQUENCY(val));
3182                 else
3183                         I915_WRITE(GEN6_RPNSWREQ,
3184                                    GEN6_FREQUENCY(val) |
3185                                    GEN6_OFFSET(0) |
3186                                    GEN6_AGGRESSIVE_TURBO);
3187         }
3188
3189         /* Make sure we continue to get interrupts
3190          * until we hit the minimum or maximum frequencies.
3191          */
3192         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3193         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3194
3195         POSTING_READ(GEN6_RPNSWREQ);
3196
3197         dev_priv->rps.cur_freq = val;
3198         trace_intel_gpu_freq_change(val * 50);
3199 }
3200
3201 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3202  *
3203  * * If Gfx is Idle, then
3204  * 1. Mask Turbo interrupts
3205  * 2. Bring up Gfx clock
3206  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3207  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3208  * 5. Unmask Turbo interrupts
3209 */
3210 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3211 {
3212         /*
3213          * When we are idle.  Drop to min voltage state.
3214          */
3215
3216         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3217                 return;
3218
3219         /* Mask turbo interrupt so that they will not come in between */
3220         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3221
3222         vlv_force_gfx_clock(dev_priv, true);
3223
3224         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3225
3226         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3227                                         dev_priv->rps.min_freq_softlimit);
3228
3229         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3230                                 & GENFREQSTATUS) == 0, 5))
3231                 DRM_ERROR("timed out waiting for Punit\n");
3232
3233         vlv_force_gfx_clock(dev_priv, false);
3234
3235         I915_WRITE(GEN6_PMINTRMSK,
3236                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3237 }
3238
3239 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3240 {
3241         struct drm_device *dev = dev_priv->dev;
3242
3243         mutex_lock(&dev_priv->rps.hw_lock);
3244         if (dev_priv->rps.enabled) {
3245                 if (IS_VALLEYVIEW(dev))
3246                         vlv_set_rps_idle(dev_priv);
3247                 else
3248                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3249                 dev_priv->rps.last_adj = 0;
3250         }
3251         mutex_unlock(&dev_priv->rps.hw_lock);
3252 }
3253
3254 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3255 {
3256         struct drm_device *dev = dev_priv->dev;
3257
3258         mutex_lock(&dev_priv->rps.hw_lock);
3259         if (dev_priv->rps.enabled) {
3260                 if (IS_VALLEYVIEW(dev))
3261                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3262                 else
3263                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3264                 dev_priv->rps.last_adj = 0;
3265         }
3266         mutex_unlock(&dev_priv->rps.hw_lock);
3267 }
3268
3269 void valleyview_set_rps(struct drm_device *dev, u8 val)
3270 {
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272
3273         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3274         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3275         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3276
3277         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3278                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3279                          dev_priv->rps.cur_freq,
3280                          vlv_gpu_freq(dev_priv, val), val);
3281
3282         if (val != dev_priv->rps.cur_freq)
3283                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3284
3285         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3286
3287         dev_priv->rps.cur_freq = val;
3288         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3289 }
3290
3291 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3292 {
3293         struct drm_i915_private *dev_priv = dev->dev_private;
3294
3295         I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3296         I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3297                                    ~dev_priv->pm_rps_events);
3298         /* Complete PM interrupt masking here doesn't race with the rps work
3299          * item again unmasking PM interrupts because that is using a different
3300          * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3301          * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3302          * gen8_enable_rps will clean up. */
3303
3304         spin_lock_irq(&dev_priv->irq_lock);
3305         dev_priv->rps.pm_iir = 0;
3306         spin_unlock_irq(&dev_priv->irq_lock);
3307
3308         I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3309 }
3310
3311 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3312 {
3313         struct drm_i915_private *dev_priv = dev->dev_private;
3314
3315         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3316         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3317                                 ~dev_priv->pm_rps_events);
3318         /* Complete PM interrupt masking here doesn't race with the rps work
3319          * item again unmasking PM interrupts because that is using a different
3320          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3321          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3322
3323         spin_lock_irq(&dev_priv->irq_lock);
3324         dev_priv->rps.pm_iir = 0;
3325         spin_unlock_irq(&dev_priv->irq_lock);
3326
3327         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3328 }
3329
3330 static void gen6_disable_rps(struct drm_device *dev)
3331 {
3332         struct drm_i915_private *dev_priv = dev->dev_private;
3333
3334         I915_WRITE(GEN6_RC_CONTROL, 0);
3335         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3336
3337         if (IS_BROADWELL(dev))
3338                 gen8_disable_rps_interrupts(dev);
3339         else
3340                 gen6_disable_rps_interrupts(dev);
3341 }
3342
3343 static void valleyview_disable_rps(struct drm_device *dev)
3344 {
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346
3347         I915_WRITE(GEN6_RC_CONTROL, 0);
3348
3349         gen6_disable_rps_interrupts(dev);
3350 }
3351
3352 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3353 {
3354         if (IS_VALLEYVIEW(dev)) {
3355                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3356                         mode = GEN6_RC_CTL_RC6_ENABLE;
3357                 else
3358                         mode = 0;
3359         }
3360         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3361                  (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3362                  (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3363                  (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3364 }
3365
3366 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3367 {
3368         /* No RC6 before Ironlake */
3369         if (INTEL_INFO(dev)->gen < 5)
3370                 return 0;
3371
3372         /* RC6 is only on Ironlake mobile not on desktop */
3373         if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3374                 return 0;
3375
3376         /* Respect the kernel parameter if it is set */
3377         if (enable_rc6 >= 0) {
3378                 int mask;
3379
3380                 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3381                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3382                                INTEL_RC6pp_ENABLE;
3383                 else
3384                         mask = INTEL_RC6_ENABLE;
3385
3386                 if ((enable_rc6 & mask) != enable_rc6)
3387                         DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3388                                  enable_rc6 & mask, enable_rc6, mask);
3389
3390                 return enable_rc6 & mask;
3391         }
3392
3393         /* Disable RC6 on Ironlake */
3394         if (INTEL_INFO(dev)->gen == 5)
3395                 return 0;
3396
3397         if (IS_IVYBRIDGE(dev))
3398                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3399
3400         return INTEL_RC6_ENABLE;
3401 }
3402
3403 int intel_enable_rc6(const struct drm_device *dev)
3404 {
3405         return i915.enable_rc6;
3406 }
3407
3408 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3409 {
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411
3412         spin_lock_irq(&dev_priv->irq_lock);
3413         WARN_ON(dev_priv->rps.pm_iir);
3414         bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3415         I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3416         spin_unlock_irq(&dev_priv->irq_lock);
3417 }
3418
3419 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3420 {
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422
3423         spin_lock_irq(&dev_priv->irq_lock);
3424         WARN_ON(dev_priv->rps.pm_iir);
3425         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3426         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3427         spin_unlock_irq(&dev_priv->irq_lock);
3428 }
3429
3430 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3431 {
3432         /* All of these values are in units of 50MHz */
3433         dev_priv->rps.cur_freq          = 0;
3434         /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3435         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
3436         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
3437         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
3438         /* XXX: only BYT has a special efficient freq */
3439         dev_priv->rps.efficient_freq    = dev_priv->rps.rp1_freq;
3440         /* hw_max = RP0 until we check for overclocking */
3441         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
3442
3443         /* Preserve min/max settings in case of re-init */
3444         if (dev_priv->rps.max_freq_softlimit == 0)
3445                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3446
3447         if (dev_priv->rps.min_freq_softlimit == 0)
3448                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3449 }
3450
3451 static void gen8_enable_rps(struct drm_device *dev)
3452 {
3453         struct drm_i915_private *dev_priv = dev->dev_private;
3454         struct intel_engine_cs *ring;
3455         uint32_t rc6_mask = 0, rp_state_cap;
3456         int unused;
3457
3458         /* 1a: Software RC state - RC0 */
3459         I915_WRITE(GEN6_RC_STATE, 0);
3460
3461         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3462          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3463         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3464
3465         /* 2a: Disable RC states. */
3466         I915_WRITE(GEN6_RC_CONTROL, 0);
3467
3468         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3469         parse_rp_state_cap(dev_priv, rp_state_cap);
3470
3471         /* 2b: Program RC6 thresholds.*/
3472         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3473         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3474         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3475         for_each_ring(ring, dev_priv, unused)
3476                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3477         I915_WRITE(GEN6_RC_SLEEP, 0);
3478         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3479
3480         /* 3: Enable RC6 */
3481         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3482                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3483         intel_print_rc6_info(dev, rc6_mask);
3484         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3485                                     GEN6_RC_CTL_EI_MODE(1) |
3486                                     rc6_mask);
3487
3488         /* 4 Program defaults and thresholds for RPS*/
3489         I915_WRITE(GEN6_RPNSWREQ,
3490                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3491         I915_WRITE(GEN6_RC_VIDEO_FREQ,
3492                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3493         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3494         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3495
3496         /* Docs recommend 900MHz, and 300 MHz respectively */
3497         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3498                    dev_priv->rps.max_freq_softlimit << 24 |
3499                    dev_priv->rps.min_freq_softlimit << 16);
3500
3501         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3502         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3503         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3504         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3505
3506         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3507
3508         /* 5: Enable RPS */
3509         I915_WRITE(GEN6_RP_CONTROL,
3510                    GEN6_RP_MEDIA_TURBO |
3511                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3512                    GEN6_RP_MEDIA_IS_GFX |
3513                    GEN6_RP_ENABLE |
3514                    GEN6_RP_UP_BUSY_AVG |
3515                    GEN6_RP_DOWN_IDLE_AVG);
3516
3517         /* 6: Ring frequency + overclocking (our driver does this later */
3518
3519         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3520
3521         gen8_enable_rps_interrupts(dev);
3522
3523         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3524 }
3525
3526 static void gen6_enable_rps(struct drm_device *dev)
3527 {
3528         struct drm_i915_private *dev_priv = dev->dev_private;
3529         struct intel_engine_cs *ring;
3530         u32 rp_state_cap;
3531         u32 gt_perf_status;
3532         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3533         u32 gtfifodbg;
3534         int rc6_mode;
3535         int i, ret;
3536
3537         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3538
3539         /* Here begins a magic sequence of register writes to enable
3540          * auto-downclocking.
3541          *
3542          * Perhaps there might be some value in exposing these to
3543          * userspace...
3544          */
3545         I915_WRITE(GEN6_RC_STATE, 0);
3546
3547         /* Clear the DBG now so we don't confuse earlier errors */
3548         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3549                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3550                 I915_WRITE(GTFIFODBG, gtfifodbg);
3551         }
3552
3553         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3554
3555         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3556         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3557
3558         parse_rp_state_cap(dev_priv, rp_state_cap);
3559
3560         /* disable the counters and set deterministic thresholds */
3561         I915_WRITE(GEN6_RC_CONTROL, 0);
3562
3563         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3564         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3565         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3566         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3567         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3568
3569         for_each_ring(ring, dev_priv, i)
3570                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3571
3572         I915_WRITE(GEN6_RC_SLEEP, 0);
3573         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3574         if (IS_IVYBRIDGE(dev))
3575                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3576         else
3577                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3578         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3579         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3580
3581         /* Check if we are enabling RC6 */
3582         rc6_mode = intel_enable_rc6(dev_priv->dev);
3583         if (rc6_mode & INTEL_RC6_ENABLE)
3584                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3585
3586         /* We don't use those on Haswell */
3587         if (!IS_HASWELL(dev)) {
3588                 if (rc6_mode & INTEL_RC6p_ENABLE)
3589                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3590
3591                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3592                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3593         }
3594
3595         intel_print_rc6_info(dev, rc6_mask);
3596
3597         I915_WRITE(GEN6_RC_CONTROL,
3598                    rc6_mask |
3599                    GEN6_RC_CTL_EI_MODE(1) |
3600                    GEN6_RC_CTL_HW_ENABLE);
3601
3602         /* Power down if completely idle for over 50ms */
3603         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3604         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3605
3606         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3607         if (ret)
3608                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3609
3610         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3611         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3612                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3613                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3614                                  (pcu_mbox & 0xff) * 50);
3615                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3616         }
3617
3618         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3619         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3620
3621         gen6_enable_rps_interrupts(dev);
3622
3623         rc6vids = 0;
3624         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3625         if (IS_GEN6(dev) && ret) {
3626                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3627         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3628                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3629                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3630                 rc6vids &= 0xffff00;
3631                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3632                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3633                 if (ret)
3634                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3635         }
3636
3637         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3638 }
3639
3640 static void __gen6_update_ring_freq(struct drm_device *dev)
3641 {
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         int min_freq = 15;
3644         unsigned int gpu_freq;
3645         unsigned int max_ia_freq, min_ring_freq;
3646         int scaling_factor = 180;
3647         struct cpufreq_policy *policy;
3648
3649         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3650
3651         policy = cpufreq_cpu_get(0);
3652         if (policy) {
3653                 max_ia_freq = policy->cpuinfo.max_freq;
3654                 cpufreq_cpu_put(policy);
3655         } else {
3656                 /*
3657                  * Default to measured freq if none found, PCU will ensure we
3658                  * don't go over
3659                  */
3660                 max_ia_freq = tsc_khz;
3661         }
3662
3663         /* Convert from kHz to MHz */
3664         max_ia_freq /= 1000;
3665
3666         min_ring_freq = I915_READ(DCLK) & 0xf;
3667         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3668         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3669
3670         /*
3671          * For each potential GPU frequency, load a ring frequency we'd like
3672          * to use for memory access.  We do this by specifying the IA frequency
3673          * the PCU should use as a reference to determine the ring frequency.
3674          */
3675         for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3676              gpu_freq--) {
3677                 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3678                 unsigned int ia_freq = 0, ring_freq = 0;
3679
3680                 if (INTEL_INFO(dev)->gen >= 8) {
3681                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3682                         ring_freq = max(min_ring_freq, gpu_freq);
3683                 } else if (IS_HASWELL(dev)) {
3684                         ring_freq = mult_frac(gpu_freq, 5, 4);
3685                         ring_freq = max(min_ring_freq, ring_freq);
3686                         /* leave ia_freq as the default, chosen by cpufreq */
3687                 } else {
3688                         /* On older processors, there is no separate ring
3689                          * clock domain, so in order to boost the bandwidth
3690                          * of the ring, we need to upclock the CPU (ia_freq).
3691                          *
3692                          * For GPU frequencies less than 750MHz,
3693                          * just use the lowest ring freq.
3694                          */
3695                         if (gpu_freq < min_freq)
3696                                 ia_freq = 800;
3697                         else
3698                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3699                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3700                 }
3701
3702                 sandybridge_pcode_write(dev_priv,
3703                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3704                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3705                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3706                                         gpu_freq);
3707         }
3708 }
3709
3710 void gen6_update_ring_freq(struct drm_device *dev)
3711 {
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713
3714         if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3715                 return;
3716
3717         mutex_lock(&dev_priv->rps.hw_lock);
3718         __gen6_update_ring_freq(dev);
3719         mutex_unlock(&dev_priv->rps.hw_lock);
3720 }
3721
3722 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3723 {
3724         u32 val, rp0;
3725
3726         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3727
3728         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3729         /* Clamp to max */
3730         rp0 = min_t(u32, rp0, 0xea);
3731
3732         return rp0;
3733 }
3734
3735 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3736 {
3737         u32 val, rpe;
3738
3739         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3740         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3741         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3742         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3743
3744         return rpe;
3745 }
3746
3747 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3748 {
3749         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3750 }
3751
3752 /* Check that the pctx buffer wasn't move under us. */
3753 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3754 {
3755         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3756
3757         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3758                              dev_priv->vlv_pctx->stolen->start);
3759 }
3760
3761 static void valleyview_setup_pctx(struct drm_device *dev)
3762 {
3763         struct drm_i915_private *dev_priv = dev->dev_private;
3764         struct drm_i915_gem_object *pctx;
3765         unsigned long pctx_paddr;
3766         u32 pcbr;
3767         int pctx_size = 24*1024;
3768
3769         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3770
3771         pcbr = I915_READ(VLV_PCBR);
3772         if (pcbr) {
3773                 /* BIOS set it up already, grab the pre-alloc'd space */
3774                 int pcbr_offset;
3775
3776                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3777                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3778                                                                       pcbr_offset,
3779                                                                       I915_GTT_OFFSET_NONE,
3780                                                                       pctx_size);
3781                 goto out;
3782         }
3783
3784         /*
3785          * From the Gunit register HAS:
3786          * The Gfx driver is expected to program this register and ensure
3787          * proper allocation within Gfx stolen memory.  For example, this
3788          * register should be programmed such than the PCBR range does not
3789          * overlap with other ranges, such as the frame buffer, protected
3790          * memory, or any other relevant ranges.
3791          */
3792         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3793         if (!pctx) {
3794                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3795                 return;
3796         }
3797
3798         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3799         I915_WRITE(VLV_PCBR, pctx_paddr);
3800
3801 out:
3802         dev_priv->vlv_pctx = pctx;
3803 }
3804
3805 static void valleyview_cleanup_pctx(struct drm_device *dev)
3806 {
3807         struct drm_i915_private *dev_priv = dev->dev_private;
3808
3809         if (WARN_ON(!dev_priv->vlv_pctx))
3810                 return;
3811
3812         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3813         dev_priv->vlv_pctx = NULL;
3814 }
3815
3816 static void valleyview_init_gt_powersave(struct drm_device *dev)
3817 {
3818         struct drm_i915_private *dev_priv = dev->dev_private;
3819
3820         valleyview_setup_pctx(dev);
3821
3822         mutex_lock(&dev_priv->rps.hw_lock);
3823
3824         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3825         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3826         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3827                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3828                          dev_priv->rps.max_freq);
3829
3830         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3831         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3832                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3833                          dev_priv->rps.efficient_freq);
3834
3835         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3836         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3837                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3838                          dev_priv->rps.min_freq);
3839
3840         /* Preserve min/max settings in case of re-init */
3841         if (dev_priv->rps.max_freq_softlimit == 0)
3842                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3843
3844         if (dev_priv->rps.min_freq_softlimit == 0)
3845                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3846
3847         mutex_unlock(&dev_priv->rps.hw_lock);
3848 }
3849
3850 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3851 {
3852         valleyview_cleanup_pctx(dev);
3853 }
3854
3855 static void valleyview_enable_rps(struct drm_device *dev)
3856 {
3857         struct drm_i915_private *dev_priv = dev->dev_private;
3858         struct intel_engine_cs *ring;
3859         u32 gtfifodbg, val, rc6_mode = 0;
3860         int i;
3861
3862         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3863
3864         valleyview_check_pctx(dev_priv);
3865
3866         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3867                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3868                                  gtfifodbg);
3869                 I915_WRITE(GTFIFODBG, gtfifodbg);
3870         }
3871
3872         /* If VLV, Forcewake all wells, else re-direct to regular path */
3873         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3874
3875         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3876         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3877         I915_WRITE(GEN6_RP_UP_EI, 66000);
3878         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3879
3880         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3881
3882         I915_WRITE(GEN6_RP_CONTROL,
3883                    GEN6_RP_MEDIA_TURBO |
3884                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3885                    GEN6_RP_MEDIA_IS_GFX |
3886                    GEN6_RP_ENABLE |
3887                    GEN6_RP_UP_BUSY_AVG |
3888                    GEN6_RP_DOWN_IDLE_CONT);
3889
3890         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3891         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3892         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3893
3894         for_each_ring(ring, dev_priv, i)
3895                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3896
3897         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3898
3899         /* allows RC6 residency counter to work */
3900         I915_WRITE(VLV_COUNTER_CONTROL,
3901                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3902                                       VLV_MEDIA_RC6_COUNT_EN |
3903                                       VLV_RENDER_RC6_COUNT_EN));
3904         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3905                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3906
3907         intel_print_rc6_info(dev, rc6_mode);
3908
3909         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3910
3911         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3912
3913         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3914         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3915
3916         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3917         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3918                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3919                          dev_priv->rps.cur_freq);
3920
3921         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3922                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3923                          dev_priv->rps.efficient_freq);
3924
3925         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3926
3927         gen6_enable_rps_interrupts(dev);
3928
3929         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3930 }
3931
3932 void ironlake_teardown_rc6(struct drm_device *dev)
3933 {
3934         struct drm_i915_private *dev_priv = dev->dev_private;
3935
3936         if (dev_priv->ips.renderctx) {
3937                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3938                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3939                 dev_priv->ips.renderctx = NULL;
3940         }
3941
3942         if (dev_priv->ips.pwrctx) {
3943                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3944                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3945                 dev_priv->ips.pwrctx = NULL;
3946         }
3947 }
3948
3949 static void ironlake_disable_rc6(struct drm_device *dev)
3950 {
3951         struct drm_i915_private *dev_priv = dev->dev_private;
3952
3953         if (I915_READ(PWRCTXA)) {
3954                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3955                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3956                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3957                          50);
3958
3959                 I915_WRITE(PWRCTXA, 0);
3960                 POSTING_READ(PWRCTXA);
3961
3962                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3963                 POSTING_READ(RSTDBYCTL);
3964         }
3965 }
3966
3967 static int ironlake_setup_rc6(struct drm_device *dev)
3968 {
3969         struct drm_i915_private *dev_priv = dev->dev_private;
3970
3971         if (dev_priv->ips.renderctx == NULL)
3972                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3973         if (!dev_priv->ips.renderctx)
3974                 return -ENOMEM;
3975
3976         if (dev_priv->ips.pwrctx == NULL)
3977                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3978         if (!dev_priv->ips.pwrctx) {
3979                 ironlake_teardown_rc6(dev);
3980                 return -ENOMEM;
3981         }
3982
3983         return 0;
3984 }
3985
3986 static void ironlake_enable_rc6(struct drm_device *dev)
3987 {
3988         struct drm_i915_private *dev_priv = dev->dev_private;
3989         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3990         bool was_interruptible;
3991         int ret;
3992
3993         /* rc6 disabled by default due to repeated reports of hanging during
3994          * boot and resume.
3995          */
3996         if (!intel_enable_rc6(dev))
3997                 return;
3998
3999         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4000
4001         ret = ironlake_setup_rc6(dev);
4002         if (ret)
4003                 return;
4004
4005         was_interruptible = dev_priv->mm.interruptible;
4006         dev_priv->mm.interruptible = false;
4007
4008         /*
4009          * GPU can automatically power down the render unit if given a page
4010          * to save state.
4011          */
4012         ret = intel_ring_begin(ring, 6);
4013         if (ret) {
4014                 ironlake_teardown_rc6(dev);
4015                 dev_priv->mm.interruptible = was_interruptible;
4016                 return;
4017         }
4018
4019         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4020         intel_ring_emit(ring, MI_SET_CONTEXT);
4021         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4022                         MI_MM_SPACE_GTT |
4023                         MI_SAVE_EXT_STATE_EN |
4024                         MI_RESTORE_EXT_STATE_EN |
4025                         MI_RESTORE_INHIBIT);
4026         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4027         intel_ring_emit(ring, MI_NOOP);
4028         intel_ring_emit(ring, MI_FLUSH);
4029         intel_ring_advance(ring);
4030
4031         /*
4032          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4033          * does an implicit flush, combined with MI_FLUSH above, it should be
4034          * safe to assume that renderctx is valid
4035          */
4036         ret = intel_ring_idle(ring);
4037         dev_priv->mm.interruptible = was_interruptible;
4038         if (ret) {
4039                 DRM_ERROR("failed to enable ironlake power savings\n");
4040                 ironlake_teardown_rc6(dev);
4041                 return;
4042         }
4043
4044         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4045         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4046
4047         intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4048 }
4049
4050 static unsigned long intel_pxfreq(u32 vidfreq)
4051 {
4052         unsigned long freq;
4053         int div = (vidfreq & 0x3f0000) >> 16;
4054         int post = (vidfreq & 0x3000) >> 12;
4055         int pre = (vidfreq & 0x7);
4056
4057         if (!pre)
4058                 return 0;
4059
4060         freq = ((div * 133333) / ((1<<post) * pre));
4061
4062         return freq;
4063 }
4064
4065 static const struct cparams {
4066         u16 i;
4067         u16 t;
4068         u16 m;
4069         u16 c;
4070 } cparams[] = {
4071         { 1, 1333, 301, 28664 },
4072         { 1, 1066, 294, 24460 },
4073         { 1, 800, 294, 25192 },
4074         { 0, 1333, 276, 27605 },
4075         { 0, 1066, 276, 27605 },
4076         { 0, 800, 231, 23784 },
4077 };
4078
4079 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4080 {
4081         u64 total_count, diff, ret;
4082         u32 count1, count2, count3, m = 0, c = 0;
4083         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4084         int i;
4085
4086         assert_spin_locked(&mchdev_lock);
4087
4088         diff1 = now - dev_priv->ips.last_time1;
4089
4090         /* Prevent division-by-zero if we are asking too fast.
4091          * Also, we don't get interesting results if we are polling
4092          * faster than once in 10ms, so just return the saved value
4093          * in such cases.
4094          */
4095         if (diff1 <= 10)
4096                 return dev_priv->ips.chipset_power;
4097
4098         count1 = I915_READ(DMIEC);
4099         count2 = I915_READ(DDREC);
4100         count3 = I915_READ(CSIEC);
4101
4102         total_count = count1 + count2 + count3;
4103
4104         /* FIXME: handle per-counter overflow */
4105         if (total_count < dev_priv->ips.last_count1) {
4106                 diff = ~0UL - dev_priv->ips.last_count1;
4107                 diff += total_count;
4108         } else {
4109                 diff = total_count - dev_priv->ips.last_count1;
4110         }
4111
4112         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4113                 if (cparams[i].i == dev_priv->ips.c_m &&
4114                     cparams[i].t == dev_priv->ips.r_t) {
4115                         m = cparams[i].m;
4116                         c = cparams[i].c;
4117                         break;
4118                 }
4119         }
4120
4121         diff = div_u64(diff, diff1);
4122         ret = ((m * diff) + c);
4123         ret = div_u64(ret, 10);
4124
4125         dev_priv->ips.last_count1 = total_count;
4126         dev_priv->ips.last_time1 = now;
4127
4128         dev_priv->ips.chipset_power = ret;
4129
4130         return ret;
4131 }
4132
4133 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4134 {
4135         struct drm_device *dev = dev_priv->dev;
4136         unsigned long val;
4137
4138         if (INTEL_INFO(dev)->gen != 5)
4139                 return 0;
4140
4141         spin_lock_irq(&mchdev_lock);
4142
4143         val = __i915_chipset_val(dev_priv);
4144
4145         spin_unlock_irq(&mchdev_lock);
4146
4147         return val;
4148 }
4149
4150 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4151 {
4152         unsigned long m, x, b;
4153         u32 tsfs;
4154
4155         tsfs = I915_READ(TSFS);
4156
4157         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4158         x = I915_READ8(TR1);
4159
4160         b = tsfs & TSFS_INTR_MASK;
4161
4162         return ((m * x) / 127) - b;
4163 }
4164
4165 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4166 {
4167         struct drm_device *dev = dev_priv->dev;
4168         static const struct v_table {
4169                 u16 vd; /* in .1 mil */
4170                 u16 vm; /* in .1 mil */
4171         } v_table[] = {
4172                 { 0, 0, },
4173                 { 375, 0, },
4174                 { 500, 0, },
4175                 { 625, 0, },
4176                 { 750, 0, },
4177                 { 875, 0, },
4178                 { 1000, 0, },
4179                 { 1125, 0, },
4180                 { 4125, 3000, },
4181                 { 4125, 3000, },
4182                 { 4125, 3000, },
4183                 { 4125, 3000, },
4184                 { 4125, 3000, },
4185                 { 4125, 3000, },
4186                 { 4125, 3000, },
4187                 { 4125, 3000, },
4188                 { 4125, 3000, },
4189                 { 4125, 3000, },
4190                 { 4125, 3000, },
4191                 { 4125, 3000, },
4192                 { 4125, 3000, },
4193                 { 4125, 3000, },
4194                 { 4125, 3000, },
4195                 { 4125, 3000, },
4196                 { 4125, 3000, },
4197                 { 4125, 3000, },
4198                 { 4125, 3000, },
4199                 { 4125, 3000, },
4200                 { 4125, 3000, },
4201                 { 4125, 3000, },
4202                 { 4125, 3000, },
4203                 { 4125, 3000, },
4204                 { 4250, 3125, },
4205                 { 4375, 3250, },
4206                 { 4500, 3375, },
4207                 { 4625, 3500, },
4208                 { 4750, 3625, },
4209                 { 4875, 3750, },
4210                 { 5000, 3875, },
4211                 { 5125, 4000, },
4212                 { 5250, 4125, },
4213                 { 5375, 4250, },
4214                 { 5500, 4375, },
4215                 { 5625, 4500, },
4216                 { 5750, 4625, },
4217                 { 5875, 4750, },
4218                 { 6000, 4875, },
4219                 { 6125, 5000, },
4220                 { 6250, 5125, },
4221                 { 6375, 5250, },
4222                 { 6500, 5375, },
4223                 { 6625, 5500, },
4224                 { 6750, 5625, },
4225                 { 6875, 5750, },
4226                 { 7000, 5875, },
4227                 { 7125, 6000, },
4228                 { 7250, 6125, },
4229                 { 7375, 6250, },
4230                 { 7500, 6375, },
4231                 { 7625, 6500, },
4232                 { 7750, 6625, },
4233                 { 7875, 6750, },
4234                 { 8000, 6875, },
4235                 { 8125, 7000, },
4236                 { 8250, 7125, },
4237                 { 8375, 7250, },
4238                 { 8500, 7375, },
4239                 { 8625, 7500, },
4240                 { 8750, 7625, },
4241                 { 8875, 7750, },
4242                 { 9000, 7875, },
4243                 { 9125, 8000, },
4244                 { 9250, 8125, },
4245                 { 9375, 8250, },
4246                 { 9500, 8375, },
4247                 { 9625, 8500, },
4248                 { 9750, 8625, },
4249                 { 9875, 8750, },
4250                 { 10000, 8875, },
4251                 { 10125, 9000, },
4252                 { 10250, 9125, },
4253                 { 10375, 9250, },
4254                 { 10500, 9375, },
4255                 { 10625, 9500, },
4256                 { 10750, 9625, },
4257                 { 10875, 9750, },
4258                 { 11000, 9875, },
4259                 { 11125, 10000, },
4260                 { 11250, 10125, },
4261                 { 11375, 10250, },
4262                 { 11500, 10375, },
4263                 { 11625, 10500, },
4264                 { 11750, 10625, },
4265                 { 11875, 10750, },
4266                 { 12000, 10875, },
4267                 { 12125, 11000, },
4268                 { 12250, 11125, },
4269                 { 12375, 11250, },
4270                 { 12500, 11375, },
4271                 { 12625, 11500, },
4272                 { 12750, 11625, },
4273                 { 12875, 11750, },
4274                 { 13000, 11875, },
4275                 { 13125, 12000, },
4276                 { 13250, 12125, },
4277                 { 13375, 12250, },
4278                 { 13500, 12375, },
4279                 { 13625, 12500, },
4280                 { 13750, 12625, },
4281                 { 13875, 12750, },
4282                 { 14000, 12875, },
4283                 { 14125, 13000, },
4284                 { 14250, 13125, },
4285                 { 14375, 13250, },
4286                 { 14500, 13375, },
4287                 { 14625, 13500, },
4288                 { 14750, 13625, },
4289                 { 14875, 13750, },
4290                 { 15000, 13875, },
4291                 { 15125, 14000, },
4292                 { 15250, 14125, },
4293                 { 15375, 14250, },
4294                 { 15500, 14375, },
4295                 { 15625, 14500, },
4296                 { 15750, 14625, },
4297                 { 15875, 14750, },
4298                 { 16000, 14875, },
4299                 { 16125, 15000, },
4300         };
4301         if (INTEL_INFO(dev)->is_mobile)
4302                 return v_table[pxvid].vm;
4303         else
4304                 return v_table[pxvid].vd;
4305 }
4306
4307 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4308 {
4309         struct timespec now, diff1;
4310         u64 diff;
4311         unsigned long diffms;
4312         u32 count;
4313
4314         assert_spin_locked(&mchdev_lock);
4315
4316         getrawmonotonic(&now);
4317         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4318
4319         /* Don't divide by 0 */
4320         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4321         if (!diffms)
4322                 return;
4323
4324         count = I915_READ(GFXEC);
4325
4326         if (count < dev_priv->ips.last_count2) {
4327                 diff = ~0UL - dev_priv->ips.last_count2;
4328                 diff += count;
4329         } else {
4330                 diff = count - dev_priv->ips.last_count2;
4331         }
4332
4333         dev_priv->ips.last_count2 = count;
4334         dev_priv->ips.last_time2 = now;
4335
4336         /* More magic constants... */
4337         diff = diff * 1181;
4338         diff = div_u64(diff, diffms * 10);
4339         dev_priv->ips.gfx_power = diff;
4340 }
4341
4342 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4343 {
4344         struct drm_device *dev = dev_priv->dev;
4345
4346         if (INTEL_INFO(dev)->gen != 5)
4347                 return;
4348
4349         spin_lock_irq(&mchdev_lock);
4350
4351         __i915_update_gfx_val(dev_priv);
4352
4353         spin_unlock_irq(&mchdev_lock);
4354 }
4355
4356 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4357 {
4358         unsigned long t, corr, state1, corr2, state2;
4359         u32 pxvid, ext_v;
4360
4361         assert_spin_locked(&mchdev_lock);
4362
4363         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4364         pxvid = (pxvid >> 24) & 0x7f;
4365         ext_v = pvid_to_extvid(dev_priv, pxvid);
4366
4367         state1 = ext_v;
4368
4369         t = i915_mch_val(dev_priv);
4370
4371         /* Revel in the empirically derived constants */
4372
4373         /* Correction factor in 1/100000 units */
4374         if (t > 80)
4375                 corr = ((t * 2349) + 135940);
4376         else if (t >= 50)
4377                 corr = ((t * 964) + 29317);
4378         else /* < 50 */
4379                 corr = ((t * 301) + 1004);
4380
4381         corr = corr * ((150142 * state1) / 10000 - 78642);
4382         corr /= 100000;
4383         corr2 = (corr * dev_priv->ips.corr);
4384
4385         state2 = (corr2 * state1) / 10000;
4386         state2 /= 100; /* convert to mW */
4387
4388         __i915_update_gfx_val(dev_priv);
4389
4390         return dev_priv->ips.gfx_power + state2;
4391 }
4392
4393 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4394 {
4395         struct drm_device *dev = dev_priv->dev;
4396         unsigned long val;
4397
4398         if (INTEL_INFO(dev)->gen != 5)
4399                 return 0;
4400
4401         spin_lock_irq(&mchdev_lock);
4402
4403         val = __i915_gfx_val(dev_priv);
4404
4405         spin_unlock_irq(&mchdev_lock);
4406
4407         return val;
4408 }
4409
4410 /**
4411  * i915_read_mch_val - return value for IPS use
4412  *
4413  * Calculate and return a value for the IPS driver to use when deciding whether
4414  * we have thermal and power headroom to increase CPU or GPU power budget.
4415  */
4416 unsigned long i915_read_mch_val(void)
4417 {
4418         struct drm_i915_private *dev_priv;
4419         unsigned long chipset_val, graphics_val, ret = 0;
4420
4421         spin_lock_irq(&mchdev_lock);
4422         if (!i915_mch_dev)
4423                 goto out_unlock;
4424         dev_priv = i915_mch_dev;
4425
4426         chipset_val = __i915_chipset_val(dev_priv);
4427         graphics_val = __i915_gfx_val(dev_priv);
4428
4429         ret = chipset_val + graphics_val;
4430
4431 out_unlock:
4432         spin_unlock_irq(&mchdev_lock);
4433
4434         return ret;
4435 }
4436 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4437
4438 /**
4439  * i915_gpu_raise - raise GPU frequency limit
4440  *
4441  * Raise the limit; IPS indicates we have thermal headroom.
4442  */
4443 bool i915_gpu_raise(void)
4444 {
4445         struct drm_i915_private *dev_priv;
4446         bool ret = true;
4447
4448         spin_lock_irq(&mchdev_lock);
4449         if (!i915_mch_dev) {
4450                 ret = false;
4451                 goto out_unlock;
4452         }
4453         dev_priv = i915_mch_dev;
4454
4455         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4456                 dev_priv->ips.max_delay--;
4457
4458 out_unlock:
4459         spin_unlock_irq(&mchdev_lock);
4460
4461         return ret;
4462 }
4463 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4464
4465 /**
4466  * i915_gpu_lower - lower GPU frequency limit
4467  *
4468  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4469  * frequency maximum.
4470  */
4471 bool i915_gpu_lower(void)
4472 {
4473         struct drm_i915_private *dev_priv;
4474         bool ret = true;
4475
4476         spin_lock_irq(&mchdev_lock);
4477         if (!i915_mch_dev) {
4478                 ret = false;
4479                 goto out_unlock;
4480         }
4481         dev_priv = i915_mch_dev;
4482
4483         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4484                 dev_priv->ips.max_delay++;
4485
4486 out_unlock:
4487         spin_unlock_irq(&mchdev_lock);
4488
4489         return ret;
4490 }
4491 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4492
4493 /**
4494  * i915_gpu_busy - indicate GPU business to IPS
4495  *
4496  * Tell the IPS driver whether or not the GPU is busy.
4497  */
4498 bool i915_gpu_busy(void)
4499 {
4500         struct drm_i915_private *dev_priv;
4501         struct intel_engine_cs *ring;
4502         bool ret = false;
4503         int i;
4504
4505         spin_lock_irq(&mchdev_lock);
4506         if (!i915_mch_dev)
4507                 goto out_unlock;
4508         dev_priv = i915_mch_dev;
4509
4510         for_each_ring(ring, dev_priv, i)
4511                 ret |= !list_empty(&ring->request_list);
4512
4513 out_unlock:
4514         spin_unlock_irq(&mchdev_lock);
4515
4516         return ret;
4517 }
4518 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4519
4520 /**
4521  * i915_gpu_turbo_disable - disable graphics turbo
4522  *
4523  * Disable graphics turbo by resetting the max frequency and setting the
4524  * current frequency to the default.
4525  */
4526 bool i915_gpu_turbo_disable(void)
4527 {
4528         struct drm_i915_private *dev_priv;
4529         bool ret = true;
4530
4531         spin_lock_irq(&mchdev_lock);
4532         if (!i915_mch_dev) {
4533                 ret = false;
4534                 goto out_unlock;
4535         }
4536         dev_priv = i915_mch_dev;
4537
4538         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4539
4540         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4541                 ret = false;
4542
4543 out_unlock:
4544         spin_unlock_irq(&mchdev_lock);
4545
4546         return ret;
4547 }
4548 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4549
4550 /**
4551  * Tells the intel_ips driver that the i915 driver is now loaded, if
4552  * IPS got loaded first.
4553  *
4554  * This awkward dance is so that neither module has to depend on the
4555  * other in order for IPS to do the appropriate communication of
4556  * GPU turbo limits to i915.
4557  */
4558 static void
4559 ips_ping_for_i915_load(void)
4560 {
4561         void (*link)(void);
4562
4563         link = symbol_get(ips_link_to_i915_driver);
4564         if (link) {
4565                 link();
4566                 symbol_put(ips_link_to_i915_driver);
4567         }
4568 }
4569
4570 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4571 {
4572         /* We only register the i915 ips part with intel-ips once everything is
4573          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4574         spin_lock_irq(&mchdev_lock);
4575         i915_mch_dev = dev_priv;
4576         spin_unlock_irq(&mchdev_lock);
4577
4578         ips_ping_for_i915_load();
4579 }
4580
4581 void intel_gpu_ips_teardown(void)
4582 {
4583         spin_lock_irq(&mchdev_lock);
4584         i915_mch_dev = NULL;
4585         spin_unlock_irq(&mchdev_lock);
4586 }
4587
4588 static void intel_init_emon(struct drm_device *dev)
4589 {
4590         struct drm_i915_private *dev_priv = dev->dev_private;
4591         u32 lcfuse;
4592         u8 pxw[16];
4593         int i;
4594
4595         /* Disable to program */
4596         I915_WRITE(ECR, 0);
4597         POSTING_READ(ECR);
4598
4599         /* Program energy weights for various events */
4600         I915_WRITE(SDEW, 0x15040d00);
4601         I915_WRITE(CSIEW0, 0x007f0000);
4602         I915_WRITE(CSIEW1, 0x1e220004);
4603         I915_WRITE(CSIEW2, 0x04000004);
4604
4605         for (i = 0; i < 5; i++)
4606                 I915_WRITE(PEW + (i * 4), 0);
4607         for (i = 0; i < 3; i++)
4608                 I915_WRITE(DEW + (i * 4), 0);
4609
4610         /* Program P-state weights to account for frequency power adjustment */
4611         for (i = 0; i < 16; i++) {
4612                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4613                 unsigned long freq = intel_pxfreq(pxvidfreq);
4614                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4615                         PXVFREQ_PX_SHIFT;
4616                 unsigned long val;
4617
4618                 val = vid * vid;
4619                 val *= (freq / 1000);
4620                 val *= 255;
4621                 val /= (127*127*900);
4622                 if (val > 0xff)
4623                         DRM_ERROR("bad pxval: %ld\n", val);
4624                 pxw[i] = val;
4625         }
4626         /* Render standby states get 0 weight */
4627         pxw[14] = 0;
4628         pxw[15] = 0;
4629
4630         for (i = 0; i < 4; i++) {
4631                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4632                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4633                 I915_WRITE(PXW + (i * 4), val);
4634         }
4635
4636         /* Adjust magic regs to magic values (more experimental results) */
4637         I915_WRITE(OGW0, 0);
4638         I915_WRITE(OGW1, 0);
4639         I915_WRITE(EG0, 0x00007f00);
4640         I915_WRITE(EG1, 0x0000000e);
4641         I915_WRITE(EG2, 0x000e0000);
4642         I915_WRITE(EG3, 0x68000300);
4643         I915_WRITE(EG4, 0x42000000);
4644         I915_WRITE(EG5, 0x00140031);
4645         I915_WRITE(EG6, 0);
4646         I915_WRITE(EG7, 0);
4647
4648         for (i = 0; i < 8; i++)
4649                 I915_WRITE(PXWL + (i * 4), 0);
4650
4651         /* Enable PMON + select events */
4652         I915_WRITE(ECR, 0x80000019);
4653
4654         lcfuse = I915_READ(LCFUSE02);
4655
4656         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4657 }
4658
4659 void intel_init_gt_powersave(struct drm_device *dev)
4660 {
4661         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4662
4663         if (IS_VALLEYVIEW(dev))
4664                 valleyview_init_gt_powersave(dev);
4665 }
4666
4667 void intel_cleanup_gt_powersave(struct drm_device *dev)
4668 {
4669         if (IS_VALLEYVIEW(dev))
4670                 valleyview_cleanup_gt_powersave(dev);
4671 }
4672
4673 void intel_disable_gt_powersave(struct drm_device *dev)
4674 {
4675         struct drm_i915_private *dev_priv = dev->dev_private;
4676
4677         /* Interrupts should be disabled already to avoid re-arming. */
4678         WARN_ON(dev->irq_enabled);
4679
4680         if (IS_IRONLAKE_M(dev)) {
4681                 ironlake_disable_drps(dev);
4682                 ironlake_disable_rc6(dev);
4683         } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4684                 if (cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work))
4685                         intel_runtime_pm_put(dev_priv);
4686
4687                 cancel_work_sync(&dev_priv->rps.work);
4688                 mutex_lock(&dev_priv->rps.hw_lock);
4689                 if (IS_VALLEYVIEW(dev))
4690                         valleyview_disable_rps(dev);
4691                 else
4692                         gen6_disable_rps(dev);
4693                 dev_priv->rps.enabled = false;
4694                 mutex_unlock(&dev_priv->rps.hw_lock);
4695         }
4696 }
4697
4698 static void intel_gen6_powersave_work(struct work_struct *work)
4699 {
4700         struct drm_i915_private *dev_priv =
4701                 container_of(work, struct drm_i915_private,
4702                              rps.delayed_resume_work.work);
4703         struct drm_device *dev = dev_priv->dev;
4704
4705         mutex_lock(&dev_priv->rps.hw_lock);
4706
4707         if (IS_VALLEYVIEW(dev)) {
4708                 valleyview_enable_rps(dev);
4709         } else if (IS_BROADWELL(dev)) {
4710                 gen8_enable_rps(dev);
4711                 __gen6_update_ring_freq(dev);
4712         } else {
4713                 gen6_enable_rps(dev);
4714                 __gen6_update_ring_freq(dev);
4715         }
4716         dev_priv->rps.enabled = true;
4717         mutex_unlock(&dev_priv->rps.hw_lock);
4718
4719         intel_runtime_pm_put(dev_priv);
4720 }
4721
4722 void intel_enable_gt_powersave(struct drm_device *dev)
4723 {
4724         struct drm_i915_private *dev_priv = dev->dev_private;
4725
4726         if (IS_IRONLAKE_M(dev)) {
4727                 mutex_lock(&dev->struct_mutex);
4728                 ironlake_enable_drps(dev);
4729                 ironlake_enable_rc6(dev);
4730                 intel_init_emon(dev);
4731                 mutex_unlock(&dev->struct_mutex);
4732         } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4733                 /*
4734                  * PCU communication is slow and this doesn't need to be
4735                  * done at any specific time, so do this out of our fast path
4736                  * to make resume and init faster.
4737                  *
4738                  * We depend on the HW RC6 power context save/restore
4739                  * mechanism when entering D3 through runtime PM suspend. So
4740                  * disable RPM until RPS/RC6 is properly setup. We can only
4741                  * get here via the driver load/system resume/runtime resume
4742                  * paths, so the _noresume version is enough (and in case of
4743                  * runtime resume it's necessary).
4744                  */
4745                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4746                                            round_jiffies_up_relative(HZ)))
4747                         intel_runtime_pm_get_noresume(dev_priv);
4748         }
4749 }
4750
4751 void intel_reset_gt_powersave(struct drm_device *dev)
4752 {
4753         struct drm_i915_private *dev_priv = dev->dev_private;
4754
4755         dev_priv->rps.enabled = false;
4756         intel_enable_gt_powersave(dev);
4757 }
4758
4759 static void ibx_init_clock_gating(struct drm_device *dev)
4760 {
4761         struct drm_i915_private *dev_priv = dev->dev_private;
4762
4763         /*
4764          * On Ibex Peak and Cougar Point, we need to disable clock
4765          * gating for the panel power sequencer or it will fail to
4766          * start up when no ports are active.
4767          */
4768         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4769 }
4770
4771 static void g4x_disable_trickle_feed(struct drm_device *dev)
4772 {
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         int pipe;
4775
4776         for_each_pipe(pipe) {
4777                 I915_WRITE(DSPCNTR(pipe),
4778                            I915_READ(DSPCNTR(pipe)) |
4779                            DISPPLANE_TRICKLE_FEED_DISABLE);
4780                 intel_flush_primary_plane(dev_priv, pipe);
4781         }
4782 }
4783
4784 static void ilk_init_lp_watermarks(struct drm_device *dev)
4785 {
4786         struct drm_i915_private *dev_priv = dev->dev_private;
4787
4788         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4789         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4790         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4791
4792         /*
4793          * Don't touch WM1S_LP_EN here.
4794          * Doing so could cause underruns.
4795          */
4796 }
4797
4798 static void ironlake_init_clock_gating(struct drm_device *dev)
4799 {
4800         struct drm_i915_private *dev_priv = dev->dev_private;
4801         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4802
4803         /*
4804          * Required for FBC
4805          * WaFbcDisableDpfcClockGating:ilk
4806          */
4807         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4808                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4809                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4810
4811         I915_WRITE(PCH_3DCGDIS0,
4812                    MARIUNIT_CLOCK_GATE_DISABLE |
4813                    SVSMUNIT_CLOCK_GATE_DISABLE);
4814         I915_WRITE(PCH_3DCGDIS1,
4815                    VFMUNIT_CLOCK_GATE_DISABLE);
4816
4817         /*
4818          * According to the spec the following bits should be set in
4819          * order to enable memory self-refresh
4820          * The bit 22/21 of 0x42004
4821          * The bit 5 of 0x42020
4822          * The bit 15 of 0x45000
4823          */
4824         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4825                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4826                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4827         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4828         I915_WRITE(DISP_ARB_CTL,
4829                    (I915_READ(DISP_ARB_CTL) |
4830                     DISP_FBC_WM_DIS));
4831
4832         ilk_init_lp_watermarks(dev);
4833
4834         /*
4835          * Based on the document from hardware guys the following bits
4836          * should be set unconditionally in order to enable FBC.
4837          * The bit 22 of 0x42000
4838          * The bit 22 of 0x42004
4839          * The bit 7,8,9 of 0x42020.
4840          */
4841         if (IS_IRONLAKE_M(dev)) {
4842                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4843                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4844                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4845                            ILK_FBCQ_DIS);
4846                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4847                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4848                            ILK_DPARB_GATE);
4849         }
4850
4851         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4852
4853         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4854                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4855                    ILK_ELPIN_409_SELECT);
4856         I915_WRITE(_3D_CHICKEN2,
4857                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4858                    _3D_CHICKEN2_WM_READ_PIPELINED);
4859
4860         /* WaDisableRenderCachePipelinedFlush:ilk */
4861         I915_WRITE(CACHE_MODE_0,
4862                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4863
4864         /* WaDisable_RenderCache_OperationalFlush:ilk */
4865         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4866
4867         g4x_disable_trickle_feed(dev);
4868
4869         ibx_init_clock_gating(dev);
4870 }
4871
4872 static void cpt_init_clock_gating(struct drm_device *dev)
4873 {
4874         struct drm_i915_private *dev_priv = dev->dev_private;
4875         int pipe;
4876         uint32_t val;
4877
4878         /*
4879          * On Ibex Peak and Cougar Point, we need to disable clock
4880          * gating for the panel power sequencer or it will fail to
4881          * start up when no ports are active.
4882          */
4883         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4884                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4885                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4886         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4887                    DPLS_EDP_PPS_FIX_DIS);
4888         /* The below fixes the weird display corruption, a few pixels shifted
4889          * downward, on (only) LVDS of some HP laptops with IVY.
4890          */
4891         for_each_pipe(pipe) {
4892                 val = I915_READ(TRANS_CHICKEN2(pipe));
4893                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4894                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4895                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4896                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4897                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4898                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4899                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4900                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4901         }
4902         /* WADP0ClockGatingDisable */
4903         for_each_pipe(pipe) {
4904                 I915_WRITE(TRANS_CHICKEN1(pipe),
4905                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4906         }
4907 }
4908
4909 static void gen6_check_mch_setup(struct drm_device *dev)
4910 {
4911         struct drm_i915_private *dev_priv = dev->dev_private;
4912         uint32_t tmp;
4913
4914         tmp = I915_READ(MCH_SSKPD);
4915         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4916                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4917                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4918                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4919         }
4920 }
4921
4922 static void gen6_init_clock_gating(struct drm_device *dev)
4923 {
4924         struct drm_i915_private *dev_priv = dev->dev_private;
4925         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4926
4927         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4928
4929         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4930                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4931                    ILK_ELPIN_409_SELECT);
4932
4933         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4934         I915_WRITE(_3D_CHICKEN,
4935                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4936
4937         /* WaSetupGtModeTdRowDispatch:snb */
4938         if (IS_SNB_GT1(dev))
4939                 I915_WRITE(GEN6_GT_MODE,
4940                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4941
4942         /* WaDisable_RenderCache_OperationalFlush:snb */
4943         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4944
4945         /*
4946          * BSpec recoomends 8x4 when MSAA is used,
4947          * however in practice 16x4 seems fastest.
4948          *
4949          * Note that PS/WM thread counts depend on the WIZ hashing
4950          * disable bit, which we don't touch here, but it's good
4951          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4952          */
4953         I915_WRITE(GEN6_GT_MODE,
4954                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4955
4956         ilk_init_lp_watermarks(dev);
4957
4958         I915_WRITE(CACHE_MODE_0,
4959                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4960
4961         I915_WRITE(GEN6_UCGCTL1,
4962                    I915_READ(GEN6_UCGCTL1) |
4963                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4964                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4965
4966         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4967          * gating disable must be set.  Failure to set it results in
4968          * flickering pixels due to Z write ordering failures after
4969          * some amount of runtime in the Mesa "fire" demo, and Unigine
4970          * Sanctuary and Tropics, and apparently anything else with
4971          * alpha test or pixel discard.
4972          *
4973          * According to the spec, bit 11 (RCCUNIT) must also be set,
4974          * but we didn't debug actual testcases to find it out.
4975          *
4976          * WaDisableRCCUnitClockGating:snb
4977          * WaDisableRCPBUnitClockGating:snb
4978          */
4979         I915_WRITE(GEN6_UCGCTL2,
4980                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4981                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4982
4983         /* WaStripsFansDisableFastClipPerformanceFix:snb */
4984         I915_WRITE(_3D_CHICKEN3,
4985                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4986
4987         /*
4988          * Bspec says:
4989          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4990          * 3DSTATE_SF number of SF output attributes is more than 16."
4991          */
4992         I915_WRITE(_3D_CHICKEN3,
4993                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4994
4995         /*
4996          * According to the spec the following bits should be
4997          * set in order to enable memory self-refresh and fbc:
4998          * The bit21 and bit22 of 0x42000
4999          * The bit21 and bit22 of 0x42004
5000          * The bit5 and bit7 of 0x42020
5001          * The bit14 of 0x70180
5002          * The bit14 of 0x71180
5003          *
5004          * WaFbcAsynchFlipDisableFbcQueue:snb
5005          */
5006         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5007                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5008                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5009         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5010                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5011                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5012         I915_WRITE(ILK_DSPCLK_GATE_D,
5013                    I915_READ(ILK_DSPCLK_GATE_D) |
5014                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5015                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5016
5017         g4x_disable_trickle_feed(dev);
5018
5019         cpt_init_clock_gating(dev);
5020
5021         gen6_check_mch_setup(dev);
5022 }
5023
5024 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5025 {
5026         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5027
5028         /*
5029          * WaVSThreadDispatchOverride:ivb,vlv
5030          *
5031          * This actually overrides the dispatch
5032          * mode for all thread types.
5033          */
5034         reg &= ~GEN7_FF_SCHED_MASK;
5035         reg |= GEN7_FF_TS_SCHED_HW;
5036         reg |= GEN7_FF_VS_SCHED_HW;
5037         reg |= GEN7_FF_DS_SCHED_HW;
5038
5039         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5040 }
5041
5042 static void lpt_init_clock_gating(struct drm_device *dev)
5043 {
5044         struct drm_i915_private *dev_priv = dev->dev_private;
5045
5046         /*
5047          * TODO: this bit should only be enabled when really needed, then
5048          * disabled when not needed anymore in order to save power.
5049          */
5050         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5051                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5052                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5053                            PCH_LP_PARTITION_LEVEL_DISABLE);
5054
5055         /* WADPOClockGatingDisable:hsw */
5056         I915_WRITE(_TRANSA_CHICKEN1,
5057                    I915_READ(_TRANSA_CHICKEN1) |
5058                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5059 }
5060
5061 static void lpt_suspend_hw(struct drm_device *dev)
5062 {
5063         struct drm_i915_private *dev_priv = dev->dev_private;
5064
5065         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5066                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5067
5068                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5069                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5070         }
5071 }
5072
5073 static void gen8_init_clock_gating(struct drm_device *dev)
5074 {
5075         struct drm_i915_private *dev_priv = dev->dev_private;
5076         enum pipe pipe;
5077
5078         I915_WRITE(WM3_LP_ILK, 0);
5079         I915_WRITE(WM2_LP_ILK, 0);
5080         I915_WRITE(WM1_LP_ILK, 0);
5081
5082         /* FIXME(BDW): Check all the w/a, some might only apply to
5083          * pre-production hw. */
5084
5085         /* WaDisablePartialInstShootdown:bdw */
5086         I915_WRITE(GEN8_ROW_CHICKEN,
5087                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5088
5089         /* WaDisableThreadStallDopClockGating:bdw */
5090         /* FIXME: Unclear whether we really need this on production bdw. */
5091         I915_WRITE(GEN8_ROW_CHICKEN,
5092                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5093
5094         /*
5095          * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5096          * pre-production hardware
5097          */
5098         I915_WRITE(HALF_SLICE_CHICKEN3,
5099                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5100         I915_WRITE(HALF_SLICE_CHICKEN3,
5101                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5102         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5103
5104         I915_WRITE(_3D_CHICKEN3,
5105                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5106
5107         I915_WRITE(COMMON_SLICE_CHICKEN2,
5108                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5109
5110         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5111                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5112
5113         /* WaDisableDopClockGating:bdw May not be needed for production */
5114         I915_WRITE(GEN7_ROW_CHICKEN2,
5115                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5116
5117         /* WaSwitchSolVfFArbitrationPriority:bdw */
5118         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5119
5120         /* WaPsrDPAMaskVBlankInSRD:bdw */
5121         I915_WRITE(CHICKEN_PAR1_1,
5122                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5123
5124         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5125         for_each_pipe(pipe) {
5126                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5127                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
5128                            BDW_DPRS_MASK_VBLANK_SRD);
5129         }
5130
5131         /* Use Force Non-Coherent whenever executing a 3D context. This is a
5132          * workaround for for a possible hang in the unlikely event a TLB
5133          * invalidation occurs during a PSD flush.
5134          */
5135         I915_WRITE(HDC_CHICKEN0,
5136                    I915_READ(HDC_CHICKEN0) |
5137                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5138
5139         /* WaVSRefCountFullforceMissDisable:bdw */
5140         /* WaDSRefCountFullforceMissDisable:bdw */
5141         I915_WRITE(GEN7_FF_THREAD_MODE,
5142                    I915_READ(GEN7_FF_THREAD_MODE) &
5143                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5144
5145         /*
5146          * BSpec recommends 8x4 when MSAA is used,
5147          * however in practice 16x4 seems fastest.
5148          *
5149          * Note that PS/WM thread counts depend on the WIZ hashing
5150          * disable bit, which we don't touch here, but it's good
5151          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5152          */
5153         I915_WRITE(GEN7_GT_MODE,
5154                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5155
5156         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5157                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5158
5159         /* WaDisableSDEUnitClockGating:bdw */
5160         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5161                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5162
5163         /* Wa4x4STCOptimizationDisable:bdw */
5164         I915_WRITE(CACHE_MODE_1,
5165                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5166 }
5167
5168 static void haswell_init_clock_gating(struct drm_device *dev)
5169 {
5170         struct drm_i915_private *dev_priv = dev->dev_private;
5171
5172         ilk_init_lp_watermarks(dev);
5173
5174         /* L3 caching of data atomics doesn't work -- disable it. */
5175         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5176         I915_WRITE(HSW_ROW_CHICKEN3,
5177                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5178
5179         /* This is required by WaCatErrorRejectionIssue:hsw */
5180         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5181                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5182                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5183
5184         /* WaVSRefCountFullforceMissDisable:hsw */
5185         I915_WRITE(GEN7_FF_THREAD_MODE,
5186                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5187
5188         /* WaDisable_RenderCache_OperationalFlush:hsw */
5189         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5190
5191         /* enable HiZ Raw Stall Optimization */
5192         I915_WRITE(CACHE_MODE_0_GEN7,
5193                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5194
5195         /* WaDisable4x2SubspanOptimization:hsw */
5196         I915_WRITE(CACHE_MODE_1,
5197                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5198
5199         /*
5200          * BSpec recommends 8x4 when MSAA is used,
5201          * however in practice 16x4 seems fastest.
5202          *
5203          * Note that PS/WM thread counts depend on the WIZ hashing
5204          * disable bit, which we don't touch here, but it's good
5205          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5206          */
5207         I915_WRITE(GEN7_GT_MODE,
5208                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5209
5210         /* WaSwitchSolVfFArbitrationPriority:hsw */
5211         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5212
5213         /* WaRsPkgCStateDisplayPMReq:hsw */
5214         I915_WRITE(CHICKEN_PAR1_1,
5215                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5216
5217         lpt_init_clock_gating(dev);
5218 }
5219
5220 static void ivybridge_init_clock_gating(struct drm_device *dev)
5221 {
5222         struct drm_i915_private *dev_priv = dev->dev_private;
5223         uint32_t snpcr;
5224
5225         ilk_init_lp_watermarks(dev);
5226
5227         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5228
5229         /* WaDisableEarlyCull:ivb */
5230         I915_WRITE(_3D_CHICKEN3,
5231                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5232
5233         /* WaDisableBackToBackFlipFix:ivb */
5234         I915_WRITE(IVB_CHICKEN3,
5235                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5236                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5237
5238         /* WaDisablePSDDualDispatchEnable:ivb */
5239         if (IS_IVB_GT1(dev))
5240                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5241                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5242
5243         /* WaDisable_RenderCache_OperationalFlush:ivb */
5244         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5245
5246         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5247         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5248                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5249
5250         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5251         I915_WRITE(GEN7_L3CNTLREG1,
5252                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5253         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5254                    GEN7_WA_L3_CHICKEN_MODE);
5255         if (IS_IVB_GT1(dev))
5256                 I915_WRITE(GEN7_ROW_CHICKEN2,
5257                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5258         else {
5259                 /* must write both registers */
5260                 I915_WRITE(GEN7_ROW_CHICKEN2,
5261                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5262                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5263                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5264         }
5265
5266         /* WaForceL3Serialization:ivb */
5267         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5268                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5269
5270         /*
5271          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5272          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5273          */
5274         I915_WRITE(GEN6_UCGCTL2,
5275                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5276
5277         /* This is required by WaCatErrorRejectionIssue:ivb */
5278         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5279                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5280                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5281
5282         g4x_disable_trickle_feed(dev);
5283
5284         gen7_setup_fixed_func_scheduler(dev_priv);
5285
5286         if (0) { /* causes HiZ corruption on ivb:gt1 */
5287                 /* enable HiZ Raw Stall Optimization */
5288                 I915_WRITE(CACHE_MODE_0_GEN7,
5289                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5290         }
5291
5292         /* WaDisable4x2SubspanOptimization:ivb */
5293         I915_WRITE(CACHE_MODE_1,
5294                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5295
5296         /*
5297          * BSpec recommends 8x4 when MSAA is used,
5298          * however in practice 16x4 seems fastest.
5299          *
5300          * Note that PS/WM thread counts depend on the WIZ hashing
5301          * disable bit, which we don't touch here, but it's good
5302          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5303          */
5304         I915_WRITE(GEN7_GT_MODE,
5305                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5306
5307         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5308         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5309         snpcr |= GEN6_MBC_SNPCR_MED;
5310         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5311
5312         if (!HAS_PCH_NOP(dev))
5313                 cpt_init_clock_gating(dev);
5314
5315         gen6_check_mch_setup(dev);
5316 }
5317
5318 static void valleyview_init_clock_gating(struct drm_device *dev)
5319 {
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321         u32 val;
5322
5323         mutex_lock(&dev_priv->rps.hw_lock);
5324         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5325         mutex_unlock(&dev_priv->rps.hw_lock);
5326         switch ((val >> 6) & 3) {
5327         case 0:
5328         case 1:
5329                 dev_priv->mem_freq = 800;
5330                 break;
5331         case 2:
5332                 dev_priv->mem_freq = 1066;
5333                 break;
5334         case 3:
5335                 dev_priv->mem_freq = 1333;
5336                 break;
5337         }
5338         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5339
5340         dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5341         DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5342                          dev_priv->vlv_cdclk_freq);
5343
5344         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5345
5346         /* WaDisableEarlyCull:vlv */
5347         I915_WRITE(_3D_CHICKEN3,
5348                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5349
5350         /* WaDisableBackToBackFlipFix:vlv */
5351         I915_WRITE(IVB_CHICKEN3,
5352                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5353                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5354
5355         /* WaPsdDispatchEnable:vlv */
5356         /* WaDisablePSDDualDispatchEnable:vlv */
5357         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5358                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5359                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5360
5361         /* WaDisable_RenderCache_OperationalFlush:vlv */
5362         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5363
5364         /* WaForceL3Serialization:vlv */
5365         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5366                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5367
5368         /* WaDisableDopClockGating:vlv */
5369         I915_WRITE(GEN7_ROW_CHICKEN2,
5370                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5371
5372         /* This is required by WaCatErrorRejectionIssue:vlv */
5373         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5374                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5375                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5376
5377         gen7_setup_fixed_func_scheduler(dev_priv);
5378
5379         /*
5380          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5381          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5382          */
5383         I915_WRITE(GEN6_UCGCTL2,
5384                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5385
5386         /* WaDisableL3Bank2xClockGate:vlv
5387          * Disabling L3 clock gating- MMIO 940c[25] = 1
5388          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5389         I915_WRITE(GEN7_UCGCTL4,
5390                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5391
5392         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5393
5394         /*
5395          * BSpec says this must be set, even though
5396          * WaDisable4x2SubspanOptimization isn't listed for VLV.
5397          */
5398         I915_WRITE(CACHE_MODE_1,
5399                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5400
5401         /*
5402          * WaIncreaseL3CreditsForVLVB0:vlv
5403          * This is the hardware default actually.
5404          */
5405         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5406
5407         /*
5408          * WaDisableVLVClockGating_VBIIssue:vlv
5409          * Disable clock gating on th GCFG unit to prevent a delay
5410          * in the reporting of vblank events.
5411          */
5412         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5413 }
5414
5415 static void cherryview_init_clock_gating(struct drm_device *dev)
5416 {
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418
5419         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5420
5421         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5422
5423         /* WaDisablePartialInstShootdown:chv */
5424         I915_WRITE(GEN8_ROW_CHICKEN,
5425                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5426
5427         /* WaDisableThreadStallDopClockGating:chv */
5428         I915_WRITE(GEN8_ROW_CHICKEN,
5429                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5430
5431         /* WaVSRefCountFullforceMissDisable:chv */
5432         /* WaDSRefCountFullforceMissDisable:chv */
5433         I915_WRITE(GEN7_FF_THREAD_MODE,
5434                    I915_READ(GEN7_FF_THREAD_MODE) &
5435                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5436
5437         /* WaDisableSemaphoreAndSyncFlipWait:chv */
5438         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5439                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5440
5441         /* WaDisableCSUnitClockGating:chv */
5442         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5443                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5444
5445         /* WaDisableSDEUnitClockGating:chv */
5446         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5447                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5448
5449         /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5450         I915_WRITE(HALF_SLICE_CHICKEN3,
5451                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5452
5453         /* WaDisableGunitClockGating:chv (pre-production hw) */
5454         I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5455                    GINT_DIS);
5456
5457         /* WaDisableFfDopClockGating:chv (pre-production hw) */
5458         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5459                    _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5460
5461         /* WaDisableDopClockGating:chv (pre-production hw) */
5462         I915_WRITE(GEN7_ROW_CHICKEN2,
5463                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5464         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5465                    GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5466 }
5467
5468 static void g4x_init_clock_gating(struct drm_device *dev)
5469 {
5470         struct drm_i915_private *dev_priv = dev->dev_private;
5471         uint32_t dspclk_gate;
5472
5473         I915_WRITE(RENCLK_GATE_D1, 0);
5474         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5475                    GS_UNIT_CLOCK_GATE_DISABLE |
5476                    CL_UNIT_CLOCK_GATE_DISABLE);
5477         I915_WRITE(RAMCLK_GATE_D, 0);
5478         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5479                 OVRUNIT_CLOCK_GATE_DISABLE |
5480                 OVCUNIT_CLOCK_GATE_DISABLE;
5481         if (IS_GM45(dev))
5482                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5483         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5484
5485         /* WaDisableRenderCachePipelinedFlush */
5486         I915_WRITE(CACHE_MODE_0,
5487                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5488
5489         /* WaDisable_RenderCache_OperationalFlush:g4x */
5490         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5491
5492         g4x_disable_trickle_feed(dev);
5493 }
5494
5495 static void crestline_init_clock_gating(struct drm_device *dev)
5496 {
5497         struct drm_i915_private *dev_priv = dev->dev_private;
5498
5499         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5500         I915_WRITE(RENCLK_GATE_D2, 0);
5501         I915_WRITE(DSPCLK_GATE_D, 0);
5502         I915_WRITE(RAMCLK_GATE_D, 0);
5503         I915_WRITE16(DEUC, 0);
5504         I915_WRITE(MI_ARB_STATE,
5505                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5506
5507         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5508         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5509 }
5510
5511 static void broadwater_init_clock_gating(struct drm_device *dev)
5512 {
5513         struct drm_i915_private *dev_priv = dev->dev_private;
5514
5515         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5516                    I965_RCC_CLOCK_GATE_DISABLE |
5517                    I965_RCPB_CLOCK_GATE_DISABLE |
5518                    I965_ISC_CLOCK_GATE_DISABLE |
5519                    I965_FBC_CLOCK_GATE_DISABLE);
5520         I915_WRITE(RENCLK_GATE_D2, 0);
5521         I915_WRITE(MI_ARB_STATE,
5522                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5523
5524         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5525         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5526 }
5527
5528 static void gen3_init_clock_gating(struct drm_device *dev)
5529 {
5530         struct drm_i915_private *dev_priv = dev->dev_private;
5531         u32 dstate = I915_READ(D_STATE);
5532
5533         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5534                 DSTATE_DOT_CLOCK_GATING;
5535         I915_WRITE(D_STATE, dstate);
5536
5537         if (IS_PINEVIEW(dev))
5538                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5539
5540         /* IIR "flip pending" means done if this bit is set */
5541         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5542
5543         /* interrupts should cause a wake up from C3 */
5544         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
5545
5546         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5547         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5548 }
5549
5550 static void i85x_init_clock_gating(struct drm_device *dev)
5551 {
5552         struct drm_i915_private *dev_priv = dev->dev_private;
5553
5554         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5555
5556         /* interrupts should cause a wake up from C3 */
5557         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5558                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
5559 }
5560
5561 static void i830_init_clock_gating(struct drm_device *dev)
5562 {
5563         struct drm_i915_private *dev_priv = dev->dev_private;
5564
5565         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5566 }
5567
5568 void intel_init_clock_gating(struct drm_device *dev)
5569 {
5570         struct drm_i915_private *dev_priv = dev->dev_private;
5571
5572         dev_priv->display.init_clock_gating(dev);
5573 }
5574
5575 void intel_suspend_hw(struct drm_device *dev)
5576 {
5577         if (HAS_PCH_LPT(dev))
5578                 lpt_suspend_hw(dev);
5579 }
5580
5581 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5582         for (i = 0;                                                     \
5583              i < (power_domains)->power_well_count &&                   \
5584                  ((power_well) = &(power_domains)->power_wells[i]);     \
5585              i++)                                                       \
5586                 if ((power_well)->domains & (domain_mask))
5587
5588 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5589         for (i = (power_domains)->power_well_count - 1;                  \
5590              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5591              i--)                                                        \
5592                 if ((power_well)->domains & (domain_mask))
5593
5594 /**
5595  * We should only use the power well if we explicitly asked the hardware to
5596  * enable it, so check if it's enabled and also check if we've requested it to
5597  * be enabled.
5598  */
5599 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5600                                    struct i915_power_well *power_well)
5601 {
5602         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5603                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5604 }
5605
5606 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5607                                           enum intel_display_power_domain domain)
5608 {
5609         struct i915_power_domains *power_domains;
5610         struct i915_power_well *power_well;
5611         bool is_enabled;
5612         int i;
5613
5614         if (dev_priv->pm.suspended)
5615                 return false;
5616
5617         power_domains = &dev_priv->power_domains;
5618
5619         is_enabled = true;
5620
5621         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5622                 if (power_well->always_on)
5623                         continue;
5624
5625                 if (!power_well->hw_enabled) {
5626                         is_enabled = false;
5627                         break;
5628                 }
5629         }
5630
5631         return is_enabled;
5632 }
5633
5634 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5635                                  enum intel_display_power_domain domain)
5636 {
5637         struct i915_power_domains *power_domains;
5638         bool ret;
5639
5640         power_domains = &dev_priv->power_domains;
5641
5642         mutex_lock(&power_domains->lock);
5643         ret = intel_display_power_enabled_unlocked(dev_priv, domain);
5644         mutex_unlock(&power_domains->lock);
5645
5646         return ret;
5647 }
5648
5649 /*
5650  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5651  * when not needed anymore. We have 4 registers that can request the power well
5652  * to be enabled, and it will only be disabled if none of the registers is
5653  * requesting it to be enabled.
5654  */
5655 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5656 {
5657         struct drm_device *dev = dev_priv->dev;
5658         unsigned long irqflags;
5659
5660         /*
5661          * After we re-enable the power well, if we touch VGA register 0x3d5
5662          * we'll get unclaimed register interrupts. This stops after we write
5663          * anything to the VGA MSR register. The vgacon module uses this
5664          * register all the time, so if we unbind our driver and, as a
5665          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5666          * console_unlock(). So make here we touch the VGA MSR register, making
5667          * sure vgacon can keep working normally without triggering interrupts
5668          * and error messages.
5669          */
5670         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5671         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5672         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5673
5674         if (IS_BROADWELL(dev)) {
5675                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5676                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5677                            dev_priv->de_irq_mask[PIPE_B]);
5678                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5679                            ~dev_priv->de_irq_mask[PIPE_B] |
5680                            GEN8_PIPE_VBLANK);
5681                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5682                            dev_priv->de_irq_mask[PIPE_C]);
5683                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5684                            ~dev_priv->de_irq_mask[PIPE_C] |
5685                            GEN8_PIPE_VBLANK);
5686                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5687                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5688         }
5689 }
5690
5691 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5692                                struct i915_power_well *power_well, bool enable)
5693 {
5694         bool is_enabled, enable_requested;
5695         uint32_t tmp;
5696
5697         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5698         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5699         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5700
5701         if (enable) {
5702                 if (!enable_requested)
5703                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5704                                    HSW_PWR_WELL_ENABLE_REQUEST);
5705
5706                 if (!is_enabled) {
5707                         DRM_DEBUG_KMS("Enabling power well\n");
5708                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5709                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5710                                 DRM_ERROR("Timeout enabling power well\n");
5711                 }
5712
5713                 hsw_power_well_post_enable(dev_priv);
5714         } else {
5715                 if (enable_requested) {
5716                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5717                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5718                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5719                 }
5720         }
5721 }
5722
5723 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5724                                    struct i915_power_well *power_well)
5725 {
5726         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5727
5728         /*
5729          * We're taking over the BIOS, so clear any requests made by it since
5730          * the driver is in charge now.
5731          */
5732         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5733                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5734 }
5735
5736 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5737                                   struct i915_power_well *power_well)
5738 {
5739         hsw_set_power_well(dev_priv, power_well, true);
5740 }
5741
5742 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5743                                    struct i915_power_well *power_well)
5744 {
5745         hsw_set_power_well(dev_priv, power_well, false);
5746 }
5747
5748 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5749                                            struct i915_power_well *power_well)
5750 {
5751 }
5752
5753 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5754                                              struct i915_power_well *power_well)
5755 {
5756         return true;
5757 }
5758
5759 void __vlv_set_power_well(struct drm_i915_private *dev_priv,
5760                           enum punit_power_well power_well_id, bool enable)
5761 {
5762         struct drm_device *dev = dev_priv->dev;
5763         u32 mask;
5764         u32 state;
5765         u32 ctrl;
5766         enum pipe pipe;
5767
5768         if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
5769                 if (enable) {
5770                         /*
5771                          * Enable the CRI clock source so we can get at the
5772                          * display and the reference clock for VGA
5773                          * hotplug / manual detection.
5774                          */
5775                         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
5776                                    DPLL_REFA_CLK_ENABLE_VLV |
5777                                    DPLL_INTEGRATED_CRI_CLK_VLV);
5778                         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
5779                 } else {
5780                         for_each_pipe(pipe)
5781                                 assert_pll_disabled(dev_priv, pipe);
5782                         /* Assert common reset */
5783                         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
5784                                    ~DPIO_CMNRST);
5785                 }
5786         }
5787
5788         mask = PUNIT_PWRGT_MASK(power_well_id);
5789         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5790                          PUNIT_PWRGT_PWR_GATE(power_well_id);
5791
5792         mutex_lock(&dev_priv->rps.hw_lock);
5793
5794 #define COND \
5795         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5796
5797         if (COND)
5798                 goto out;
5799
5800         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5801         ctrl &= ~mask;
5802         ctrl |= state;
5803         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5804
5805         if (wait_for(COND, 100))
5806                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5807                           state,
5808                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5809
5810 #undef COND
5811
5812 out:
5813         mutex_unlock(&dev_priv->rps.hw_lock);
5814
5815         /*
5816          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
5817          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
5818          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
5819          *   b. The other bits such as sfr settings / modesel may all
5820          *      be set to 0.
5821          *
5822          * This should only be done on init and resume from S3 with
5823          * both PLLs disabled, or we risk losing DPIO and PLL
5824          * synchronization.
5825          */
5826         if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable)
5827                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
5828 }
5829
5830 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5831                                struct i915_power_well *power_well, bool enable)
5832 {
5833         enum punit_power_well power_well_id = power_well->data;
5834
5835         __vlv_set_power_well(dev_priv, power_well_id, enable);
5836 }
5837
5838 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5839                                    struct i915_power_well *power_well)
5840 {
5841         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5842 }
5843
5844 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5845                                   struct i915_power_well *power_well)
5846 {
5847         vlv_set_power_well(dev_priv, power_well, true);
5848 }
5849
5850 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5851                                    struct i915_power_well *power_well)
5852 {
5853         vlv_set_power_well(dev_priv, power_well, false);
5854 }
5855
5856 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5857                                    struct i915_power_well *power_well)
5858 {
5859         int power_well_id = power_well->data;
5860         bool enabled = false;
5861         u32 mask;
5862         u32 state;
5863         u32 ctrl;
5864
5865         mask = PUNIT_PWRGT_MASK(power_well_id);
5866         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5867
5868         mutex_lock(&dev_priv->rps.hw_lock);
5869
5870         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5871         /*
5872          * We only ever set the power-on and power-gate states, anything
5873          * else is unexpected.
5874          */
5875         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5876                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5877         if (state == ctrl)
5878                 enabled = true;
5879
5880         /*
5881          * A transient state at this point would mean some unexpected party
5882          * is poking at the power controls too.
5883          */
5884         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5885         WARN_ON(ctrl != state);
5886
5887         mutex_unlock(&dev_priv->rps.hw_lock);
5888
5889         return enabled;
5890 }
5891
5892 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5893                                           struct i915_power_well *power_well)
5894 {
5895         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5896
5897         vlv_set_power_well(dev_priv, power_well, true);
5898
5899         spin_lock_irq(&dev_priv->irq_lock);
5900         valleyview_enable_display_irqs(dev_priv);
5901         spin_unlock_irq(&dev_priv->irq_lock);
5902
5903         /*
5904          * During driver initialization/resume we can avoid restoring the
5905          * part of the HW/SW state that will be inited anyway explicitly.
5906          */
5907         if (dev_priv->power_domains.initializing)
5908                 return;
5909
5910         intel_hpd_init(dev_priv->dev);
5911
5912         i915_redisable_vga_power_on(dev_priv->dev);
5913 }
5914
5915 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5916                                            struct i915_power_well *power_well)
5917 {
5918         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5919
5920         spin_lock_irq(&dev_priv->irq_lock);
5921         valleyview_disable_display_irqs(dev_priv);
5922         spin_unlock_irq(&dev_priv->irq_lock);
5923
5924         vlv_set_power_well(dev_priv, power_well, false);
5925 }
5926
5927 static void check_power_well_state(struct drm_i915_private *dev_priv,
5928                                    struct i915_power_well *power_well)
5929 {
5930         bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5931
5932         if (power_well->always_on || !i915.disable_power_well) {
5933                 if (!enabled)
5934                         goto mismatch;
5935
5936                 return;
5937         }
5938
5939         if (enabled != (power_well->count > 0))
5940                 goto mismatch;
5941
5942         return;
5943
5944 mismatch:
5945         WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5946                   power_well->name, power_well->always_on, enabled,
5947                   power_well->count, i915.disable_power_well);
5948 }
5949
5950 void intel_display_power_get(struct drm_i915_private *dev_priv,
5951                              enum intel_display_power_domain domain)
5952 {
5953         struct i915_power_domains *power_domains;
5954         struct i915_power_well *power_well;
5955         int i;
5956
5957         intel_runtime_pm_get(dev_priv);
5958
5959         power_domains = &dev_priv->power_domains;
5960
5961         mutex_lock(&power_domains->lock);
5962
5963         for_each_power_well(i, power_well, BIT(domain), power_domains) {
5964                 if (!power_well->count++) {
5965                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5966                         power_well->ops->enable(dev_priv, power_well);
5967                         power_well->hw_enabled = true;
5968                 }
5969
5970                 check_power_well_state(dev_priv, power_well);
5971         }
5972
5973         power_domains->domain_use_count[domain]++;
5974
5975         mutex_unlock(&power_domains->lock);
5976 }
5977
5978 void intel_display_power_put(struct drm_i915_private *dev_priv,
5979                              enum intel_display_power_domain domain)
5980 {
5981         struct i915_power_domains *power_domains;
5982         struct i915_power_well *power_well;
5983         int i;
5984
5985         power_domains = &dev_priv->power_domains;
5986
5987         mutex_lock(&power_domains->lock);
5988
5989         WARN_ON(!power_domains->domain_use_count[domain]);
5990         power_domains->domain_use_count[domain]--;
5991
5992         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5993                 WARN_ON(!power_well->count);
5994
5995                 if (!--power_well->count && i915.disable_power_well) {
5996                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
5997                         power_well->hw_enabled = false;
5998                         power_well->ops->disable(dev_priv, power_well);
5999                 }
6000
6001                 check_power_well_state(dev_priv, power_well);
6002         }
6003
6004         mutex_unlock(&power_domains->lock);
6005
6006         intel_runtime_pm_put(dev_priv);
6007 }
6008
6009 static struct i915_power_domains *hsw_pwr;
6010
6011 /* Display audio driver power well request */
6012 int i915_request_power_well(void)
6013 {
6014         struct drm_i915_private *dev_priv;
6015
6016         if (!hsw_pwr)
6017                 return -ENODEV;
6018
6019         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6020                                 power_domains);
6021         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6022         return 0;
6023 }
6024 EXPORT_SYMBOL_GPL(i915_request_power_well);
6025
6026 /* Display audio driver power well release */
6027 int i915_release_power_well(void)
6028 {
6029         struct drm_i915_private *dev_priv;
6030
6031         if (!hsw_pwr)
6032                 return -ENODEV;
6033
6034         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6035                                 power_domains);
6036         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6037         return 0;
6038 }
6039 EXPORT_SYMBOL_GPL(i915_release_power_well);
6040
6041 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6042
6043 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
6044         BIT(POWER_DOMAIN_PIPE_A) |                      \
6045         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
6046         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
6047         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
6048         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
6049         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
6050         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
6051         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
6052         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
6053         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
6054         BIT(POWER_DOMAIN_PORT_CRT) |                    \
6055         BIT(POWER_DOMAIN_INIT))
6056 #define HSW_DISPLAY_POWER_DOMAINS (                             \
6057         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
6058         BIT(POWER_DOMAIN_INIT))
6059
6060 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
6061         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
6062         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6063 #define BDW_DISPLAY_POWER_DOMAINS (                             \
6064         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
6065         BIT(POWER_DOMAIN_INIT))
6066
6067 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
6068 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
6069
6070 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
6071         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6072         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6073         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6074         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6075         BIT(POWER_DOMAIN_PORT_CRT) |            \
6076         BIT(POWER_DOMAIN_INIT))
6077
6078 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
6079         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6080         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6081         BIT(POWER_DOMAIN_INIT))
6082
6083 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
6084         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6085         BIT(POWER_DOMAIN_INIT))
6086
6087 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
6088         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6089         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6090         BIT(POWER_DOMAIN_INIT))
6091
6092 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
6093         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6094         BIT(POWER_DOMAIN_INIT))
6095
6096 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6097         .sync_hw = i9xx_always_on_power_well_noop,
6098         .enable = i9xx_always_on_power_well_noop,
6099         .disable = i9xx_always_on_power_well_noop,
6100         .is_enabled = i9xx_always_on_power_well_enabled,
6101 };
6102
6103 static struct i915_power_well i9xx_always_on_power_well[] = {
6104         {
6105                 .name = "always-on",
6106                 .always_on = 1,
6107                 .domains = POWER_DOMAIN_MASK,
6108                 .ops = &i9xx_always_on_power_well_ops,
6109         },
6110 };
6111
6112 static const struct i915_power_well_ops hsw_power_well_ops = {
6113         .sync_hw = hsw_power_well_sync_hw,
6114         .enable = hsw_power_well_enable,
6115         .disable = hsw_power_well_disable,
6116         .is_enabled = hsw_power_well_enabled,
6117 };
6118
6119 static struct i915_power_well hsw_power_wells[] = {
6120         {
6121                 .name = "always-on",
6122                 .always_on = 1,
6123                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6124                 .ops = &i9xx_always_on_power_well_ops,
6125         },
6126         {
6127                 .name = "display",
6128                 .domains = HSW_DISPLAY_POWER_DOMAINS,
6129                 .ops = &hsw_power_well_ops,
6130         },
6131 };
6132
6133 static struct i915_power_well bdw_power_wells[] = {
6134         {
6135                 .name = "always-on",
6136                 .always_on = 1,
6137                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6138                 .ops = &i9xx_always_on_power_well_ops,
6139         },
6140         {
6141                 .name = "display",
6142                 .domains = BDW_DISPLAY_POWER_DOMAINS,
6143                 .ops = &hsw_power_well_ops,
6144         },
6145 };
6146
6147 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6148         .sync_hw = vlv_power_well_sync_hw,
6149         .enable = vlv_display_power_well_enable,
6150         .disable = vlv_display_power_well_disable,
6151         .is_enabled = vlv_power_well_enabled,
6152 };
6153
6154 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6155         .sync_hw = vlv_power_well_sync_hw,
6156         .enable = vlv_power_well_enable,
6157         .disable = vlv_power_well_disable,
6158         .is_enabled = vlv_power_well_enabled,
6159 };
6160
6161 static struct i915_power_well vlv_power_wells[] = {
6162         {
6163                 .name = "always-on",
6164                 .always_on = 1,
6165                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6166                 .ops = &i9xx_always_on_power_well_ops,
6167         },
6168         {
6169                 .name = "display",
6170                 .domains = VLV_DISPLAY_POWER_DOMAINS,
6171                 .data = PUNIT_POWER_WELL_DISP2D,
6172                 .ops = &vlv_display_power_well_ops,
6173         },
6174         {
6175                 .name = "dpio-tx-b-01",
6176                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6177                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6178                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6179                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6180                 .ops = &vlv_dpio_power_well_ops,
6181                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6182         },
6183         {
6184                 .name = "dpio-tx-b-23",
6185                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6186                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6187                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6188                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6189                 .ops = &vlv_dpio_power_well_ops,
6190                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6191         },
6192         {
6193                 .name = "dpio-tx-c-01",
6194                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6195                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6196                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6197                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6198                 .ops = &vlv_dpio_power_well_ops,
6199                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6200         },
6201         {
6202                 .name = "dpio-tx-c-23",
6203                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6204                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6205                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6206                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6207                 .ops = &vlv_dpio_power_well_ops,
6208                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6209         },
6210         {
6211                 .name = "dpio-common",
6212                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6213                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6214                 .ops = &vlv_dpio_power_well_ops,
6215         },
6216 };
6217
6218 #define set_power_wells(power_domains, __power_wells) ({                \
6219         (power_domains)->power_wells = (__power_wells);                 \
6220         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
6221 })
6222
6223 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6224 {
6225         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6226
6227         mutex_init(&power_domains->lock);
6228
6229         /*
6230          * The enabling order will be from lower to higher indexed wells,
6231          * the disabling order is reversed.
6232          */
6233         if (IS_HASWELL(dev_priv->dev)) {
6234                 set_power_wells(power_domains, hsw_power_wells);
6235                 hsw_pwr = power_domains;
6236         } else if (IS_BROADWELL(dev_priv->dev)) {
6237                 set_power_wells(power_domains, bdw_power_wells);
6238                 hsw_pwr = power_domains;
6239         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6240                 set_power_wells(power_domains, vlv_power_wells);
6241         } else {
6242                 set_power_wells(power_domains, i9xx_always_on_power_well);
6243         }
6244
6245         return 0;
6246 }
6247
6248 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6249 {
6250         hsw_pwr = NULL;
6251 }
6252
6253 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6254 {
6255         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6256         struct i915_power_well *power_well;
6257         int i;
6258
6259         mutex_lock(&power_domains->lock);
6260         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6261                 power_well->ops->sync_hw(dev_priv, power_well);
6262                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6263                                                                      power_well);
6264         }
6265         mutex_unlock(&power_domains->lock);
6266 }
6267
6268 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6269 {
6270         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6271
6272         power_domains->initializing = true;
6273         /* For now, we need the power well to be always enabled. */
6274         intel_display_set_init_power(dev_priv, true);
6275         intel_power_domains_resume(dev_priv);
6276         power_domains->initializing = false;
6277 }
6278
6279 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6280 {
6281         intel_runtime_pm_get(dev_priv);
6282 }
6283
6284 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6285 {
6286         intel_runtime_pm_put(dev_priv);
6287 }
6288
6289 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6290 {
6291         struct drm_device *dev = dev_priv->dev;
6292         struct device *device = &dev->pdev->dev;
6293
6294         if (!HAS_RUNTIME_PM(dev))
6295                 return;
6296
6297         pm_runtime_get_sync(device);
6298         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6299 }
6300
6301 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6302 {
6303         struct drm_device *dev = dev_priv->dev;
6304         struct device *device = &dev->pdev->dev;
6305
6306         if (!HAS_RUNTIME_PM(dev))
6307                 return;
6308
6309         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6310         pm_runtime_get_noresume(device);
6311 }
6312
6313 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6314 {
6315         struct drm_device *dev = dev_priv->dev;
6316         struct device *device = &dev->pdev->dev;
6317
6318         if (!HAS_RUNTIME_PM(dev))
6319                 return;
6320
6321         pm_runtime_mark_last_busy(device);
6322         pm_runtime_put_autosuspend(device);
6323 }
6324
6325 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6326 {
6327         struct drm_device *dev = dev_priv->dev;
6328         struct device *device = &dev->pdev->dev;
6329
6330         if (!HAS_RUNTIME_PM(dev))
6331                 return;
6332
6333         pm_runtime_set_active(device);
6334
6335         /*
6336          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6337          * requirement.
6338          */
6339         if (!intel_enable_rc6(dev)) {
6340                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6341                 return;
6342         }
6343
6344         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6345         pm_runtime_mark_last_busy(device);
6346         pm_runtime_use_autosuspend(device);
6347
6348         pm_runtime_put_autosuspend(device);
6349 }
6350
6351 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6352 {
6353         struct drm_device *dev = dev_priv->dev;
6354         struct device *device = &dev->pdev->dev;
6355
6356         if (!HAS_RUNTIME_PM(dev))
6357                 return;
6358
6359         if (!intel_enable_rc6(dev))
6360                 return;
6361
6362         /* Make sure we're not suspended first. */
6363         pm_runtime_get_sync(device);
6364         pm_runtime_disable(device);
6365 }
6366
6367 /* Set up chip specific power management-related functions */
6368 void intel_init_pm(struct drm_device *dev)
6369 {
6370         struct drm_i915_private *dev_priv = dev->dev_private;
6371
6372         if (HAS_FBC(dev)) {
6373                 if (INTEL_INFO(dev)->gen >= 7) {
6374                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6375                         dev_priv->display.enable_fbc = gen7_enable_fbc;
6376                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6377                 } else if (INTEL_INFO(dev)->gen >= 5) {
6378                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6379                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6380                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6381                 } else if (IS_GM45(dev)) {
6382                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6383                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6384                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6385                 } else {
6386                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6387                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6388                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6389
6390                         /* This value was pulled out of someone's hat */
6391                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6392                 }
6393         }
6394
6395         /* For cxsr */
6396         if (IS_PINEVIEW(dev))
6397                 i915_pineview_get_mem_freq(dev);
6398         else if (IS_GEN5(dev))
6399                 i915_ironlake_get_mem_freq(dev);
6400
6401         /* For FIFO watermark updates */
6402         if (HAS_PCH_SPLIT(dev)) {
6403                 ilk_setup_wm_latency(dev);
6404
6405                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6406                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6407                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6408                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6409                         dev_priv->display.update_wm = ilk_update_wm;
6410                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6411                 } else {
6412                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6413                                       "Disable CxSR\n");
6414                 }
6415
6416                 if (IS_GEN5(dev))
6417                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6418                 else if (IS_GEN6(dev))
6419                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6420                 else if (IS_IVYBRIDGE(dev))
6421                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6422                 else if (IS_HASWELL(dev))
6423                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6424                 else if (INTEL_INFO(dev)->gen == 8)
6425                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6426         } else if (IS_CHERRYVIEW(dev)) {
6427                 dev_priv->display.update_wm = valleyview_update_wm;
6428                 dev_priv->display.init_clock_gating =
6429                         cherryview_init_clock_gating;
6430         } else if (IS_VALLEYVIEW(dev)) {
6431                 dev_priv->display.update_wm = valleyview_update_wm;
6432                 dev_priv->display.init_clock_gating =
6433                         valleyview_init_clock_gating;
6434         } else if (IS_PINEVIEW(dev)) {
6435                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6436                                             dev_priv->is_ddr3,
6437                                             dev_priv->fsb_freq,
6438                                             dev_priv->mem_freq)) {
6439                         DRM_INFO("failed to find known CxSR latency "
6440                                  "(found ddr%s fsb freq %d, mem freq %d), "
6441                                  "disabling CxSR\n",
6442                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6443                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6444                         /* Disable CxSR and never update its watermark again */
6445                         pineview_disable_cxsr(dev);
6446                         dev_priv->display.update_wm = NULL;
6447                 } else
6448                         dev_priv->display.update_wm = pineview_update_wm;
6449                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6450         } else if (IS_G4X(dev)) {
6451                 dev_priv->display.update_wm = g4x_update_wm;
6452                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6453         } else if (IS_GEN4(dev)) {
6454                 dev_priv->display.update_wm = i965_update_wm;
6455                 if (IS_CRESTLINE(dev))
6456                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6457                 else if (IS_BROADWATER(dev))
6458                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6459         } else if (IS_GEN3(dev)) {
6460                 dev_priv->display.update_wm = i9xx_update_wm;
6461                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6462                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6463         } else if (IS_GEN2(dev)) {
6464                 if (INTEL_INFO(dev)->num_pipes == 1) {
6465                         dev_priv->display.update_wm = i845_update_wm;
6466                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6467                 } else {
6468                         dev_priv->display.update_wm = i9xx_update_wm;
6469                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6470                 }
6471
6472                 if (IS_I85X(dev) || IS_I865G(dev))
6473                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6474                 else
6475                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6476         } else {
6477                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6478         }
6479 }
6480
6481 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6482 {
6483         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6484
6485         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6486                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6487                 return -EAGAIN;
6488         }
6489
6490         I915_WRITE(GEN6_PCODE_DATA, *val);
6491         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6492
6493         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6494                      500)) {
6495                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6496                 return -ETIMEDOUT;
6497         }
6498
6499         *val = I915_READ(GEN6_PCODE_DATA);
6500         I915_WRITE(GEN6_PCODE_DATA, 0);
6501
6502         return 0;
6503 }
6504
6505 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6506 {
6507         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6508
6509         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6510                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6511                 return -EAGAIN;
6512         }
6513
6514         I915_WRITE(GEN6_PCODE_DATA, val);
6515         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6516
6517         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6518                      500)) {
6519                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6520                 return -ETIMEDOUT;
6521         }
6522
6523         I915_WRITE(GEN6_PCODE_DATA, 0);
6524
6525         return 0;
6526 }
6527
6528 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6529 {
6530         int div;
6531
6532         /* 4 x czclk */
6533         switch (dev_priv->mem_freq) {
6534         case 800:
6535                 div = 10;
6536                 break;
6537         case 1066:
6538                 div = 12;
6539                 break;
6540         case 1333:
6541                 div = 16;
6542                 break;
6543         default:
6544                 return -1;
6545         }
6546
6547         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6548 }
6549
6550 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6551 {
6552         int mul;
6553
6554         /* 4 x czclk */
6555         switch (dev_priv->mem_freq) {
6556         case 800:
6557                 mul = 10;
6558                 break;
6559         case 1066:
6560                 mul = 12;
6561                 break;
6562         case 1333:
6563                 mul = 16;
6564                 break;
6565         default:
6566                 return -1;
6567         }
6568
6569         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6570 }
6571
6572 void intel_pm_setup(struct drm_device *dev)
6573 {
6574         struct drm_i915_private *dev_priv = dev->dev_private;
6575
6576         mutex_init(&dev_priv->rps.hw_lock);
6577
6578         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6579                           intel_gen6_powersave_work);
6580
6581         dev_priv->pm.suspended = false;
6582         dev_priv->pm.irqs_disabled = false;
6583 }