drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_reg.h"
  32 #include "intel_drv.h"
  33 #include "intel_frontbuffer.h"
  34
  35 /* Limits for overlay size. According to intel doc, the real limits are:
  36  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  37  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  38  * the mininum of both.  */
  39 #define IMAGE_MAX_WIDTH         2048
  40 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  41 /* on 830 and 845 these large limits result in the card hanging */
  42 #define IMAGE_MAX_WIDTH_LEGACY  1024
  43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  44
  45 /* overlay register definitions */
  46 /* OCMD register */
  47 #define OCMD_TILED_SURFACE      (0x1<<19)
  48 #define OCMD_MIRROR_MASK        (0x3<<17)
  49 #define OCMD_MIRROR_MODE        (0x3<<17)
  50 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  51 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  52 #define OCMD_MIRROR_BOTH        (0x3<<17)
  53 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  54 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  55 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  56 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  58 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  60 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  61 #define OCMD_YUV_422_PACKED     (0x8<<10)
  62 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  64 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  65 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  66 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  67 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  68 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  69 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  70 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  71 #define OCMD_TEST_MODE          (0x1<<4)
  72 #define OCMD_BUFFER_SELECT      (0x3<<2)
  73 #define OCMD_BUFFER0            (0x0<<2)
  74 #define OCMD_BUFFER1            (0x1<<2)
  75 #define OCMD_FIELD_SELECT       (0x1<<2)
  76 #define OCMD_FIELD0             (0x0<<1)
  77 #define OCMD_FIELD1             (0x1<<1)
  78 #define OCMD_ENABLE             (0x1<<0)
  79
  80 /* OCONFIG register */
  81 #define OCONF_PIPE_MASK         (0x1<<18)
  82 #define OCONF_PIPE_A            (0x0<<18)
  83 #define OCONF_PIPE_B            (0x1<<18)
  84 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  85 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  86 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  87 #define OCONF_CSC_BYPASS        (0x1<<4)
  88 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  89 #define OCONF_TEST_MODE         (0x1<<2)
  90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  91 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  92
  93 /* DCLRKM (dst-key) register */
  94 #define DST_KEY_ENABLE          (0x1<<31)
  95 #define CLK_RGB24_MASK          0x0
  96 #define CLK_RGB16_MASK          0x070307
  97 #define CLK_RGB15_MASK          0x070707
  98 #define CLK_RGB8I_MASK          0xffffff
  99
 100 #define RGB16_TO_COLORKEY(c) \
 101         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 102 #define RGB15_TO_COLORKEY(c) \
 103         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 104
 105 /* overlay flip addr flag */
 106 #define OFC_UPDATE              0x1
 107
 108 /* polyphase filter coefficients */
 109 #define N_HORIZ_Y_TAPS          5
 110 #define N_VERT_Y_TAPS           3
 111 #define N_HORIZ_UV_TAPS         3
 112 #define N_VERT_UV_TAPS          3
 113 #define N_PHASES                17
 114 #define MAX_TAPS                5
 115
 116 /* memory bufferd overlay registers */
 117 struct overlay_registers {
 118         u32 OBUF_0Y;
 119         u32 OBUF_1Y;
 120         u32 OBUF_0U;
 121         u32 OBUF_0V;
 122         u32 OBUF_1U;
 123         u32 OBUF_1V;
 124         u32 OSTRIDE;
 125         u32 YRGB_VPH;
 126         u32 UV_VPH;
 127         u32 HORZ_PH;
 128         u32 INIT_PHS;
 129         u32 DWINPOS;
 130         u32 DWINSZ;
 131         u32 SWIDTH;
 132         u32 SWIDTHSW;
 133         u32 SHEIGHT;
 134         u32 YRGBSCALE;
 135         u32 UVSCALE;
 136         u32 OCLRC0;
 137         u32 OCLRC1;
 138         u32 DCLRKV;
 139         u32 DCLRKM;
 140         u32 SCLRKVH;
 141         u32 SCLRKVL;
 142         u32 SCLRKEN;
 143         u32 OCONFIG;
 144         u32 OCMD;
 145         u32 RESERVED1; /* 0x6C */
 146         u32 OSTART_0Y;
 147         u32 OSTART_1Y;
 148         u32 OSTART_0U;
 149         u32 OSTART_0V;
 150         u32 OSTART_1U;
 151         u32 OSTART_1V;
 152         u32 OTILEOFF_0Y;
 153         u32 OTILEOFF_1Y;
 154         u32 OTILEOFF_0U;
 155         u32 OTILEOFF_0V;
 156         u32 OTILEOFF_1U;
 157         u32 OTILEOFF_1V;
 158         u32 FASTHSCALE; /* 0xA0 */
 159         u32 UVSCALEV; /* 0xA4 */
 160         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 161         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 162         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 163         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 164         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 165         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 166         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 167         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 168         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 169 };
 170
 171 struct intel_overlay {
 172         struct drm_i915_private *i915;
 173         struct intel_crtc *crtc;
 174         struct i915_vma *vma;
 175         struct i915_vma *old_vma;
 176         bool active;
 177         bool pfit_active;
 178         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 179         u32 color_key:24;
 180         u32 color_key_enabled:1;
 181         u32 brightness, contrast, saturation;
 182         u32 old_xscale, old_yscale;
 183         /* register access */
 184         struct drm_i915_gem_object *reg_bo;
 185         struct overlay_registers __iomem *regs;
 186         u32 flip_addr;
 187         /* flip handling */
 188         struct i915_gem_active last_flip;
 189 };
 190
 191 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
 192                                       bool enable)
 193 {
 194         struct pci_dev *pdev = dev_priv->drm.pdev;
 195         u8 val;
 196
 197         /* WA_OVERLAY_CLKGATE:alm */
 198         if (enable)
 199                 I915_WRITE(DSPCLK_GATE_D, 0);
 200         else
 201                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 202
 203         /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
 204         pci_bus_read_config_byte(pdev->bus,
 205                                  PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
 206         if (enable)
 207                 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
 208         else
 209                 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
 210         pci_bus_write_config_byte(pdev->bus,
 211                                   PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
 212 }
 213
 214 static void intel_overlay_submit_request(struct intel_overlay *overlay,
 215                                          struct i915_request *rq,
 216                                          i915_gem_retire_fn retire)
 217 {
 218         GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
 219                                         &overlay->i915->drm.struct_mutex));
 220         i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
 221                                       &overlay->i915->drm.struct_mutex);
 222         i915_gem_active_set(&overlay->last_flip, rq);
 223         i915_request_add(rq);
 224 }
 225
 226 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 227                                          struct i915_request *rq,
 228                                          i915_gem_retire_fn retire)
 229 {
 230         intel_overlay_submit_request(overlay, rq, retire);
 231         return i915_gem_active_retire(&overlay->last_flip,
 232                                       &overlay->i915->drm.struct_mutex);
 233 }
 234
 235 static struct i915_request *alloc_request(struct intel_overlay *overlay)
 236 {
 237         struct drm_i915_private *dev_priv = overlay->i915;
 238         struct intel_engine_cs *engine = dev_priv->engine[RCS];
 239
 240         return i915_request_alloc(engine, dev_priv->kernel_context);
 241 }
 242
 243 /* overlay needs to be disable in OCMD reg */
 244 static int intel_overlay_on(struct intel_overlay *overlay)
 245 {
 246         struct drm_i915_private *dev_priv = overlay->i915;
 247         struct i915_request *rq;
 248         u32 *cs;
 249
 250         WARN_ON(overlay->active);
 251
 252         rq = alloc_request(overlay);
 253         if (IS_ERR(rq))
 254                 return PTR_ERR(rq);
 255
 256         cs = intel_ring_begin(rq, 4);
 257         if (IS_ERR(cs)) {
 258                 i915_request_add(rq);
 259                 return PTR_ERR(cs);
 260         }
 261
 262         overlay->active = true;
 263
 264         if (IS_I830(dev_priv))
 265                 i830_overlay_clock_gating(dev_priv, false);
 266
 267         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
 268         *cs++ = overlay->flip_addr | OFC_UPDATE;
 269         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 270         *cs++ = MI_NOOP;
 271         intel_ring_advance(rq, cs);
 272
 273         return intel_overlay_do_wait_request(overlay, rq, NULL);
 274 }
 275
 276 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 277                                        struct i915_vma *vma)
 278 {
 279         enum pipe pipe = overlay->crtc->pipe;
 280
 281         WARN_ON(overlay->old_vma);
 282
 283         i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
 284                           vma ? vma->obj : NULL,
 285                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 286
 287         intel_frontbuffer_flip_prepare(overlay->i915,
 288                                        INTEL_FRONTBUFFER_OVERLAY(pipe));
 289
 290         overlay->old_vma = overlay->vma;
 291         if (vma)
 292                 overlay->vma = i915_vma_get(vma);
 293         else
 294                 overlay->vma = NULL;
 295 }
 296
 297 /* overlay needs to be enabled in OCMD reg */
 298 static int intel_overlay_continue(struct intel_overlay *overlay,
 299                                   struct i915_vma *vma,
 300                                   bool load_polyphase_filter)
 301 {
 302         struct drm_i915_private *dev_priv = overlay->i915;
 303         struct i915_request *rq;
 304         u32 flip_addr = overlay->flip_addr;
 305         u32 tmp, *cs;
 306
 307         WARN_ON(!overlay->active);
 308
 309         if (load_polyphase_filter)
 310                 flip_addr |= OFC_UPDATE;
 311
 312         /* check for underruns */
 313         tmp = I915_READ(DOVSTA);
 314         if (tmp & (1 << 17))
 315                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 316
 317         rq = alloc_request(overlay);
 318         if (IS_ERR(rq))
 319                 return PTR_ERR(rq);
 320
 321         cs = intel_ring_begin(rq, 2);
 322         if (IS_ERR(cs)) {
 323                 i915_request_add(rq);
 324                 return PTR_ERR(cs);
 325         }
 326
 327         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 328         *cs++ = flip_addr;
 329         intel_ring_advance(rq, cs);
 330
 331         intel_overlay_flip_prepare(overlay, vma);
 332
 333         intel_overlay_submit_request(overlay, rq, NULL);
 334
 335         return 0;
 336 }
 337
 338 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 339 {
 340         struct i915_vma *vma;
 341
 342         vma = fetch_and_zero(&overlay->old_vma);
 343         if (WARN_ON(!vma))
 344                 return;
 345
 346         intel_frontbuffer_flip_complete(overlay->i915,
 347                                         INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 348
 349         i915_gem_object_unpin_from_display_plane(vma);
 350         i915_vma_put(vma);
 351 }
 352
 353 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
 354                                                struct i915_request *rq)
 355 {
 356         struct intel_overlay *overlay =
 357                 container_of(active, typeof(*overlay), last_flip);
 358
 359         intel_overlay_release_old_vma(overlay);
 360 }
 361
 362 static void intel_overlay_off_tail(struct i915_gem_active *active,
 363                                    struct i915_request *rq)
 364 {
 365         struct intel_overlay *overlay =
 366                 container_of(active, typeof(*overlay), last_flip);
 367         struct drm_i915_private *dev_priv = overlay->i915;
 368
 369         intel_overlay_release_old_vma(overlay);
 370
 371         overlay->crtc->overlay = NULL;
 372         overlay->crtc = NULL;
 373         overlay->active = false;
 374
 375         if (IS_I830(dev_priv))
 376                 i830_overlay_clock_gating(dev_priv, true);
 377 }
 378
 379 /* overlay needs to be disabled in OCMD reg */
 380 static int intel_overlay_off(struct intel_overlay *overlay)
 381 {
 382         struct i915_request *rq;
 383         u32 *cs, flip_addr = overlay->flip_addr;
 384
 385         WARN_ON(!overlay->active);
 386
 387         /* According to intel docs the overlay hw may hang (when switching
 388          * off) without loading the filter coeffs. It is however unclear whether
 389          * this applies to the disabling of the overlay or to the switching off
 390          * of the hw. Do it in both cases */
 391         flip_addr |= OFC_UPDATE;
 392
 393         rq = alloc_request(overlay);
 394         if (IS_ERR(rq))
 395                 return PTR_ERR(rq);
 396
 397         cs = intel_ring_begin(rq, 6);
 398         if (IS_ERR(cs)) {
 399                 i915_request_add(rq);
 400                 return PTR_ERR(cs);
 401         }
 402
 403         /* wait for overlay to go idle */
 404         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 405         *cs++ = flip_addr;
 406         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 407
 408         /* turn overlay off */
 409         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
 410         *cs++ = flip_addr;
 411         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 412
 413         intel_ring_advance(rq, cs);
 414
 415         intel_overlay_flip_prepare(overlay, NULL);
 416
 417         return intel_overlay_do_wait_request(overlay, rq,
 418                                              intel_overlay_off_tail);
 419 }
 420
 421 /* recover from an interruption due to a signal
 422  * We have to be careful not to repeat work forever an make forward progess. */
 423 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 424 {
 425         return i915_gem_active_retire(&overlay->last_flip,
 426                                       &overlay->i915->drm.struct_mutex);
 427 }
 428
 429 /* Wait for pending overlay flip and release old frame.
 430  * Needs to be called before the overlay register are changed
 431  * via intel_overlay_(un)map_regs
 432  */
 433 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 434 {
 435         struct drm_i915_private *dev_priv = overlay->i915;
 436         u32 *cs;
 437         int ret;
 438
 439         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 440
 441         /* Only wait if there is actually an old frame to release to
 442          * guarantee forward progress.
 443          */
 444         if (!overlay->old_vma)
 445                 return 0;
 446
 447         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 448                 /* synchronous slowpath */
 449                 struct i915_request *rq;
 450
 451                 rq = alloc_request(overlay);
 452                 if (IS_ERR(rq))
 453                         return PTR_ERR(rq);
 454
 455                 cs = intel_ring_begin(rq, 2);
 456                 if (IS_ERR(cs)) {
 457                         i915_request_add(rq);
 458                         return PTR_ERR(cs);
 459                 }
 460
 461                 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 462                 *cs++ = MI_NOOP;
 463                 intel_ring_advance(rq, cs);
 464
 465                 ret = intel_overlay_do_wait_request(overlay, rq,
 466                                                     intel_overlay_release_old_vid_tail);
 467                 if (ret)
 468                         return ret;
 469         } else
 470                 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
 471
 472         return 0;
 473 }
 474
 475 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 476 {
 477         struct intel_overlay *overlay = dev_priv->overlay;
 478
 479         if (!overlay)
 480                 return;
 481
 482         intel_overlay_release_old_vid(overlay);
 483
 484         overlay->old_xscale = 0;
 485         overlay->old_yscale = 0;
 486         overlay->crtc = NULL;
 487         overlay->active = false;
 488 }
 489
 490 static int packed_depth_bytes(u32 format)
 491 {
 492         switch (format & I915_OVERLAY_DEPTH_MASK) {
 493         case I915_OVERLAY_YUV422:
 494                 return 4;
 495         case I915_OVERLAY_YUV411:
 496                 /* return 6; not implemented */
 497         default:
 498                 return -EINVAL;
 499         }
 500 }
 501
 502 static int packed_width_bytes(u32 format, short width)
 503 {
 504         switch (format & I915_OVERLAY_DEPTH_MASK) {
 505         case I915_OVERLAY_YUV422:
 506                 return width << 1;
 507         default:
 508                 return -EINVAL;
 509         }
 510 }
 511
 512 static int uv_hsubsampling(u32 format)
 513 {
 514         switch (format & I915_OVERLAY_DEPTH_MASK) {
 515         case I915_OVERLAY_YUV422:
 516         case I915_OVERLAY_YUV420:
 517                 return 2;
 518         case I915_OVERLAY_YUV411:
 519         case I915_OVERLAY_YUV410:
 520                 return 4;
 521         default:
 522                 return -EINVAL;
 523         }
 524 }
 525
 526 static int uv_vsubsampling(u32 format)
 527 {
 528         switch (format & I915_OVERLAY_DEPTH_MASK) {
 529         case I915_OVERLAY_YUV420:
 530         case I915_OVERLAY_YUV410:
 531                 return 2;
 532         case I915_OVERLAY_YUV422:
 533         case I915_OVERLAY_YUV411:
 534                 return 1;
 535         default:
 536                 return -EINVAL;
 537         }
 538 }
 539
 540 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 541 {
 542         u32 sw;
 543
 544         if (IS_GEN2(dev_priv))
 545                 sw = ALIGN((offset & 31) + width, 32);
 546         else
 547                 sw = ALIGN((offset & 63) + width, 64);
 548
 549         if (sw == 0)
 550                 return 0;
 551
 552         return (sw - 32) >> 3;
 553 }
 554
 555 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
 556         [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
 557         [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
 558         [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
 559         [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
 560         [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
 561         [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
 562         [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
 563         [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
 564         [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
 565         [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
 566         [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
 567         [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
 568         [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
 569         [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
 570         [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
 571         [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
 572         [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
 573 };
 574
 575 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
 576         [ 0] = { 0x3000, 0x1800, 0x1800, },
 577         [ 1] = { 0xb000, 0x18d0, 0x2e60, },
 578         [ 2] = { 0xb000, 0x1990, 0x2ce0, },
 579         [ 3] = { 0xb020, 0x1a68, 0x2b40, },
 580         [ 4] = { 0xb040, 0x1b20, 0x29e0, },
 581         [ 5] = { 0xb060, 0x1bd8, 0x2880, },
 582         [ 6] = { 0xb080, 0x1c88, 0x3e60, },
 583         [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
 584         [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
 585         [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
 586         [10] = { 0xb100, 0x1eb8, 0x3620, },
 587         [11] = { 0xb100, 0x1f18, 0x34a0, },
 588         [12] = { 0xb100, 0x1f68, 0x3360, },
 589         [13] = { 0xb0e0, 0x1fa8, 0x3240, },
 590         [14] = { 0xb0c0, 0x1fe0, 0x3140, },
 591         [15] = { 0xb060, 0x1ff0, 0x30a0, },
 592         [16] = { 0x3000, 0x0800, 0x3000, },
 593 };
 594
 595 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 596 {
 597         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 598         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 599                     sizeof(uv_static_hcoeffs));
 600 }
 601
 602 static bool update_scaling_factors(struct intel_overlay *overlay,
 603                                    struct overlay_registers __iomem *regs,
 604                                    struct drm_intel_overlay_put_image *params)
 605 {
 606         /* fixed point with a 12 bit shift */
 607         u32 xscale, yscale, xscale_UV, yscale_UV;
 608 #define FP_SHIFT 12
 609 #define FRACT_MASK 0xfff
 610         bool scale_changed = false;
 611         int uv_hscale = uv_hsubsampling(params->flags);
 612         int uv_vscale = uv_vsubsampling(params->flags);
 613
 614         if (params->dst_width > 1)
 615                 xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
 616                         params->dst_width;
 617         else
 618                 xscale = 1 << FP_SHIFT;
 619
 620         if (params->dst_height > 1)
 621                 yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
 622                         params->dst_height;
 623         else
 624                 yscale = 1 << FP_SHIFT;
 625
 626         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 627         xscale_UV = xscale/uv_hscale;
 628         yscale_UV = yscale/uv_vscale;
 629         /* make the Y scale to UV scale ratio an exact multiply */
 630         xscale = xscale_UV * uv_hscale;
 631         yscale = yscale_UV * uv_vscale;
 632         /*} else {
 633           xscale_UV = 0;
 634           yscale_UV = 0;
 635           }*/
 636
 637         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 638                 scale_changed = true;
 639         overlay->old_xscale = xscale;
 640         overlay->old_yscale = yscale;
 641
 642         iowrite32(((yscale & FRACT_MASK) << 20) |
 643                   ((xscale >> FP_SHIFT)  << 16) |
 644                   ((xscale & FRACT_MASK) << 3),
 645                  &regs->YRGBSCALE);
 646
 647         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 648                   ((xscale_UV >> FP_SHIFT)  << 16) |
 649                   ((xscale_UV & FRACT_MASK) << 3),
 650                  &regs->UVSCALE);
 651
 652         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 653                    ((yscale_UV >> FP_SHIFT) << 0)),
 654                  &regs->UVSCALEV);
 655
 656         if (scale_changed)
 657                 update_polyphase_filter(regs);
 658
 659         return scale_changed;
 660 }
 661
 662 static void update_colorkey(struct intel_overlay *overlay,
 663                             struct overlay_registers __iomem *regs)
 664 {
 665         const struct intel_plane_state *state =
 666                 to_intel_plane_state(overlay->crtc->base.primary->state);
 667         u32 key = overlay->color_key;
 668         u32 format = 0;
 669         u32 flags = 0;
 670
 671         if (overlay->color_key_enabled)
 672                 flags |= DST_KEY_ENABLE;
 673
 674         if (state->base.visible)
 675                 format = state->base.fb->format->format;
 676
 677         switch (format) {
 678         case DRM_FORMAT_C8:
 679                 key = 0;
 680                 flags |= CLK_RGB8I_MASK;
 681                 break;
 682         case DRM_FORMAT_XRGB1555:
 683                 key = RGB15_TO_COLORKEY(key);
 684                 flags |= CLK_RGB15_MASK;
 685                 break;
 686         case DRM_FORMAT_RGB565:
 687                 key = RGB16_TO_COLORKEY(key);
 688                 flags |= CLK_RGB16_MASK;
 689                 break;
 690         default:
 691                 flags |= CLK_RGB24_MASK;
 692                 break;
 693         }
 694
 695         iowrite32(key, &regs->DCLRKV);
 696         iowrite32(flags, &regs->DCLRKM);
 697 }
 698
 699 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
 700 {
 701         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 702
 703         if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 704                 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 705                 case I915_OVERLAY_YUV422:
 706                         cmd |= OCMD_YUV_422_PLANAR;
 707                         break;
 708                 case I915_OVERLAY_YUV420:
 709                         cmd |= OCMD_YUV_420_PLANAR;
 710                         break;
 711                 case I915_OVERLAY_YUV411:
 712                 case I915_OVERLAY_YUV410:
 713                         cmd |= OCMD_YUV_410_PLANAR;
 714                         break;
 715                 }
 716         } else { /* YUV packed */
 717                 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 718                 case I915_OVERLAY_YUV422:
 719                         cmd |= OCMD_YUV_422_PACKED;
 720                         break;
 721                 case I915_OVERLAY_YUV411:
 722                         cmd |= OCMD_YUV_411_PACKED;
 723                         break;
 724                 }
 725
 726                 switch (params->flags & I915_OVERLAY_SWAP_MASK) {
 727                 case I915_OVERLAY_NO_SWAP:
 728                         break;
 729                 case I915_OVERLAY_UV_SWAP:
 730                         cmd |= OCMD_UV_SWAP;
 731                         break;
 732                 case I915_OVERLAY_Y_SWAP:
 733                         cmd |= OCMD_Y_SWAP;
 734                         break;
 735                 case I915_OVERLAY_Y_AND_UV_SWAP:
 736                         cmd |= OCMD_Y_AND_UV_SWAP;
 737                         break;
 738                 }
 739         }
 740
 741         return cmd;
 742 }
 743
 744 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 745                                       struct drm_i915_gem_object *new_bo,
 746                                       struct drm_intel_overlay_put_image *params)
 747 {
 748         struct overlay_registers __iomem *regs = overlay->regs;
 749         struct drm_i915_private *dev_priv = overlay->i915;
 750         u32 swidth, swidthsw, sheight, ostride;
 751         enum pipe pipe = overlay->crtc->pipe;
 752         bool scale_changed = false;
 753         struct i915_vma *vma;
 754         int ret, tmp_width;
 755
 756         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 757         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 758
 759         ret = intel_overlay_release_old_vid(overlay);
 760         if (ret != 0)
 761                 return ret;
 762
 763         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
 764
 765         vma = i915_gem_object_pin_to_display_plane(new_bo,
 766                                                    0, NULL, PIN_MAPPABLE);
 767         if (IS_ERR(vma)) {
 768                 ret = PTR_ERR(vma);
 769                 goto out_pin_section;
 770         }
 771         intel_fb_obj_flush(new_bo, ORIGIN_DIRTYFB);
 772
 773         ret = i915_vma_put_fence(vma);
 774         if (ret)
 775                 goto out_unpin;
 776
 777         if (!overlay->active) {
 778                 u32 oconfig;
 779
 780                 oconfig = OCONF_CC_OUT_8BIT;
 781                 if (IS_GEN4(dev_priv))
 782                         oconfig |= OCONF_CSC_MODE_BT709;
 783                 oconfig |= pipe == 0 ?
 784                         OCONF_PIPE_A : OCONF_PIPE_B;
 785                 iowrite32(oconfig, &regs->OCONFIG);
 786
 787                 ret = intel_overlay_on(overlay);
 788                 if (ret != 0)
 789                         goto out_unpin;
 790         }
 791
 792         iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);
 793         iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);
 794
 795         if (params->flags & I915_OVERLAY_YUV_PACKED)
 796                 tmp_width = packed_width_bytes(params->flags,
 797                                                params->src_width);
 798         else
 799                 tmp_width = params->src_width;
 800
 801         swidth = params->src_width;
 802         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 803         sheight = params->src_height;
 804         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 805         ostride = params->stride_Y;
 806
 807         if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 808                 int uv_hscale = uv_hsubsampling(params->flags);
 809                 int uv_vscale = uv_vsubsampling(params->flags);
 810                 u32 tmp_U, tmp_V;
 811
 812                 swidth |= (params->src_width / uv_hscale) << 16;
 813                 sheight |= (params->src_height / uv_vscale) << 16;
 814
 815                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 816                                       params->src_width / uv_hscale);
 817                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 818                                       params->src_width / uv_hscale);
 819                 swidthsw |= max(tmp_U, tmp_V) << 16;
 820
 821                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 822                           &regs->OBUF_0U);
 823                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 824                           &regs->OBUF_0V);
 825
 826                 ostride |= params->stride_UV << 16;
 827         }
 828
 829         iowrite32(swidth, &regs->SWIDTH);
 830         iowrite32(swidthsw, &regs->SWIDTHSW);
 831         iowrite32(sheight, &regs->SHEIGHT);
 832         iowrite32(ostride, &regs->OSTRIDE);
 833
 834         scale_changed = update_scaling_factors(overlay, regs, params);
 835
 836         update_colorkey(overlay, regs);
 837
 838         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 839
 840         ret = intel_overlay_continue(overlay, vma, scale_changed);
 841         if (ret)
 842                 goto out_unpin;
 843
 844         return 0;
 845
 846 out_unpin:
 847         i915_gem_object_unpin_from_display_plane(vma);
 848 out_pin_section:
 849         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
 850
 851         return ret;
 852 }
 853
 854 int intel_overlay_switch_off(struct intel_overlay *overlay)
 855 {
 856         struct drm_i915_private *dev_priv = overlay->i915;
 857         int ret;
 858
 859         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 860         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 861
 862         ret = intel_overlay_recover_from_interrupt(overlay);
 863         if (ret != 0)
 864                 return ret;
 865
 866         if (!overlay->active)
 867                 return 0;
 868
 869         ret = intel_overlay_release_old_vid(overlay);
 870         if (ret != 0)
 871                 return ret;
 872
 873         iowrite32(0, &overlay->regs->OCMD);
 874
 875         return intel_overlay_off(overlay);
 876 }
 877
 878 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 879                                           struct intel_crtc *crtc)
 880 {
 881         if (!crtc->active)
 882                 return -EINVAL;
 883
 884         /* can't use the overlay with double wide pipe */
 885         if (crtc->config->double_wide)
 886                 return -EINVAL;
 887
 888         return 0;
 889 }
 890
 891 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 892 {
 893         struct drm_i915_private *dev_priv = overlay->i915;
 894         u32 pfit_control = I915_READ(PFIT_CONTROL);
 895         u32 ratio;
 896
 897         /* XXX: This is not the same logic as in the xorg driver, but more in
 898          * line with the intel documentation for the i965
 899          */
 900         if (INTEL_GEN(dev_priv) >= 4) {
 901                 /* on i965 use the PGM reg to read out the autoscaler values */
 902                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 903         } else {
 904                 if (pfit_control & VERT_AUTO_SCALE)
 905                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 906                 else
 907                         ratio = I915_READ(PFIT_PGM_RATIOS);
 908                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 909         }
 910
 911         overlay->pfit_vscale_ratio = ratio;
 912 }
 913
 914 static int check_overlay_dst(struct intel_overlay *overlay,
 915                              struct drm_intel_overlay_put_image *rec)
 916 {
 917         const struct intel_crtc_state *pipe_config =
 918                 overlay->crtc->config;
 919
 920         if (rec->dst_x < pipe_config->pipe_src_w &&
 921             rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
 922             rec->dst_y < pipe_config->pipe_src_h &&
 923             rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
 924                 return 0;
 925         else
 926                 return -EINVAL;
 927 }
 928
 929 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
 930 {
 931         u32 tmp;
 932
 933         /* downscaling limit is 8.0 */
 934         tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
 935         if (tmp > 7)
 936                 return -EINVAL;
 937
 938         tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
 939         if (tmp > 7)
 940                 return -EINVAL;
 941
 942         return 0;
 943 }
 944
 945 static int check_overlay_src(struct drm_i915_private *dev_priv,
 946                              struct drm_intel_overlay_put_image *rec,
 947                              struct drm_i915_gem_object *new_bo)
 948 {
 949         int uv_hscale = uv_hsubsampling(rec->flags);
 950         int uv_vscale = uv_vsubsampling(rec->flags);
 951         u32 stride_mask;
 952         int depth;
 953         u32 tmp;
 954
 955         /* check src dimensions */
 956         if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
 957                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 958                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 959                         return -EINVAL;
 960         } else {
 961                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 962                     rec->src_width  > IMAGE_MAX_WIDTH)
 963                         return -EINVAL;
 964         }
 965
 966         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 967         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 968             rec->src_width  < N_HORIZ_Y_TAPS*4)
 969                 return -EINVAL;
 970
 971         /* check alignment constraints */
 972         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 973         case I915_OVERLAY_RGB:
 974                 /* not implemented */
 975                 return -EINVAL;
 976
 977         case I915_OVERLAY_YUV_PACKED:
 978                 if (uv_vscale != 1)
 979                         return -EINVAL;
 980
 981                 depth = packed_depth_bytes(rec->flags);
 982                 if (depth < 0)
 983                         return depth;
 984
 985                 /* ignore UV planes */
 986                 rec->stride_UV = 0;
 987                 rec->offset_U = 0;
 988                 rec->offset_V = 0;
 989                 /* check pixel alignment */
 990                 if (rec->offset_Y % depth)
 991                         return -EINVAL;
 992                 break;
 993
 994         case I915_OVERLAY_YUV_PLANAR:
 995                 if (uv_vscale < 0 || uv_hscale < 0)
 996                         return -EINVAL;
 997                 /* no offset restrictions for planar formats */
 998                 break;
 999
1000         default:
1001                 return -EINVAL;
1002         }
1003
1004         if (rec->src_width % uv_hscale)
1005                 return -EINVAL;
1006
1007         /* stride checking */
1008         if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1009                 stride_mask = 255;
1010         else
1011                 stride_mask = 63;
1012
1013         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1014                 return -EINVAL;
1015         if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
1016                 return -EINVAL;
1017
1018         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1019                 4096 : 8192;
1020         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1021                 return -EINVAL;
1022
1023         /* check buffer dimensions */
1024         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1025         case I915_OVERLAY_RGB:
1026         case I915_OVERLAY_YUV_PACKED:
1027                 /* always 4 Y values per depth pixels */
1028                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1029                         return -EINVAL;
1030
1031                 tmp = rec->stride_Y*rec->src_height;
1032                 if (rec->offset_Y + tmp > new_bo->base.size)
1033                         return -EINVAL;
1034                 break;
1035
1036         case I915_OVERLAY_YUV_PLANAR:
1037                 if (rec->src_width > rec->stride_Y)
1038                         return -EINVAL;
1039                 if (rec->src_width/uv_hscale > rec->stride_UV)
1040                         return -EINVAL;
1041
1042                 tmp = rec->stride_Y * rec->src_height;
1043                 if (rec->offset_Y + tmp > new_bo->base.size)
1044                         return -EINVAL;
1045
1046                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1047                 if (rec->offset_U + tmp > new_bo->base.size ||
1048                     rec->offset_V + tmp > new_bo->base.size)
1049                         return -EINVAL;
1050                 break;
1051         }
1052
1053         return 0;
1054 }
1055
1056 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1057                                   struct drm_file *file_priv)
1058 {
1059         struct drm_intel_overlay_put_image *params = data;
1060         struct drm_i915_private *dev_priv = to_i915(dev);
1061         struct intel_overlay *overlay;
1062         struct drm_crtc *drmmode_crtc;
1063         struct intel_crtc *crtc;
1064         struct drm_i915_gem_object *new_bo;
1065         int ret;
1066
1067         overlay = dev_priv->overlay;
1068         if (!overlay) {
1069                 DRM_DEBUG("userspace bug: no overlay\n");
1070                 return -ENODEV;
1071         }
1072
1073         if (!(params->flags & I915_OVERLAY_ENABLE)) {
1074                 drm_modeset_lock_all(dev);
1075                 mutex_lock(&dev->struct_mutex);
1076
1077                 ret = intel_overlay_switch_off(overlay);
1078
1079                 mutex_unlock(&dev->struct_mutex);
1080                 drm_modeset_unlock_all(dev);
1081
1082                 return ret;
1083         }
1084
1085         drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1086         if (!drmmode_crtc)
1087                 return -ENOENT;
1088         crtc = to_intel_crtc(drmmode_crtc);
1089
1090         new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1091         if (!new_bo)
1092                 return -ENOENT;
1093
1094         drm_modeset_lock_all(dev);
1095         mutex_lock(&dev->struct_mutex);
1096
1097         if (i915_gem_object_is_tiled(new_bo)) {
1098                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1099                 ret = -EINVAL;
1100                 goto out_unlock;
1101         }
1102
1103         ret = intel_overlay_recover_from_interrupt(overlay);
1104         if (ret != 0)
1105                 goto out_unlock;
1106
1107         if (overlay->crtc != crtc) {
1108                 ret = intel_overlay_switch_off(overlay);
1109                 if (ret != 0)
1110                         goto out_unlock;
1111
1112                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1113                 if (ret != 0)
1114                         goto out_unlock;
1115
1116                 overlay->crtc = crtc;
1117                 crtc->overlay = overlay;
1118
1119                 /* line too wide, i.e. one-line-mode */
1120                 if (crtc->config->pipe_src_w > 1024 &&
1121                     crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1122                         overlay->pfit_active = true;
1123                         update_pfit_vscale_ratio(overlay);
1124                 } else
1125                         overlay->pfit_active = false;
1126         }
1127
1128         ret = check_overlay_dst(overlay, params);
1129         if (ret != 0)
1130                 goto out_unlock;
1131
1132         if (overlay->pfit_active) {
1133                 params->dst_y = (((u32)params->dst_y << 12) /
1134                                  overlay->pfit_vscale_ratio);
1135                 /* shifting right rounds downwards, so add 1 */
1136                 params->dst_height = (((u32)params->dst_height << 12) /
1137                                  overlay->pfit_vscale_ratio) + 1;
1138         }
1139
1140         if (params->src_scan_height > params->src_height ||
1141             params->src_scan_width > params->src_width) {
1142                 ret = -EINVAL;
1143                 goto out_unlock;
1144         }
1145
1146         ret = check_overlay_src(dev_priv, params, new_bo);
1147         if (ret != 0)
1148                 goto out_unlock;
1149
1150         /* Check scaling after src size to prevent a divide-by-zero. */
1151         ret = check_overlay_scaling(params);
1152         if (ret != 0)
1153                 goto out_unlock;
1154
1155         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1156         if (ret != 0)
1157                 goto out_unlock;
1158
1159         mutex_unlock(&dev->struct_mutex);
1160         drm_modeset_unlock_all(dev);
1161         i915_gem_object_put(new_bo);
1162
1163         return 0;
1164
1165 out_unlock:
1166         mutex_unlock(&dev->struct_mutex);
1167         drm_modeset_unlock_all(dev);
1168         i915_gem_object_put(new_bo);
1169
1170         return ret;
1171 }
1172
1173 static void update_reg_attrs(struct intel_overlay *overlay,
1174                              struct overlay_registers __iomem *regs)
1175 {
1176         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1177                   &regs->OCLRC0);
1178         iowrite32(overlay->saturation, &regs->OCLRC1);
1179 }
1180
1181 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1182 {
1183         int i;
1184
1185         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1186                 return false;
1187
1188         for (i = 0; i < 3; i++) {
1189                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1190                         return false;
1191         }
1192
1193         return true;
1194 }
1195
1196 static bool check_gamma5_errata(u32 gamma5)
1197 {
1198         int i;
1199
1200         for (i = 0; i < 3; i++) {
1201                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1202                         return false;
1203         }
1204
1205         return true;
1206 }
1207
1208 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1209 {
1210         if (!check_gamma_bounds(0, attrs->gamma0) ||
1211             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1212             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1213             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1214             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1215             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1216             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1217                 return -EINVAL;
1218
1219         if (!check_gamma5_errata(attrs->gamma5))
1220                 return -EINVAL;
1221
1222         return 0;
1223 }
1224
1225 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1226                               struct drm_file *file_priv)
1227 {
1228         struct drm_intel_overlay_attrs *attrs = data;
1229         struct drm_i915_private *dev_priv = to_i915(dev);
1230         struct intel_overlay *overlay;
1231         int ret;
1232
1233         overlay = dev_priv->overlay;
1234         if (!overlay) {
1235                 DRM_DEBUG("userspace bug: no overlay\n");
1236                 return -ENODEV;
1237         }
1238
1239         drm_modeset_lock_all(dev);
1240         mutex_lock(&dev->struct_mutex);
1241
1242         ret = -EINVAL;
1243         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1244                 attrs->color_key  = overlay->color_key;
1245                 attrs->brightness = overlay->brightness;
1246                 attrs->contrast   = overlay->contrast;
1247                 attrs->saturation = overlay->saturation;
1248
1249                 if (!IS_GEN2(dev_priv)) {
1250                         attrs->gamma0 = I915_READ(OGAMC0);
1251                         attrs->gamma1 = I915_READ(OGAMC1);
1252                         attrs->gamma2 = I915_READ(OGAMC2);
1253                         attrs->gamma3 = I915_READ(OGAMC3);
1254                         attrs->gamma4 = I915_READ(OGAMC4);
1255                         attrs->gamma5 = I915_READ(OGAMC5);
1256                 }
1257         } else {
1258                 if (attrs->brightness < -128 || attrs->brightness > 127)
1259                         goto out_unlock;
1260                 if (attrs->contrast > 255)
1261                         goto out_unlock;
1262                 if (attrs->saturation > 1023)
1263                         goto out_unlock;
1264
1265                 overlay->color_key  = attrs->color_key;
1266                 overlay->brightness = attrs->brightness;
1267                 overlay->contrast   = attrs->contrast;
1268                 overlay->saturation = attrs->saturation;
1269
1270                 update_reg_attrs(overlay, overlay->regs);
1271
1272                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1273                         if (IS_GEN2(dev_priv))
1274                                 goto out_unlock;
1275
1276                         if (overlay->active) {
1277                                 ret = -EBUSY;
1278                                 goto out_unlock;
1279                         }
1280
1281                         ret = check_gamma(attrs);
1282                         if (ret)
1283                                 goto out_unlock;
1284
1285                         I915_WRITE(OGAMC0, attrs->gamma0);
1286                         I915_WRITE(OGAMC1, attrs->gamma1);
1287                         I915_WRITE(OGAMC2, attrs->gamma2);
1288                         I915_WRITE(OGAMC3, attrs->gamma3);
1289                         I915_WRITE(OGAMC4, attrs->gamma4);
1290                         I915_WRITE(OGAMC5, attrs->gamma5);
1291                 }
1292         }
1293         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1294
1295         ret = 0;
1296 out_unlock:
1297         mutex_unlock(&dev->struct_mutex);
1298         drm_modeset_unlock_all(dev);
1299
1300         return ret;
1301 }
1302
1303 static int get_registers(struct intel_overlay *overlay, bool use_phys)
1304 {
1305         struct drm_i915_gem_object *obj;
1306         struct i915_vma *vma;
1307         int err;
1308
1309         obj = i915_gem_object_create_stolen(overlay->i915, PAGE_SIZE);
1310         if (obj == NULL)
1311                 obj = i915_gem_object_create_internal(overlay->i915, PAGE_SIZE);
1312         if (IS_ERR(obj))
1313                 return PTR_ERR(obj);
1314
1315         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1316         if (IS_ERR(vma)) {
1317                 err = PTR_ERR(vma);
1318                 goto err_put_bo;
1319         }
1320
1321         if (use_phys)
1322                 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1323         else
1324                 overlay->flip_addr = i915_ggtt_offset(vma);
1325         overlay->regs = i915_vma_pin_iomap(vma);
1326         i915_vma_unpin(vma);
1327
1328         if (IS_ERR(overlay->regs)) {
1329                 err = PTR_ERR(overlay->regs);
1330                 goto err_put_bo;
1331         }
1332
1333         overlay->reg_bo = obj;
1334         return 0;
1335
1336 err_put_bo:
1337         i915_gem_object_put(obj);
1338         return err;
1339 }
1340
1341 void intel_overlay_setup(struct drm_i915_private *dev_priv)
1342 {
1343         struct intel_overlay *overlay;
1344         int ret;
1345
1346         if (!HAS_OVERLAY(dev_priv))
1347                 return;
1348
1349         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1350         if (!overlay)
1351                 return;
1352
1353         overlay->i915 = dev_priv;
1354
1355         overlay->color_key = 0x0101fe;
1356         overlay->color_key_enabled = true;
1357         overlay->brightness = -19;
1358         overlay->contrast = 75;
1359         overlay->saturation = 146;
1360
1361         init_request_active(&overlay->last_flip, NULL);
1362
1363         mutex_lock(&dev_priv->drm.struct_mutex);
1364
1365         ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1366         if (ret)
1367                 goto out_free;
1368
1369         ret = i915_gem_object_set_to_gtt_domain(overlay->reg_bo, true);
1370         if (ret)
1371                 goto out_reg_bo;
1372
1373         mutex_unlock(&dev_priv->drm.struct_mutex);
1374
1375         memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1376         update_polyphase_filter(overlay->regs);
1377         update_reg_attrs(overlay, overlay->regs);
1378
1379         dev_priv->overlay = overlay;
1380         DRM_INFO("Initialized overlay support.\n");
1381         return;
1382
1383 out_reg_bo:
1384         i915_gem_object_put(overlay->reg_bo);
1385 out_free:
1386         mutex_unlock(&dev_priv->drm.struct_mutex);
1387         kfree(overlay);
1388 }
1389
1390 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1391 {
1392         struct intel_overlay *overlay;
1393
1394         overlay = fetch_and_zero(&dev_priv->overlay);
1395         if (!overlay)
1396                 return;
1397
1398         /*
1399          * The bo's should be free'd by the generic code already.
1400          * Furthermore modesetting teardown happens beforehand so the
1401          * hardware should be off already.
1402          */
1403         WARN_ON(overlay->active);
1404
1405         i915_gem_object_put(overlay->reg_bo);
1406
1407         kfree(overlay);
1408 }
1409
1410 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1411
1412 struct intel_overlay_error_state {
1413         struct overlay_registers regs;
1414         unsigned long base;
1415         u32 dovsta;
1416         u32 isr;
1417 };
1418
1419 struct intel_overlay_error_state *
1420 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1421 {
1422         struct intel_overlay *overlay = dev_priv->overlay;
1423         struct intel_overlay_error_state *error;
1424
1425         if (!overlay || !overlay->active)
1426                 return NULL;
1427
1428         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1429         if (error == NULL)
1430                 return NULL;
1431
1432         error->dovsta = I915_READ(DOVSTA);
1433         error->isr = I915_READ(ISR);
1434         error->base = overlay->flip_addr;
1435
1436         memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1437
1438         return error;
1439 }
1440
1441 void
1442 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1443                                 struct intel_overlay_error_state *error)
1444 {
1445         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1446                           error->dovsta, error->isr);
1447         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1448                           error->base);
1449
1450 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1451         P(OBUF_0Y);
1452         P(OBUF_1Y);
1453         P(OBUF_0U);
1454         P(OBUF_0V);
1455         P(OBUF_1U);
1456         P(OBUF_1V);
1457         P(OSTRIDE);
1458         P(YRGB_VPH);
1459         P(UV_VPH);
1460         P(HORZ_PH);
1461         P(INIT_PHS);
1462         P(DWINPOS);
1463         P(DWINSZ);
1464         P(SWIDTH);
1465         P(SWIDTHSW);
1466         P(SHEIGHT);
1467         P(YRGBSCALE);
1468         P(UVSCALE);
1469         P(OCLRC0);
1470         P(OCLRC1);
1471         P(DCLRKV);
1472         P(DCLRKM);
1473         P(SCLRKVH);
1474         P(SCLRKVL);
1475         P(SCLRKEN);
1476         P(OCONFIG);
1477         P(OCMD);
1478         P(OSTART_0Y);
1479         P(OSTART_1Y);
1480         P(OSTART_0U);
1481         P(OSTART_0V);
1482         P(OSTART_1U);
1483         P(OSTART_1V);
1484         P(OTILEOFF_0Y);
1485         P(OTILEOFF_1Y);
1486         P(OTILEOFF_0U);
1487         P(OTILEOFF_0V);
1488         P(OTILEOFF_1U);
1489         P(OTILEOFF_1V);
1490         P(FASTHSCALE);
1491         P(UVSCALEV);
1492 #undef P
1493 }
1494
1495 #endif