drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_reg.h"
  32 #include "intel_drv.h"
  33 #include "intel_frontbuffer.h"
  34
  35 /* Limits for overlay size. According to intel doc, the real limits are:
  36  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  37  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  38  * the mininum of both.  */
  39 #define IMAGE_MAX_WIDTH         2048
  40 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  41 /* on 830 and 845 these large limits result in the card hanging */
  42 #define IMAGE_MAX_WIDTH_LEGACY  1024
  43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  44
  45 /* overlay register definitions */
  46 /* OCMD register */
  47 #define OCMD_TILED_SURFACE      (0x1<<19)
  48 #define OCMD_MIRROR_MASK        (0x3<<17)
  49 #define OCMD_MIRROR_MODE        (0x3<<17)
  50 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  51 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  52 #define OCMD_MIRROR_BOTH        (0x3<<17)
  53 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  54 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  55 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  56 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  58 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  60 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  61 #define OCMD_YUV_422_PACKED     (0x8<<10)
  62 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  64 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  65 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  66 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  67 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  68 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  69 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  70 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  71 #define OCMD_TEST_MODE          (0x1<<4)
  72 #define OCMD_BUFFER_SELECT      (0x3<<2)
  73 #define OCMD_BUFFER0            (0x0<<2)
  74 #define OCMD_BUFFER1            (0x1<<2)
  75 #define OCMD_FIELD_SELECT       (0x1<<2)
  76 #define OCMD_FIELD0             (0x0<<1)
  77 #define OCMD_FIELD1             (0x1<<1)
  78 #define OCMD_ENABLE             (0x1<<0)
  79
  80 /* OCONFIG register */
  81 #define OCONF_PIPE_MASK         (0x1<<18)
  82 #define OCONF_PIPE_A            (0x0<<18)
  83 #define OCONF_PIPE_B            (0x1<<18)
  84 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  85 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  86 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  87 #define OCONF_CSC_BYPASS        (0x1<<4)
  88 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  89 #define OCONF_TEST_MODE         (0x1<<2)
  90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  91 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  92
  93 /* DCLRKM (dst-key) register */
  94 #define DST_KEY_ENABLE          (0x1<<31)
  95 #define CLK_RGB24_MASK          0x0
  96 #define CLK_RGB16_MASK          0x070307
  97 #define CLK_RGB15_MASK          0x070707
  98 #define CLK_RGB8I_MASK          0xffffff
  99
 100 #define RGB16_TO_COLORKEY(c) \
 101         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 102 #define RGB15_TO_COLORKEY(c) \
 103         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 104
 105 /* overlay flip addr flag */
 106 #define OFC_UPDATE              0x1
 107
 108 /* polyphase filter coefficients */
 109 #define N_HORIZ_Y_TAPS          5
 110 #define N_VERT_Y_TAPS           3
 111 #define N_HORIZ_UV_TAPS         3
 112 #define N_VERT_UV_TAPS          3
 113 #define N_PHASES                17
 114 #define MAX_TAPS                5
 115
 116 /* memory bufferd overlay registers */
 117 struct overlay_registers {
 118         u32 OBUF_0Y;
 119         u32 OBUF_1Y;
 120         u32 OBUF_0U;
 121         u32 OBUF_0V;
 122         u32 OBUF_1U;
 123         u32 OBUF_1V;
 124         u32 OSTRIDE;
 125         u32 YRGB_VPH;
 126         u32 UV_VPH;
 127         u32 HORZ_PH;
 128         u32 INIT_PHS;
 129         u32 DWINPOS;
 130         u32 DWINSZ;
 131         u32 SWIDTH;
 132         u32 SWIDTHSW;
 133         u32 SHEIGHT;
 134         u32 YRGBSCALE;
 135         u32 UVSCALE;
 136         u32 OCLRC0;
 137         u32 OCLRC1;
 138         u32 DCLRKV;
 139         u32 DCLRKM;
 140         u32 SCLRKVH;
 141         u32 SCLRKVL;
 142         u32 SCLRKEN;
 143         u32 OCONFIG;
 144         u32 OCMD;
 145         u32 RESERVED1; /* 0x6C */
 146         u32 OSTART_0Y;
 147         u32 OSTART_1Y;
 148         u32 OSTART_0U;
 149         u32 OSTART_0V;
 150         u32 OSTART_1U;
 151         u32 OSTART_1V;
 152         u32 OTILEOFF_0Y;
 153         u32 OTILEOFF_1Y;
 154         u32 OTILEOFF_0U;
 155         u32 OTILEOFF_0V;
 156         u32 OTILEOFF_1U;
 157         u32 OTILEOFF_1V;
 158         u32 FASTHSCALE; /* 0xA0 */
 159         u32 UVSCALEV; /* 0xA4 */
 160         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 161         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 162         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 163         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 164         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 165         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 166         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 167         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 168         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 169 };
 170
 171 struct intel_overlay {
 172         struct drm_i915_private *i915;
 173         struct intel_crtc *crtc;
 174         struct i915_vma *vma;
 175         struct i915_vma *old_vma;
 176         bool active;
 177         bool pfit_active;
 178         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 179         u32 color_key:24;
 180         u32 color_key_enabled:1;
 181         u32 brightness, contrast, saturation;
 182         u32 old_xscale, old_yscale;
 183         /* register access */
 184         u32 flip_addr;
 185         struct drm_i915_gem_object *reg_bo;
 186         /* flip handling */
 187         struct i915_gem_active last_flip;
 188 };
 189
 190 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
 191                                       bool enable)
 192 {
 193         struct pci_dev *pdev = dev_priv->drm.pdev;
 194         u8 val;
 195
 196         /* WA_OVERLAY_CLKGATE:alm */
 197         if (enable)
 198                 I915_WRITE(DSPCLK_GATE_D, 0);
 199         else
 200                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 201
 202         /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
 203         pci_bus_read_config_byte(pdev->bus,
 204                                  PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
 205         if (enable)
 206                 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
 207         else
 208                 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
 209         pci_bus_write_config_byte(pdev->bus,
 210                                   PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
 211 }
 212
 213 static struct overlay_registers __iomem *
 214 intel_overlay_map_regs(struct intel_overlay *overlay)
 215 {
 216         struct drm_i915_private *dev_priv = overlay->i915;
 217         struct overlay_registers __iomem *regs;
 218
 219         if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
 220                 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
 221         else
 222                 regs = io_mapping_map_wc(&dev_priv->ggtt.mappable,
 223                                          overlay->flip_addr,
 224                                          PAGE_SIZE);
 225
 226         return regs;
 227 }
 228
 229 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 230                                      struct overlay_registers __iomem *regs)
 231 {
 232         if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
 233                 io_mapping_unmap(regs);
 234 }
 235
 236 static void intel_overlay_submit_request(struct intel_overlay *overlay,
 237                                          struct drm_i915_gem_request *req,
 238                                          i915_gem_retire_fn retire)
 239 {
 240         GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
 241                                         &overlay->i915->drm.struct_mutex));
 242         i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
 243                                       &overlay->i915->drm.struct_mutex);
 244         i915_gem_active_set(&overlay->last_flip, req);
 245         i915_add_request(req);
 246 }
 247
 248 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 249                                          struct drm_i915_gem_request *req,
 250                                          i915_gem_retire_fn retire)
 251 {
 252         intel_overlay_submit_request(overlay, req, retire);
 253         return i915_gem_active_retire(&overlay->last_flip,
 254                                       &overlay->i915->drm.struct_mutex);
 255 }
 256
 257 static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay)
 258 {
 259         struct drm_i915_private *dev_priv = overlay->i915;
 260         struct intel_engine_cs *engine = dev_priv->engine[RCS];
 261
 262         return i915_gem_request_alloc(engine, dev_priv->kernel_context);
 263 }
 264
 265 /* overlay needs to be disable in OCMD reg */
 266 static int intel_overlay_on(struct intel_overlay *overlay)
 267 {
 268         struct drm_i915_private *dev_priv = overlay->i915;
 269         struct drm_i915_gem_request *req;
 270         struct intel_ring *ring;
 271         int ret;
 272
 273         WARN_ON(overlay->active);
 274         WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
 275
 276         req = alloc_request(overlay);
 277         if (IS_ERR(req))
 278                 return PTR_ERR(req);
 279
 280         ret = intel_ring_begin(req, 4);
 281         if (ret) {
 282                 i915_add_request_no_flush(req);
 283                 return ret;
 284         }
 285
 286         overlay->active = true;
 287
 288         if (IS_I830(dev_priv))
 289                 i830_overlay_clock_gating(dev_priv, false);
 290
 291         ring = req->ring;
 292         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 293         intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
 294         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 295         intel_ring_emit(ring, MI_NOOP);
 296         intel_ring_advance(ring);
 297
 298         return intel_overlay_do_wait_request(overlay, req, NULL);
 299 }
 300
 301 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 302                                        struct i915_vma *vma)
 303 {
 304         enum pipe pipe = overlay->crtc->pipe;
 305
 306         WARN_ON(overlay->old_vma);
 307
 308         i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
 309                           vma ? vma->obj : NULL,
 310                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 311
 312         intel_frontbuffer_flip_prepare(overlay->i915,
 313                                        INTEL_FRONTBUFFER_OVERLAY(pipe));
 314
 315         overlay->old_vma = overlay->vma;
 316         if (vma)
 317                 overlay->vma = i915_vma_get(vma);
 318         else
 319                 overlay->vma = NULL;
 320 }
 321
 322 /* overlay needs to be enabled in OCMD reg */
 323 static int intel_overlay_continue(struct intel_overlay *overlay,
 324                                   struct i915_vma *vma,
 325                                   bool load_polyphase_filter)
 326 {
 327         struct drm_i915_private *dev_priv = overlay->i915;
 328         struct drm_i915_gem_request *req;
 329         struct intel_ring *ring;
 330         u32 flip_addr = overlay->flip_addr;
 331         u32 tmp;
 332         int ret;
 333
 334         WARN_ON(!overlay->active);
 335
 336         if (load_polyphase_filter)
 337                 flip_addr |= OFC_UPDATE;
 338
 339         /* check for underruns */
 340         tmp = I915_READ(DOVSTA);
 341         if (tmp & (1 << 17))
 342                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 343
 344         req = alloc_request(overlay);
 345         if (IS_ERR(req))
 346                 return PTR_ERR(req);
 347
 348         ret = intel_ring_begin(req, 2);
 349         if (ret) {
 350                 i915_add_request_no_flush(req);
 351                 return ret;
 352         }
 353
 354         ring = req->ring;
 355         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 356         intel_ring_emit(ring, flip_addr);
 357         intel_ring_advance(ring);
 358
 359         intel_overlay_flip_prepare(overlay, vma);
 360
 361         intel_overlay_submit_request(overlay, req, NULL);
 362
 363         return 0;
 364 }
 365
 366 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 367 {
 368         struct i915_vma *vma;
 369
 370         vma = fetch_and_zero(&overlay->old_vma);
 371         if (WARN_ON(!vma))
 372                 return;
 373
 374         intel_frontbuffer_flip_complete(overlay->i915,
 375                                         INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 376
 377         i915_gem_object_unpin_from_display_plane(vma);
 378         i915_vma_put(vma);
 379 }
 380
 381 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
 382                                                struct drm_i915_gem_request *req)
 383 {
 384         struct intel_overlay *overlay =
 385                 container_of(active, typeof(*overlay), last_flip);
 386
 387         intel_overlay_release_old_vma(overlay);
 388 }
 389
 390 static void intel_overlay_off_tail(struct i915_gem_active *active,
 391                                    struct drm_i915_gem_request *req)
 392 {
 393         struct intel_overlay *overlay =
 394                 container_of(active, typeof(*overlay), last_flip);
 395         struct drm_i915_private *dev_priv = overlay->i915;
 396
 397         intel_overlay_release_old_vma(overlay);
 398
 399         overlay->crtc->overlay = NULL;
 400         overlay->crtc = NULL;
 401         overlay->active = false;
 402
 403         if (IS_I830(dev_priv))
 404                 i830_overlay_clock_gating(dev_priv, true);
 405 }
 406
 407 /* overlay needs to be disabled in OCMD reg */
 408 static int intel_overlay_off(struct intel_overlay *overlay)
 409 {
 410         struct drm_i915_gem_request *req;
 411         struct intel_ring *ring;
 412         u32 flip_addr = overlay->flip_addr;
 413         int ret;
 414
 415         WARN_ON(!overlay->active);
 416
 417         /* According to intel docs the overlay hw may hang (when switching
 418          * off) without loading the filter coeffs. It is however unclear whether
 419          * this applies to the disabling of the overlay or to the switching off
 420          * of the hw. Do it in both cases */
 421         flip_addr |= OFC_UPDATE;
 422
 423         req = alloc_request(overlay);
 424         if (IS_ERR(req))
 425                 return PTR_ERR(req);
 426
 427         ret = intel_ring_begin(req, 6);
 428         if (ret) {
 429                 i915_add_request_no_flush(req);
 430                 return ret;
 431         }
 432
 433         ring = req->ring;
 434
 435         /* wait for overlay to go idle */
 436         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 437         intel_ring_emit(ring, flip_addr);
 438         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 439
 440         /* turn overlay off */
 441         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 442         intel_ring_emit(ring, flip_addr);
 443         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 444
 445         intel_ring_advance(ring);
 446
 447         intel_overlay_flip_prepare(overlay, NULL);
 448
 449         return intel_overlay_do_wait_request(overlay, req,
 450                                              intel_overlay_off_tail);
 451 }
 452
 453 /* recover from an interruption due to a signal
 454  * We have to be careful not to repeat work forever an make forward progess. */
 455 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 456 {
 457         return i915_gem_active_retire(&overlay->last_flip,
 458                                       &overlay->i915->drm.struct_mutex);
 459 }
 460
 461 /* Wait for pending overlay flip and release old frame.
 462  * Needs to be called before the overlay register are changed
 463  * via intel_overlay_(un)map_regs
 464  */
 465 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 466 {
 467         struct drm_i915_private *dev_priv = overlay->i915;
 468         int ret;
 469
 470         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 471
 472         /* Only wait if there is actually an old frame to release to
 473          * guarantee forward progress.
 474          */
 475         if (!overlay->old_vma)
 476                 return 0;
 477
 478         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 479                 /* synchronous slowpath */
 480                 struct drm_i915_gem_request *req;
 481                 struct intel_ring *ring;
 482
 483                 req = alloc_request(overlay);
 484                 if (IS_ERR(req))
 485                         return PTR_ERR(req);
 486
 487                 ret = intel_ring_begin(req, 2);
 488                 if (ret) {
 489                         i915_add_request_no_flush(req);
 490                         return ret;
 491                 }
 492
 493                 ring = req->ring;
 494                 intel_ring_emit(ring,
 495                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 496                 intel_ring_emit(ring, MI_NOOP);
 497                 intel_ring_advance(ring);
 498
 499                 ret = intel_overlay_do_wait_request(overlay, req,
 500                                                     intel_overlay_release_old_vid_tail);
 501                 if (ret)
 502                         return ret;
 503         } else
 504                 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
 505
 506         return 0;
 507 }
 508
 509 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 510 {
 511         struct intel_overlay *overlay = dev_priv->overlay;
 512
 513         if (!overlay)
 514                 return;
 515
 516         intel_overlay_release_old_vid(overlay);
 517
 518         overlay->old_xscale = 0;
 519         overlay->old_yscale = 0;
 520         overlay->crtc = NULL;
 521         overlay->active = false;
 522 }
 523
 524 struct put_image_params {
 525         int format;
 526         short dst_x;
 527         short dst_y;
 528         short dst_w;
 529         short dst_h;
 530         short src_w;
 531         short src_scan_h;
 532         short src_scan_w;
 533         short src_h;
 534         short stride_Y;
 535         short stride_UV;
 536         int offset_Y;
 537         int offset_U;
 538         int offset_V;
 539 };
 540
 541 static int packed_depth_bytes(u32 format)
 542 {
 543         switch (format & I915_OVERLAY_DEPTH_MASK) {
 544         case I915_OVERLAY_YUV422:
 545                 return 4;
 546         case I915_OVERLAY_YUV411:
 547                 /* return 6; not implemented */
 548         default:
 549                 return -EINVAL;
 550         }
 551 }
 552
 553 static int packed_width_bytes(u32 format, short width)
 554 {
 555         switch (format & I915_OVERLAY_DEPTH_MASK) {
 556         case I915_OVERLAY_YUV422:
 557                 return width << 1;
 558         default:
 559                 return -EINVAL;
 560         }
 561 }
 562
 563 static int uv_hsubsampling(u32 format)
 564 {
 565         switch (format & I915_OVERLAY_DEPTH_MASK) {
 566         case I915_OVERLAY_YUV422:
 567         case I915_OVERLAY_YUV420:
 568                 return 2;
 569         case I915_OVERLAY_YUV411:
 570         case I915_OVERLAY_YUV410:
 571                 return 4;
 572         default:
 573                 return -EINVAL;
 574         }
 575 }
 576
 577 static int uv_vsubsampling(u32 format)
 578 {
 579         switch (format & I915_OVERLAY_DEPTH_MASK) {
 580         case I915_OVERLAY_YUV420:
 581         case I915_OVERLAY_YUV410:
 582                 return 2;
 583         case I915_OVERLAY_YUV422:
 584         case I915_OVERLAY_YUV411:
 585                 return 1;
 586         default:
 587                 return -EINVAL;
 588         }
 589 }
 590
 591 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 592 {
 593         u32 sw;
 594
 595         if (IS_GEN2(dev_priv))
 596                 sw = ALIGN((offset & 31) + width, 32);
 597         else
 598                 sw = ALIGN((offset & 63) + width, 64);
 599
 600         if (sw == 0)
 601                 return 0;
 602
 603         return (sw - 32) >> 3;
 604 }
 605
 606 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
 607         [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
 608         [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
 609         [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
 610         [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
 611         [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
 612         [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
 613         [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
 614         [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
 615         [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
 616         [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
 617         [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
 618         [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
 619         [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
 620         [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
 621         [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
 622         [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
 623         [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
 624 };
 625
 626 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
 627         [ 0] = { 0x3000, 0x1800, 0x1800, },
 628         [ 1] = { 0xb000, 0x18d0, 0x2e60, },
 629         [ 2] = { 0xb000, 0x1990, 0x2ce0, },
 630         [ 3] = { 0xb020, 0x1a68, 0x2b40, },
 631         [ 4] = { 0xb040, 0x1b20, 0x29e0, },
 632         [ 5] = { 0xb060, 0x1bd8, 0x2880, },
 633         [ 6] = { 0xb080, 0x1c88, 0x3e60, },
 634         [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
 635         [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
 636         [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
 637         [10] = { 0xb100, 0x1eb8, 0x3620, },
 638         [11] = { 0xb100, 0x1f18, 0x34a0, },
 639         [12] = { 0xb100, 0x1f68, 0x3360, },
 640         [13] = { 0xb0e0, 0x1fa8, 0x3240, },
 641         [14] = { 0xb0c0, 0x1fe0, 0x3140, },
 642         [15] = { 0xb060, 0x1ff0, 0x30a0, },
 643         [16] = { 0x3000, 0x0800, 0x3000, },
 644 };
 645
 646 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 647 {
 648         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 649         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 650                     sizeof(uv_static_hcoeffs));
 651 }
 652
 653 static bool update_scaling_factors(struct intel_overlay *overlay,
 654                                    struct overlay_registers __iomem *regs,
 655                                    struct put_image_params *params)
 656 {
 657         /* fixed point with a 12 bit shift */
 658         u32 xscale, yscale, xscale_UV, yscale_UV;
 659 #define FP_SHIFT 12
 660 #define FRACT_MASK 0xfff
 661         bool scale_changed = false;
 662         int uv_hscale = uv_hsubsampling(params->format);
 663         int uv_vscale = uv_vsubsampling(params->format);
 664
 665         if (params->dst_w > 1)
 666                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 667                         /(params->dst_w);
 668         else
 669                 xscale = 1 << FP_SHIFT;
 670
 671         if (params->dst_h > 1)
 672                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 673                         /(params->dst_h);
 674         else
 675                 yscale = 1 << FP_SHIFT;
 676
 677         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 678         xscale_UV = xscale/uv_hscale;
 679         yscale_UV = yscale/uv_vscale;
 680         /* make the Y scale to UV scale ratio an exact multiply */
 681         xscale = xscale_UV * uv_hscale;
 682         yscale = yscale_UV * uv_vscale;
 683         /*} else {
 684           xscale_UV = 0;
 685           yscale_UV = 0;
 686           }*/
 687
 688         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 689                 scale_changed = true;
 690         overlay->old_xscale = xscale;
 691         overlay->old_yscale = yscale;
 692
 693         iowrite32(((yscale & FRACT_MASK) << 20) |
 694                   ((xscale >> FP_SHIFT)  << 16) |
 695                   ((xscale & FRACT_MASK) << 3),
 696                  &regs->YRGBSCALE);
 697
 698         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 699                   ((xscale_UV >> FP_SHIFT)  << 16) |
 700                   ((xscale_UV & FRACT_MASK) << 3),
 701                  &regs->UVSCALE);
 702
 703         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 704                    ((yscale_UV >> FP_SHIFT) << 0)),
 705                  &regs->UVSCALEV);
 706
 707         if (scale_changed)
 708                 update_polyphase_filter(regs);
 709
 710         return scale_changed;
 711 }
 712
 713 static void update_colorkey(struct intel_overlay *overlay,
 714                             struct overlay_registers __iomem *regs)
 715 {
 716         const struct intel_plane_state *state =
 717                 to_intel_plane_state(overlay->crtc->base.primary->state);
 718         u32 key = overlay->color_key;
 719         u32 format = 0;
 720         u32 flags = 0;
 721
 722         if (overlay->color_key_enabled)
 723                 flags |= DST_KEY_ENABLE;
 724
 725         if (state->base.visible)
 726                 format = state->base.fb->format->format;
 727
 728         switch (format) {
 729         case DRM_FORMAT_C8:
 730                 key = 0;
 731                 flags |= CLK_RGB8I_MASK;
 732                 break;
 733         case DRM_FORMAT_XRGB1555:
 734                 key = RGB15_TO_COLORKEY(key);
 735                 flags |= CLK_RGB15_MASK;
 736                 break;
 737         case DRM_FORMAT_RGB565:
 738                 key = RGB16_TO_COLORKEY(key);
 739                 flags |= CLK_RGB16_MASK;
 740                 break;
 741         default:
 742                 flags |= CLK_RGB24_MASK;
 743                 break;
 744         }
 745
 746         iowrite32(key, &regs->DCLRKV);
 747         iowrite32(flags, &regs->DCLRKM);
 748 }
 749
 750 static u32 overlay_cmd_reg(struct put_image_params *params)
 751 {
 752         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 753
 754         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 755                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 756                 case I915_OVERLAY_YUV422:
 757                         cmd |= OCMD_YUV_422_PLANAR;
 758                         break;
 759                 case I915_OVERLAY_YUV420:
 760                         cmd |= OCMD_YUV_420_PLANAR;
 761                         break;
 762                 case I915_OVERLAY_YUV411:
 763                 case I915_OVERLAY_YUV410:
 764                         cmd |= OCMD_YUV_410_PLANAR;
 765                         break;
 766                 }
 767         } else { /* YUV packed */
 768                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 769                 case I915_OVERLAY_YUV422:
 770                         cmd |= OCMD_YUV_422_PACKED;
 771                         break;
 772                 case I915_OVERLAY_YUV411:
 773                         cmd |= OCMD_YUV_411_PACKED;
 774                         break;
 775                 }
 776
 777                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 778                 case I915_OVERLAY_NO_SWAP:
 779                         break;
 780                 case I915_OVERLAY_UV_SWAP:
 781                         cmd |= OCMD_UV_SWAP;
 782                         break;
 783                 case I915_OVERLAY_Y_SWAP:
 784                         cmd |= OCMD_Y_SWAP;
 785                         break;
 786                 case I915_OVERLAY_Y_AND_UV_SWAP:
 787                         cmd |= OCMD_Y_AND_UV_SWAP;
 788                         break;
 789                 }
 790         }
 791
 792         return cmd;
 793 }
 794
 795 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 796                                       struct drm_i915_gem_object *new_bo,
 797                                       struct put_image_params *params)
 798 {
 799         int ret, tmp_width;
 800         struct overlay_registers __iomem *regs;
 801         bool scale_changed = false;
 802         struct drm_i915_private *dev_priv = overlay->i915;
 803         u32 swidth, swidthsw, sheight, ostride;
 804         enum pipe pipe = overlay->crtc->pipe;
 805         struct i915_vma *vma;
 806
 807         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 808         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 809
 810         ret = intel_overlay_release_old_vid(overlay);
 811         if (ret != 0)
 812                 return ret;
 813
 814         vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
 815         if (IS_ERR(vma))
 816                 return PTR_ERR(vma);
 817
 818         ret = i915_vma_put_fence(vma);
 819         if (ret)
 820                 goto out_unpin;
 821
 822         if (!overlay->active) {
 823                 u32 oconfig;
 824                 regs = intel_overlay_map_regs(overlay);
 825                 if (!regs) {
 826                         ret = -ENOMEM;
 827                         goto out_unpin;
 828                 }
 829                 oconfig = OCONF_CC_OUT_8BIT;
 830                 if (IS_GEN4(dev_priv))
 831                         oconfig |= OCONF_CSC_MODE_BT709;
 832                 oconfig |= pipe == 0 ?
 833                         OCONF_PIPE_A : OCONF_PIPE_B;
 834                 iowrite32(oconfig, &regs->OCONFIG);
 835                 intel_overlay_unmap_regs(overlay, regs);
 836
 837                 ret = intel_overlay_on(overlay);
 838                 if (ret != 0)
 839                         goto out_unpin;
 840         }
 841
 842         regs = intel_overlay_map_regs(overlay);
 843         if (!regs) {
 844                 ret = -ENOMEM;
 845                 goto out_unpin;
 846         }
 847
 848         iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
 849         iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
 850
 851         if (params->format & I915_OVERLAY_YUV_PACKED)
 852                 tmp_width = packed_width_bytes(params->format, params->src_w);
 853         else
 854                 tmp_width = params->src_w;
 855
 856         swidth = params->src_w;
 857         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 858         sheight = params->src_h;
 859         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 860         ostride = params->stride_Y;
 861
 862         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 863                 int uv_hscale = uv_hsubsampling(params->format);
 864                 int uv_vscale = uv_vsubsampling(params->format);
 865                 u32 tmp_U, tmp_V;
 866                 swidth |= (params->src_w/uv_hscale) << 16;
 867                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 868                                       params->src_w/uv_hscale);
 869                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 870                                       params->src_w/uv_hscale);
 871                 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
 872                 sheight |= (params->src_h/uv_vscale) << 16;
 873                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 874                           &regs->OBUF_0U);
 875                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 876                           &regs->OBUF_0V);
 877                 ostride |= params->stride_UV << 16;
 878         }
 879
 880         iowrite32(swidth, &regs->SWIDTH);
 881         iowrite32(swidthsw, &regs->SWIDTHSW);
 882         iowrite32(sheight, &regs->SHEIGHT);
 883         iowrite32(ostride, &regs->OSTRIDE);
 884
 885         scale_changed = update_scaling_factors(overlay, regs, params);
 886
 887         update_colorkey(overlay, regs);
 888
 889         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 890
 891         intel_overlay_unmap_regs(overlay, regs);
 892
 893         ret = intel_overlay_continue(overlay, vma, scale_changed);
 894         if (ret)
 895                 goto out_unpin;
 896
 897         return 0;
 898
 899 out_unpin:
 900         i915_gem_object_unpin_from_display_plane(vma);
 901         return ret;
 902 }
 903
 904 int intel_overlay_switch_off(struct intel_overlay *overlay)
 905 {
 906         struct drm_i915_private *dev_priv = overlay->i915;
 907         struct overlay_registers __iomem *regs;
 908         int ret;
 909
 910         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 911         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 912
 913         ret = intel_overlay_recover_from_interrupt(overlay);
 914         if (ret != 0)
 915                 return ret;
 916
 917         if (!overlay->active)
 918                 return 0;
 919
 920         ret = intel_overlay_release_old_vid(overlay);
 921         if (ret != 0)
 922                 return ret;
 923
 924         regs = intel_overlay_map_regs(overlay);
 925         iowrite32(0, &regs->OCMD);
 926         intel_overlay_unmap_regs(overlay, regs);
 927
 928         return intel_overlay_off(overlay);
 929 }
 930
 931 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 932                                           struct intel_crtc *crtc)
 933 {
 934         if (!crtc->active)
 935                 return -EINVAL;
 936
 937         /* can't use the overlay with double wide pipe */
 938         if (crtc->config->double_wide)
 939                 return -EINVAL;
 940
 941         return 0;
 942 }
 943
 944 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 945 {
 946         struct drm_i915_private *dev_priv = overlay->i915;
 947         u32 pfit_control = I915_READ(PFIT_CONTROL);
 948         u32 ratio;
 949
 950         /* XXX: This is not the same logic as in the xorg driver, but more in
 951          * line with the intel documentation for the i965
 952          */
 953         if (INTEL_GEN(dev_priv) >= 4) {
 954                 /* on i965 use the PGM reg to read out the autoscaler values */
 955                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 956         } else {
 957                 if (pfit_control & VERT_AUTO_SCALE)
 958                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 959                 else
 960                         ratio = I915_READ(PFIT_PGM_RATIOS);
 961                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 962         }
 963
 964         overlay->pfit_vscale_ratio = ratio;
 965 }
 966
 967 static int check_overlay_dst(struct intel_overlay *overlay,
 968                              struct drm_intel_overlay_put_image *rec)
 969 {
 970         const struct intel_crtc_state *pipe_config =
 971                 overlay->crtc->config;
 972
 973         if (rec->dst_x < pipe_config->pipe_src_w &&
 974             rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
 975             rec->dst_y < pipe_config->pipe_src_h &&
 976             rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
 977                 return 0;
 978         else
 979                 return -EINVAL;
 980 }
 981
 982 static int check_overlay_scaling(struct put_image_params *rec)
 983 {
 984         u32 tmp;
 985
 986         /* downscaling limit is 8.0 */
 987         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 988         if (tmp > 7)
 989                 return -EINVAL;
 990         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 991         if (tmp > 7)
 992                 return -EINVAL;
 993
 994         return 0;
 995 }
 996
 997 static int check_overlay_src(struct drm_i915_private *dev_priv,
 998                              struct drm_intel_overlay_put_image *rec,
 999                              struct drm_i915_gem_object *new_bo)
1000 {
1001         int uv_hscale = uv_hsubsampling(rec->flags);
1002         int uv_vscale = uv_vsubsampling(rec->flags);
1003         u32 stride_mask;
1004         int depth;
1005         u32 tmp;
1006
1007         /* check src dimensions */
1008         if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
1009                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
1010                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
1011                         return -EINVAL;
1012         } else {
1013                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
1014                     rec->src_width  > IMAGE_MAX_WIDTH)
1015                         return -EINVAL;
1016         }
1017
1018         /* better safe than sorry, use 4 as the maximal subsampling ratio */
1019         if (rec->src_height < N_VERT_Y_TAPS*4 ||
1020             rec->src_width  < N_HORIZ_Y_TAPS*4)
1021                 return -EINVAL;
1022
1023         /* check alignment constraints */
1024         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1025         case I915_OVERLAY_RGB:
1026                 /* not implemented */
1027                 return -EINVAL;
1028
1029         case I915_OVERLAY_YUV_PACKED:
1030                 if (uv_vscale != 1)
1031                         return -EINVAL;
1032
1033                 depth = packed_depth_bytes(rec->flags);
1034                 if (depth < 0)
1035                         return depth;
1036
1037                 /* ignore UV planes */
1038                 rec->stride_UV = 0;
1039                 rec->offset_U = 0;
1040                 rec->offset_V = 0;
1041                 /* check pixel alignment */
1042                 if (rec->offset_Y % depth)
1043                         return -EINVAL;
1044                 break;
1045
1046         case I915_OVERLAY_YUV_PLANAR:
1047                 if (uv_vscale < 0 || uv_hscale < 0)
1048                         return -EINVAL;
1049                 /* no offset restrictions for planar formats */
1050                 break;
1051
1052         default:
1053                 return -EINVAL;
1054         }
1055
1056         if (rec->src_width % uv_hscale)
1057                 return -EINVAL;
1058
1059         /* stride checking */
1060         if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1061                 stride_mask = 255;
1062         else
1063                 stride_mask = 63;
1064
1065         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1066                 return -EINVAL;
1067         if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
1068                 return -EINVAL;
1069
1070         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1071                 4096 : 8192;
1072         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1073                 return -EINVAL;
1074
1075         /* check buffer dimensions */
1076         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1077         case I915_OVERLAY_RGB:
1078         case I915_OVERLAY_YUV_PACKED:
1079                 /* always 4 Y values per depth pixels */
1080                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1081                         return -EINVAL;
1082
1083                 tmp = rec->stride_Y*rec->src_height;
1084                 if (rec->offset_Y + tmp > new_bo->base.size)
1085                         return -EINVAL;
1086                 break;
1087
1088         case I915_OVERLAY_YUV_PLANAR:
1089                 if (rec->src_width > rec->stride_Y)
1090                         return -EINVAL;
1091                 if (rec->src_width/uv_hscale > rec->stride_UV)
1092                         return -EINVAL;
1093
1094                 tmp = rec->stride_Y * rec->src_height;
1095                 if (rec->offset_Y + tmp > new_bo->base.size)
1096                         return -EINVAL;
1097
1098                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1099                 if (rec->offset_U + tmp > new_bo->base.size ||
1100                     rec->offset_V + tmp > new_bo->base.size)
1101                         return -EINVAL;
1102                 break;
1103         }
1104
1105         return 0;
1106 }
1107
1108 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1109                                   struct drm_file *file_priv)
1110 {
1111         struct drm_intel_overlay_put_image *put_image_rec = data;
1112         struct drm_i915_private *dev_priv = to_i915(dev);
1113         struct intel_overlay *overlay;
1114         struct drm_crtc *drmmode_crtc;
1115         struct intel_crtc *crtc;
1116         struct drm_i915_gem_object *new_bo;
1117         struct put_image_params *params;
1118         int ret;
1119
1120         overlay = dev_priv->overlay;
1121         if (!overlay) {
1122                 DRM_DEBUG("userspace bug: no overlay\n");
1123                 return -ENODEV;
1124         }
1125
1126         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1127                 drm_modeset_lock_all(dev);
1128                 mutex_lock(&dev->struct_mutex);
1129
1130                 ret = intel_overlay_switch_off(overlay);
1131
1132                 mutex_unlock(&dev->struct_mutex);
1133                 drm_modeset_unlock_all(dev);
1134
1135                 return ret;
1136         }
1137
1138         params = kmalloc(sizeof(*params), GFP_KERNEL);
1139         if (!params)
1140                 return -ENOMEM;
1141
1142         drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1143         if (!drmmode_crtc) {
1144                 ret = -ENOENT;
1145                 goto out_free;
1146         }
1147         crtc = to_intel_crtc(drmmode_crtc);
1148
1149         new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle);
1150         if (!new_bo) {
1151                 ret = -ENOENT;
1152                 goto out_free;
1153         }
1154
1155         drm_modeset_lock_all(dev);
1156         mutex_lock(&dev->struct_mutex);
1157
1158         if (i915_gem_object_is_tiled(new_bo)) {
1159                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1160                 ret = -EINVAL;
1161                 goto out_unlock;
1162         }
1163
1164         ret = intel_overlay_recover_from_interrupt(overlay);
1165         if (ret != 0)
1166                 goto out_unlock;
1167
1168         if (overlay->crtc != crtc) {
1169                 ret = intel_overlay_switch_off(overlay);
1170                 if (ret != 0)
1171                         goto out_unlock;
1172
1173                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1174                 if (ret != 0)
1175                         goto out_unlock;
1176
1177                 overlay->crtc = crtc;
1178                 crtc->overlay = overlay;
1179
1180                 /* line too wide, i.e. one-line-mode */
1181                 if (crtc->config->pipe_src_w > 1024 &&
1182                     crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1183                         overlay->pfit_active = true;
1184                         update_pfit_vscale_ratio(overlay);
1185                 } else
1186                         overlay->pfit_active = false;
1187         }
1188
1189         ret = check_overlay_dst(overlay, put_image_rec);
1190         if (ret != 0)
1191                 goto out_unlock;
1192
1193         if (overlay->pfit_active) {
1194                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1195                                  overlay->pfit_vscale_ratio);
1196                 /* shifting right rounds downwards, so add 1 */
1197                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1198                                  overlay->pfit_vscale_ratio) + 1;
1199         } else {
1200                 params->dst_y = put_image_rec->dst_y;
1201                 params->dst_h = put_image_rec->dst_height;
1202         }
1203         params->dst_x = put_image_rec->dst_x;
1204         params->dst_w = put_image_rec->dst_width;
1205
1206         params->src_w = put_image_rec->src_width;
1207         params->src_h = put_image_rec->src_height;
1208         params->src_scan_w = put_image_rec->src_scan_width;
1209         params->src_scan_h = put_image_rec->src_scan_height;
1210         if (params->src_scan_h > params->src_h ||
1211             params->src_scan_w > params->src_w) {
1212                 ret = -EINVAL;
1213                 goto out_unlock;
1214         }
1215
1216         ret = check_overlay_src(dev_priv, put_image_rec, new_bo);
1217         if (ret != 0)
1218                 goto out_unlock;
1219         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1220         params->stride_Y = put_image_rec->stride_Y;
1221         params->stride_UV = put_image_rec->stride_UV;
1222         params->offset_Y = put_image_rec->offset_Y;
1223         params->offset_U = put_image_rec->offset_U;
1224         params->offset_V = put_image_rec->offset_V;
1225
1226         /* Check scaling after src size to prevent a divide-by-zero. */
1227         ret = check_overlay_scaling(params);
1228         if (ret != 0)
1229                 goto out_unlock;
1230
1231         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1232         if (ret != 0)
1233                 goto out_unlock;
1234
1235         mutex_unlock(&dev->struct_mutex);
1236         drm_modeset_unlock_all(dev);
1237         i915_gem_object_put(new_bo);
1238
1239         kfree(params);
1240
1241         return 0;
1242
1243 out_unlock:
1244         mutex_unlock(&dev->struct_mutex);
1245         drm_modeset_unlock_all(dev);
1246         i915_gem_object_put(new_bo);
1247 out_free:
1248         kfree(params);
1249
1250         return ret;
1251 }
1252
1253 static void update_reg_attrs(struct intel_overlay *overlay,
1254                              struct overlay_registers __iomem *regs)
1255 {
1256         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1257                   &regs->OCLRC0);
1258         iowrite32(overlay->saturation, &regs->OCLRC1);
1259 }
1260
1261 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1262 {
1263         int i;
1264
1265         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1266                 return false;
1267
1268         for (i = 0; i < 3; i++) {
1269                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1270                         return false;
1271         }
1272
1273         return true;
1274 }
1275
1276 static bool check_gamma5_errata(u32 gamma5)
1277 {
1278         int i;
1279
1280         for (i = 0; i < 3; i++) {
1281                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1282                         return false;
1283         }
1284
1285         return true;
1286 }
1287
1288 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1289 {
1290         if (!check_gamma_bounds(0, attrs->gamma0) ||
1291             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1292             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1293             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1294             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1295             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1296             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1297                 return -EINVAL;
1298
1299         if (!check_gamma5_errata(attrs->gamma5))
1300                 return -EINVAL;
1301
1302         return 0;
1303 }
1304
1305 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1306                               struct drm_file *file_priv)
1307 {
1308         struct drm_intel_overlay_attrs *attrs = data;
1309         struct drm_i915_private *dev_priv = to_i915(dev);
1310         struct intel_overlay *overlay;
1311         struct overlay_registers __iomem *regs;
1312         int ret;
1313
1314         overlay = dev_priv->overlay;
1315         if (!overlay) {
1316                 DRM_DEBUG("userspace bug: no overlay\n");
1317                 return -ENODEV;
1318         }
1319
1320         drm_modeset_lock_all(dev);
1321         mutex_lock(&dev->struct_mutex);
1322
1323         ret = -EINVAL;
1324         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1325                 attrs->color_key  = overlay->color_key;
1326                 attrs->brightness = overlay->brightness;
1327                 attrs->contrast   = overlay->contrast;
1328                 attrs->saturation = overlay->saturation;
1329
1330                 if (!IS_GEN2(dev_priv)) {
1331                         attrs->gamma0 = I915_READ(OGAMC0);
1332                         attrs->gamma1 = I915_READ(OGAMC1);
1333                         attrs->gamma2 = I915_READ(OGAMC2);
1334                         attrs->gamma3 = I915_READ(OGAMC3);
1335                         attrs->gamma4 = I915_READ(OGAMC4);
1336                         attrs->gamma5 = I915_READ(OGAMC5);
1337                 }
1338         } else {
1339                 if (attrs->brightness < -128 || attrs->brightness > 127)
1340                         goto out_unlock;
1341                 if (attrs->contrast > 255)
1342                         goto out_unlock;
1343                 if (attrs->saturation > 1023)
1344                         goto out_unlock;
1345
1346                 overlay->color_key  = attrs->color_key;
1347                 overlay->brightness = attrs->brightness;
1348                 overlay->contrast   = attrs->contrast;
1349                 overlay->saturation = attrs->saturation;
1350
1351                 regs = intel_overlay_map_regs(overlay);
1352                 if (!regs) {
1353                         ret = -ENOMEM;
1354                         goto out_unlock;
1355                 }
1356
1357                 update_reg_attrs(overlay, regs);
1358
1359                 intel_overlay_unmap_regs(overlay, regs);
1360
1361                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1362                         if (IS_GEN2(dev_priv))
1363                                 goto out_unlock;
1364
1365                         if (overlay->active) {
1366                                 ret = -EBUSY;
1367                                 goto out_unlock;
1368                         }
1369
1370                         ret = check_gamma(attrs);
1371                         if (ret)
1372                                 goto out_unlock;
1373
1374                         I915_WRITE(OGAMC0, attrs->gamma0);
1375                         I915_WRITE(OGAMC1, attrs->gamma1);
1376                         I915_WRITE(OGAMC2, attrs->gamma2);
1377                         I915_WRITE(OGAMC3, attrs->gamma3);
1378                         I915_WRITE(OGAMC4, attrs->gamma4);
1379                         I915_WRITE(OGAMC5, attrs->gamma5);
1380                 }
1381         }
1382         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1383
1384         ret = 0;
1385 out_unlock:
1386         mutex_unlock(&dev->struct_mutex);
1387         drm_modeset_unlock_all(dev);
1388
1389         return ret;
1390 }
1391
1392 void intel_setup_overlay(struct drm_i915_private *dev_priv)
1393 {
1394         struct intel_overlay *overlay;
1395         struct drm_i915_gem_object *reg_bo;
1396         struct overlay_registers __iomem *regs;
1397         struct i915_vma *vma = NULL;
1398         int ret;
1399
1400         if (!HAS_OVERLAY(dev_priv))
1401                 return;
1402
1403         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1404         if (!overlay)
1405                 return;
1406
1407         mutex_lock(&dev_priv->drm.struct_mutex);
1408         if (WARN_ON(dev_priv->overlay))
1409                 goto out_free;
1410
1411         overlay->i915 = dev_priv;
1412
1413         reg_bo = NULL;
1414         if (!OVERLAY_NEEDS_PHYSICAL(dev_priv))
1415                 reg_bo = i915_gem_object_create_stolen(dev_priv, PAGE_SIZE);
1416         if (reg_bo == NULL)
1417                 reg_bo = i915_gem_object_create(dev_priv, PAGE_SIZE);
1418         if (IS_ERR(reg_bo))
1419                 goto out_free;
1420         overlay->reg_bo = reg_bo;
1421
1422         if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) {
1423                 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1424                 if (ret) {
1425                         DRM_ERROR("failed to attach phys overlay regs\n");
1426                         goto out_free_bo;
1427                 }
1428                 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1429         } else {
1430                 vma = i915_gem_object_ggtt_pin(reg_bo, NULL,
1431                                                0, PAGE_SIZE, PIN_MAPPABLE);
1432                 if (IS_ERR(vma)) {
1433                         DRM_ERROR("failed to pin overlay register bo\n");
1434                         ret = PTR_ERR(vma);
1435                         goto out_free_bo;
1436                 }
1437                 overlay->flip_addr = i915_ggtt_offset(vma);
1438
1439                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1440                 if (ret) {
1441                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1442                         goto out_unpin_bo;
1443                 }
1444         }
1445
1446         /* init all values */
1447         overlay->color_key = 0x0101fe;
1448         overlay->color_key_enabled = true;
1449         overlay->brightness = -19;
1450         overlay->contrast = 75;
1451         overlay->saturation = 146;
1452
1453         init_request_active(&overlay->last_flip, NULL);
1454
1455         regs = intel_overlay_map_regs(overlay);
1456         if (!regs)
1457                 goto out_unpin_bo;
1458
1459         memset_io(regs, 0, sizeof(struct overlay_registers));
1460         update_polyphase_filter(regs);
1461         update_reg_attrs(overlay, regs);
1462
1463         intel_overlay_unmap_regs(overlay, regs);
1464
1465         dev_priv->overlay = overlay;
1466         mutex_unlock(&dev_priv->drm.struct_mutex);
1467         DRM_INFO("initialized overlay support\n");
1468         return;
1469
1470 out_unpin_bo:
1471         if (vma)
1472                 i915_vma_unpin(vma);
1473 out_free_bo:
1474         i915_gem_object_put(reg_bo);
1475 out_free:
1476         mutex_unlock(&dev_priv->drm.struct_mutex);
1477         kfree(overlay);
1478         return;
1479 }
1480
1481 void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
1482 {
1483         if (!dev_priv->overlay)
1484                 return;
1485
1486         /* The bo's should be free'd by the generic code already.
1487          * Furthermore modesetting teardown happens beforehand so the
1488          * hardware should be off already */
1489         WARN_ON(dev_priv->overlay->active);
1490
1491         i915_gem_object_put(dev_priv->overlay->reg_bo);
1492         kfree(dev_priv->overlay);
1493 }
1494
1495 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1496
1497 struct intel_overlay_error_state {
1498         struct overlay_registers regs;
1499         unsigned long base;
1500         u32 dovsta;
1501         u32 isr;
1502 };
1503
1504 static struct overlay_registers __iomem *
1505 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1506 {
1507         struct drm_i915_private *dev_priv = overlay->i915;
1508         struct overlay_registers __iomem *regs;
1509
1510         if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
1511                 /* Cast to make sparse happy, but it's wc memory anyway, so
1512                  * equivalent to the wc io mapping on X86. */
1513                 regs = (struct overlay_registers __iomem *)
1514                         overlay->reg_bo->phys_handle->vaddr;
1515         else
1516                 regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable,
1517                                                 overlay->flip_addr);
1518
1519         return regs;
1520 }
1521
1522 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1523                                         struct overlay_registers __iomem *regs)
1524 {
1525         if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
1526                 io_mapping_unmap_atomic(regs);
1527 }
1528
1529 struct intel_overlay_error_state *
1530 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1531 {
1532         struct intel_overlay *overlay = dev_priv->overlay;
1533         struct intel_overlay_error_state *error;
1534         struct overlay_registers __iomem *regs;
1535
1536         if (!overlay || !overlay->active)
1537                 return NULL;
1538
1539         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1540         if (error == NULL)
1541                 return NULL;
1542
1543         error->dovsta = I915_READ(DOVSTA);
1544         error->isr = I915_READ(ISR);
1545         error->base = overlay->flip_addr;
1546
1547         regs = intel_overlay_map_regs_atomic(overlay);
1548         if (!regs)
1549                 goto err;
1550
1551         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1552         intel_overlay_unmap_regs_atomic(overlay, regs);
1553
1554         return error;
1555
1556 err:
1557         kfree(error);
1558         return NULL;
1559 }
1560
1561 void
1562 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1563                                 struct intel_overlay_error_state *error)
1564 {
1565         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1566                           error->dovsta, error->isr);
1567         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1568                           error->base);
1569
1570 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1571         P(OBUF_0Y);
1572         P(OBUF_1Y);
1573         P(OBUF_0U);
1574         P(OBUF_0V);
1575         P(OBUF_1U);
1576         P(OBUF_1V);
1577         P(OSTRIDE);
1578         P(YRGB_VPH);
1579         P(UV_VPH);
1580         P(HORZ_PH);
1581         P(INIT_PHS);
1582         P(DWINPOS);
1583         P(DWINSZ);
1584         P(SWIDTH);
1585         P(SWIDTHSW);
1586         P(SHEIGHT);
1587         P(YRGBSCALE);
1588         P(UVSCALE);
1589         P(OCLRC0);
1590         P(OCLRC1);
1591         P(DCLRKV);
1592         P(DCLRKM);
1593         P(SCLRKVH);
1594         P(SCLRKVL);
1595         P(SCLRKEN);
1596         P(OCONFIG);
1597         P(OCMD);
1598         P(OSTART_0Y);
1599         P(OSTART_1Y);
1600         P(OSTART_0U);
1601         P(OSTART_0V);
1602         P(OSTART_1U);
1603         P(OSTART_1V);
1604         P(OTILEOFF_0Y);
1605         P(OTILEOFF_1Y);
1606         P(OTILEOFF_0U);
1607         P(OTILEOFF_0V);
1608         P(OTILEOFF_1U);
1609         P(OTILEOFF_1V);
1610         P(FASTHSCALE);
1611         P(UVSCALEV);
1612 #undef P
1613 }
1614
1615 #endif