drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47
  48         struct notifier_block lid_notifier;
  49 };
  50
  51 struct intel_lvds_pps {
  52         /* 100us units */
  53         int t1_t2;
  54         int t3;
  55         int t4;
  56         int t5;
  57         int tx;
  58
  59         int divider;
  60
  61         int port;
  62         bool powerdown_on_reset;
  63 };
  64
  65 struct intel_lvds_encoder {
  66         struct intel_encoder base;
  67
  68         bool is_dual_link;
  69         i915_reg_t reg;
  70         u32 a3_power;
  71
  72         struct intel_lvds_pps init_pps;
  73         u32 init_lvds_val;
  74
  75         struct intel_lvds_connector *attached_connector;
  76 };
  77
  78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  79 {
  80         return container_of(encoder, struct intel_lvds_encoder, base.base);
  81 }
  82
  83 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  84 {
  85         return container_of(connector, struct intel_lvds_connector, base.base);
  86 }
  87
  88 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  89                                     enum pipe *pipe)
  90 {
  91         struct drm_device *dev = encoder->base.dev;
  92         struct drm_i915_private *dev_priv = to_i915(dev);
  93         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  94         u32 tmp;
  95         bool ret;
  96
  97         if (!intel_display_power_get_if_enabled(dev_priv,
  98                                                 encoder->power_domain))
  99                 return false;
 100
 101         ret = false;
 102
 103         tmp = I915_READ(lvds_encoder->reg);
 104
 105         if (!(tmp & LVDS_PORT_EN))
 106                 goto out;
 107
 108         if (HAS_PCH_CPT(dev_priv))
 109                 *pipe = PORT_TO_PIPE_CPT(tmp);
 110         else
 111                 *pipe = PORT_TO_PIPE(tmp);
 112
 113         ret = true;
 114
 115 out:
 116         intel_display_power_put(dev_priv, encoder->power_domain);
 117
 118         return ret;
 119 }
 120
 121 static void intel_lvds_get_config(struct intel_encoder *encoder,
 122                                   struct intel_crtc_state *pipe_config)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 125         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 126         u32 tmp, flags = 0;
 127
 128         pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 129
 130         tmp = I915_READ(lvds_encoder->reg);
 131         if (tmp & LVDS_HSYNC_POLARITY)
 132                 flags |= DRM_MODE_FLAG_NHSYNC;
 133         else
 134                 flags |= DRM_MODE_FLAG_PHSYNC;
 135         if (tmp & LVDS_VSYNC_POLARITY)
 136                 flags |= DRM_MODE_FLAG_NVSYNC;
 137         else
 138                 flags |= DRM_MODE_FLAG_PVSYNC;
 139
 140         pipe_config->base.adjusted_mode.flags |= flags;
 141
 142         if (INTEL_GEN(dev_priv) < 5)
 143                 pipe_config->gmch_pfit.lvds_border_bits =
 144                         tmp & LVDS_BORDER_ENABLE;
 145
 146         /* gen2/3 store dither state in pfit control, needs to match */
 147         if (INTEL_GEN(dev_priv) < 4) {
 148                 tmp = I915_READ(PFIT_CONTROL);
 149
 150                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 151         }
 152
 153         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 154 }
 155
 156 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 157                                         struct intel_lvds_pps *pps)
 158 {
 159         u32 val;
 160
 161         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 162
 163         val = I915_READ(PP_ON_DELAYS(0));
 164         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 165                     PANEL_PORT_SELECT_SHIFT;
 166         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 167                      PANEL_POWER_UP_DELAY_SHIFT;
 168         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 169                   PANEL_LIGHT_ON_DELAY_SHIFT;
 170
 171         val = I915_READ(PP_OFF_DELAYS(0));
 172         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 173                   PANEL_POWER_DOWN_DELAY_SHIFT;
 174         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 175                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 176
 177         val = I915_READ(PP_DIVISOR(0));
 178         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 179                        PP_REFERENCE_DIVIDER_SHIFT;
 180         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 181               PANEL_POWER_CYCLE_DELAY_SHIFT;
 182         /*
 183          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 184          * too short power-cycle delay due to the asynchronous programming of
 185          * the register.
 186          */
 187         if (val)
 188                 val--;
 189         /* Convert from 100ms to 100us units */
 190         pps->t4 = val * 1000;
 191
 192         if (INTEL_GEN(dev_priv) <= 4 &&
 193             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 194                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 195                               "setting defaults\n");
 196                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 197                 pps->t1_t2 = 40 * 10;
 198                 pps->t5 = 200 * 10;
 199                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 200                 pps->t3 = 35 * 10;
 201                 pps->tx = 200 * 10;
 202         }
 203
 204         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 205                          "divider %d port %d powerdown_on_reset %d\n",
 206                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 207                          pps->divider, pps->port, pps->powerdown_on_reset);
 208 }
 209
 210 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 211                                    struct intel_lvds_pps *pps)
 212 {
 213         u32 val;
 214
 215         val = I915_READ(PP_CONTROL(0));
 216         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 217         if (pps->powerdown_on_reset)
 218                 val |= PANEL_POWER_RESET;
 219         I915_WRITE(PP_CONTROL(0), val);
 220
 221         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 222                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 223                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 224         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 225                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 226
 227         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 228         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 229                PANEL_POWER_CYCLE_DELAY_SHIFT;
 230         I915_WRITE(PP_DIVISOR(0), val);
 231 }
 232
 233 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 234                                   const struct intel_crtc_state *pipe_config,
 235                                   const struct drm_connector_state *conn_state)
 236 {
 237         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 239         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 240         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 241         int pipe = crtc->pipe;
 242         u32 temp;
 243
 244         if (HAS_PCH_SPLIT(dev_priv)) {
 245                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 246                 assert_shared_dpll_disabled(dev_priv,
 247                                             pipe_config->shared_dpll);
 248         } else {
 249                 assert_pll_disabled(dev_priv, pipe);
 250         }
 251
 252         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 253
 254         temp = lvds_encoder->init_lvds_val;
 255         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 256
 257         if (HAS_PCH_CPT(dev_priv)) {
 258                 temp &= ~PORT_TRANS_SEL_MASK;
 259                 temp |= PORT_TRANS_SEL_CPT(pipe);
 260         } else {
 261                 if (pipe == 1) {
 262                         temp |= LVDS_PIPEB_SELECT;
 263                 } else {
 264                         temp &= ~LVDS_PIPEB_SELECT;
 265                 }
 266         }
 267
 268         /* set the corresponsding LVDS_BORDER bit */
 269         temp &= ~LVDS_BORDER_ENABLE;
 270         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 271
 272         /*
 273          * Set the B0-B3 data pairs corresponding to whether we're going to
 274          * set the DPLLs for dual-channel mode or not.
 275          */
 276         if (lvds_encoder->is_dual_link)
 277                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 278         else
 279                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 280
 281         /*
 282          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 283          * appropriately here, but we need to look more thoroughly into how
 284          * panels behave in the two modes. For now, let's just maintain the
 285          * value we got from the BIOS.
 286          */
 287         temp &= ~LVDS_A3_POWER_MASK;
 288         temp |= lvds_encoder->a3_power;
 289
 290         /*
 291          * Set the dithering flag on LVDS as needed, note that there is no
 292          * special lvds dither control bit on pch-split platforms, dithering is
 293          * only controlled through the PIPECONF reg.
 294          */
 295         if (IS_GEN4(dev_priv)) {
 296                 /*
 297                  * Bspec wording suggests that LVDS port dithering only exists
 298                  * for 18bpp panels.
 299                  */
 300                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 301                         temp |= LVDS_ENABLE_DITHER;
 302                 else
 303                         temp &= ~LVDS_ENABLE_DITHER;
 304         }
 305         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 306         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 307                 temp |= LVDS_HSYNC_POLARITY;
 308         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 309                 temp |= LVDS_VSYNC_POLARITY;
 310
 311         I915_WRITE(lvds_encoder->reg, temp);
 312 }
 313
 314 /*
 315  * Sets the power state for the panel.
 316  */
 317 static void intel_enable_lvds(struct intel_encoder *encoder,
 318                               const struct intel_crtc_state *pipe_config,
 319                               const struct drm_connector_state *conn_state)
 320 {
 321         struct drm_device *dev = encoder->base.dev;
 322         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 323         struct drm_i915_private *dev_priv = to_i915(dev);
 324
 325         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 326
 327         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 328         POSTING_READ(lvds_encoder->reg);
 329
 330         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
 331                 DRM_ERROR("timed out waiting for panel to power on\n");
 332
 333         intel_panel_enable_backlight(pipe_config, conn_state);
 334 }
 335
 336 static void intel_disable_lvds(struct intel_encoder *encoder,
 337                                const struct intel_crtc_state *old_crtc_state,
 338                                const struct drm_connector_state *old_conn_state)
 339 {
 340         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 341         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 342
 343         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 344         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 345                 DRM_ERROR("timed out waiting for panel to power off\n");
 346
 347         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 348         POSTING_READ(lvds_encoder->reg);
 349 }
 350
 351 static void gmch_disable_lvds(struct intel_encoder *encoder,
 352                               const struct intel_crtc_state *old_crtc_state,
 353                               const struct drm_connector_state *old_conn_state)
 354
 355 {
 356         intel_panel_disable_backlight(old_conn_state);
 357
 358         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 359 }
 360
 361 static void pch_disable_lvds(struct intel_encoder *encoder,
 362                              const struct intel_crtc_state *old_crtc_state,
 363                              const struct drm_connector_state *old_conn_state)
 364 {
 365         intel_panel_disable_backlight(old_conn_state);
 366 }
 367
 368 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 369                                   const struct intel_crtc_state *old_crtc_state,
 370                                   const struct drm_connector_state *old_conn_state)
 371 {
 372         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 373 }
 374
 375 static enum drm_mode_status
 376 intel_lvds_mode_valid(struct drm_connector *connector,
 377                       struct drm_display_mode *mode)
 378 {
 379         struct intel_connector *intel_connector = to_intel_connector(connector);
 380         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 381         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 382
 383         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 384                 return MODE_NO_DBLESCAN;
 385         if (mode->hdisplay > fixed_mode->hdisplay)
 386                 return MODE_PANEL;
 387         if (mode->vdisplay > fixed_mode->vdisplay)
 388                 return MODE_PANEL;
 389         if (fixed_mode->clock > max_pixclk)
 390                 return MODE_CLOCK_HIGH;
 391
 392         return MODE_OK;
 393 }
 394
 395 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 396                                       struct intel_crtc_state *pipe_config,
 397                                       struct drm_connector_state *conn_state)
 398 {
 399         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 400         struct intel_lvds_encoder *lvds_encoder =
 401                 to_lvds_encoder(&intel_encoder->base);
 402         struct intel_connector *intel_connector =
 403                 &lvds_encoder->attached_connector->base;
 404         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 405         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 406         unsigned int lvds_bpp;
 407
 408         /* Should never happen!! */
 409         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 410                 DRM_ERROR("Can't support LVDS on pipe A\n");
 411                 return false;
 412         }
 413
 414         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 415                 lvds_bpp = 8*3;
 416         else
 417                 lvds_bpp = 6*3;
 418
 419         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 420                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 421                               pipe_config->pipe_bpp, lvds_bpp);
 422                 pipe_config->pipe_bpp = lvds_bpp;
 423         }
 424
 425         /*
 426          * We have timings from the BIOS for the panel, put them in
 427          * to the adjusted mode.  The CRTC will be set up for this mode,
 428          * with the panel scaling set up to source from the H/VDisplay
 429          * of the original mode.
 430          */
 431         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 432                                adjusted_mode);
 433
 434         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 435                 return false;
 436
 437         if (HAS_PCH_SPLIT(dev_priv)) {
 438                 pipe_config->has_pch_encoder = true;
 439
 440                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 441                                         conn_state->scaling_mode);
 442         } else {
 443                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 444                                          conn_state->scaling_mode);
 445
 446         }
 447
 448         /*
 449          * XXX: It would be nice to support lower refresh rates on the
 450          * panels to reduce power consumption, and perhaps match the
 451          * user's requested refresh rate.
 452          */
 453
 454         return true;
 455 }
 456
 457 /*
 458  * Detect the LVDS connection.
 459  *
 460  * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means
 461  * connected and closed means disconnected.  We also send hotplug events as
 462  * needed, using lid status notification from the input layer.
 463  */
 464 static enum drm_connector_status
 465 intel_lvds_detect(struct drm_connector *connector, bool force)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 468         enum drm_connector_status status;
 469
 470         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 471                       connector->base.id, connector->name);
 472
 473         status = intel_panel_detect(dev_priv);
 474         if (status != connector_status_unknown)
 475                 return status;
 476
 477         return connector_status_connected;
 478 }
 479
 480 /*
 481  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 482  */
 483 static int intel_lvds_get_modes(struct drm_connector *connector)
 484 {
 485         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 486         struct drm_device *dev = connector->dev;
 487         struct drm_display_mode *mode;
 488
 489         /* use cached edid if we have one */
 490         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 491                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 492
 493         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 494         if (mode == NULL)
 495                 return 0;
 496
 497         drm_mode_probed_add(connector, mode);
 498         return 1;
 499 }
 500
 501 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
 502 {
 503         DRM_INFO("Skipping forced modeset for %s\n", id->ident);
 504         return 1;
 505 }
 506
 507 /* The GPU hangs up on these systems if modeset is performed on LID open */
 508 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
 509         {
 510                 .callback = intel_no_modeset_on_lid_dmi_callback,
 511                 .ident = "Toshiba Tecra A11",
 512                 .matches = {
 513                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 514                         DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
 515                 },
 516         },
 517
 518         { }     /* terminating entry */
 519 };
 520
 521 /*
 522  * Lid events. Note the use of 'modeset':
 523  *  - we set it to MODESET_ON_LID_OPEN on lid close,
 524  *    and set it to MODESET_DONE on open
 525  *  - we use it as a "only once" bit (ie we ignore
 526  *    duplicate events where it was already properly set)
 527  *  - the suspend/resume paths will set it to
 528  *    MODESET_SUSPENDED and ignore the lid open event,
 529  *    because they restore the mode ("lid open").
 530  */
 531 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
 532                             void *unused)
 533 {
 534         struct intel_lvds_connector *lvds_connector =
 535                 container_of(nb, struct intel_lvds_connector, lid_notifier);
 536         struct drm_connector *connector = &lvds_connector->base.base;
 537         struct drm_device *dev = connector->dev;
 538         struct drm_i915_private *dev_priv = to_i915(dev);
 539
 540         if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
 541                 return NOTIFY_OK;
 542
 543         mutex_lock(&dev_priv->modeset_restore_lock);
 544         if (dev_priv->modeset_restore == MODESET_SUSPENDED)
 545                 goto exit;
 546         /*
 547          * check and update the status of LVDS connector after receiving
 548          * the LID nofication event.
 549          */
 550         connector->status = connector->funcs->detect(connector, false);
 551
 552         /* Don't force modeset on machines where it causes a GPU lockup */
 553         if (dmi_check_system(intel_no_modeset_on_lid))
 554                 goto exit;
 555         if (!acpi_lid_open()) {
 556                 /* do modeset on next lid open event */
 557                 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
 558                 goto exit;
 559         }
 560
 561         if (dev_priv->modeset_restore == MODESET_DONE)
 562                 goto exit;
 563
 564         /*
 565          * Some old platform's BIOS love to wreak havoc while the lid is closed.
 566          * We try to detect this here and undo any damage. The split for PCH
 567          * platforms is rather conservative and a bit arbitrary expect that on
 568          * those platforms VGA disabling requires actual legacy VGA I/O access,
 569          * and as part of the cleanup in the hw state restore we also redisable
 570          * the vga plane.
 571          */
 572         if (!HAS_PCH_SPLIT(dev_priv))
 573                 intel_display_resume(dev);
 574
 575         dev_priv->modeset_restore = MODESET_DONE;
 576
 577 exit:
 578         mutex_unlock(&dev_priv->modeset_restore_lock);
 579         return NOTIFY_OK;
 580 }
 581
 582 static int
 583 intel_lvds_connector_register(struct drm_connector *connector)
 584 {
 585         struct intel_lvds_connector *lvds = to_lvds_connector(connector);
 586         int ret;
 587
 588         ret = intel_connector_register(connector);
 589         if (ret)
 590                 return ret;
 591
 592         lvds->lid_notifier.notifier_call = intel_lid_notify;
 593         if (acpi_lid_notifier_register(&lvds->lid_notifier)) {
 594                 DRM_DEBUG_KMS("lid notifier registration failed\n");
 595                 lvds->lid_notifier.notifier_call = NULL;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static void
 602 intel_lvds_connector_unregister(struct drm_connector *connector)
 603 {
 604         struct intel_lvds_connector *lvds = to_lvds_connector(connector);
 605
 606         if (lvds->lid_notifier.notifier_call)
 607                 acpi_lid_notifier_unregister(&lvds->lid_notifier);
 608
 609         intel_connector_unregister(connector);
 610 }
 611
 612 /**
 613  * intel_lvds_destroy - unregister and free LVDS structures
 614  * @connector: connector to free
 615  *
 616  * Unregister the DDC bus for this connector then free the driver private
 617  * structure.
 618  */
 619 static void intel_lvds_destroy(struct drm_connector *connector)
 620 {
 621         struct intel_lvds_connector *lvds_connector =
 622                 to_lvds_connector(connector);
 623
 624         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 625                 kfree(lvds_connector->base.edid);
 626
 627         intel_panel_fini(&lvds_connector->base.panel);
 628
 629         drm_connector_cleanup(connector);
 630         kfree(connector);
 631 }
 632
 633 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 634         .get_modes = intel_lvds_get_modes,
 635         .mode_valid = intel_lvds_mode_valid,
 636         .atomic_check = intel_digital_connector_atomic_check,
 637 };
 638
 639 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 640         .detect = intel_lvds_detect,
 641         .fill_modes = drm_helper_probe_single_connector_modes,
 642         .atomic_get_property = intel_digital_connector_atomic_get_property,
 643         .atomic_set_property = intel_digital_connector_atomic_set_property,
 644         .late_register = intel_lvds_connector_register,
 645         .early_unregister = intel_lvds_connector_unregister,
 646         .destroy = intel_lvds_destroy,
 647         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 648         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 649 };
 650
 651 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 652         .destroy = intel_encoder_destroy,
 653 };
 654
 655 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 656 {
 657         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 658         return 1;
 659 }
 660
 661 /* These systems claim to have LVDS, but really don't */
 662 static const struct dmi_system_id intel_no_lvds[] = {
 663         {
 664                 .callback = intel_no_lvds_dmi_callback,
 665                 .ident = "Apple Mac Mini (Core series)",
 666                 .matches = {
 667                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 668                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 669                 },
 670         },
 671         {
 672                 .callback = intel_no_lvds_dmi_callback,
 673                 .ident = "Apple Mac Mini (Core 2 series)",
 674                 .matches = {
 675                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 676                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 677                 },
 678         },
 679         {
 680                 .callback = intel_no_lvds_dmi_callback,
 681                 .ident = "MSI IM-945GSE-A",
 682                 .matches = {
 683                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 684                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 685                 },
 686         },
 687         {
 688                 .callback = intel_no_lvds_dmi_callback,
 689                 .ident = "Dell Studio Hybrid",
 690                 .matches = {
 691                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 692                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 693                 },
 694         },
 695         {
 696                 .callback = intel_no_lvds_dmi_callback,
 697                 .ident = "Dell OptiPlex FX170",
 698                 .matches = {
 699                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 700                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 701                 },
 702         },
 703         {
 704                 .callback = intel_no_lvds_dmi_callback,
 705                 .ident = "AOpen Mini PC",
 706                 .matches = {
 707                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 708                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 709                 },
 710         },
 711         {
 712                 .callback = intel_no_lvds_dmi_callback,
 713                 .ident = "AOpen Mini PC MP915",
 714                 .matches = {
 715                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 716                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 717                 },
 718         },
 719         {
 720                 .callback = intel_no_lvds_dmi_callback,
 721                 .ident = "AOpen i915GMm-HFS",
 722                 .matches = {
 723                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 724                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 725                 },
 726         },
 727         {
 728                 .callback = intel_no_lvds_dmi_callback,
 729                 .ident = "AOpen i45GMx-I",
 730                 .matches = {
 731                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 732                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 733                 },
 734         },
 735         {
 736                 .callback = intel_no_lvds_dmi_callback,
 737                 .ident = "Aopen i945GTt-VFA",
 738                 .matches = {
 739                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 740                 },
 741         },
 742         {
 743                 .callback = intel_no_lvds_dmi_callback,
 744                 .ident = "Clientron U800",
 745                 .matches = {
 746                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 747                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 748                 },
 749         },
 750         {
 751                 .callback = intel_no_lvds_dmi_callback,
 752                 .ident = "Clientron E830",
 753                 .matches = {
 754                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 755                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 756                 },
 757         },
 758         {
 759                 .callback = intel_no_lvds_dmi_callback,
 760                 .ident = "Asus EeeBox PC EB1007",
 761                 .matches = {
 762                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 763                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 764                 },
 765         },
 766         {
 767                 .callback = intel_no_lvds_dmi_callback,
 768                 .ident = "Asus AT5NM10T-I",
 769                 .matches = {
 770                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 771                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 772                 },
 773         },
 774         {
 775                 .callback = intel_no_lvds_dmi_callback,
 776                 .ident = "Hewlett-Packard HP t5740",
 777                 .matches = {
 778                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 779                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 780                 },
 781         },
 782         {
 783                 .callback = intel_no_lvds_dmi_callback,
 784                 .ident = "Hewlett-Packard t5745",
 785                 .matches = {
 786                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 787                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 788                 },
 789         },
 790         {
 791                 .callback = intel_no_lvds_dmi_callback,
 792                 .ident = "Hewlett-Packard st5747",
 793                 .matches = {
 794                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 795                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 796                 },
 797         },
 798         {
 799                 .callback = intel_no_lvds_dmi_callback,
 800                 .ident = "MSI Wind Box DC500",
 801                 .matches = {
 802                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 803                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 804                 },
 805         },
 806         {
 807                 .callback = intel_no_lvds_dmi_callback,
 808                 .ident = "Gigabyte GA-D525TUD",
 809                 .matches = {
 810                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 811                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 812                 },
 813         },
 814         {
 815                 .callback = intel_no_lvds_dmi_callback,
 816                 .ident = "Supermicro X7SPA-H",
 817                 .matches = {
 818                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 819                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 820                 },
 821         },
 822         {
 823                 .callback = intel_no_lvds_dmi_callback,
 824                 .ident = "Fujitsu Esprimo Q900",
 825                 .matches = {
 826                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 827                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 828                 },
 829         },
 830         {
 831                 .callback = intel_no_lvds_dmi_callback,
 832                 .ident = "Intel D410PT",
 833                 .matches = {
 834                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 835                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 836                 },
 837         },
 838         {
 839                 .callback = intel_no_lvds_dmi_callback,
 840                 .ident = "Intel D425KT",
 841                 .matches = {
 842                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 843                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 844                 },
 845         },
 846         {
 847                 .callback = intel_no_lvds_dmi_callback,
 848                 .ident = "Intel D510MO",
 849                 .matches = {
 850                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 851                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 852                 },
 853         },
 854         {
 855                 .callback = intel_no_lvds_dmi_callback,
 856                 .ident = "Intel D525MW",
 857                 .matches = {
 858                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 859                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 860                 },
 861         },
 862         {
 863                 .callback = intel_no_lvds_dmi_callback,
 864                 .ident = "Radiant P845",
 865                 .matches = {
 866                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 867                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 868                 },
 869         },
 870
 871         { }     /* terminating entry */
 872 };
 873
 874 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 875 {
 876         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 877         return 1;
 878 }
 879
 880 static const struct dmi_system_id intel_dual_link_lvds[] = {
 881         {
 882                 .callback = intel_dual_link_lvds_callback,
 883                 .ident = "Apple MacBook Pro 15\" (2010)",
 884                 .matches = {
 885                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 886                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 887                 },
 888         },
 889         {
 890                 .callback = intel_dual_link_lvds_callback,
 891                 .ident = "Apple MacBook Pro 15\" (2011)",
 892                 .matches = {
 893                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 894                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 895                 },
 896         },
 897         {
 898                 .callback = intel_dual_link_lvds_callback,
 899                 .ident = "Apple MacBook Pro 15\" (2012)",
 900                 .matches = {
 901                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 902                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 903                 },
 904         },
 905         { }     /* terminating entry */
 906 };
 907
 908 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 909 {
 910         struct intel_encoder *intel_encoder;
 911
 912         for_each_intel_encoder(dev, intel_encoder)
 913                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 914                         return intel_encoder;
 915
 916         return NULL;
 917 }
 918
 919 bool intel_is_dual_link_lvds(struct drm_device *dev)
 920 {
 921         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 922
 923         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 924 }
 925
 926 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 927 {
 928         struct drm_device *dev = lvds_encoder->base.base.dev;
 929         unsigned int val;
 930         struct drm_i915_private *dev_priv = to_i915(dev);
 931
 932         /* use the module option value if specified */
 933         if (i915_modparams.lvds_channel_mode > 0)
 934                 return i915_modparams.lvds_channel_mode == 2;
 935
 936         /* single channel LVDS is limited to 112 MHz */
 937         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 938             > 112999)
 939                 return true;
 940
 941         if (dmi_check_system(intel_dual_link_lvds))
 942                 return true;
 943
 944         /*
 945          * BIOS should set the proper LVDS register value at boot, but
 946          * in reality, it doesn't set the value when the lid is closed;
 947          * we need to check "the value to be set" in VBT when LVDS
 948          * register is uninitialized.
 949          */
 950         val = I915_READ(lvds_encoder->reg);
 951         if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 952                 val = dev_priv->vbt.bios_lvds_val;
 953
 954         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 955 }
 956
 957 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 958 {
 959         /*
 960          * With the introduction of the PCH we gained a dedicated
 961          * LVDS presence pin, use it.
 962          */
 963         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 964                 return true;
 965
 966         /*
 967          * Otherwise LVDS was only attached to mobile products,
 968          * except for the inglorious 830gm
 969          */
 970         if (INTEL_GEN(dev_priv) <= 4 &&
 971             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 972                 return true;
 973
 974         return false;
 975 }
 976
 977 /**
 978  * intel_lvds_init - setup LVDS connectors on this device
 979  * @dev_priv: i915 device
 980  *
 981  * Create the connector, register the LVDS DDC bus, and try to figure out what
 982  * modes we can display on the LVDS panel (if present).
 983  */
 984 void intel_lvds_init(struct drm_i915_private *dev_priv)
 985 {
 986         struct drm_device *dev = &dev_priv->drm;
 987         struct intel_lvds_encoder *lvds_encoder;
 988         struct intel_encoder *intel_encoder;
 989         struct intel_lvds_connector *lvds_connector;
 990         struct intel_connector *intel_connector;
 991         struct drm_connector *connector;
 992         struct drm_encoder *encoder;
 993         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 994         struct drm_display_mode *fixed_mode = NULL;
 995         struct drm_display_mode *downclock_mode = NULL;
 996         struct edid *edid;
 997         i915_reg_t lvds_reg;
 998         u32 lvds;
 999         u8 pin;
1000         u32 allowed_scalers;
1001
1002         if (!intel_lvds_supported(dev_priv))
1003                 return;
1004
1005         /* Skip init on machines we know falsely report LVDS */
1006         if (dmi_check_system(intel_no_lvds))
1007                 return;
1008
1009         if (HAS_PCH_SPLIT(dev_priv))
1010                 lvds_reg = PCH_LVDS;
1011         else
1012                 lvds_reg = LVDS;
1013
1014         lvds = I915_READ(lvds_reg);
1015
1016         if (HAS_PCH_SPLIT(dev_priv)) {
1017                 if ((lvds & LVDS_DETECTED) == 0)
1018                         return;
1019                 if (dev_priv->vbt.edp.support) {
1020                         DRM_DEBUG_KMS("disable LVDS for eDP support\n");
1021                         return;
1022                 }
1023         }
1024
1025         pin = GMBUS_PIN_PANEL;
1026         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
1027                 if ((lvds & LVDS_PORT_EN) == 0) {
1028                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
1029                         return;
1030                 }
1031                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
1032         }
1033
1034         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
1035         if (!lvds_encoder)
1036                 return;
1037
1038         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
1039         if (!lvds_connector) {
1040                 kfree(lvds_encoder);
1041                 return;
1042         }
1043
1044         if (intel_connector_init(&lvds_connector->base) < 0) {
1045                 kfree(lvds_connector);
1046                 kfree(lvds_encoder);
1047                 return;
1048         }
1049
1050         lvds_encoder->attached_connector = lvds_connector;
1051
1052         intel_encoder = &lvds_encoder->base;
1053         encoder = &intel_encoder->base;
1054         intel_connector = &lvds_connector->base;
1055         connector = &intel_connector->base;
1056         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1057                            DRM_MODE_CONNECTOR_LVDS);
1058
1059         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1060                          DRM_MODE_ENCODER_LVDS, "LVDS");
1061
1062         intel_encoder->enable = intel_enable_lvds;
1063         intel_encoder->pre_enable = intel_pre_enable_lvds;
1064         intel_encoder->compute_config = intel_lvds_compute_config;
1065         if (HAS_PCH_SPLIT(dev_priv)) {
1066                 intel_encoder->disable = pch_disable_lvds;
1067                 intel_encoder->post_disable = pch_post_disable_lvds;
1068         } else {
1069                 intel_encoder->disable = gmch_disable_lvds;
1070         }
1071         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1072         intel_encoder->get_config = intel_lvds_get_config;
1073         intel_connector->get_hw_state = intel_connector_get_hw_state;
1074
1075         intel_connector_attach_encoder(intel_connector, intel_encoder);
1076
1077         intel_encoder->type = INTEL_OUTPUT_LVDS;
1078         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1079         intel_encoder->port = PORT_NONE;
1080         intel_encoder->cloneable = 0;
1081         if (HAS_PCH_SPLIT(dev_priv))
1082                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1083         else if (IS_GEN4(dev_priv))
1084                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1085         else
1086                 intel_encoder->crtc_mask = (1 << 1);
1087
1088         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1089         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1090         connector->interlace_allowed = false;
1091         connector->doublescan_allowed = false;
1092
1093         lvds_encoder->reg = lvds_reg;
1094
1095         /* create the scaling mode property */
1096         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
1097         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
1098         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1099         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
1100         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1101
1102         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
1103         lvds_encoder->init_lvds_val = lvds;
1104
1105         /*
1106          * LVDS discovery:
1107          * 1) check for EDID on DDC
1108          * 2) check for VBT data
1109          * 3) check to see if LVDS is already on
1110          *    if none of the above, no panel
1111          * 4) make sure lid is open
1112          *    if closed, act like it's not there for now
1113          */
1114
1115         /*
1116          * Attempt to get the fixed panel mode from DDC.  Assume that the
1117          * preferred mode is the right one.
1118          */
1119         mutex_lock(&dev->mode_config.mutex);
1120         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1121                 edid = drm_get_edid_switcheroo(connector,
1122                                     intel_gmbus_get_adapter(dev_priv, pin));
1123         else
1124                 edid = drm_get_edid(connector,
1125                                     intel_gmbus_get_adapter(dev_priv, pin));
1126         if (edid) {
1127                 if (drm_add_edid_modes(connector, edid)) {
1128                         drm_mode_connector_update_edid_property(connector,
1129                                                                 edid);
1130                 } else {
1131                         kfree(edid);
1132                         edid = ERR_PTR(-EINVAL);
1133                 }
1134         } else {
1135                 edid = ERR_PTR(-ENOENT);
1136         }
1137         lvds_connector->base.edid = edid;
1138
1139         list_for_each_entry(scan, &connector->probed_modes, head) {
1140                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1141                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
1142                         drm_mode_debug_printmodeline(scan);
1143
1144                         fixed_mode = drm_mode_duplicate(dev, scan);
1145                         if (fixed_mode)
1146                                 goto out;
1147                 }
1148         }
1149
1150         /* Failed to get EDID, what about VBT? */
1151         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1152                 DRM_DEBUG_KMS("using mode from VBT: ");
1153                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1154
1155                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1156                 if (fixed_mode) {
1157                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1158                         connector->display_info.width_mm = fixed_mode->width_mm;
1159                         connector->display_info.height_mm = fixed_mode->height_mm;
1160                         goto out;
1161                 }
1162         }
1163
1164         /*
1165          * If we didn't get EDID, try checking if the panel is already turned
1166          * on.  If so, assume that whatever is currently programmed is the
1167          * correct mode.
1168          */
1169         fixed_mode = intel_encoder_current_mode(intel_encoder);
1170         if (fixed_mode) {
1171                 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1172                 drm_mode_debug_printmodeline(fixed_mode);
1173                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1174         }
1175
1176         /* If we still don't have a mode after all that, give up. */
1177         if (!fixed_mode)
1178                 goto failed;
1179
1180 out:
1181         mutex_unlock(&dev->mode_config.mutex);
1182
1183         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1184         intel_panel_setup_backlight(connector, INVALID_PIPE);
1185
1186         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1187         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1188                       lvds_encoder->is_dual_link ? "dual" : "single");
1189
1190         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1191
1192         return;
1193
1194 failed:
1195         mutex_unlock(&dev->mode_config.mutex);
1196
1197         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1198         drm_connector_cleanup(connector);
1199         drm_encoder_cleanup(encoder);
1200         kfree(lvds_encoder);
1201         kfree(lvds_connector);
1202         return;
1203 }