drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_scdc_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41 #include "i915_drv.h"
  42
  43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  44 {
  45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  46 }
  47
  48 static void
  49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  50 {
  51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  52         struct drm_i915_private *dev_priv = to_i915(dev);
  53         uint32_t enabled_bits;
  54
  55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  56
  57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  58              "HDMI port enabled, expecting disabled\n");
  59 }
  60
  61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  62 {
  63         struct intel_digital_port *intel_dig_port =
  64                 container_of(encoder, struct intel_digital_port, base.base);
  65         return &intel_dig_port->hdmi;
  66 }
  67
  68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  69 {
  70         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  71 }
  72
  73 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  74 {
  75         switch (type) {
  76         case HDMI_INFOFRAME_TYPE_AVI:
  77                 return VIDEO_DIP_SELECT_AVI;
  78         case HDMI_INFOFRAME_TYPE_SPD:
  79                 return VIDEO_DIP_SELECT_SPD;
  80         case HDMI_INFOFRAME_TYPE_VENDOR:
  81                 return VIDEO_DIP_SELECT_VENDOR;
  82         default:
  83                 MISSING_CASE(type);
  84                 return 0;
  85         }
  86 }
  87
  88 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  89 {
  90         switch (type) {
  91         case HDMI_INFOFRAME_TYPE_AVI:
  92                 return VIDEO_DIP_ENABLE_AVI;
  93         case HDMI_INFOFRAME_TYPE_SPD:
  94                 return VIDEO_DIP_ENABLE_SPD;
  95         case HDMI_INFOFRAME_TYPE_VENDOR:
  96                 return VIDEO_DIP_ENABLE_VENDOR;
  97         default:
  98                 MISSING_CASE(type);
  99                 return 0;
 100         }
 101 }
 102
 103 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 104 {
 105         switch (type) {
 106         case HDMI_INFOFRAME_TYPE_AVI:
 107                 return VIDEO_DIP_ENABLE_AVI_HSW;
 108         case HDMI_INFOFRAME_TYPE_SPD:
 109                 return VIDEO_DIP_ENABLE_SPD_HSW;
 110         case HDMI_INFOFRAME_TYPE_VENDOR:
 111                 return VIDEO_DIP_ENABLE_VS_HSW;
 112         default:
 113                 MISSING_CASE(type);
 114                 return 0;
 115         }
 116 }
 117
 118 static i915_reg_t
 119 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 120                  enum transcoder cpu_transcoder,
 121                  enum hdmi_infoframe_type type,
 122                  int i)
 123 {
 124         switch (type) {
 125         case HDMI_INFOFRAME_TYPE_AVI:
 126                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 127         case HDMI_INFOFRAME_TYPE_SPD:
 128                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 129         case HDMI_INFOFRAME_TYPE_VENDOR:
 130                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 131         default:
 132                 MISSING_CASE(type);
 133                 return INVALID_MMIO_REG;
 134         }
 135 }
 136
 137 static void g4x_write_infoframe(struct drm_encoder *encoder,
 138                                 const struct intel_crtc_state *crtc_state,
 139                                 enum hdmi_infoframe_type type,
 140                                 const void *frame, ssize_t len)
 141 {
 142         const uint32_t *data = frame;
 143         struct drm_device *dev = encoder->dev;
 144         struct drm_i915_private *dev_priv = to_i915(dev);
 145         u32 val = I915_READ(VIDEO_DIP_CTL);
 146         int i;
 147
 148         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 149
 150         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 151         val |= g4x_infoframe_index(type);
 152
 153         val &= ~g4x_infoframe_enable(type);
 154
 155         I915_WRITE(VIDEO_DIP_CTL, val);
 156
 157         mmiowb();
 158         for (i = 0; i < len; i += 4) {
 159                 I915_WRITE(VIDEO_DIP_DATA, *data);
 160                 data++;
 161         }
 162         /* Write every possible data byte to force correct ECC calculation. */
 163         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 164                 I915_WRITE(VIDEO_DIP_DATA, 0);
 165         mmiowb();
 166
 167         val |= g4x_infoframe_enable(type);
 168         val &= ~VIDEO_DIP_FREQ_MASK;
 169         val |= VIDEO_DIP_FREQ_VSYNC;
 170
 171         I915_WRITE(VIDEO_DIP_CTL, val);
 172         POSTING_READ(VIDEO_DIP_CTL);
 173 }
 174
 175 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 176                                   const struct intel_crtc_state *pipe_config)
 177 {
 178         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 179         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 180         u32 val = I915_READ(VIDEO_DIP_CTL);
 181
 182         if ((val & VIDEO_DIP_ENABLE) == 0)
 183                 return false;
 184
 185         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 186                 return false;
 187
 188         return val & (VIDEO_DIP_ENABLE_AVI |
 189                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 190 }
 191
 192 static void ibx_write_infoframe(struct drm_encoder *encoder,
 193                                 const struct intel_crtc_state *crtc_state,
 194                                 enum hdmi_infoframe_type type,
 195                                 const void *frame, ssize_t len)
 196 {
 197         const uint32_t *data = frame;
 198         struct drm_device *dev = encoder->dev;
 199         struct drm_i915_private *dev_priv = to_i915(dev);
 200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 201         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 202         u32 val = I915_READ(reg);
 203         int i;
 204
 205         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 206
 207         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 208         val |= g4x_infoframe_index(type);
 209
 210         val &= ~g4x_infoframe_enable(type);
 211
 212         I915_WRITE(reg, val);
 213
 214         mmiowb();
 215         for (i = 0; i < len; i += 4) {
 216                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 217                 data++;
 218         }
 219         /* Write every possible data byte to force correct ECC calculation. */
 220         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 221                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 222         mmiowb();
 223
 224         val |= g4x_infoframe_enable(type);
 225         val &= ~VIDEO_DIP_FREQ_MASK;
 226         val |= VIDEO_DIP_FREQ_VSYNC;
 227
 228         I915_WRITE(reg, val);
 229         POSTING_READ(reg);
 230 }
 231
 232 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 233                                   const struct intel_crtc_state *pipe_config)
 234 {
 235         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 236         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 237         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 238         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 239         u32 val = I915_READ(reg);
 240
 241         if ((val & VIDEO_DIP_ENABLE) == 0)
 242                 return false;
 243
 244         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 245                 return false;
 246
 247         return val & (VIDEO_DIP_ENABLE_AVI |
 248                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 249                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 250 }
 251
 252 static void cpt_write_infoframe(struct drm_encoder *encoder,
 253                                 const struct intel_crtc_state *crtc_state,
 254                                 enum hdmi_infoframe_type type,
 255                                 const void *frame, ssize_t len)
 256 {
 257         const uint32_t *data = frame;
 258         struct drm_device *dev = encoder->dev;
 259         struct drm_i915_private *dev_priv = to_i915(dev);
 260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 261         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 262         u32 val = I915_READ(reg);
 263         int i;
 264
 265         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 266
 267         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 268         val |= g4x_infoframe_index(type);
 269
 270         /* The DIP control register spec says that we need to update the AVI
 271          * infoframe without clearing its enable bit */
 272         if (type != HDMI_INFOFRAME_TYPE_AVI)
 273                 val &= ~g4x_infoframe_enable(type);
 274
 275         I915_WRITE(reg, val);
 276
 277         mmiowb();
 278         for (i = 0; i < len; i += 4) {
 279                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 280                 data++;
 281         }
 282         /* Write every possible data byte to force correct ECC calculation. */
 283         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 284                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 285         mmiowb();
 286
 287         val |= g4x_infoframe_enable(type);
 288         val &= ~VIDEO_DIP_FREQ_MASK;
 289         val |= VIDEO_DIP_FREQ_VSYNC;
 290
 291         I915_WRITE(reg, val);
 292         POSTING_READ(reg);
 293 }
 294
 295 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 296                                   const struct intel_crtc_state *pipe_config)
 297 {
 298         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 299         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 300         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 301
 302         if ((val & VIDEO_DIP_ENABLE) == 0)
 303                 return false;
 304
 305         return val & (VIDEO_DIP_ENABLE_AVI |
 306                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 307                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 308 }
 309
 310 static void vlv_write_infoframe(struct drm_encoder *encoder,
 311                                 const struct intel_crtc_state *crtc_state,
 312                                 enum hdmi_infoframe_type type,
 313                                 const void *frame, ssize_t len)
 314 {
 315         const uint32_t *data = frame;
 316         struct drm_device *dev = encoder->dev;
 317         struct drm_i915_private *dev_priv = to_i915(dev);
 318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 319         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 320         u32 val = I915_READ(reg);
 321         int i;
 322
 323         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 324
 325         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 326         val |= g4x_infoframe_index(type);
 327
 328         val &= ~g4x_infoframe_enable(type);
 329
 330         I915_WRITE(reg, val);
 331
 332         mmiowb();
 333         for (i = 0; i < len; i += 4) {
 334                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 335                 data++;
 336         }
 337         /* Write every possible data byte to force correct ECC calculation. */
 338         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 339                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 340         mmiowb();
 341
 342         val |= g4x_infoframe_enable(type);
 343         val &= ~VIDEO_DIP_FREQ_MASK;
 344         val |= VIDEO_DIP_FREQ_VSYNC;
 345
 346         I915_WRITE(reg, val);
 347         POSTING_READ(reg);
 348 }
 349
 350 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 351                                   const struct intel_crtc_state *pipe_config)
 352 {
 353         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 354         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 355         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 356         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 357
 358         if ((val & VIDEO_DIP_ENABLE) == 0)
 359                 return false;
 360
 361         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 362                 return false;
 363
 364         return val & (VIDEO_DIP_ENABLE_AVI |
 365                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 366                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 367 }
 368
 369 static void hsw_write_infoframe(struct drm_encoder *encoder,
 370                                 const struct intel_crtc_state *crtc_state,
 371                                 enum hdmi_infoframe_type type,
 372                                 const void *frame, ssize_t len)
 373 {
 374         const uint32_t *data = frame;
 375         struct drm_device *dev = encoder->dev;
 376         struct drm_i915_private *dev_priv = to_i915(dev);
 377         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 378         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 379         i915_reg_t data_reg;
 380         int i;
 381         u32 val = I915_READ(ctl_reg);
 382
 383         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 384
 385         val &= ~hsw_infoframe_enable(type);
 386         I915_WRITE(ctl_reg, val);
 387
 388         mmiowb();
 389         for (i = 0; i < len; i += 4) {
 390                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 391                                             type, i >> 2), *data);
 392                 data++;
 393         }
 394         /* Write every possible data byte to force correct ECC calculation. */
 395         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 396                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 397                                             type, i >> 2), 0);
 398         mmiowb();
 399
 400         val |= hsw_infoframe_enable(type);
 401         I915_WRITE(ctl_reg, val);
 402         POSTING_READ(ctl_reg);
 403 }
 404
 405 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 406                                   const struct intel_crtc_state *pipe_config)
 407 {
 408         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 409         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 410
 411         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 412                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 413                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 414 }
 415
 416 /*
 417  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 418  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 419  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 420  * used for both technologies.
 421  *
 422  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 423  * DW1:       DB3       | DB2 | DB1 | DB0
 424  * DW2:       DB7       | DB6 | DB5 | DB4
 425  * DW3: ...
 426  *
 427  * (HB is Header Byte, DB is Data Byte)
 428  *
 429  * The hdmi pack() functions don't know about that hardware specific hole so we
 430  * trick them by giving an offset into the buffer and moving back the header
 431  * bytes by one.
 432  */
 433 static void intel_write_infoframe(struct drm_encoder *encoder,
 434                                   const struct intel_crtc_state *crtc_state,
 435                                   union hdmi_infoframe *frame)
 436 {
 437         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 438         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 439         ssize_t len;
 440
 441         /* see comment above for the reason for this offset */
 442         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 443         if (len < 0)
 444                 return;
 445
 446         /* Insert the 'hole' (see big comment above) at position 3 */
 447         buffer[0] = buffer[1];
 448         buffer[1] = buffer[2];
 449         buffer[2] = buffer[3];
 450         buffer[3] = 0;
 451         len++;
 452
 453         intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
 454 }
 455
 456 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 457                                          const struct intel_crtc_state *crtc_state)
 458 {
 459         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 460         const struct drm_display_mode *adjusted_mode =
 461                 &crtc_state->base.adjusted_mode;
 462         union hdmi_infoframe frame;
 463         int ret;
 464
 465         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 466                                                        adjusted_mode);
 467         if (ret < 0) {
 468                 DRM_ERROR("couldn't fill AVI infoframe\n");
 469                 return;
 470         }
 471
 472         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 473                                            crtc_state->limited_color_range ?
 474                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 475                                            HDMI_QUANTIZATION_RANGE_FULL,
 476                                            intel_hdmi->rgb_quant_range_selectable);
 477
 478         intel_write_infoframe(encoder, crtc_state, &frame);
 479 }
 480
 481 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
 482                                          const struct intel_crtc_state *crtc_state)
 483 {
 484         union hdmi_infoframe frame;
 485         int ret;
 486
 487         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 488         if (ret < 0) {
 489                 DRM_ERROR("couldn't fill SPD infoframe\n");
 490                 return;
 491         }
 492
 493         frame.spd.sdi = HDMI_SPD_SDI_PC;
 494
 495         intel_write_infoframe(encoder, crtc_state, &frame);
 496 }
 497
 498 static void
 499 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 500                               const struct intel_crtc_state *crtc_state)
 501 {
 502         union hdmi_infoframe frame;
 503         int ret;
 504
 505         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 506                                                           &crtc_state->base.adjusted_mode);
 507         if (ret < 0)
 508                 return;
 509
 510         intel_write_infoframe(encoder, crtc_state, &frame);
 511 }
 512
 513 static void g4x_set_infoframes(struct drm_encoder *encoder,
 514                                bool enable,
 515                                const struct intel_crtc_state *crtc_state,
 516                                const struct drm_connector_state *conn_state)
 517 {
 518         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 519         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 520         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 521         i915_reg_t reg = VIDEO_DIP_CTL;
 522         u32 val = I915_READ(reg);
 523         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 524
 525         assert_hdmi_port_disabled(intel_hdmi);
 526
 527         /* If the registers were not initialized yet, they might be zeroes,
 528          * which means we're selecting the AVI DIP and we're setting its
 529          * frequency to once. This seems to really confuse the HW and make
 530          * things stop working (the register spec says the AVI always needs to
 531          * be sent every VSync). So here we avoid writing to the register more
 532          * than we need and also explicitly select the AVI DIP and explicitly
 533          * set its frequency to every VSync. Avoiding to write it twice seems to
 534          * be enough to solve the problem, but being defensive shouldn't hurt us
 535          * either. */
 536         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 537
 538         if (!enable) {
 539                 if (!(val & VIDEO_DIP_ENABLE))
 540                         return;
 541                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 542                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 543                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 544                         return;
 545                 }
 546                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 547                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 548                 I915_WRITE(reg, val);
 549                 POSTING_READ(reg);
 550                 return;
 551         }
 552
 553         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 554                 if (val & VIDEO_DIP_ENABLE) {
 555                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 556                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 557                         return;
 558                 }
 559                 val &= ~VIDEO_DIP_PORT_MASK;
 560                 val |= port;
 561         }
 562
 563         val |= VIDEO_DIP_ENABLE;
 564         val &= ~(VIDEO_DIP_ENABLE_AVI |
 565                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 566
 567         I915_WRITE(reg, val);
 568         POSTING_READ(reg);
 569
 570         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 571         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 572         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 573 }
 574
 575 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 576 {
 577         struct drm_connector *connector = conn_state->connector;
 578
 579         /*
 580          * HDMI cloning is only supported on g4x which doesn't
 581          * support deep color or GCP infoframes anyway so no
 582          * need to worry about multiple HDMI sinks here.
 583          */
 584
 585         return connector->display_info.bpc > 8;
 586 }
 587
 588 /*
 589  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 590  *
 591  * From HDMI specification 1.4a:
 592  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 593  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 594  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 595  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 596  *   phase of 0
 597  */
 598 static bool gcp_default_phase_possible(int pipe_bpp,
 599                                        const struct drm_display_mode *mode)
 600 {
 601         unsigned int pixels_per_group;
 602
 603         switch (pipe_bpp) {
 604         case 30:
 605                 /* 4 pixels in 5 clocks */
 606                 pixels_per_group = 4;
 607                 break;
 608         case 36:
 609                 /* 2 pixels in 3 clocks */
 610                 pixels_per_group = 2;
 611                 break;
 612         case 48:
 613                 /* 1 pixel in 2 clocks */
 614                 pixels_per_group = 1;
 615                 break;
 616         default:
 617                 /* phase information not relevant for 8bpc */
 618                 return false;
 619         }
 620
 621         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 622                 mode->crtc_htotal % pixels_per_group == 0 &&
 623                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 624                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 625                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 626                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 627                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 628                  mode->crtc_htotal/2 % pixels_per_group == 0);
 629 }
 630
 631 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
 632                                          const struct intel_crtc_state *crtc_state,
 633                                          const struct drm_connector_state *conn_state)
 634 {
 635         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 636         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 637         i915_reg_t reg;
 638         u32 val = 0;
 639
 640         if (HAS_DDI(dev_priv))
 641                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 642         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 643                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 644         else if (HAS_PCH_SPLIT(dev_priv))
 645                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 646         else
 647                 return false;
 648
 649         /* Indicate color depth whenever the sink supports deep color */
 650         if (hdmi_sink_is_deep_color(conn_state))
 651                 val |= GCP_COLOR_INDICATION;
 652
 653         /* Enable default_phase whenever the display mode is suitably aligned */
 654         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 655                                        &crtc_state->base.adjusted_mode))
 656                 val |= GCP_DEFAULT_PHASE_ENABLE;
 657
 658         I915_WRITE(reg, val);
 659
 660         return val != 0;
 661 }
 662
 663 static void ibx_set_infoframes(struct drm_encoder *encoder,
 664                                bool enable,
 665                                const struct intel_crtc_state *crtc_state,
 666                                const struct drm_connector_state *conn_state)
 667 {
 668         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 670         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 671         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 672         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 673         u32 val = I915_READ(reg);
 674         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 675
 676         assert_hdmi_port_disabled(intel_hdmi);
 677
 678         /* See the big comment in g4x_set_infoframes() */
 679         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 680
 681         if (!enable) {
 682                 if (!(val & VIDEO_DIP_ENABLE))
 683                         return;
 684                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 685                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 686                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 687                 I915_WRITE(reg, val);
 688                 POSTING_READ(reg);
 689                 return;
 690         }
 691
 692         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 693                 WARN(val & VIDEO_DIP_ENABLE,
 694                      "DIP already enabled on port %c\n",
 695                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 696                 val &= ~VIDEO_DIP_PORT_MASK;
 697                 val |= port;
 698         }
 699
 700         val |= VIDEO_DIP_ENABLE;
 701         val &= ~(VIDEO_DIP_ENABLE_AVI |
 702                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 703                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 704
 705         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 706                 val |= VIDEO_DIP_ENABLE_GCP;
 707
 708         I915_WRITE(reg, val);
 709         POSTING_READ(reg);
 710
 711         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 712         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 713         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 714 }
 715
 716 static void cpt_set_infoframes(struct drm_encoder *encoder,
 717                                bool enable,
 718                                const struct intel_crtc_state *crtc_state,
 719                                const struct drm_connector_state *conn_state)
 720 {
 721         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 723         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 724         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 725         u32 val = I915_READ(reg);
 726
 727         assert_hdmi_port_disabled(intel_hdmi);
 728
 729         /* See the big comment in g4x_set_infoframes() */
 730         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 731
 732         if (!enable) {
 733                 if (!(val & VIDEO_DIP_ENABLE))
 734                         return;
 735                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 736                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 737                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 738                 I915_WRITE(reg, val);
 739                 POSTING_READ(reg);
 740                 return;
 741         }
 742
 743         /* Set both together, unset both together: see the spec. */
 744         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 745         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 746                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 747
 748         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 749                 val |= VIDEO_DIP_ENABLE_GCP;
 750
 751         I915_WRITE(reg, val);
 752         POSTING_READ(reg);
 753
 754         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 755         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 756         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 757 }
 758
 759 static void vlv_set_infoframes(struct drm_encoder *encoder,
 760                                bool enable,
 761                                const struct intel_crtc_state *crtc_state,
 762                                const struct drm_connector_state *conn_state)
 763 {
 764         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 765         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 767         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 768         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 769         u32 val = I915_READ(reg);
 770         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 771
 772         assert_hdmi_port_disabled(intel_hdmi);
 773
 774         /* See the big comment in g4x_set_infoframes() */
 775         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 776
 777         if (!enable) {
 778                 if (!(val & VIDEO_DIP_ENABLE))
 779                         return;
 780                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 781                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 782                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 783                 I915_WRITE(reg, val);
 784                 POSTING_READ(reg);
 785                 return;
 786         }
 787
 788         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 789                 WARN(val & VIDEO_DIP_ENABLE,
 790                      "DIP already enabled on port %c\n",
 791                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 792                 val &= ~VIDEO_DIP_PORT_MASK;
 793                 val |= port;
 794         }
 795
 796         val |= VIDEO_DIP_ENABLE;
 797         val &= ~(VIDEO_DIP_ENABLE_AVI |
 798                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 799                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 800
 801         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 802                 val |= VIDEO_DIP_ENABLE_GCP;
 803
 804         I915_WRITE(reg, val);
 805         POSTING_READ(reg);
 806
 807         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 808         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 809         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 810 }
 811
 812 static void hsw_set_infoframes(struct drm_encoder *encoder,
 813                                bool enable,
 814                                const struct intel_crtc_state *crtc_state,
 815                                const struct drm_connector_state *conn_state)
 816 {
 817         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 818         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 819         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 820         u32 val = I915_READ(reg);
 821
 822         assert_hdmi_port_disabled(intel_hdmi);
 823
 824         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 825                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 826                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 827
 828         if (!enable) {
 829                 I915_WRITE(reg, val);
 830                 POSTING_READ(reg);
 831                 return;
 832         }
 833
 834         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 835                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 836
 837         I915_WRITE(reg, val);
 838         POSTING_READ(reg);
 839
 840         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 841         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 842         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 843 }
 844
 845 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 846 {
 847         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 848         struct i2c_adapter *adapter =
 849                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 850
 851         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 852                 return;
 853
 854         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 855                       enable ? "Enabling" : "Disabling");
 856
 857         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 858                                          adapter, enable);
 859 }
 860
 861 static void intel_hdmi_prepare(struct intel_encoder *encoder,
 862                                const struct intel_crtc_state *crtc_state)
 863 {
 864         struct drm_device *dev = encoder->base.dev;
 865         struct drm_i915_private *dev_priv = to_i915(dev);
 866         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 867         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 868         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 869         u32 hdmi_val;
 870
 871         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 872
 873         hdmi_val = SDVO_ENCODING_HDMI;
 874         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 875                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 876         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 877                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 878         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 879                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 880
 881         if (crtc_state->pipe_bpp > 24)
 882                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 883         else
 884                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 885
 886         if (crtc_state->has_hdmi_sink)
 887                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 888
 889         if (HAS_PCH_CPT(dev_priv))
 890                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 891         else if (IS_CHERRYVIEW(dev_priv))
 892                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 893         else
 894                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 895
 896         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 897         POSTING_READ(intel_hdmi->hdmi_reg);
 898 }
 899
 900 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 901                                     enum pipe *pipe)
 902 {
 903         struct drm_device *dev = encoder->base.dev;
 904         struct drm_i915_private *dev_priv = to_i915(dev);
 905         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 906         u32 tmp;
 907         bool ret;
 908
 909         if (!intel_display_power_get_if_enabled(dev_priv,
 910                                                 encoder->power_domain))
 911                 return false;
 912
 913         ret = false;
 914
 915         tmp = I915_READ(intel_hdmi->hdmi_reg);
 916
 917         if (!(tmp & SDVO_ENABLE))
 918                 goto out;
 919
 920         if (HAS_PCH_CPT(dev_priv))
 921                 *pipe = PORT_TO_PIPE_CPT(tmp);
 922         else if (IS_CHERRYVIEW(dev_priv))
 923                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 924         else
 925                 *pipe = PORT_TO_PIPE(tmp);
 926
 927         ret = true;
 928
 929 out:
 930         intel_display_power_put(dev_priv, encoder->power_domain);
 931
 932         return ret;
 933 }
 934
 935 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 936                                   struct intel_crtc_state *pipe_config)
 937 {
 938         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 939         struct drm_device *dev = encoder->base.dev;
 940         struct drm_i915_private *dev_priv = to_i915(dev);
 941         u32 tmp, flags = 0;
 942         int dotclock;
 943
 944         tmp = I915_READ(intel_hdmi->hdmi_reg);
 945
 946         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 947                 flags |= DRM_MODE_FLAG_PHSYNC;
 948         else
 949                 flags |= DRM_MODE_FLAG_NHSYNC;
 950
 951         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 952                 flags |= DRM_MODE_FLAG_PVSYNC;
 953         else
 954                 flags |= DRM_MODE_FLAG_NVSYNC;
 955
 956         if (tmp & HDMI_MODE_SELECT_HDMI)
 957                 pipe_config->has_hdmi_sink = true;
 958
 959         if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
 960                 pipe_config->has_infoframe = true;
 961
 962         if (tmp & SDVO_AUDIO_ENABLE)
 963                 pipe_config->has_audio = true;
 964
 965         if (!HAS_PCH_SPLIT(dev_priv) &&
 966             tmp & HDMI_COLOR_RANGE_16_235)
 967                 pipe_config->limited_color_range = true;
 968
 969         pipe_config->base.adjusted_mode.flags |= flags;
 970
 971         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 972                 dotclock = pipe_config->port_clock * 2 / 3;
 973         else
 974                 dotclock = pipe_config->port_clock;
 975
 976         if (pipe_config->pixel_multiplier)
 977                 dotclock /= pipe_config->pixel_multiplier;
 978
 979         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 980
 981         pipe_config->lane_count = 4;
 982 }
 983
 984 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 985                                     struct intel_crtc_state *pipe_config,
 986                                     struct drm_connector_state *conn_state)
 987 {
 988         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 989
 990         WARN_ON(!pipe_config->has_hdmi_sink);
 991         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 992                          pipe_name(crtc->pipe));
 993         intel_audio_codec_enable(encoder, pipe_config, conn_state);
 994 }
 995
 996 static void g4x_enable_hdmi(struct intel_encoder *encoder,
 997                             struct intel_crtc_state *pipe_config,
 998                             struct drm_connector_state *conn_state)
 999 {
1000         struct drm_device *dev = encoder->base.dev;
1001         struct drm_i915_private *dev_priv = to_i915(dev);
1002         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1003         u32 temp;
1004
1005         temp = I915_READ(intel_hdmi->hdmi_reg);
1006
1007         temp |= SDVO_ENABLE;
1008         if (pipe_config->has_audio)
1009                 temp |= SDVO_AUDIO_ENABLE;
1010
1011         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1012         POSTING_READ(intel_hdmi->hdmi_reg);
1013
1014         if (pipe_config->has_audio)
1015                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1016 }
1017
1018 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1019                             struct intel_crtc_state *pipe_config,
1020                             struct drm_connector_state *conn_state)
1021 {
1022         struct drm_device *dev = encoder->base.dev;
1023         struct drm_i915_private *dev_priv = to_i915(dev);
1024         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1025         u32 temp;
1026
1027         temp = I915_READ(intel_hdmi->hdmi_reg);
1028
1029         temp |= SDVO_ENABLE;
1030         if (pipe_config->has_audio)
1031                 temp |= SDVO_AUDIO_ENABLE;
1032
1033         /*
1034          * HW workaround, need to write this twice for issue
1035          * that may result in first write getting masked.
1036          */
1037         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1038         POSTING_READ(intel_hdmi->hdmi_reg);
1039         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1040         POSTING_READ(intel_hdmi->hdmi_reg);
1041
1042         /*
1043          * HW workaround, need to toggle enable bit off and on
1044          * for 12bpc with pixel repeat.
1045          *
1046          * FIXME: BSpec says this should be done at the end of
1047          * of the modeset sequence, so not sure if this isn't too soon.
1048          */
1049         if (pipe_config->pipe_bpp > 24 &&
1050             pipe_config->pixel_multiplier > 1) {
1051                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1052                 POSTING_READ(intel_hdmi->hdmi_reg);
1053
1054                 /*
1055                  * HW workaround, need to write this twice for issue
1056                  * that may result in first write getting masked.
1057                  */
1058                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1059                 POSTING_READ(intel_hdmi->hdmi_reg);
1060                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1061                 POSTING_READ(intel_hdmi->hdmi_reg);
1062         }
1063
1064         if (pipe_config->has_audio)
1065                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1066 }
1067
1068 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1069                             struct intel_crtc_state *pipe_config,
1070                             struct drm_connector_state *conn_state)
1071 {
1072         struct drm_device *dev = encoder->base.dev;
1073         struct drm_i915_private *dev_priv = to_i915(dev);
1074         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1075         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1076         enum pipe pipe = crtc->pipe;
1077         u32 temp;
1078
1079         temp = I915_READ(intel_hdmi->hdmi_reg);
1080
1081         temp |= SDVO_ENABLE;
1082         if (pipe_config->has_audio)
1083                 temp |= SDVO_AUDIO_ENABLE;
1084
1085         /*
1086          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1087          *
1088          * The procedure for 12bpc is as follows:
1089          * 1. disable HDMI clock gating
1090          * 2. enable HDMI with 8bpc
1091          * 3. enable HDMI with 12bpc
1092          * 4. enable HDMI clock gating
1093          */
1094
1095         if (pipe_config->pipe_bpp > 24) {
1096                 I915_WRITE(TRANS_CHICKEN1(pipe),
1097                            I915_READ(TRANS_CHICKEN1(pipe)) |
1098                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1099
1100                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1101                 temp |= SDVO_COLOR_FORMAT_8bpc;
1102         }
1103
1104         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1105         POSTING_READ(intel_hdmi->hdmi_reg);
1106
1107         if (pipe_config->pipe_bpp > 24) {
1108                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1109                 temp |= HDMI_COLOR_FORMAT_12bpc;
1110
1111                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1112                 POSTING_READ(intel_hdmi->hdmi_reg);
1113
1114                 I915_WRITE(TRANS_CHICKEN1(pipe),
1115                            I915_READ(TRANS_CHICKEN1(pipe)) &
1116                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1117         }
1118
1119         if (pipe_config->has_audio)
1120                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1121 }
1122
1123 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1124                             struct intel_crtc_state *pipe_config,
1125                             struct drm_connector_state *conn_state)
1126 {
1127 }
1128
1129 static void intel_disable_hdmi(struct intel_encoder *encoder,
1130                                struct intel_crtc_state *old_crtc_state,
1131                                struct drm_connector_state *old_conn_state)
1132 {
1133         struct drm_device *dev = encoder->base.dev;
1134         struct drm_i915_private *dev_priv = to_i915(dev);
1135         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1136         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1137         u32 temp;
1138
1139         temp = I915_READ(intel_hdmi->hdmi_reg);
1140
1141         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1142         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1143         POSTING_READ(intel_hdmi->hdmi_reg);
1144
1145         /*
1146          * HW workaround for IBX, we need to move the port
1147          * to transcoder A after disabling it to allow the
1148          * matching DP port to be enabled on transcoder A.
1149          */
1150         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1151                 /*
1152                  * We get CPU/PCH FIFO underruns on the other pipe when
1153                  * doing the workaround. Sweep them under the rug.
1154                  */
1155                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1156                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1157
1158                 temp &= ~SDVO_PIPE_B_SELECT;
1159                 temp |= SDVO_ENABLE;
1160                 /*
1161                  * HW workaround, need to write this twice for issue
1162                  * that may result in first write getting masked.
1163                  */
1164                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1165                 POSTING_READ(intel_hdmi->hdmi_reg);
1166                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1167                 POSTING_READ(intel_hdmi->hdmi_reg);
1168
1169                 temp &= ~SDVO_ENABLE;
1170                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1171                 POSTING_READ(intel_hdmi->hdmi_reg);
1172
1173                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1174                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1175                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1176         }
1177
1178         intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
1179
1180         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1181 }
1182
1183 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1184                              struct intel_crtc_state *old_crtc_state,
1185                              struct drm_connector_state *old_conn_state)
1186 {
1187         if (old_crtc_state->has_audio)
1188                 intel_audio_codec_disable(encoder);
1189
1190         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1191 }
1192
1193 static void pch_disable_hdmi(struct intel_encoder *encoder,
1194                              struct intel_crtc_state *old_crtc_state,
1195                              struct drm_connector_state *old_conn_state)
1196 {
1197         if (old_crtc_state->has_audio)
1198                 intel_audio_codec_disable(encoder);
1199 }
1200
1201 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1202                                   struct intel_crtc_state *old_crtc_state,
1203                                   struct drm_connector_state *old_conn_state)
1204 {
1205         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1206 }
1207
1208 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1209 {
1210         if (IS_G4X(dev_priv))
1211                 return 165000;
1212         else if (IS_GEMINILAKE(dev_priv))
1213                 return 594000;
1214         else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1215                 return 300000;
1216         else
1217                 return 225000;
1218 }
1219
1220 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1221                                  bool respect_downstream_limits,
1222                                  bool force_dvi)
1223 {
1224         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1225         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1226
1227         if (respect_downstream_limits) {
1228                 struct intel_connector *connector = hdmi->attached_connector;
1229                 const struct drm_display_info *info = &connector->base.display_info;
1230
1231                 if (hdmi->dp_dual_mode.max_tmds_clock)
1232                         max_tmds_clock = min(max_tmds_clock,
1233                                              hdmi->dp_dual_mode.max_tmds_clock);
1234
1235                 if (info->max_tmds_clock)
1236                         max_tmds_clock = min(max_tmds_clock,
1237                                              info->max_tmds_clock);
1238                 else if (!hdmi->has_hdmi_sink || force_dvi)
1239                         max_tmds_clock = min(max_tmds_clock, 165000);
1240         }
1241
1242         return max_tmds_clock;
1243 }
1244
1245 static enum drm_mode_status
1246 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1247                       int clock, bool respect_downstream_limits,
1248                       bool force_dvi)
1249 {
1250         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1251
1252         if (clock < 25000)
1253                 return MODE_CLOCK_LOW;
1254         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1255                 return MODE_CLOCK_HIGH;
1256
1257         /* BXT DPLL can't generate 223-240 MHz */
1258         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1259                 return MODE_CLOCK_RANGE;
1260
1261         /* CHV DPLL can't generate 216-240 MHz */
1262         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1263                 return MODE_CLOCK_RANGE;
1264
1265         return MODE_OK;
1266 }
1267
1268 static enum drm_mode_status
1269 intel_hdmi_mode_valid(struct drm_connector *connector,
1270                       struct drm_display_mode *mode)
1271 {
1272         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1273         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1274         struct drm_i915_private *dev_priv = to_i915(dev);
1275         enum drm_mode_status status;
1276         int clock;
1277         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1278         bool force_dvi =
1279                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1280
1281         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1282                 return MODE_NO_DBLESCAN;
1283
1284         clock = mode->clock;
1285
1286         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1287                 clock *= 2;
1288
1289         if (clock > max_dotclk)
1290                 return MODE_CLOCK_HIGH;
1291
1292         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1293                 clock *= 2;
1294
1295         /* check if we can do 8bpc */
1296         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1297
1298         /* if we can't do 8bpc we may still be able to do 12bpc */
1299         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1300                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1301
1302         return status;
1303 }
1304
1305 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1306 {
1307         struct drm_i915_private *dev_priv =
1308                 to_i915(crtc_state->base.crtc->dev);
1309         struct drm_atomic_state *state = crtc_state->base.state;
1310         struct drm_connector_state *connector_state;
1311         struct drm_connector *connector;
1312         int i;
1313
1314         if (HAS_GMCH_DISPLAY(dev_priv))
1315                 return false;
1316
1317         /*
1318          * HDMI 12bpc affects the clocks, so it's only possible
1319          * when not cloning with other encoder types.
1320          */
1321         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1322                 return false;
1323
1324         for_each_connector_in_state(state, connector, connector_state, i) {
1325                 const struct drm_display_info *info = &connector->display_info;
1326
1327                 if (connector_state->crtc != crtc_state->base.crtc)
1328                         continue;
1329
1330                 if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0)
1331                         return false;
1332         }
1333
1334         /* Display Wa #1139 */
1335         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1336             crtc_state->base.adjusted_mode.htotal > 5460)
1337                 return false;
1338
1339         return true;
1340 }
1341
1342 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1343                                struct intel_crtc_state *pipe_config,
1344                                struct drm_connector_state *conn_state)
1345 {
1346         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1347         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1348         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1349         struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc;
1350         struct intel_digital_connector_state *intel_conn_state =
1351                 to_intel_digital_connector_state(conn_state);
1352         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1353         int clock_12bpc = clock_8bpc * 3 / 2;
1354         int desired_bpp;
1355         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1356
1357         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1358
1359         if (pipe_config->has_hdmi_sink)
1360                 pipe_config->has_infoframe = true;
1361
1362         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1363                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1364                 pipe_config->limited_color_range =
1365                         pipe_config->has_hdmi_sink &&
1366                         drm_default_rgb_quant_range(adjusted_mode) ==
1367                         HDMI_QUANTIZATION_RANGE_LIMITED;
1368         } else {
1369                 pipe_config->limited_color_range =
1370                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1371         }
1372
1373         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1374                 pipe_config->pixel_multiplier = 2;
1375                 clock_8bpc *= 2;
1376                 clock_12bpc *= 2;
1377         }
1378
1379         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1380                 pipe_config->has_pch_encoder = true;
1381
1382         if (pipe_config->has_hdmi_sink) {
1383                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1384                         pipe_config->has_audio = intel_hdmi->has_audio;
1385                 else
1386                         pipe_config->has_audio =
1387                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1388         }
1389
1390         /*
1391          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1392          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1393          * outputs. We also need to check that the higher clock still fits
1394          * within limits.
1395          */
1396         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi &&
1397             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK &&
1398             hdmi_12bpc_possible(pipe_config)) {
1399                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1400                 desired_bpp = 12*3;
1401
1402                 /* Need to adjust the port link by 1.5x for 12bpc. */
1403                 pipe_config->port_clock = clock_12bpc;
1404         } else {
1405                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1406                 desired_bpp = 8*3;
1407
1408                 pipe_config->port_clock = clock_8bpc;
1409         }
1410
1411         if (!pipe_config->bw_constrained) {
1412                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1413                 pipe_config->pipe_bpp = desired_bpp;
1414         }
1415
1416         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1417                                   false, force_dvi) != MODE_OK) {
1418                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1419                 return false;
1420         }
1421
1422         /* Set user selected PAR to incoming mode's member */
1423         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1424
1425         pipe_config->lane_count = 4;
1426
1427         if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
1428                 if (scdc->scrambling.low_rates)
1429                         pipe_config->hdmi_scrambling = true;
1430
1431                 if (pipe_config->port_clock > 340000) {
1432                         pipe_config->hdmi_scrambling = true;
1433                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1434                 }
1435         }
1436
1437         return true;
1438 }
1439
1440 static void
1441 intel_hdmi_unset_edid(struct drm_connector *connector)
1442 {
1443         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1444
1445         intel_hdmi->has_hdmi_sink = false;
1446         intel_hdmi->has_audio = false;
1447         intel_hdmi->rgb_quant_range_selectable = false;
1448
1449         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1450         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1451
1452         kfree(to_intel_connector(connector)->detect_edid);
1453         to_intel_connector(connector)->detect_edid = NULL;
1454 }
1455
1456 static void
1457 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1458 {
1459         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1460         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1461         enum port port = hdmi_to_dig_port(hdmi)->port;
1462         struct i2c_adapter *adapter =
1463                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1464         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1465
1466         /*
1467          * Type 1 DVI adaptors are not required to implement any
1468          * registers, so we can't always detect their presence.
1469          * Ideally we should be able to check the state of the
1470          * CONFIG1 pin, but no such luck on our hardware.
1471          *
1472          * The only method left to us is to check the VBT to see
1473          * if the port is a dual mode capable DP port. But let's
1474          * only do that when we sucesfully read the EDID, to avoid
1475          * confusing log messages about DP dual mode adaptors when
1476          * there's nothing connected to the port.
1477          */
1478         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1479                 if (has_edid &&
1480                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1481                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1482                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1483                 } else {
1484                         type = DRM_DP_DUAL_MODE_NONE;
1485                 }
1486         }
1487
1488         if (type == DRM_DP_DUAL_MODE_NONE)
1489                 return;
1490
1491         hdmi->dp_dual_mode.type = type;
1492         hdmi->dp_dual_mode.max_tmds_clock =
1493                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1494
1495         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1496                       drm_dp_get_dual_mode_type_name(type),
1497                       hdmi->dp_dual_mode.max_tmds_clock);
1498 }
1499
1500 static bool
1501 intel_hdmi_set_edid(struct drm_connector *connector)
1502 {
1503         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1504         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1505         struct edid *edid;
1506         bool connected = false;
1507
1508         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1509
1510         edid = drm_get_edid(connector,
1511                             intel_gmbus_get_adapter(dev_priv,
1512                             intel_hdmi->ddc_bus));
1513
1514         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1515
1516         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1517
1518         to_intel_connector(connector)->detect_edid = edid;
1519         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1520                 intel_hdmi->rgb_quant_range_selectable =
1521                         drm_rgb_quant_range_selectable(edid);
1522
1523                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1524                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1525
1526                 connected = true;
1527         }
1528
1529         return connected;
1530 }
1531
1532 static enum drm_connector_status
1533 intel_hdmi_detect(struct drm_connector *connector, bool force)
1534 {
1535         enum drm_connector_status status;
1536         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1537
1538         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1539                       connector->base.id, connector->name);
1540
1541         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1542
1543         intel_hdmi_unset_edid(connector);
1544
1545         if (intel_hdmi_set_edid(connector)) {
1546                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1547
1548                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1549                 status = connector_status_connected;
1550         } else
1551                 status = connector_status_disconnected;
1552
1553         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1554
1555         return status;
1556 }
1557
1558 static void
1559 intel_hdmi_force(struct drm_connector *connector)
1560 {
1561         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1562
1563         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1564                       connector->base.id, connector->name);
1565
1566         intel_hdmi_unset_edid(connector);
1567
1568         if (connector->status != connector_status_connected)
1569                 return;
1570
1571         intel_hdmi_set_edid(connector);
1572         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1573 }
1574
1575 static int intel_hdmi_get_modes(struct drm_connector *connector)
1576 {
1577         struct edid *edid;
1578
1579         edid = to_intel_connector(connector)->detect_edid;
1580         if (edid == NULL)
1581                 return 0;
1582
1583         return intel_connector_update_modes(connector, edid);
1584 }
1585
1586 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1587                                   struct intel_crtc_state *pipe_config,
1588                                   struct drm_connector_state *conn_state)
1589 {
1590         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1591
1592         intel_hdmi_prepare(encoder, pipe_config);
1593
1594         intel_hdmi->set_infoframes(&encoder->base,
1595                                    pipe_config->has_hdmi_sink,
1596                                    pipe_config, conn_state);
1597 }
1598
1599 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1600                                 struct intel_crtc_state *pipe_config,
1601                                 struct drm_connector_state *conn_state)
1602 {
1603         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1604         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1605         struct drm_device *dev = encoder->base.dev;
1606         struct drm_i915_private *dev_priv = to_i915(dev);
1607
1608         vlv_phy_pre_encoder_enable(encoder);
1609
1610         /* HDMI 1.0V-2dB */
1611         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1612                                  0x2b247878);
1613
1614         intel_hdmi->set_infoframes(&encoder->base,
1615                                    pipe_config->has_hdmi_sink,
1616                                    pipe_config, conn_state);
1617
1618         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1619
1620         vlv_wait_port_ready(dev_priv, dport, 0x0);
1621 }
1622
1623 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1624                                     struct intel_crtc_state *pipe_config,
1625                                     struct drm_connector_state *conn_state)
1626 {
1627         intel_hdmi_prepare(encoder, pipe_config);
1628
1629         vlv_phy_pre_pll_enable(encoder);
1630 }
1631
1632 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1633                                     struct intel_crtc_state *pipe_config,
1634                                     struct drm_connector_state *conn_state)
1635 {
1636         intel_hdmi_prepare(encoder, pipe_config);
1637
1638         chv_phy_pre_pll_enable(encoder);
1639 }
1640
1641 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1642                                       struct intel_crtc_state *old_crtc_state,
1643                                       struct drm_connector_state *old_conn_state)
1644 {
1645         chv_phy_post_pll_disable(encoder);
1646 }
1647
1648 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1649                                   struct intel_crtc_state *old_crtc_state,
1650                                   struct drm_connector_state *old_conn_state)
1651 {
1652         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1653         vlv_phy_reset_lanes(encoder);
1654 }
1655
1656 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1657                                   struct intel_crtc_state *old_crtc_state,
1658                                   struct drm_connector_state *old_conn_state)
1659 {
1660         struct drm_device *dev = encoder->base.dev;
1661         struct drm_i915_private *dev_priv = to_i915(dev);
1662
1663         mutex_lock(&dev_priv->sb_lock);
1664
1665         /* Assert data lane reset */
1666         chv_data_lane_soft_reset(encoder, true);
1667
1668         mutex_unlock(&dev_priv->sb_lock);
1669 }
1670
1671 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1672                                 struct intel_crtc_state *pipe_config,
1673                                 struct drm_connector_state *conn_state)
1674 {
1675         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1676         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1677         struct drm_device *dev = encoder->base.dev;
1678         struct drm_i915_private *dev_priv = to_i915(dev);
1679
1680         chv_phy_pre_encoder_enable(encoder);
1681
1682         /* FIXME: Program the support xxx V-dB */
1683         /* Use 800mV-0dB */
1684         chv_set_phy_signal_level(encoder, 128, 102, false);
1685
1686         intel_hdmi->set_infoframes(&encoder->base,
1687                                    pipe_config->has_hdmi_sink,
1688                                    pipe_config, conn_state);
1689
1690         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1691
1692         vlv_wait_port_ready(dev_priv, dport, 0x0);
1693
1694         /* Second common lane will stay alive on its own now */
1695         chv_phy_release_cl2_override(encoder);
1696 }
1697
1698 static void intel_hdmi_destroy(struct drm_connector *connector)
1699 {
1700         kfree(to_intel_connector(connector)->detect_edid);
1701         drm_connector_cleanup(connector);
1702         kfree(connector);
1703 }
1704
1705 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1706         .dpms = drm_atomic_helper_connector_dpms,
1707         .detect = intel_hdmi_detect,
1708         .force = intel_hdmi_force,
1709         .fill_modes = drm_helper_probe_single_connector_modes,
1710         .set_property = drm_atomic_helper_connector_set_property,
1711         .atomic_get_property = intel_digital_connector_atomic_get_property,
1712         .atomic_set_property = intel_digital_connector_atomic_set_property,
1713         .late_register = intel_connector_register,
1714         .early_unregister = intel_connector_unregister,
1715         .destroy = intel_hdmi_destroy,
1716         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1717         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1718 };
1719
1720 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1721         .get_modes = intel_hdmi_get_modes,
1722         .mode_valid = intel_hdmi_mode_valid,
1723         .atomic_check = intel_digital_connector_atomic_check,
1724 };
1725
1726 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1727         .destroy = intel_encoder_destroy,
1728 };
1729
1730 static void
1731 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1732 {
1733         intel_attach_force_audio_property(connector);
1734         intel_attach_broadcast_rgb_property(connector);
1735         intel_attach_aspect_ratio_property(connector);
1736         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1737 }
1738
1739 /*
1740  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1741  * @encoder: intel_encoder
1742  * @connector: drm_connector
1743  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1744  *  or reset the high tmds clock ratio for scrambling
1745  * @scrambling: bool to Indicate if the function needs to set or reset
1746  *  sink scrambling
1747  *
1748  * This function handles scrambling on HDMI 2.0 capable sinks.
1749  * If required clock rate is > 340 Mhz && scrambling is supported by sink
1750  * it enables scrambling. This should be called before enabling the HDMI
1751  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1752  * detect a scrambled clock within 100 ms.
1753  */
1754 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1755                                        struct drm_connector *connector,
1756                                        bool high_tmds_clock_ratio,
1757                                        bool scrambling)
1758 {
1759         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1760         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1761         struct drm_scrambling *sink_scrambling =
1762                                 &connector->display_info.hdmi.scdc.scrambling;
1763         struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1764                                                            intel_hdmi->ddc_bus);
1765         bool ret;
1766
1767         if (!sink_scrambling->supported)
1768                 return;
1769
1770         DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1771                       encoder->base.name, connector->name);
1772
1773         /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1774         ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1775         if (!ret) {
1776                 DRM_ERROR("Set TMDS ratio failed\n");
1777                 return;
1778         }
1779
1780         /* Enable/disable sink scrambling */
1781         ret = drm_scdc_set_scrambling(adptr, scrambling);
1782         if (!ret) {
1783                 DRM_ERROR("Set sink scrambling failed\n");
1784                 return;
1785         }
1786
1787         DRM_DEBUG_KMS("sink scrambling handled\n");
1788 }
1789
1790 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1791                              enum port port)
1792 {
1793         const struct ddi_vbt_port_info *info =
1794                 &dev_priv->vbt.ddi_port_info[port];
1795         u8 ddc_pin;
1796
1797         if (info->alternate_ddc_pin) {
1798                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1799                               info->alternate_ddc_pin, port_name(port));
1800                 return info->alternate_ddc_pin;
1801         }
1802
1803         switch (port) {
1804         case PORT_B:
1805                 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
1806                         ddc_pin = GMBUS_PIN_1_BXT;
1807                 else
1808                         ddc_pin = GMBUS_PIN_DPB;
1809                 break;
1810         case PORT_C:
1811                 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
1812                         ddc_pin = GMBUS_PIN_2_BXT;
1813                 else
1814                         ddc_pin = GMBUS_PIN_DPC;
1815                 break;
1816         case PORT_D:
1817                 if (HAS_PCH_CNP(dev_priv))
1818                         ddc_pin = GMBUS_PIN_4_CNP;
1819                 else if (IS_CHERRYVIEW(dev_priv))
1820                         ddc_pin = GMBUS_PIN_DPD_CHV;
1821                 else
1822                         ddc_pin = GMBUS_PIN_DPD;
1823                 break;
1824         default:
1825                 MISSING_CASE(port);
1826                 ddc_pin = GMBUS_PIN_DPB;
1827                 break;
1828         }
1829
1830         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1831                       ddc_pin, port_name(port));
1832
1833         return ddc_pin;
1834 }
1835
1836 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1837                                struct intel_connector *intel_connector)
1838 {
1839         struct drm_connector *connector = &intel_connector->base;
1840         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1841         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1842         struct drm_device *dev = intel_encoder->base.dev;
1843         struct drm_i915_private *dev_priv = to_i915(dev);
1844         enum port port = intel_dig_port->port;
1845
1846         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1847                       port_name(port));
1848
1849         if (WARN(intel_dig_port->max_lanes < 4,
1850                  "Not enough lanes (%d) for HDMI on port %c\n",
1851                  intel_dig_port->max_lanes, port_name(port)))
1852                 return;
1853
1854         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1855                            DRM_MODE_CONNECTOR_HDMIA);
1856         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1857
1858         connector->interlace_allowed = 1;
1859         connector->doublescan_allowed = 0;
1860         connector->stereo_allowed = 1;
1861
1862         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
1863
1864         switch (port) {
1865         case PORT_B:
1866                 intel_encoder->hpd_pin = HPD_PORT_B;
1867                 break;
1868         case PORT_C:
1869                 intel_encoder->hpd_pin = HPD_PORT_C;
1870                 break;
1871         case PORT_D:
1872                 intel_encoder->hpd_pin = HPD_PORT_D;
1873                 break;
1874         case PORT_E:
1875                 intel_encoder->hpd_pin = HPD_PORT_E;
1876                 break;
1877         default:
1878                 MISSING_CASE(port);
1879                 return;
1880         }
1881
1882         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1883                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1884                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1885                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1886         } else if (IS_G4X(dev_priv)) {
1887                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1888                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1889                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1890         } else if (HAS_DDI(dev_priv)) {
1891                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1892                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1893                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1894         } else if (HAS_PCH_IBX(dev_priv)) {
1895                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1896                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1897                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1898         } else {
1899                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1900                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1901                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1902         }
1903
1904         if (HAS_DDI(dev_priv))
1905                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1906         else
1907                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1908
1909         intel_hdmi_add_properties(intel_hdmi, connector);
1910
1911         intel_connector_attach_encoder(intel_connector, intel_encoder);
1912         intel_hdmi->attached_connector = intel_connector;
1913
1914         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1915          * 0xd.  Failure to do so will result in spurious interrupts being
1916          * generated on the port when a cable is not attached.
1917          */
1918         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
1919                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1920                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1921         }
1922 }
1923
1924 void intel_hdmi_init(struct drm_i915_private *dev_priv,
1925                      i915_reg_t hdmi_reg, enum port port)
1926 {
1927         struct intel_digital_port *intel_dig_port;
1928         struct intel_encoder *intel_encoder;
1929         struct intel_connector *intel_connector;
1930
1931         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1932         if (!intel_dig_port)
1933                 return;
1934
1935         intel_connector = intel_connector_alloc();
1936         if (!intel_connector) {
1937                 kfree(intel_dig_port);
1938                 return;
1939         }
1940
1941         intel_encoder = &intel_dig_port->base;
1942
1943         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
1944                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
1945                          "HDMI %c", port_name(port));
1946
1947         intel_encoder->compute_config = intel_hdmi_compute_config;
1948         if (HAS_PCH_SPLIT(dev_priv)) {
1949                 intel_encoder->disable = pch_disable_hdmi;
1950                 intel_encoder->post_disable = pch_post_disable_hdmi;
1951         } else {
1952                 intel_encoder->disable = g4x_disable_hdmi;
1953         }
1954         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1955         intel_encoder->get_config = intel_hdmi_get_config;
1956         if (IS_CHERRYVIEW(dev_priv)) {
1957                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1958                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1959                 intel_encoder->enable = vlv_enable_hdmi;
1960                 intel_encoder->post_disable = chv_hdmi_post_disable;
1961                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
1962         } else if (IS_VALLEYVIEW(dev_priv)) {
1963                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1964                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1965                 intel_encoder->enable = vlv_enable_hdmi;
1966                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1967         } else {
1968                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1969                 if (HAS_PCH_CPT(dev_priv))
1970                         intel_encoder->enable = cpt_enable_hdmi;
1971                 else if (HAS_PCH_IBX(dev_priv))
1972                         intel_encoder->enable = ibx_enable_hdmi;
1973                 else
1974                         intel_encoder->enable = g4x_enable_hdmi;
1975         }
1976
1977         intel_encoder->type = INTEL_OUTPUT_HDMI;
1978         intel_encoder->power_domain = intel_port_to_power_domain(port);
1979         intel_encoder->port = port;
1980         if (IS_CHERRYVIEW(dev_priv)) {
1981                 if (port == PORT_D)
1982                         intel_encoder->crtc_mask = 1 << 2;
1983                 else
1984                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1985         } else {
1986                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1987         }
1988         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1989         /*
1990          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1991          * to work on real hardware. And since g4x can send infoframes to
1992          * only one port anyway, nothing is lost by allowing it.
1993          */
1994         if (IS_G4X(dev_priv))
1995                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1996
1997         intel_dig_port->port = port;
1998         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1999         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2000         intel_dig_port->max_lanes = 4;
2001
2002         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2003 }