2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
30 #include "intel_guc_fw.h"
33 #define __MAKE_GUC_FW_PATH(KEY) \
35 __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
36 __stringify(KEY##_GUC_FW_MAJOR) "." \
37 __stringify(KEY##_GUC_FW_MINOR) "." \
38 __stringify(KEY##_GUC_FW_PATCH) ".bin"
40 #define SKL_GUC_FW_PREFIX skl
41 #define SKL_GUC_FW_MAJOR 33
42 #define SKL_GUC_FW_MINOR 0
43 #define SKL_GUC_FW_PATCH 0
44 #define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
45 MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
47 #define BXT_GUC_FW_PREFIX bxt
48 #define BXT_GUC_FW_MAJOR 33
49 #define BXT_GUC_FW_MINOR 0
50 #define BXT_GUC_FW_PATCH 0
51 #define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
52 MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
54 #define KBL_GUC_FW_PREFIX kbl
55 #define KBL_GUC_FW_MAJOR 33
56 #define KBL_GUC_FW_MINOR 0
57 #define KBL_GUC_FW_PATCH 0
58 #define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
59 MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
61 #define GLK_GUC_FW_PREFIX glk
62 #define GLK_GUC_FW_MAJOR 33
63 #define GLK_GUC_FW_MINOR 0
64 #define GLK_GUC_FW_PATCH 0
65 #define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
66 MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
68 #define ICL_GUC_FW_PREFIX icl
69 #define ICL_GUC_FW_MAJOR 33
70 #define ICL_GUC_FW_MINOR 0
71 #define ICL_GUC_FW_PATCH 0
72 #define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
73 MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
75 static void guc_fw_select(struct intel_uc_fw *guc_fw)
77 struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
78 struct drm_i915_private *i915 = guc_to_i915(guc);
80 GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
85 if (i915_modparams.guc_firmware_path) {
86 guc_fw->path = i915_modparams.guc_firmware_path;
87 guc_fw->major_ver_wanted = 0;
88 guc_fw->minor_ver_wanted = 0;
89 } else if (IS_ICELAKE(i915)) {
90 guc_fw->path = ICL_GUC_FIRMWARE_PATH;
91 guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
92 guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
93 } else if (IS_GEMINILAKE(i915)) {
94 guc_fw->path = GLK_GUC_FIRMWARE_PATH;
95 guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
96 guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
97 } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
98 guc_fw->path = KBL_GUC_FIRMWARE_PATH;
99 guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
100 guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
101 } else if (IS_BROXTON(i915)) {
102 guc_fw->path = BXT_GUC_FIRMWARE_PATH;
103 guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
104 guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
105 } else if (IS_SKYLAKE(i915)) {
106 guc_fw->path = SKL_GUC_FIRMWARE_PATH;
107 guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
108 guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
113 * intel_guc_fw_init_early() - initializes GuC firmware struct
114 * @guc: intel_guc struct
116 * On platforms with GuC selects firmware for uploading
118 void intel_guc_fw_init_early(struct intel_guc *guc)
120 struct intel_uc_fw *guc_fw = &guc->fw;
122 intel_uc_fw_init_early(guc_fw, INTEL_UC_FW_TYPE_GUC);
123 guc_fw_select(guc_fw);
126 static void guc_prepare_xfer(struct intel_guc *guc)
128 struct drm_i915_private *dev_priv = guc_to_i915(guc);
130 /* Must program this register before loading the ucode with DMA */
131 I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
132 GUC_ENABLE_READ_CACHE_LOGIC |
133 GUC_ENABLE_MIA_CACHING |
134 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
135 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
136 GUC_ENABLE_MIA_CLOCK_GATING);
138 if (IS_GEN9_LP(dev_priv))
139 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
141 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
143 if (IS_GEN(dev_priv, 9)) {
144 /* DOP Clock Gating Enable for GuC clocks */
145 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
146 I915_READ(GEN7_MISCCPCTL)));
148 /* allows for 5us (in 10ns units) before GT can go to RC6 */
149 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
153 /* Copy RSA signature from the fw image to HW for verification */
154 static void guc_xfer_rsa(struct intel_guc *guc)
156 struct drm_i915_private *dev_priv = guc_to_i915(guc);
157 struct intel_uc_fw *fw = &guc->fw;
158 struct sg_table *pages = fw->obj->mm.pages;
159 u32 rsa[UOS_RSA_SCRATCH_COUNT];
162 sg_pcopy_to_buffer(pages->sgl, pages->nents,
163 rsa, sizeof(rsa), fw->rsa_offset);
165 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
166 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
169 static bool guc_xfer_completed(struct intel_guc *guc, u32 *status)
171 struct drm_i915_private *dev_priv = guc_to_i915(guc);
173 /* Did we complete the xfer? */
174 *status = I915_READ(DMA_CTRL);
175 return !(*status & START_DMA);
179 * Read the GuC status register (GUC_STATUS) and store it in the
180 * specified location; then return a boolean indicating whether
181 * the value matches either of two values representing completion
182 * of the GuC boot process.
184 * This is used for polling the GuC status in a wait_for()
187 static inline bool guc_ready(struct intel_guc *guc, u32 *status)
189 struct drm_i915_private *dev_priv = guc_to_i915(guc);
190 u32 val = I915_READ(GUC_STATUS);
191 u32 uk_val = val & GS_UKERNEL_MASK;
194 return (uk_val == GS_UKERNEL_READY) ||
195 ((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
198 static int guc_wait_ucode(struct intel_guc *guc)
200 struct drm_i915_private *i915 = guc_to_i915(guc);
205 * Wait for the GuC to start up.
206 * NB: Docs recommend not using the interrupt for completion.
207 * Measurements indicate this should take no more than 20ms, so a
208 * timeout here indicates that the GuC has failed and is unusable.
209 * (Higher levels of the driver may decide to reset the GuC and
210 * attempt the ucode load again if this happens.)
212 ret = wait_for(guc_ready(guc, &status), 100);
213 DRM_DEBUG_DRIVER("GuC status %#x\n", status);
215 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
216 DRM_ERROR("GuC firmware signature verification failed\n");
220 if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
221 DRM_ERROR("GuC firmware exception. EIP: %#x\n",
222 intel_uncore_read(&i915->uncore, SOFT_SCRATCH(13)));
226 if (ret == 0 && !guc_xfer_completed(guc, &status)) {
227 DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
236 * Transfer the firmware image to RAM for execution by the microcontroller.
238 * Architecturally, the DMA engine is bidirectional, and can potentially even
239 * transfer between GTT locations. This functionality is left out of the API
240 * for now as there is no need for it.
242 static int guc_xfer_ucode(struct intel_guc *guc)
244 struct drm_i915_private *dev_priv = guc_to_i915(guc);
245 struct intel_uc_fw *guc_fw = &guc->fw;
246 unsigned long offset;
249 * The header plus uCode will be copied to WOPCM via DMA, excluding any
252 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
254 /* Set the source address for the new blob */
255 offset = intel_uc_fw_ggtt_offset(guc_fw) + guc_fw->header_offset;
256 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
257 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
260 * Set the DMA destination. Current uCode expects the code to be
261 * loaded at 8k; locations below this are used for the stack.
263 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
264 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
266 /* Finally start the DMA */
267 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
269 return guc_wait_ucode(guc);
272 * Load the GuC firmware blob into the MinuteIA.
274 static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
276 struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
277 struct drm_i915_private *dev_priv = guc_to_i915(guc);
280 GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
282 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
284 guc_prepare_xfer(guc);
287 * Note that GuC needs the CSS header plus uKernel code to be copied
288 * by the DMA engine in one operation, whereas the RSA signature is
293 ret = guc_xfer_ucode(guc);
295 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
301 * intel_guc_fw_upload() - load GuC uCode to device
302 * @guc: intel_guc structure
304 * Called from intel_uc_init_hw() during driver load, resume from sleep and
307 * The firmware image should have already been fetched into memory, so only
308 * check that fetch succeeded, and then transfer the image to the h/w.
310 * Return: non-zero code on error
312 int intel_guc_fw_upload(struct intel_guc *guc)
314 return intel_uc_fw_upload(&guc->fw, guc_fw_xfer);