2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include "intel_drv.h"
32 * DOC: fifo underrun handling
34 * The i915 driver checks for display fifo underruns using the interrupt signals
35 * provided by the hardware. This is enabled by default and fairly useful to
36 * debug display issues, especially watermark settings.
38 * If an underrun is detected this is logged into dmesg. To avoid flooding logs
39 * and occupying the cpu underrun interrupts are disabled after the first
40 * occurrence until the next modeset on a given pipe.
42 * Note that underrun detection on gmch platforms is a bit more ugly since there
43 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
44 * interrupt register). Also on some other platforms underrun interrupts are
45 * shared, which means that if we detect an underrun we need to disable underrun
46 * reporting on all pipes.
48 * The code also supports underrun detection on the PCH transcoder.
51 static bool ivb_can_enable_err_int(struct drm_device *dev)
53 struct drm_i915_private *dev_priv = to_i915(dev);
54 struct intel_crtc *crtc;
57 lockdep_assert_held(&dev_priv->irq_lock);
59 for_each_pipe(dev_priv, pipe) {
60 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
62 if (crtc->cpu_fifo_underrun_disabled)
69 static bool cpt_can_enable_serr_int(struct drm_device *dev)
71 struct drm_i915_private *dev_priv = to_i915(dev);
73 struct intel_crtc *crtc;
75 lockdep_assert_held(&dev_priv->irq_lock);
77 for_each_pipe(dev_priv, pipe) {
78 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
80 if (crtc->pch_fifo_underrun_disabled)
87 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
89 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
90 i915_reg_t reg = PIPESTAT(crtc->pipe);
91 u32 pipestat = I915_READ(reg) & 0xffff0000;
93 lockdep_assert_held(&dev_priv->irq_lock);
95 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
98 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
101 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
102 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
105 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
107 bool enable, bool old)
109 struct drm_i915_private *dev_priv = to_i915(dev);
110 i915_reg_t reg = PIPESTAT(pipe);
111 u32 pipestat = I915_READ(reg) & 0xffff0000;
113 lockdep_assert_held(&dev_priv->irq_lock);
116 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
119 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
120 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
124 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
125 enum pipe pipe, bool enable)
127 struct drm_i915_private *dev_priv = to_i915(dev);
128 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
129 DE_PIPEB_FIFO_UNDERRUN;
132 ilk_enable_display_irq(dev_priv, bit);
134 ilk_disable_display_irq(dev_priv, bit);
137 static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
139 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
140 enum pipe pipe = crtc->pipe;
141 uint32_t err_int = I915_READ(GEN7_ERR_INT);
143 lockdep_assert_held(&dev_priv->irq_lock);
145 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
148 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
149 POSTING_READ(GEN7_ERR_INT);
151 trace_intel_cpu_fifo_underrun(dev_priv, pipe);
152 DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));
155 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
157 bool enable, bool old)
159 struct drm_i915_private *dev_priv = to_i915(dev);
161 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
163 if (!ivb_can_enable_err_int(dev))
166 ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
168 ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
171 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
172 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
178 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
179 enum pipe pipe, bool enable)
181 struct drm_i915_private *dev_priv = to_i915(dev);
184 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
186 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
189 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
190 enum pipe pch_transcoder,
193 struct drm_i915_private *dev_priv = to_i915(dev);
194 uint32_t bit = (pch_transcoder == PIPE_A) ?
195 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
198 ibx_enable_display_interrupt(dev_priv, bit);
200 ibx_disable_display_interrupt(dev_priv, bit);
203 static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
206 enum pipe pch_transcoder = crtc->pipe;
207 uint32_t serr_int = I915_READ(SERR_INT);
209 lockdep_assert_held(&dev_priv->irq_lock);
211 if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
214 I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
215 POSTING_READ(SERR_INT);
217 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
218 DRM_ERROR("pch fifo underrun on pch transcoder %c\n",
219 pipe_name(pch_transcoder));
222 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
223 enum pipe pch_transcoder,
224 bool enable, bool old)
226 struct drm_i915_private *dev_priv = to_i915(dev);
230 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
232 if (!cpt_can_enable_serr_int(dev))
235 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
237 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
239 if (old && I915_READ(SERR_INT) &
240 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
241 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
242 pipe_name(pch_transcoder));
247 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
248 enum pipe pipe, bool enable)
250 struct drm_i915_private *dev_priv = to_i915(dev);
251 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
254 lockdep_assert_held(&dev_priv->irq_lock);
256 old = !crtc->cpu_fifo_underrun_disabled;
257 crtc->cpu_fifo_underrun_disabled = !enable;
259 if (HAS_GMCH_DISPLAY(dev_priv))
260 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
261 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
262 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
263 else if (IS_GEN7(dev_priv))
264 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
265 else if (INTEL_GEN(dev_priv) >= 8)
266 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
272 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
273 * @dev_priv: i915 device instance
274 * @pipe: (CPU) pipe to set state for
275 * @enable: whether underruns should be reported or not
277 * This function sets the fifo underrun state for @pipe. It is used in the
278 * modeset code to avoid false positives since on many platforms underruns are
279 * expected when disabling or enabling the pipe.
281 * Notice that on some platforms disabling underrun reports for one pipe
282 * disables for all due to shared interrupts. Actual reporting is still per-pipe
285 * Returns the previous state of underrun reporting.
287 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
288 enum pipe pipe, bool enable)
293 spin_lock_irqsave(&dev_priv->irq_lock, flags);
294 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
296 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
302 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
303 * @dev_priv: i915 device instance
304 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
305 * @enable: whether underruns should be reported or not
307 * This function makes us disable or enable PCH fifo underruns for a specific
308 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
309 * underrun reporting for one transcoder may also disable all the other PCH
310 * error interruts for the other transcoders, due to the fact that there's just
311 * one interrupt mask/enable bit for all the transcoders.
313 * Returns the previous state of underrun reporting.
315 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
316 enum pipe pch_transcoder,
319 struct intel_crtc *crtc =
320 intel_get_crtc_for_pipe(dev_priv, pch_transcoder);
325 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
326 * has only one pch transcoder A that all pipes can use. To avoid racy
327 * pch transcoder -> pipe lookups from interrupt code simply store the
328 * underrun statistics in crtc A. Since we never expose this anywhere
329 * nor use it outside of the fifo underrun code here using the "wrong"
330 * crtc on LPT won't cause issues.
333 spin_lock_irqsave(&dev_priv->irq_lock, flags);
335 old = !crtc->pch_fifo_underrun_disabled;
336 crtc->pch_fifo_underrun_disabled = !enable;
338 if (HAS_PCH_IBX(dev_priv))
339 ibx_set_fifo_underrun_reporting(&dev_priv->drm,
343 cpt_set_fifo_underrun_reporting(&dev_priv->drm,
347 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
352 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
353 * @dev_priv: i915 device instance
354 * @pipe: (CPU) pipe to set state for
356 * This handles a CPU fifo underrun interrupt, generating an underrun warning
357 * into dmesg if underrun reporting is enabled and then disables the underrun
358 * interrupt to avoid an irq storm.
360 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
363 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
365 /* We may be called too early in init, thanks BIOS! */
369 /* GMCH can't disable fifo underruns, filter them. */
370 if (HAS_GMCH_DISPLAY(dev_priv) &&
371 crtc->cpu_fifo_underrun_disabled)
374 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
375 trace_intel_cpu_fifo_underrun(dev_priv, pipe);
376 DRM_ERROR("CPU pipe %c FIFO underrun\n",
380 intel_fbc_handle_fifo_underrun_irq(dev_priv);
384 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
385 * @dev_priv: i915 device instance
386 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
388 * This handles a PCH fifo underrun interrupt, generating an underrun warning
389 * into dmesg if underrun reporting is enabled and then disables the underrun
390 * interrupt to avoid an irq storm.
392 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
393 enum pipe pch_transcoder)
395 if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
397 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
398 DRM_ERROR("PCH transcoder %c FIFO underrun\n",
399 pipe_name(pch_transcoder));
404 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
405 * @dev_priv: i915 device instance
407 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
408 * error interrupt may have been disabled, and so CPU fifo underruns won't
409 * necessarily raise an interrupt, and on GMCH platforms where underruns never
410 * raise an interrupt.
412 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
414 struct intel_crtc *crtc;
416 spin_lock_irq(&dev_priv->irq_lock);
418 for_each_intel_crtc(&dev_priv->drm, crtc) {
419 if (crtc->cpu_fifo_underrun_disabled)
422 if (HAS_GMCH_DISPLAY(dev_priv))
423 i9xx_check_fifo_underruns(crtc);
424 else if (IS_GEN7(dev_priv))
425 ivybridge_check_fifo_underruns(crtc);
428 spin_unlock_irq(&dev_priv->irq_lock);
432 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
433 * @dev_priv: i915 device instance
435 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
436 * error interrupt may have been disabled, and so PCH fifo underruns won't
437 * necessarily raise an interrupt.
439 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
441 struct intel_crtc *crtc;
443 spin_lock_irq(&dev_priv->irq_lock);
445 for_each_intel_crtc(&dev_priv->drm, crtc) {
446 if (crtc->pch_fifo_underrun_disabled)
449 if (HAS_PCH_CPT(dev_priv))
450 cpt_check_pch_fifo_underruns(crtc);
453 spin_unlock_irq(&dev_priv->irq_lock);