drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  *
  51  * TODO: When modesetting has fully transitioned to atomic, the below
  52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  53  * added.
  54  */
  55 #define _wait_for(COND, US, W) ({ \
  56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  57         int ret__;                                                      \
  58         for (;;) {                                                      \
  59                 bool expired__ = time_after(jiffies, timeout__);        \
  60                 if (COND) {                                             \
  61                         ret__ = 0;                                      \
  62                         break;                                          \
  63                 }                                                       \
  64                 if (expired__) {                                        \
  65                         ret__ = -ETIMEDOUT;                             \
  66                         break;                                          \
  67                 }                                                       \
  68                 if ((W) && drm_can_sleep()) {                           \
  69                         usleep_range((W), (W)*2);                       \
  70                 } else {                                                \
  71                         cpu_relax();                                    \
  72                 }                                                       \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  78
  79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  82 #else
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  84 #endif
  85
  86 #define _wait_for_atomic(COND, US, ATOMIC) \
  87 ({ \
  88         int cpu, ret, timeout = (US) * 1000; \
  89         u64 base; \
  90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  91         BUILD_BUG_ON((US) > 50000); \
  92         if (!(ATOMIC)) { \
  93                 preempt_disable(); \
  94                 cpu = smp_processor_id(); \
  95         } \
  96         base = local_clock(); \
  97         for (;;) { \
  98                 u64 now = local_clock(); \
  99                 if (!(ATOMIC)) \
 100                         preempt_enable(); \
 101                 if (COND) { \
 102                         ret = 0; \
 103                         break; \
 104                 } \
 105                 if (now - base >= timeout) { \
 106                         ret = -ETIMEDOUT; \
 107                         break; \
 108                 } \
 109                 cpu_relax(); \
 110                 if (!(ATOMIC)) { \
 111                         preempt_disable(); \
 112                         if (unlikely(cpu != smp_processor_id())) { \
 113                                 timeout -= now - base; \
 114                                 cpu = smp_processor_id(); \
 115                                 base = local_clock(); \
 116                         } \
 117                 } \
 118         } \
 119         ret; \
 120 })
 121
 122 #define wait_for_us(COND, US) \
 123 ({ \
 124         int ret__; \
 125         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 126         if ((US) > 10) \
 127                 ret__ = _wait_for((COND), (US), 10); \
 128         else \
 129                 ret__ = _wait_for_atomic((COND), (US), 0); \
 130         ret__; \
 131 })
 132
 133 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 134 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 135
 136 #define KHz(x) (1000 * (x))
 137 #define MHz(x) KHz(1000 * (x))
 138
 139 /*
 140  * Display related stuff
 141  */
 142
 143 /* store information about an Ixxx DVO */
 144 /* The i830->i865 use multiple DVOs with multiple i2cs */
 145 /* the i915, i945 have a single sDVO i2c bus - which is different */
 146 #define MAX_OUTPUTS 6
 147 /* maximum connectors per crtcs in the mode set */
 148
 149 /* Maximum cursor sizes */
 150 #define GEN2_CURSOR_WIDTH 64
 151 #define GEN2_CURSOR_HEIGHT 64
 152 #define MAX_CURSOR_WIDTH 256
 153 #define MAX_CURSOR_HEIGHT 256
 154
 155 #define INTEL_I2C_BUS_DVO 1
 156 #define INTEL_I2C_BUS_SDVO 2
 157
 158 /* these are outputs from the chip - integrated only
 159    external chips are via DVO or SDVO output */
 160 enum intel_output_type {
 161         INTEL_OUTPUT_UNUSED = 0,
 162         INTEL_OUTPUT_ANALOG = 1,
 163         INTEL_OUTPUT_DVO = 2,
 164         INTEL_OUTPUT_SDVO = 3,
 165         INTEL_OUTPUT_LVDS = 4,
 166         INTEL_OUTPUT_TVOUT = 5,
 167         INTEL_OUTPUT_HDMI = 6,
 168         INTEL_OUTPUT_DP = 7,
 169         INTEL_OUTPUT_EDP = 8,
 170         INTEL_OUTPUT_DSI = 9,
 171         INTEL_OUTPUT_UNKNOWN = 10,
 172         INTEL_OUTPUT_DP_MST = 11,
 173 };
 174
 175 #define INTEL_DVO_CHIP_NONE 0
 176 #define INTEL_DVO_CHIP_LVDS 1
 177 #define INTEL_DVO_CHIP_TMDS 2
 178 #define INTEL_DVO_CHIP_TVOUT 4
 179
 180 #define INTEL_DSI_VIDEO_MODE    0
 181 #define INTEL_DSI_COMMAND_MODE  1
 182
 183 struct intel_framebuffer {
 184         struct drm_framebuffer base;
 185         struct drm_i915_gem_object *obj;
 186         struct intel_rotation_info rot_info;
 187
 188         /* for each plane in the normal GTT view */
 189         struct {
 190                 unsigned int x, y;
 191         } normal[2];
 192         /* for each plane in the rotated GTT view */
 193         struct {
 194                 unsigned int x, y;
 195                 unsigned int pitch; /* pixels */
 196         } rotated[2];
 197 };
 198
 199 struct intel_fbdev {
 200         struct drm_fb_helper helper;
 201         struct intel_framebuffer *fb;
 202         struct i915_vma *vma;
 203         async_cookie_t cookie;
 204         int preferred_bpp;
 205 };
 206
 207 struct intel_encoder {
 208         struct drm_encoder base;
 209
 210         enum intel_output_type type;
 211         enum port port;
 212         unsigned int cloneable;
 213         void (*hot_plug)(struct intel_encoder *);
 214         bool (*compute_config)(struct intel_encoder *,
 215                                struct intel_crtc_state *,
 216                                struct drm_connector_state *);
 217         void (*pre_pll_enable)(struct intel_encoder *,
 218                                struct intel_crtc_state *,
 219                                struct drm_connector_state *);
 220         void (*pre_enable)(struct intel_encoder *,
 221                            struct intel_crtc_state *,
 222                            struct drm_connector_state *);
 223         void (*enable)(struct intel_encoder *,
 224                        struct intel_crtc_state *,
 225                        struct drm_connector_state *);
 226         void (*disable)(struct intel_encoder *,
 227                         struct intel_crtc_state *,
 228                         struct drm_connector_state *);
 229         void (*post_disable)(struct intel_encoder *,
 230                              struct intel_crtc_state *,
 231                              struct drm_connector_state *);
 232         void (*post_pll_disable)(struct intel_encoder *,
 233                                  struct intel_crtc_state *,
 234                                  struct drm_connector_state *);
 235         /* Read out the current hw state of this connector, returning true if
 236          * the encoder is active. If the encoder is enabled it also set the pipe
 237          * it is connected to in the pipe parameter. */
 238         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 239         /* Reconstructs the equivalent mode flags for the current hardware
 240          * state. This must be called _after_ display->get_pipe_config has
 241          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 242          * be set correctly before calling this function. */
 243         void (*get_config)(struct intel_encoder *,
 244                            struct intel_crtc_state *pipe_config);
 245         /* Returns a mask of power domains that need to be referenced as part
 246          * of the hardware state readout code. */
 247         u64 (*get_power_domains)(struct intel_encoder *encoder);
 248         /*
 249          * Called during system suspend after all pending requests for the
 250          * encoder are flushed (for example for DP AUX transactions) and
 251          * device interrupts are disabled.
 252          */
 253         void (*suspend)(struct intel_encoder *);
 254         int crtc_mask;
 255         enum hpd_pin hpd_pin;
 256         enum intel_display_power_domain power_domain;
 257         /* for communication with audio component; protected by av_mutex */
 258         const struct drm_connector *audio_connector;
 259 };
 260
 261 struct intel_panel {
 262         struct drm_display_mode *fixed_mode;
 263         struct drm_display_mode *downclock_mode;
 264         int fitting_mode;
 265
 266         /* backlight */
 267         struct {
 268                 bool present;
 269                 u32 level;
 270                 u32 min;
 271                 u32 max;
 272                 bool enabled;
 273                 bool combination_mode;  /* gen 2/4 only */
 274                 bool active_low_pwm;
 275                 bool alternate_pwm_increment;   /* lpt+ */
 276
 277                 /* PWM chip */
 278                 bool util_pin_active_low;       /* bxt+ */
 279                 u8 controller;          /* bxt+ only */
 280                 struct pwm_device *pwm;
 281
 282                 struct backlight_device *device;
 283
 284                 /* Connector and platform specific backlight functions */
 285                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 286                 uint32_t (*get)(struct intel_connector *connector);
 287                 void (*set)(struct intel_connector *connector, uint32_t level);
 288                 void (*disable)(struct intel_connector *connector);
 289                 void (*enable)(struct intel_connector *connector);
 290                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 291                                       uint32_t hz);
 292                 void (*power)(struct intel_connector *, bool enable);
 293         } backlight;
 294 };
 295
 296 struct intel_connector {
 297         struct drm_connector base;
 298         /*
 299          * The fixed encoder this connector is connected to.
 300          */
 301         struct intel_encoder *encoder;
 302
 303         /* ACPI device id for ACPI and driver cooperation */
 304         u32 acpi_device_id;
 305
 306         /* Reads out the current hw, returning true if the connector is enabled
 307          * and active (i.e. dpms ON state). */
 308         bool (*get_hw_state)(struct intel_connector *);
 309
 310         /* Panel info for eDP and LVDS */
 311         struct intel_panel panel;
 312
 313         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 314         struct edid *edid;
 315         struct edid *detect_edid;
 316
 317         /* since POLL and HPD connectors may use the same HPD line keep the native
 318            state of connector->polled in case hotplug storm detection changes it */
 319         u8 polled;
 320
 321         void *port; /* store this opaque as its illegal to dereference it */
 322
 323         struct intel_dp *mst_port;
 324 };
 325
 326 struct dpll {
 327         /* given values */
 328         int n;
 329         int m1, m2;
 330         int p1, p2;
 331         /* derived values */
 332         int     dot;
 333         int     vco;
 334         int     m;
 335         int     p;
 336 };
 337
 338 struct intel_atomic_state {
 339         struct drm_atomic_state base;
 340
 341         struct {
 342                 /*
 343                  * Logical state of cdclk (used for all scaling, watermark,
 344                  * etc. calculations and checks). This is computed as if all
 345                  * enabled crtcs were active.
 346                  */
 347                 struct intel_cdclk_state logical;
 348
 349                 /*
 350                  * Actual state of cdclk, can be different from the logical
 351                  * state only when all crtc's are DPMS off.
 352                  */
 353                 struct intel_cdclk_state actual;
 354         } cdclk;
 355
 356         bool dpll_set, modeset;
 357
 358         /*
 359          * Does this transaction change the pipes that are active?  This mask
 360          * tracks which CRTC's have changed their active state at the end of
 361          * the transaction (not counting the temporary disable during modesets).
 362          * This mask should only be non-zero when intel_state->modeset is true,
 363          * but the converse is not necessarily true; simply changing a mode may
 364          * not flip the final active status of any CRTC's
 365          */
 366         unsigned int active_pipe_changes;
 367
 368         unsigned int active_crtcs;
 369         unsigned int min_pixclk[I915_MAX_PIPES];
 370
 371         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 372
 373         /*
 374          * Current watermarks can't be trusted during hardware readout, so
 375          * don't bother calculating intermediate watermarks.
 376          */
 377         bool skip_intermediate_wm;
 378
 379         /* Gen9+ only */
 380         struct skl_wm_values wm_results;
 381
 382         struct i915_sw_fence commit_ready;
 383
 384         struct llist_node freed;
 385 };
 386
 387 struct intel_plane_state {
 388         struct drm_plane_state base;
 389         struct drm_rect clip;
 390         struct i915_vma *vma;
 391
 392         struct {
 393                 u32 offset;
 394                 int x, y;
 395         } main;
 396         struct {
 397                 u32 offset;
 398                 int x, y;
 399         } aux;
 400
 401         /*
 402          * scaler_id
 403          *    = -1 : not using a scaler
 404          *    >=  0 : using a scalers
 405          *
 406          * plane requiring a scaler:
 407          *   - During check_plane, its bit is set in
 408          *     crtc_state->scaler_state.scaler_users by calling helper function
 409          *     update_scaler_plane.
 410          *   - scaler_id indicates the scaler it got assigned.
 411          *
 412          * plane doesn't require a scaler:
 413          *   - this can happen when scaling is no more required or plane simply
 414          *     got disabled.
 415          *   - During check_plane, corresponding bit is reset in
 416          *     crtc_state->scaler_state.scaler_users by calling helper function
 417          *     update_scaler_plane.
 418          */
 419         int scaler_id;
 420
 421         struct drm_intel_sprite_colorkey ckey;
 422 };
 423
 424 struct intel_initial_plane_config {
 425         struct intel_framebuffer *fb;
 426         unsigned int tiling;
 427         int size;
 428         u32 base;
 429 };
 430
 431 #define SKL_MIN_SRC_W 8
 432 #define SKL_MAX_SRC_W 4096
 433 #define SKL_MIN_SRC_H 8
 434 #define SKL_MAX_SRC_H 4096
 435 #define SKL_MIN_DST_W 8
 436 #define SKL_MAX_DST_W 4096
 437 #define SKL_MIN_DST_H 8
 438 #define SKL_MAX_DST_H 4096
 439
 440 struct intel_scaler {
 441         int in_use;
 442         uint32_t mode;
 443 };
 444
 445 struct intel_crtc_scaler_state {
 446 #define SKL_NUM_SCALERS 2
 447         struct intel_scaler scalers[SKL_NUM_SCALERS];
 448
 449         /*
 450          * scaler_users: keeps track of users requesting scalers on this crtc.
 451          *
 452          *     If a bit is set, a user is using a scaler.
 453          *     Here user can be a plane or crtc as defined below:
 454          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 455          *       bit 31    - crtc
 456          *
 457          * Instead of creating a new index to cover planes and crtc, using
 458          * existing drm_plane_index for planes which is well less than 31
 459          * planes and bit 31 for crtc. This should be fine to cover all
 460          * our platforms.
 461          *
 462          * intel_atomic_setup_scalers will setup available scalers to users
 463          * requesting scalers. It will gracefully fail if request exceeds
 464          * avilability.
 465          */
 466 #define SKL_CRTC_INDEX 31
 467         unsigned scaler_users;
 468
 469         /* scaler used by crtc for panel fitting purpose */
 470         int scaler_id;
 471 };
 472
 473 /* drm_mode->private_flags */
 474 #define I915_MODE_FLAG_INHERITED 1
 475
 476 struct intel_pipe_wm {
 477         struct intel_wm_level wm[5];
 478         struct intel_wm_level raw_wm[5];
 479         uint32_t linetime;
 480         bool fbc_wm_enabled;
 481         bool pipe_enabled;
 482         bool sprites_enabled;
 483         bool sprites_scaled;
 484 };
 485
 486 struct skl_plane_wm {
 487         struct skl_wm_level wm[8];
 488         struct skl_wm_level trans_wm;
 489 };
 490
 491 struct skl_pipe_wm {
 492         struct skl_plane_wm planes[I915_MAX_PLANES];
 493         uint32_t linetime;
 494 };
 495
 496 enum vlv_wm_level {
 497         VLV_WM_LEVEL_PM2,
 498         VLV_WM_LEVEL_PM5,
 499         VLV_WM_LEVEL_DDR_DVFS,
 500         NUM_VLV_WM_LEVELS,
 501 };
 502
 503 struct vlv_wm_state {
 504         struct vlv_pipe_wm wm[NUM_VLV_WM_LEVELS];
 505         struct vlv_sr_wm sr[NUM_VLV_WM_LEVELS];
 506         uint8_t num_levels;
 507         bool cxsr;
 508 };
 509
 510 struct vlv_fifo_state {
 511         u16 plane[I915_MAX_PLANES];
 512 };
 513
 514 struct intel_crtc_wm_state {
 515         union {
 516                 struct {
 517                         /*
 518                          * Intermediate watermarks; these can be
 519                          * programmed immediately since they satisfy
 520                          * both the current configuration we're
 521                          * switching away from and the new
 522                          * configuration we're switching to.
 523                          */
 524                         struct intel_pipe_wm intermediate;
 525
 526                         /*
 527                          * Optimal watermarks, programmed post-vblank
 528                          * when this state is committed.
 529                          */
 530                         struct intel_pipe_wm optimal;
 531                 } ilk;
 532
 533                 struct {
 534                         /* gen9+ only needs 1-step wm programming */
 535                         struct skl_pipe_wm optimal;
 536                         struct skl_ddb_entry ddb;
 537                 } skl;
 538
 539                 struct {
 540                         /* "raw" watermarks (not inverted) */
 541                         struct vlv_pipe_wm raw[NUM_VLV_WM_LEVELS];
 542                         /* intermediate watermarks (inverted) */
 543                         struct vlv_wm_state intermediate;
 544                         /* optimal watermarks (inverted) */
 545                         struct vlv_wm_state optimal;
 546                         /* display FIFO split */
 547                         struct vlv_fifo_state fifo_state;
 548                 } vlv;
 549         };
 550
 551         /*
 552          * Platforms with two-step watermark programming will need to
 553          * update watermark programming post-vblank to switch from the
 554          * safe intermediate watermarks to the optimal final
 555          * watermarks.
 556          */
 557         bool need_postvbl_update;
 558 };
 559
 560 struct intel_crtc_state {
 561         struct drm_crtc_state base;
 562
 563         /**
 564          * quirks - bitfield with hw state readout quirks
 565          *
 566          * For various reasons the hw state readout code might not be able to
 567          * completely faithfully read out the current state. These cases are
 568          * tracked with quirk flags so that fastboot and state checker can act
 569          * accordingly.
 570          */
 571 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 572         unsigned long quirks;
 573
 574         unsigned fb_bits; /* framebuffers to flip */
 575         bool update_pipe; /* can a fast modeset be performed? */
 576         bool disable_cxsr;
 577         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 578         bool fb_changed; /* fb on any of the planes is changed */
 579         bool fifo_changed; /* FIFO split is changed */
 580
 581         /* Pipe source size (ie. panel fitter input size)
 582          * All planes will be positioned inside this space,
 583          * and get clipped at the edges. */
 584         int pipe_src_w, pipe_src_h;
 585
 586         /*
 587          * Pipe pixel rate, adjusted for
 588          * panel fitter/pipe scaler downscaling.
 589          */
 590         unsigned int pixel_rate;
 591
 592         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 593          * between pch encoders and cpu encoders. */
 594         bool has_pch_encoder;
 595
 596         /* Are we sending infoframes on the attached port */
 597         bool has_infoframe;
 598
 599         /* CPU Transcoder for the pipe. Currently this can only differ from the
 600          * pipe on Haswell and later (where we have a special eDP transcoder)
 601          * and Broxton (where we have special DSI transcoders). */
 602         enum transcoder cpu_transcoder;
 603
 604         /*
 605          * Use reduced/limited/broadcast rbg range, compressing from the full
 606          * range fed into the crtcs.
 607          */
 608         bool limited_color_range;
 609
 610         /* Bitmask of encoder types (enum intel_output_type)
 611          * driven by the pipe.
 612          */
 613         unsigned int output_types;
 614
 615         /* Whether we should send NULL infoframes. Required for audio. */
 616         bool has_hdmi_sink;
 617
 618         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 619          * has_dp_encoder is set. */
 620         bool has_audio;
 621
 622         /*
 623          * Enable dithering, used when the selected pipe bpp doesn't match the
 624          * plane bpp.
 625          */
 626         bool dither;
 627
 628         /*
 629          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 630          * compliance video pattern tests.
 631          * Disable dither only if it is a compliance test request for
 632          * 18bpp.
 633          */
 634         bool dither_force_disable;
 635
 636         /* Controls for the clock computation, to override various stages. */
 637         bool clock_set;
 638
 639         /* SDVO TV has a bunch of special case. To make multifunction encoders
 640          * work correctly, we need to track this at runtime.*/
 641         bool sdvo_tv_clock;
 642
 643         /*
 644          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 645          * required. This is set in the 2nd loop of calling encoder's
 646          * ->compute_config if the first pick doesn't work out.
 647          */
 648         bool bw_constrained;
 649
 650         /* Settings for the intel dpll used on pretty much everything but
 651          * haswell. */
 652         struct dpll dpll;
 653
 654         /* Selected dpll when shared or NULL. */
 655         struct intel_shared_dpll *shared_dpll;
 656
 657         /* Actual register state of the dpll, for shared dpll cross-checking. */
 658         struct intel_dpll_hw_state dpll_hw_state;
 659
 660         /* DSI PLL registers */
 661         struct {
 662                 u32 ctrl, div;
 663         } dsi_pll;
 664
 665         int pipe_bpp;
 666         struct intel_link_m_n dp_m_n;
 667
 668         /* m2_n2 for eDP downclock */
 669         struct intel_link_m_n dp_m2_n2;
 670         bool has_drrs;
 671
 672         /*
 673          * Frequence the dpll for the port should run at. Differs from the
 674          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 675          * already multiplied by pixel_multiplier.
 676          */
 677         int port_clock;
 678
 679         /* Used by SDVO (and if we ever fix it, HDMI). */
 680         unsigned pixel_multiplier;
 681
 682         uint8_t lane_count;
 683
 684         /*
 685          * Used by platforms having DP/HDMI PHY with programmable lane
 686          * latency optimization.
 687          */
 688         uint8_t lane_lat_optim_mask;
 689
 690         /* Panel fitter controls for gen2-gen4 + VLV */
 691         struct {
 692                 u32 control;
 693                 u32 pgm_ratios;
 694                 u32 lvds_border_bits;
 695         } gmch_pfit;
 696
 697         /* Panel fitter placement and size for Ironlake+ */
 698         struct {
 699                 u32 pos;
 700                 u32 size;
 701                 bool enabled;
 702                 bool force_thru;
 703         } pch_pfit;
 704
 705         /* FDI configuration, only valid if has_pch_encoder is set. */
 706         int fdi_lanes;
 707         struct intel_link_m_n fdi_m_n;
 708
 709         bool ips_enabled;
 710
 711         bool enable_fbc;
 712
 713         bool double_wide;
 714
 715         int pbn;
 716
 717         struct intel_crtc_scaler_state scaler_state;
 718
 719         /* w/a for waiting 2 vblanks during crtc enable */
 720         enum pipe hsw_workaround_pipe;
 721
 722         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 723         bool disable_lp_wm;
 724
 725         struct intel_crtc_wm_state wm;
 726
 727         /* Gamma mode programmed on the pipe */
 728         uint32_t gamma_mode;
 729
 730         /* bitmask of visible planes (enum plane_id) */
 731         u8 active_planes;
 732 };
 733
 734 struct intel_crtc {
 735         struct drm_crtc base;
 736         enum pipe pipe;
 737         enum plane plane;
 738         u8 lut_r[256], lut_g[256], lut_b[256];
 739         /*
 740          * Whether the crtc and the connected output pipeline is active. Implies
 741          * that crtc->enabled is set, i.e. the current mode configuration has
 742          * some outputs connected to this crtc.
 743          */
 744         bool active;
 745         bool lowfreq_avail;
 746         u8 plane_ids_mask;
 747         unsigned long long enabled_power_domains;
 748         struct intel_overlay *overlay;
 749         struct intel_flip_work *flip_work;
 750
 751         atomic_t unpin_work_count;
 752
 753         /* Display surface base address adjustement for pageflips. Note that on
 754          * gen4+ this only adjusts up to a tile, offsets within a tile are
 755          * handled in the hw itself (with the TILEOFF register). */
 756         u32 dspaddr_offset;
 757         int adjusted_x;
 758         int adjusted_y;
 759
 760         uint32_t cursor_addr;
 761         uint32_t cursor_cntl;
 762         uint32_t cursor_size;
 763         uint32_t cursor_base;
 764
 765         struct intel_crtc_state *config;
 766
 767         /* global reset count when the last flip was submitted */
 768         unsigned int reset_count;
 769
 770         /* Access to these should be protected by dev_priv->irq_lock. */
 771         bool cpu_fifo_underrun_disabled;
 772         bool pch_fifo_underrun_disabled;
 773
 774         /* per-pipe watermark state */
 775         struct {
 776                 /* watermarks currently being used  */
 777                 union {
 778                         struct intel_pipe_wm ilk;
 779                         struct vlv_wm_state vlv;
 780                 } active;
 781         } wm;
 782
 783         int scanline_offset;
 784
 785         struct {
 786                 unsigned start_vbl_count;
 787                 ktime_t start_vbl_time;
 788                 int min_vbl, max_vbl;
 789                 int scanline_start;
 790         } debug;
 791
 792         /* scalers available on this crtc */
 793         int num_scalers;
 794 };
 795
 796 struct intel_plane {
 797         struct drm_plane base;
 798         u8 plane;
 799         enum plane_id id;
 800         enum pipe pipe;
 801         bool can_scale;
 802         int max_downscale;
 803         uint32_t frontbuffer_bit;
 804
 805         /*
 806          * NOTE: Do not place new plane state fields here (e.g., when adding
 807          * new plane properties).  New runtime state should now be placed in
 808          * the intel_plane_state structure and accessed via plane_state.
 809          */
 810
 811         void (*update_plane)(struct drm_plane *plane,
 812                              const struct intel_crtc_state *crtc_state,
 813                              const struct intel_plane_state *plane_state);
 814         void (*disable_plane)(struct drm_plane *plane,
 815                               struct drm_crtc *crtc);
 816         int (*check_plane)(struct drm_plane *plane,
 817                            struct intel_crtc_state *crtc_state,
 818                            struct intel_plane_state *state);
 819 };
 820
 821 struct intel_watermark_params {
 822         u16 fifo_size;
 823         u16 max_wm;
 824         u8 default_wm;
 825         u8 guard_size;
 826         u8 cacheline_size;
 827 };
 828
 829 struct cxsr_latency {
 830         bool is_desktop : 1;
 831         bool is_ddr3 : 1;
 832         u16 fsb_freq;
 833         u16 mem_freq;
 834         u16 display_sr;
 835         u16 display_hpll_disable;
 836         u16 cursor_sr;
 837         u16 cursor_hpll_disable;
 838 };
 839
 840 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 841 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 842 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 843 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 844 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 845 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 846 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 847 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 848 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 849
 850 struct intel_hdmi {
 851         i915_reg_t hdmi_reg;
 852         int ddc_bus;
 853         struct {
 854                 enum drm_dp_dual_mode_type type;
 855                 int max_tmds_clock;
 856         } dp_dual_mode;
 857         bool limited_color_range;
 858         bool color_range_auto;
 859         bool has_hdmi_sink;
 860         bool has_audio;
 861         enum hdmi_force_audio force_audio;
 862         bool rgb_quant_range_selectable;
 863         enum hdmi_picture_aspect aspect_ratio;
 864         struct intel_connector *attached_connector;
 865         void (*write_infoframe)(struct drm_encoder *encoder,
 866                                 const struct intel_crtc_state *crtc_state,
 867                                 enum hdmi_infoframe_type type,
 868                                 const void *frame, ssize_t len);
 869         void (*set_infoframes)(struct drm_encoder *encoder,
 870                                bool enable,
 871                                const struct intel_crtc_state *crtc_state,
 872                                const struct drm_connector_state *conn_state);
 873         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 874                                   const struct intel_crtc_state *pipe_config);
 875 };
 876
 877 struct intel_dp_mst_encoder;
 878 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 879
 880 /*
 881  * enum link_m_n_set:
 882  *      When platform provides two set of M_N registers for dp, we can
 883  *      program them and switch between them incase of DRRS.
 884  *      But When only one such register is provided, we have to program the
 885  *      required divider value on that registers itself based on the DRRS state.
 886  *
 887  * M1_N1        : Program dp_m_n on M1_N1 registers
 888  *                        dp_m2_n2 on M2_N2 registers (If supported)
 889  *
 890  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 891  *                        M2_N2 registers are not supported
 892  */
 893
 894 enum link_m_n_set {
 895         /* Sets the m1_n1 and m2_n2 */
 896         M1_N1 = 0,
 897         M2_N2
 898 };
 899
 900 struct intel_dp_desc {
 901         u8 oui[3];
 902         u8 device_id[6];
 903         u8 hw_rev;
 904         u8 sw_major_rev;
 905         u8 sw_minor_rev;
 906 } __packed;
 907
 908 struct intel_dp_compliance_data {
 909         unsigned long edid;
 910         uint8_t video_pattern;
 911         uint16_t hdisplay, vdisplay;
 912         uint8_t bpc;
 913 };
 914
 915 struct intel_dp_compliance {
 916         unsigned long test_type;
 917         struct intel_dp_compliance_data test_data;
 918         bool test_active;
 919         int test_link_rate;
 920         u8 test_lane_count;
 921 };
 922
 923 struct intel_dp {
 924         i915_reg_t output_reg;
 925         i915_reg_t aux_ch_ctl_reg;
 926         i915_reg_t aux_ch_data_reg[5];
 927         uint32_t DP;
 928         int link_rate;
 929         uint8_t lane_count;
 930         uint8_t sink_count;
 931         bool link_mst;
 932         bool has_audio;
 933         bool detect_done;
 934         bool channel_eq_status;
 935         bool reset_link_params;
 936         enum hdmi_force_audio force_audio;
 937         bool limited_color_range;
 938         bool color_range_auto;
 939         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 940         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 941         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 942         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 943         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 944         uint8_t num_sink_rates;
 945         int sink_rates[DP_MAX_SUPPORTED_RATES];
 946         /* Max lane count for the sink as per DPCD registers */
 947         uint8_t max_sink_lane_count;
 948         /* Max link BW for the sink as per DPCD registers */
 949         int max_sink_link_bw;
 950         /* sink or branch descriptor */
 951         struct intel_dp_desc desc;
 952         struct drm_dp_aux aux;
 953         enum intel_display_power_domain aux_power_domain;
 954         uint8_t train_set[4];
 955         int panel_power_up_delay;
 956         int panel_power_down_delay;
 957         int panel_power_cycle_delay;
 958         int backlight_on_delay;
 959         int backlight_off_delay;
 960         struct delayed_work panel_vdd_work;
 961         bool want_panel_vdd;
 962         unsigned long last_power_on;
 963         unsigned long last_backlight_off;
 964         ktime_t panel_power_off_time;
 965
 966         struct notifier_block edp_notifier;
 967
 968         /*
 969          * Pipe whose power sequencer is currently locked into
 970          * this port. Only relevant on VLV/CHV.
 971          */
 972         enum pipe pps_pipe;
 973         /*
 974          * Pipe currently driving the port. Used for preventing
 975          * the use of the PPS for any pipe currentrly driving
 976          * external DP as that will mess things up on VLV.
 977          */
 978         enum pipe active_pipe;
 979         /*
 980          * Set if the sequencer may be reset due to a power transition,
 981          * requiring a reinitialization. Only relevant on BXT.
 982          */
 983         bool pps_reset;
 984         struct edp_power_seq pps_delays;
 985
 986         bool can_mst; /* this port supports mst */
 987         bool is_mst;
 988         int active_mst_links;
 989         /* connector directly attached - won't be use for modeset in mst world */
 990         struct intel_connector *attached_connector;
 991
 992         /* mst connector list */
 993         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 994         struct drm_dp_mst_topology_mgr mst_mgr;
 995
 996         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 997         /*
 998          * This function returns the value we have to program the AUX_CTL
 999          * register with to kick off an AUX transaction.
1000          */
1001         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1002                                      bool has_aux_irq,
1003                                      int send_bytes,
1004                                      uint32_t aux_clock_divider);
1005
1006         /* This is called before a link training is starterd */
1007         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1008
1009         /* Displayport compliance testing */
1010         struct intel_dp_compliance compliance;
1011 };
1012
1013 struct intel_lspcon {
1014         bool active;
1015         enum drm_lspcon_mode mode;
1016 };
1017
1018 struct intel_digital_port {
1019         struct intel_encoder base;
1020         enum port port;
1021         u32 saved_port_bits;
1022         struct intel_dp dp;
1023         struct intel_hdmi hdmi;
1024         struct intel_lspcon lspcon;
1025         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1026         bool release_cl2_override;
1027         uint8_t max_lanes;
1028         enum intel_display_power_domain ddi_io_power_domain;
1029 };
1030
1031 struct intel_dp_mst_encoder {
1032         struct intel_encoder base;
1033         enum pipe pipe;
1034         struct intel_digital_port *primary;
1035         struct intel_connector *connector;
1036 };
1037
1038 static inline enum dpio_channel
1039 vlv_dport_to_channel(struct intel_digital_port *dport)
1040 {
1041         switch (dport->port) {
1042         case PORT_B:
1043         case PORT_D:
1044                 return DPIO_CH0;
1045         case PORT_C:
1046                 return DPIO_CH1;
1047         default:
1048                 BUG();
1049         }
1050 }
1051
1052 static inline enum dpio_phy
1053 vlv_dport_to_phy(struct intel_digital_port *dport)
1054 {
1055         switch (dport->port) {
1056         case PORT_B:
1057         case PORT_C:
1058                 return DPIO_PHY0;
1059         case PORT_D:
1060                 return DPIO_PHY1;
1061         default:
1062                 BUG();
1063         }
1064 }
1065
1066 static inline enum dpio_channel
1067 vlv_pipe_to_channel(enum pipe pipe)
1068 {
1069         switch (pipe) {
1070         case PIPE_A:
1071         case PIPE_C:
1072                 return DPIO_CH0;
1073         case PIPE_B:
1074                 return DPIO_CH1;
1075         default:
1076                 BUG();
1077         }
1078 }
1079
1080 static inline struct intel_crtc *
1081 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1082 {
1083         return dev_priv->pipe_to_crtc_mapping[pipe];
1084 }
1085
1086 static inline struct intel_crtc *
1087 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1088 {
1089         return dev_priv->plane_to_crtc_mapping[plane];
1090 }
1091
1092 struct intel_flip_work {
1093         struct work_struct unpin_work;
1094         struct work_struct mmio_work;
1095
1096         struct drm_crtc *crtc;
1097         struct i915_vma *old_vma;
1098         struct drm_framebuffer *old_fb;
1099         struct drm_i915_gem_object *pending_flip_obj;
1100         struct drm_pending_vblank_event *event;
1101         atomic_t pending;
1102         u32 flip_count;
1103         u32 gtt_offset;
1104         struct drm_i915_gem_request *flip_queued_req;
1105         u32 flip_queued_vblank;
1106         u32 flip_ready_vblank;
1107         unsigned int rotation;
1108 };
1109
1110 struct intel_load_detect_pipe {
1111         struct drm_atomic_state *restore_state;
1112 };
1113
1114 static inline struct intel_encoder *
1115 intel_attached_encoder(struct drm_connector *connector)
1116 {
1117         return to_intel_connector(connector)->encoder;
1118 }
1119
1120 static inline struct intel_digital_port *
1121 enc_to_dig_port(struct drm_encoder *encoder)
1122 {
1123         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1124
1125         switch (intel_encoder->type) {
1126         case INTEL_OUTPUT_UNKNOWN:
1127                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1128         case INTEL_OUTPUT_DP:
1129         case INTEL_OUTPUT_EDP:
1130         case INTEL_OUTPUT_HDMI:
1131                 return container_of(encoder, struct intel_digital_port,
1132                                     base.base);
1133         default:
1134                 return NULL;
1135         }
1136 }
1137
1138 static inline struct intel_dp_mst_encoder *
1139 enc_to_mst(struct drm_encoder *encoder)
1140 {
1141         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1142 }
1143
1144 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1145 {
1146         return &enc_to_dig_port(encoder)->dp;
1147 }
1148
1149 static inline struct intel_digital_port *
1150 dp_to_dig_port(struct intel_dp *intel_dp)
1151 {
1152         return container_of(intel_dp, struct intel_digital_port, dp);
1153 }
1154
1155 static inline struct intel_lspcon *
1156 dp_to_lspcon(struct intel_dp *intel_dp)
1157 {
1158         return &dp_to_dig_port(intel_dp)->lspcon;
1159 }
1160
1161 static inline struct intel_digital_port *
1162 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1163 {
1164         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1165 }
1166
1167 /* intel_fifo_underrun.c */
1168 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1169                                            enum pipe pipe, bool enable);
1170 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1171                                            enum transcoder pch_transcoder,
1172                                            bool enable);
1173 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1174                                          enum pipe pipe);
1175 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1176                                          enum transcoder pch_transcoder);
1177 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1178 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1179
1180 /* i915_irq.c */
1181 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1182 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1183 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1184 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1185 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1186 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1187 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1188 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1189 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1190 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1191
1192 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1193                                             u32 mask)
1194 {
1195         return mask & ~i915->rps.pm_intrmsk_mbz;
1196 }
1197
1198 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1199 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1200 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1201 {
1202         /*
1203          * We only use drm_irq_uninstall() at unload and VT switch, so
1204          * this is the only thing we need to check.
1205          */
1206         return dev_priv->pm.irqs_enabled;
1207 }
1208
1209 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1210 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1211                                      unsigned int pipe_mask);
1212 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1213                                      unsigned int pipe_mask);
1214 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1215 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1216 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1217
1218 /* intel_crt.c */
1219 void intel_crt_init(struct drm_i915_private *dev_priv);
1220 void intel_crt_reset(struct drm_encoder *encoder);
1221
1222 /* intel_ddi.c */
1223 void intel_ddi_clk_select(struct intel_encoder *encoder,
1224                           struct intel_shared_dpll *pll);
1225 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1226                                 struct intel_crtc_state *old_crtc_state,
1227                                 struct drm_connector_state *old_conn_state);
1228 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1229 void hsw_fdi_link_train(struct intel_crtc *crtc,
1230                         const struct intel_crtc_state *crtc_state);
1231 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1232 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1233 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1234 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1235 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1236                                        enum transcoder cpu_transcoder);
1237 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1238 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1239 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1240                           struct intel_crtc_state *crtc_state);
1241 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1242 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1243 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1244 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1245                                  struct intel_crtc *intel_crtc);
1246 void intel_ddi_get_config(struct intel_encoder *encoder,
1247                           struct intel_crtc_state *pipe_config);
1248
1249 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1250 void intel_ddi_clock_get(struct intel_encoder *encoder,
1251                          struct intel_crtc_state *pipe_config);
1252 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1253                                     bool state);
1254 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1255 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1256
1257 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1258                                    int plane, unsigned int height);
1259
1260 /* intel_audio.c */
1261 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1262 void intel_audio_codec_enable(struct intel_encoder *encoder,
1263                               const struct intel_crtc_state *crtc_state,
1264                               const struct drm_connector_state *conn_state);
1265 void intel_audio_codec_disable(struct intel_encoder *encoder);
1266 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1267 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1268 void intel_audio_init(struct drm_i915_private *dev_priv);
1269 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1270
1271 /* intel_cdclk.c */
1272 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1273 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1274 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1275 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1276 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1277 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1278 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1279 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1280 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1281                                const struct intel_cdclk_state *b);
1282 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1283                      const struct intel_cdclk_state *cdclk_state);
1284
1285 /* intel_display.c */
1286 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1287 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1288 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1289 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1290                       const char *name, u32 reg, int ref_freq);
1291 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1292                            const char *name, u32 reg);
1293 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1294 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1295 extern const struct drm_plane_funcs intel_plane_funcs;
1296 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1297 unsigned int intel_fb_xy_to_linear(int x, int y,
1298                                    const struct intel_plane_state *state,
1299                                    int plane);
1300 void intel_add_fb_offsets(int *x, int *y,
1301                           const struct intel_plane_state *state, int plane);
1302 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1303 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1304 void intel_mark_busy(struct drm_i915_private *dev_priv);
1305 void intel_mark_idle(struct drm_i915_private *dev_priv);
1306 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1307 int intel_display_suspend(struct drm_device *dev);
1308 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1309 void intel_encoder_destroy(struct drm_encoder *encoder);
1310 int intel_connector_init(struct intel_connector *);
1311 struct intel_connector *intel_connector_alloc(void);
1312 bool intel_connector_get_hw_state(struct intel_connector *connector);
1313 void intel_connector_attach_encoder(struct intel_connector *connector,
1314                                     struct intel_encoder *encoder);
1315 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1316                                              struct drm_crtc *crtc);
1317 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1318 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1319                                 struct drm_file *file_priv);
1320 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1321                                              enum pipe pipe);
1322 static inline bool
1323 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1324                     enum intel_output_type type)
1325 {
1326         return crtc_state->output_types & (1 << type);
1327 }
1328 static inline bool
1329 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1330 {
1331         return crtc_state->output_types &
1332                 ((1 << INTEL_OUTPUT_DP) |
1333                  (1 << INTEL_OUTPUT_DP_MST) |
1334                  (1 << INTEL_OUTPUT_EDP));
1335 }
1336 static inline void
1337 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1338 {
1339         drm_wait_one_vblank(&dev_priv->drm, pipe);
1340 }
1341 static inline void
1342 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1343 {
1344         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1345
1346         if (crtc->active)
1347                 intel_wait_for_vblank(dev_priv, pipe);
1348 }
1349
1350 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1351
1352 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1353 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1354                          struct intel_digital_port *dport,
1355                          unsigned int expected_mask);
1356 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1357                                 struct drm_display_mode *mode,
1358                                 struct intel_load_detect_pipe *old,
1359                                 struct drm_modeset_acquire_ctx *ctx);
1360 void intel_release_load_detect_pipe(struct drm_connector *connector,
1361                                     struct intel_load_detect_pipe *old,
1362                                     struct drm_modeset_acquire_ctx *ctx);
1363 struct i915_vma *
1364 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1365 void intel_unpin_fb_vma(struct i915_vma *vma);
1366 struct drm_framebuffer *
1367 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1368                          struct drm_mode_fb_cmd2 *mode_cmd);
1369 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1370 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1371 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1372 int intel_prepare_plane_fb(struct drm_plane *plane,
1373                            struct drm_plane_state *new_state);
1374 void intel_cleanup_plane_fb(struct drm_plane *plane,
1375                             struct drm_plane_state *old_state);
1376 int intel_plane_atomic_get_property(struct drm_plane *plane,
1377                                     const struct drm_plane_state *state,
1378                                     struct drm_property *property,
1379                                     uint64_t *val);
1380 int intel_plane_atomic_set_property(struct drm_plane *plane,
1381                                     struct drm_plane_state *state,
1382                                     struct drm_property *property,
1383                                     uint64_t val);
1384 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1385                                     struct drm_plane_state *plane_state);
1386
1387 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1388                                     enum pipe pipe);
1389
1390 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1391                      const struct dpll *dpll);
1392 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1393 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1394
1395 /* modesetting asserts */
1396 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1397                            enum pipe pipe);
1398 void assert_pll(struct drm_i915_private *dev_priv,
1399                 enum pipe pipe, bool state);
1400 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1401 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1402 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1403 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1404 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1405 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1406                        enum pipe pipe, bool state);
1407 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1408 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1409 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1410 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1411 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1412 u32 intel_compute_tile_offset(int *x, int *y,
1413                               const struct intel_plane_state *state, int plane);
1414 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1415 void intel_finish_reset(struct drm_i915_private *dev_priv);
1416 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1417 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1418 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1419 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1420 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1421 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1422 unsigned int skl_cdclk_get_vco(unsigned int freq);
1423 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1424 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1425 void intel_dp_get_m_n(struct intel_crtc *crtc,
1426                       struct intel_crtc_state *pipe_config);
1427 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1428 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1429 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1430                         struct dpll *best_clock);
1431 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1432
1433 bool intel_crtc_active(struct intel_crtc *crtc);
1434 void hsw_enable_ips(struct intel_crtc *crtc);
1435 void hsw_disable_ips(struct intel_crtc *crtc);
1436 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1437 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1438                                  struct intel_crtc_state *pipe_config);
1439
1440 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1441 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1442
1443 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1444 {
1445         return i915_ggtt_offset(state->vma);
1446 }
1447
1448 u32 skl_plane_ctl_format(uint32_t pixel_format);
1449 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1450 u32 skl_plane_ctl_rotation(unsigned int rotation);
1451 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1452                      unsigned int rotation);
1453 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1454
1455 /* intel_csr.c */
1456 void intel_csr_ucode_init(struct drm_i915_private *);
1457 void intel_csr_load_program(struct drm_i915_private *);
1458 void intel_csr_ucode_fini(struct drm_i915_private *);
1459 void intel_csr_ucode_suspend(struct drm_i915_private *);
1460 void intel_csr_ucode_resume(struct drm_i915_private *);
1461
1462 /* intel_dp.c */
1463 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1464                    enum port port);
1465 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1466                              struct intel_connector *intel_connector);
1467 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1468                               int link_rate, uint8_t lane_count,
1469                               bool link_mst);
1470 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1471                                             int link_rate, uint8_t lane_count);
1472 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1473 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1474 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1475 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1476 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1477 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1478 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1479 bool intel_dp_compute_config(struct intel_encoder *encoder,
1480                              struct intel_crtc_state *pipe_config,
1481                              struct drm_connector_state *conn_state);
1482 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1483 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1484                                   bool long_hpd);
1485 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1486 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1487 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1488 void intel_edp_panel_on(struct intel_dp *intel_dp);
1489 void intel_edp_panel_off(struct intel_dp *intel_dp);
1490 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1491 void intel_dp_mst_suspend(struct drm_device *dev);
1492 void intel_dp_mst_resume(struct drm_device *dev);
1493 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1494 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1495 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1496 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1497 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1498 void intel_plane_destroy(struct drm_plane *plane);
1499 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1500                            struct intel_crtc_state *crtc_state);
1501 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1502                            struct intel_crtc_state *crtc_state);
1503 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1504                                unsigned int frontbuffer_bits);
1505 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1506                           unsigned int frontbuffer_bits);
1507
1508 void
1509 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1510                                        uint8_t dp_train_pat);
1511 void
1512 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1513 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1514 uint8_t
1515 intel_dp_voltage_max(struct intel_dp *intel_dp);
1516 uint8_t
1517 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1518 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1519                            uint8_t *link_bw, uint8_t *rate_select);
1520 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1521 bool
1522 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1523
1524 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1525 {
1526         return ~((1 << lane_count) - 1) & 0xf;
1527 }
1528
1529 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1530 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1531                           struct intel_dp_desc *desc);
1532 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1533 int intel_dp_link_required(int pixel_clock, int bpp);
1534 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1535 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1536                                   struct intel_digital_port *port);
1537
1538 /* intel_dp_aux_backlight.c */
1539 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1540
1541 /* intel_dp_mst.c */
1542 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1543 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1544 /* intel_dsi.c */
1545 void intel_dsi_init(struct drm_i915_private *dev_priv);
1546
1547 /* intel_dsi_dcs_backlight.c */
1548 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1549
1550 /* intel_dvo.c */
1551 void intel_dvo_init(struct drm_i915_private *dev_priv);
1552 /* intel_hotplug.c */
1553 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1554
1555
1556 /* legacy fbdev emulation in intel_fbdev.c */
1557 #ifdef CONFIG_DRM_FBDEV_EMULATION
1558 extern int intel_fbdev_init(struct drm_device *dev);
1559 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1560 extern void intel_fbdev_fini(struct drm_device *dev);
1561 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1562 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1563 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1564 #else
1565 static inline int intel_fbdev_init(struct drm_device *dev)
1566 {
1567         return 0;
1568 }
1569
1570 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1571 {
1572 }
1573
1574 static inline void intel_fbdev_fini(struct drm_device *dev)
1575 {
1576 }
1577
1578 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1579 {
1580 }
1581
1582 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1583 {
1584 }
1585
1586 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1587 {
1588 }
1589 #endif
1590
1591 /* intel_fbc.c */
1592 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1593                            struct drm_atomic_state *state);
1594 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1595 void intel_fbc_pre_update(struct intel_crtc *crtc,
1596                           struct intel_crtc_state *crtc_state,
1597                           struct intel_plane_state *plane_state);
1598 void intel_fbc_post_update(struct intel_crtc *crtc);
1599 void intel_fbc_init(struct drm_i915_private *dev_priv);
1600 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1601 void intel_fbc_enable(struct intel_crtc *crtc,
1602                       struct intel_crtc_state *crtc_state,
1603                       struct intel_plane_state *plane_state);
1604 void intel_fbc_disable(struct intel_crtc *crtc);
1605 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1606 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1607                           unsigned int frontbuffer_bits,
1608                           enum fb_op_origin origin);
1609 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1610                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1611 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1612 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1613
1614 /* intel_hdmi.c */
1615 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1616                      enum port port);
1617 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1618                                struct intel_connector *intel_connector);
1619 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1620 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1621                                struct intel_crtc_state *pipe_config,
1622                                struct drm_connector_state *conn_state);
1623 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1624
1625
1626 /* intel_lvds.c */
1627 void intel_lvds_init(struct drm_i915_private *dev_priv);
1628 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1629 bool intel_is_dual_link_lvds(struct drm_device *dev);
1630
1631
1632 /* intel_modes.c */
1633 int intel_connector_update_modes(struct drm_connector *connector,
1634                                  struct edid *edid);
1635 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1636 void intel_attach_force_audio_property(struct drm_connector *connector);
1637 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1638 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1639
1640
1641 /* intel_overlay.c */
1642 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1643 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1644 int intel_overlay_switch_off(struct intel_overlay *overlay);
1645 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1646                                   struct drm_file *file_priv);
1647 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1648                               struct drm_file *file_priv);
1649 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1650
1651
1652 /* intel_panel.c */
1653 int intel_panel_init(struct intel_panel *panel,
1654                      struct drm_display_mode *fixed_mode,
1655                      struct drm_display_mode *downclock_mode);
1656 void intel_panel_fini(struct intel_panel *panel);
1657 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1658                             struct drm_display_mode *adjusted_mode);
1659 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1660                              struct intel_crtc_state *pipe_config,
1661                              int fitting_mode);
1662 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1663                               struct intel_crtc_state *pipe_config,
1664                               int fitting_mode);
1665 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1666                                     u32 level, u32 max);
1667 int intel_panel_setup_backlight(struct drm_connector *connector,
1668                                 enum pipe pipe);
1669 void intel_panel_enable_backlight(struct intel_connector *connector);
1670 void intel_panel_disable_backlight(struct intel_connector *connector);
1671 void intel_panel_destroy_backlight(struct drm_connector *connector);
1672 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1673 extern struct drm_display_mode *intel_find_panel_downclock(
1674                                 struct drm_i915_private *dev_priv,
1675                                 struct drm_display_mode *fixed_mode,
1676                                 struct drm_connector *connector);
1677
1678 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1679 int intel_backlight_device_register(struct intel_connector *connector);
1680 void intel_backlight_device_unregister(struct intel_connector *connector);
1681 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1682 static int intel_backlight_device_register(struct intel_connector *connector)
1683 {
1684         return 0;
1685 }
1686 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1687 {
1688 }
1689 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1690
1691
1692 /* intel_psr.c */
1693 void intel_psr_enable(struct intel_dp *intel_dp);
1694 void intel_psr_disable(struct intel_dp *intel_dp);
1695 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1696                           unsigned frontbuffer_bits);
1697 void intel_psr_flush(struct drm_i915_private *dev_priv,
1698                      unsigned frontbuffer_bits,
1699                      enum fb_op_origin origin);
1700 void intel_psr_init(struct drm_i915_private *dev_priv);
1701 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1702                                    unsigned frontbuffer_bits);
1703
1704 /* intel_runtime_pm.c */
1705 int intel_power_domains_init(struct drm_i915_private *);
1706 void intel_power_domains_fini(struct drm_i915_private *);
1707 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1708 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1709 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1710 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1711 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1712 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1713 const char *
1714 intel_display_power_domain_str(enum intel_display_power_domain domain);
1715
1716 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1717                                     enum intel_display_power_domain domain);
1718 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1719                                       enum intel_display_power_domain domain);
1720 void intel_display_power_get(struct drm_i915_private *dev_priv,
1721                              enum intel_display_power_domain domain);
1722 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1723                                         enum intel_display_power_domain domain);
1724 void intel_display_power_put(struct drm_i915_private *dev_priv,
1725                              enum intel_display_power_domain domain);
1726
1727 static inline void
1728 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1729 {
1730         WARN_ONCE(dev_priv->pm.suspended,
1731                   "Device suspended during HW access\n");
1732 }
1733
1734 static inline void
1735 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1736 {
1737         assert_rpm_device_not_suspended(dev_priv);
1738         WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1739                   "RPM wakelock ref not held during HW access");
1740 }
1741
1742 /**
1743  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1744  * @dev_priv: i915 device instance
1745  *
1746  * This function disable asserts that check if we hold an RPM wakelock
1747  * reference, while keeping the device-not-suspended checks still enabled.
1748  * It's meant to be used only in special circumstances where our rule about
1749  * the wakelock refcount wrt. the device power state doesn't hold. According
1750  * to this rule at any point where we access the HW or want to keep the HW in
1751  * an active state we must hold an RPM wakelock reference acquired via one of
1752  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1753  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1754  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1755  * users should avoid using this function.
1756  *
1757  * Any calls to this function must have a symmetric call to
1758  * enable_rpm_wakeref_asserts().
1759  */
1760 static inline void
1761 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1762 {
1763         atomic_inc(&dev_priv->pm.wakeref_count);
1764 }
1765
1766 /**
1767  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1768  * @dev_priv: i915 device instance
1769  *
1770  * This function re-enables the RPM assert checks after disabling them with
1771  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1772  * circumstances otherwise its use should be avoided.
1773  *
1774  * Any calls to this function must have a symmetric call to
1775  * disable_rpm_wakeref_asserts().
1776  */
1777 static inline void
1778 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1779 {
1780         atomic_dec(&dev_priv->pm.wakeref_count);
1781 }
1782
1783 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1784 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1785 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1786 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1787
1788 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1789
1790 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1791                              bool override, unsigned int mask);
1792 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1793                           enum dpio_channel ch, bool override);
1794
1795
1796 /* intel_pm.c */
1797 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1798 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1799 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1800 void intel_update_watermarks(struct intel_crtc *crtc);
1801 void intel_init_pm(struct drm_i915_private *dev_priv);
1802 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1803 void intel_pm_setup(struct drm_i915_private *dev_priv);
1804 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1805 void intel_gpu_ips_teardown(void);
1806 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1807 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1808 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1809 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1810 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1811 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1812 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1813 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1814 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1815 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1816 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1817                     struct intel_rps_client *rps,
1818                     unsigned long submitted);
1819 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1820 void vlv_wm_get_hw_state(struct drm_device *dev);
1821 void ilk_wm_get_hw_state(struct drm_device *dev);
1822 void skl_wm_get_hw_state(struct drm_device *dev);
1823 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1824                           struct skl_ddb_allocation *ddb /* out */);
1825 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1826                               struct skl_pipe_wm *out);
1827 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1828 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1829 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1830 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1831 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1832                          const struct skl_wm_level *l2);
1833 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1834                                  const struct skl_ddb_entry *ddb,
1835                                  int ignore);
1836 bool ilk_disable_lp_wm(struct drm_device *dev);
1837 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1838 static inline int intel_enable_rc6(void)
1839 {
1840         return i915.enable_rc6;
1841 }
1842
1843 /* intel_sdvo.c */
1844 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1845                      i915_reg_t reg, enum port port);
1846
1847
1848 /* intel_sprite.c */
1849 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1850                              int usecs);
1851 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1852                                               enum pipe pipe, int plane);
1853 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1854                               struct drm_file *file_priv);
1855 void intel_pipe_update_start(struct intel_crtc *crtc);
1856 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1857
1858 /* intel_tv.c */
1859 void intel_tv_init(struct drm_i915_private *dev_priv);
1860
1861 /* intel_atomic.c */
1862 int intel_connector_atomic_get_property(struct drm_connector *connector,
1863                                         const struct drm_connector_state *state,
1864                                         struct drm_property *property,
1865                                         uint64_t *val);
1866 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1867 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1868                                struct drm_crtc_state *state);
1869 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1870 void intel_atomic_state_clear(struct drm_atomic_state *);
1871
1872 static inline struct intel_crtc_state *
1873 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1874                             struct intel_crtc *crtc)
1875 {
1876         struct drm_crtc_state *crtc_state;
1877         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1878         if (IS_ERR(crtc_state))
1879                 return ERR_CAST(crtc_state);
1880
1881         return to_intel_crtc_state(crtc_state);
1882 }
1883
1884 static inline struct intel_crtc_state *
1885 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1886                                      struct intel_crtc *crtc)
1887 {
1888         struct drm_crtc_state *crtc_state;
1889
1890         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1891
1892         if (crtc_state)
1893                 return to_intel_crtc_state(crtc_state);
1894         else
1895                 return NULL;
1896 }
1897
1898 static inline struct intel_plane_state *
1899 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1900                                       struct intel_plane *plane)
1901 {
1902         struct drm_plane_state *plane_state;
1903
1904         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1905
1906         return to_intel_plane_state(plane_state);
1907 }
1908
1909 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1910                                struct intel_crtc *intel_crtc,
1911                                struct intel_crtc_state *crtc_state);
1912
1913 /* intel_atomic_plane.c */
1914 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1915 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1916 void intel_plane_destroy_state(struct drm_plane *plane,
1917                                struct drm_plane_state *state);
1918 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1919 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1920                                         struct intel_plane_state *intel_state);
1921
1922 /* intel_color.c */
1923 void intel_color_init(struct drm_crtc *crtc);
1924 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1925 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1926 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1927
1928 /* intel_lspcon.c */
1929 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1930 void lspcon_resume(struct intel_lspcon *lspcon);
1931 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1932
1933 /* intel_pipe_crc.c */
1934 int intel_pipe_crc_create(struct drm_minor *minor);
1935 #ifdef CONFIG_DEBUG_FS
1936 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1937                               size_t *values_cnt);
1938 #else
1939 #define intel_crtc_set_crc_source NULL
1940 #endif
1941 extern const struct file_operations i915_display_crc_ctl_fops;
1942 #endif /* __INTEL_DRV_H__ */