drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 133
 134 static int
 135 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 136 {
 137         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 138
 139         switch (max_link_bw) {
 140         case DP_LINK_BW_1_62:
 141         case DP_LINK_BW_2_7:
 142         case DP_LINK_BW_5_4:
 143                 break;
 144         default:
 145                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 146                      max_link_bw);
 147                 max_link_bw = DP_LINK_BW_1_62;
 148                 break;
 149         }
 150         return max_link_bw;
 151 }
 152
 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 154 {
 155         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 156         u8 source_max, sink_max;
 157
 158         source_max = intel_dig_port->max_lanes;
 159         sink_max = intel_dp->max_sink_lane_count;
 160
 161         return min(source_max, sink_max);
 162 }
 163
 164 int
 165 intel_dp_link_required(int pixel_clock, int bpp)
 166 {
 167         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 168         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 169 }
 170
 171 int
 172 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 173 {
 174         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 175          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 176          * is transmitted every LS_Clk per lane, there is no need to account for
 177          * the channel encoding that is done in the PHY layer here.
 178          */
 179
 180         return max_link_clock * max_lanes;
 181 }
 182
 183 static int
 184 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 185 {
 186         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 187         struct intel_encoder *encoder = &intel_dig_port->base;
 188         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 189         int max_dotclk = dev_priv->max_dotclk_freq;
 190         int ds_max_dotclk;
 191
 192         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 193
 194         if (type != DP_DS_PORT_TYPE_VGA)
 195                 return max_dotclk;
 196
 197         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 198                                                     intel_dp->downstream_ports);
 199
 200         if (ds_max_dotclk != 0)
 201                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 202
 203         return max_dotclk;
 204 }
 205
 206 static int
 207 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 208 {
 209         if (intel_dp->num_sink_rates) {
 210                 *sink_rates = intel_dp->sink_rates;
 211                 return intel_dp->num_sink_rates;
 212         }
 213
 214         *sink_rates = default_rates;
 215
 216         return (intel_dp->max_sink_link_bw >> 3) + 1;
 217 }
 218
 219 static int
 220 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
 221 {
 222         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 223         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 224         int size;
 225
 226         if (IS_GEN9_LP(dev_priv)) {
 227                 *source_rates = bxt_rates;
 228                 size = ARRAY_SIZE(bxt_rates);
 229         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 230                 *source_rates = skl_rates;
 231                 size = ARRAY_SIZE(skl_rates);
 232         } else {
 233                 *source_rates = default_rates;
 234                 size = ARRAY_SIZE(default_rates);
 235         }
 236
 237         /* This depends on the fact that 5.4 is last value in the array */
 238         if (!intel_dp_source_supports_hbr2(intel_dp))
 239                 size--;
 240
 241         return size;
 242 }
 243
 244 static int intersect_rates(const int *source_rates, int source_len,
 245                            const int *sink_rates, int sink_len,
 246                            int *common_rates)
 247 {
 248         int i = 0, j = 0, k = 0;
 249
 250         while (i < source_len && j < sink_len) {
 251                 if (source_rates[i] == sink_rates[j]) {
 252                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 253                                 return k;
 254                         common_rates[k] = source_rates[i];
 255                         ++k;
 256                         ++i;
 257                         ++j;
 258                 } else if (source_rates[i] < sink_rates[j]) {
 259                         ++i;
 260                 } else {
 261                         ++j;
 262                 }
 263         }
 264         return k;
 265 }
 266
 267 static int intel_dp_common_rates(struct intel_dp *intel_dp,
 268                                  int *common_rates)
 269 {
 270         const int *source_rates, *sink_rates;
 271         int source_len, sink_len;
 272
 273         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
 274         source_len = intel_dp_source_rates(intel_dp, &source_rates);
 275
 276         return intersect_rates(source_rates, source_len,
 277                                sink_rates, sink_len,
 278                                common_rates);
 279 }
 280
 281 static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
 282                                     int *common_rates, int link_rate)
 283 {
 284         int common_len;
 285         int index;
 286
 287         common_len = intel_dp_common_rates(intel_dp, common_rates);
 288         for (index = 0; index < common_len; index++) {
 289                 if (link_rate == common_rates[common_len - index - 1])
 290                         return common_len - index - 1;
 291         }
 292
 293         return -1;
 294 }
 295
 296 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 297                                             int link_rate, uint8_t lane_count)
 298 {
 299         int common_rates[DP_MAX_SUPPORTED_RATES];
 300         int link_rate_index;
 301
 302         link_rate_index = intel_dp_link_rate_index(intel_dp,
 303                                                    common_rates,
 304                                                    link_rate);
 305         if (link_rate_index > 0) {
 306                 intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]);
 307                 intel_dp->max_sink_lane_count = lane_count;
 308         } else if (lane_count > 1) {
 309                 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
 310                 intel_dp->max_sink_lane_count = lane_count >> 1;
 311         } else {
 312                 DRM_ERROR("Link Training Unsuccessful\n");
 313                 return -1;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static enum drm_mode_status
 320 intel_dp_mode_valid(struct drm_connector *connector,
 321                     struct drm_display_mode *mode)
 322 {
 323         struct intel_dp *intel_dp = intel_attached_dp(connector);
 324         struct intel_connector *intel_connector = to_intel_connector(connector);
 325         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 326         int target_clock = mode->clock;
 327         int max_rate, mode_rate, max_lanes, max_link_clock;
 328         int max_dotclk;
 329
 330         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 331
 332         if (is_edp(intel_dp) && fixed_mode) {
 333                 if (mode->hdisplay > fixed_mode->hdisplay)
 334                         return MODE_PANEL;
 335
 336                 if (mode->vdisplay > fixed_mode->vdisplay)
 337                         return MODE_PANEL;
 338
 339                 target_clock = fixed_mode->clock;
 340         }
 341
 342         max_link_clock = intel_dp_max_link_rate(intel_dp);
 343         max_lanes = intel_dp_max_lane_count(intel_dp);
 344
 345         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 346         mode_rate = intel_dp_link_required(target_clock, 18);
 347
 348         if (mode_rate > max_rate || target_clock > max_dotclk)
 349                 return MODE_CLOCK_HIGH;
 350
 351         if (mode->clock < 10000)
 352                 return MODE_CLOCK_LOW;
 353
 354         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 355                 return MODE_H_ILLEGAL;
 356
 357         return MODE_OK;
 358 }
 359
 360 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 361 {
 362         int     i;
 363         uint32_t v = 0;
 364
 365         if (src_bytes > 4)
 366                 src_bytes = 4;
 367         for (i = 0; i < src_bytes; i++)
 368                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 369         return v;
 370 }
 371
 372 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 373 {
 374         int i;
 375         if (dst_bytes > 4)
 376                 dst_bytes = 4;
 377         for (i = 0; i < dst_bytes; i++)
 378                 dst[i] = src >> ((3-i) * 8);
 379 }
 380
 381 static void
 382 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 383                                     struct intel_dp *intel_dp);
 384 static void
 385 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 386                                               struct intel_dp *intel_dp,
 387                                               bool force_disable_vdd);
 388 static void
 389 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 390
 391 static void pps_lock(struct intel_dp *intel_dp)
 392 {
 393         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 394         struct intel_encoder *encoder = &intel_dig_port->base;
 395         struct drm_device *dev = encoder->base.dev;
 396         struct drm_i915_private *dev_priv = to_i915(dev);
 397         enum intel_display_power_domain power_domain;
 398
 399         /*
 400          * See vlv_power_sequencer_reset() why we need
 401          * a power domain reference here.
 402          */
 403         power_domain = intel_display_port_aux_power_domain(encoder);
 404         intel_display_power_get(dev_priv, power_domain);
 405
 406         mutex_lock(&dev_priv->pps_mutex);
 407 }
 408
 409 static void pps_unlock(struct intel_dp *intel_dp)
 410 {
 411         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 412         struct intel_encoder *encoder = &intel_dig_port->base;
 413         struct drm_device *dev = encoder->base.dev;
 414         struct drm_i915_private *dev_priv = to_i915(dev);
 415         enum intel_display_power_domain power_domain;
 416
 417         mutex_unlock(&dev_priv->pps_mutex);
 418
 419         power_domain = intel_display_port_aux_power_domain(encoder);
 420         intel_display_power_put(dev_priv, power_domain);
 421 }
 422
 423 static void
 424 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 425 {
 426         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 427         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 428         enum pipe pipe = intel_dp->pps_pipe;
 429         bool pll_enabled, release_cl_override = false;
 430         enum dpio_phy phy = DPIO_PHY(pipe);
 431         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 432         uint32_t DP;
 433
 434         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 435                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 436                  pipe_name(pipe), port_name(intel_dig_port->port)))
 437                 return;
 438
 439         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 440                       pipe_name(pipe), port_name(intel_dig_port->port));
 441
 442         /* Preserve the BIOS-computed detected bit. This is
 443          * supposed to be read-only.
 444          */
 445         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 446         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 447         DP |= DP_PORT_WIDTH(1);
 448         DP |= DP_LINK_TRAIN_PAT_1;
 449
 450         if (IS_CHERRYVIEW(dev_priv))
 451                 DP |= DP_PIPE_SELECT_CHV(pipe);
 452         else if (pipe == PIPE_B)
 453                 DP |= DP_PIPEB_SELECT;
 454
 455         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 456
 457         /*
 458          * The DPLL for the pipe must be enabled for this to work.
 459          * So enable temporarily it if it's not already enabled.
 460          */
 461         if (!pll_enabled) {
 462                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 463                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 464
 465                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 466                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 467                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 468                                   pipe_name(pipe));
 469                         return;
 470                 }
 471         }
 472
 473         /*
 474          * Similar magic as in intel_dp_enable_port().
 475          * We _must_ do this port enable + disable trick
 476          * to make this power seqeuencer lock onto the port.
 477          * Otherwise even VDD force bit won't work.
 478          */
 479         I915_WRITE(intel_dp->output_reg, DP);
 480         POSTING_READ(intel_dp->output_reg);
 481
 482         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 483         POSTING_READ(intel_dp->output_reg);
 484
 485         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 486         POSTING_READ(intel_dp->output_reg);
 487
 488         if (!pll_enabled) {
 489                 vlv_force_pll_off(dev_priv, pipe);
 490
 491                 if (release_cl_override)
 492                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 493         }
 494 }
 495
 496 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 497 {
 498         struct intel_encoder *encoder;
 499         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 500
 501         /*
 502          * We don't have power sequencer currently.
 503          * Pick one that's not used by other ports.
 504          */
 505         for_each_intel_encoder(&dev_priv->drm, encoder) {
 506                 struct intel_dp *intel_dp;
 507
 508                 if (encoder->type != INTEL_OUTPUT_DP &&
 509                     encoder->type != INTEL_OUTPUT_EDP)
 510                         continue;
 511
 512                 intel_dp = enc_to_intel_dp(&encoder->base);
 513
 514                 if (encoder->type == INTEL_OUTPUT_EDP) {
 515                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 516                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 517
 518                         if (intel_dp->pps_pipe != INVALID_PIPE)
 519                                 pipes &= ~(1 << intel_dp->pps_pipe);
 520                 } else {
 521                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 522
 523                         if (intel_dp->active_pipe != INVALID_PIPE)
 524                                 pipes &= ~(1 << intel_dp->active_pipe);
 525                 }
 526         }
 527
 528         if (pipes == 0)
 529                 return INVALID_PIPE;
 530
 531         return ffs(pipes) - 1;
 532 }
 533
 534 static enum pipe
 535 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 536 {
 537         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 538         struct drm_device *dev = intel_dig_port->base.base.dev;
 539         struct drm_i915_private *dev_priv = to_i915(dev);
 540         enum pipe pipe;
 541
 542         lockdep_assert_held(&dev_priv->pps_mutex);
 543
 544         /* We should never land here with regular DP ports */
 545         WARN_ON(!is_edp(intel_dp));
 546
 547         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 548                 intel_dp->active_pipe != intel_dp->pps_pipe);
 549
 550         if (intel_dp->pps_pipe != INVALID_PIPE)
 551                 return intel_dp->pps_pipe;
 552
 553         pipe = vlv_find_free_pps(dev_priv);
 554
 555         /*
 556          * Didn't find one. This should not happen since there
 557          * are two power sequencers and up to two eDP ports.
 558          */
 559         if (WARN_ON(pipe == INVALID_PIPE))
 560                 pipe = PIPE_A;
 561
 562         vlv_steal_power_sequencer(dev, pipe);
 563         intel_dp->pps_pipe = pipe;
 564
 565         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 566                       pipe_name(intel_dp->pps_pipe),
 567                       port_name(intel_dig_port->port));
 568
 569         /* init power sequencer on this pipe and port */
 570         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 571         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
 572
 573         /*
 574          * Even vdd force doesn't work until we've made
 575          * the power sequencer lock in on the port.
 576          */
 577         vlv_power_sequencer_kick(intel_dp);
 578
 579         return intel_dp->pps_pipe;
 580 }
 581
 582 static int
 583 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 584 {
 585         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 586         struct drm_device *dev = intel_dig_port->base.base.dev;
 587         struct drm_i915_private *dev_priv = to_i915(dev);
 588
 589         lockdep_assert_held(&dev_priv->pps_mutex);
 590
 591         /* We should never land here with regular DP ports */
 592         WARN_ON(!is_edp(intel_dp));
 593
 594         /*
 595          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 596          * mapping needs to be retrieved from VBT, for now just hard-code to
 597          * use instance #0 always.
 598          */
 599         if (!intel_dp->pps_reset)
 600                 return 0;
 601
 602         intel_dp->pps_reset = false;
 603
 604         /*
 605          * Only the HW needs to be reprogrammed, the SW state is fixed and
 606          * has been setup during connector init.
 607          */
 608         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 609
 610         return 0;
 611 }
 612
 613 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 614                                enum pipe pipe);
 615
 616 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 617                                enum pipe pipe)
 618 {
 619         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 620 }
 621
 622 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 623                                 enum pipe pipe)
 624 {
 625         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 626 }
 627
 628 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 629                          enum pipe pipe)
 630 {
 631         return true;
 632 }
 633
 634 static enum pipe
 635 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 636                      enum port port,
 637                      vlv_pipe_check pipe_check)
 638 {
 639         enum pipe pipe;
 640
 641         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 642                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 643                         PANEL_PORT_SELECT_MASK;
 644
 645                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 646                         continue;
 647
 648                 if (!pipe_check(dev_priv, pipe))
 649                         continue;
 650
 651                 return pipe;
 652         }
 653
 654         return INVALID_PIPE;
 655 }
 656
 657 static void
 658 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 659 {
 660         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 661         struct drm_device *dev = intel_dig_port->base.base.dev;
 662         struct drm_i915_private *dev_priv = to_i915(dev);
 663         enum port port = intel_dig_port->port;
 664
 665         lockdep_assert_held(&dev_priv->pps_mutex);
 666
 667         /* try to find a pipe with this port selected */
 668         /* first pick one where the panel is on */
 669         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 670                                                   vlv_pipe_has_pp_on);
 671         /* didn't find one? pick one where vdd is on */
 672         if (intel_dp->pps_pipe == INVALID_PIPE)
 673                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 674                                                           vlv_pipe_has_vdd_on);
 675         /* didn't find one? pick one with just the correct port */
 676         if (intel_dp->pps_pipe == INVALID_PIPE)
 677                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 678                                                           vlv_pipe_any);
 679
 680         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 681         if (intel_dp->pps_pipe == INVALID_PIPE) {
 682                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 683                               port_name(port));
 684                 return;
 685         }
 686
 687         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 688                       port_name(port), pipe_name(intel_dp->pps_pipe));
 689
 690         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 691         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 692 }
 693
 694 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 695 {
 696         struct drm_device *dev = &dev_priv->drm;
 697         struct intel_encoder *encoder;
 698
 699         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 700                     !IS_GEN9_LP(dev_priv)))
 701                 return;
 702
 703         /*
 704          * We can't grab pps_mutex here due to deadlock with power_domain
 705          * mutex when power_domain functions are called while holding pps_mutex.
 706          * That also means that in order to use pps_pipe the code needs to
 707          * hold both a power domain reference and pps_mutex, and the power domain
 708          * reference get/put must be done while _not_ holding pps_mutex.
 709          * pps_{lock,unlock}() do these steps in the correct order, so one
 710          * should use them always.
 711          */
 712
 713         for_each_intel_encoder(dev, encoder) {
 714                 struct intel_dp *intel_dp;
 715
 716                 if (encoder->type != INTEL_OUTPUT_DP &&
 717                     encoder->type != INTEL_OUTPUT_EDP)
 718                         continue;
 719
 720                 intel_dp = enc_to_intel_dp(&encoder->base);
 721
 722                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 723
 724                 if (encoder->type != INTEL_OUTPUT_EDP)
 725                         continue;
 726
 727                 if (IS_GEN9_LP(dev_priv))
 728                         intel_dp->pps_reset = true;
 729                 else
 730                         intel_dp->pps_pipe = INVALID_PIPE;
 731         }
 732 }
 733
 734 struct pps_registers {
 735         i915_reg_t pp_ctrl;
 736         i915_reg_t pp_stat;
 737         i915_reg_t pp_on;
 738         i915_reg_t pp_off;
 739         i915_reg_t pp_div;
 740 };
 741
 742 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 743                                     struct intel_dp *intel_dp,
 744                                     struct pps_registers *regs)
 745 {
 746         int pps_idx = 0;
 747
 748         memset(regs, 0, sizeof(*regs));
 749
 750         if (IS_GEN9_LP(dev_priv))
 751                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 752         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 753                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 754
 755         regs->pp_ctrl = PP_CONTROL(pps_idx);
 756         regs->pp_stat = PP_STATUS(pps_idx);
 757         regs->pp_on = PP_ON_DELAYS(pps_idx);
 758         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 759         if (!IS_GEN9_LP(dev_priv))
 760                 regs->pp_div = PP_DIVISOR(pps_idx);
 761 }
 762
 763 static i915_reg_t
 764 _pp_ctrl_reg(struct intel_dp *intel_dp)
 765 {
 766         struct pps_registers regs;
 767
 768         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 769                                 &regs);
 770
 771         return regs.pp_ctrl;
 772 }
 773
 774 static i915_reg_t
 775 _pp_stat_reg(struct intel_dp *intel_dp)
 776 {
 777         struct pps_registers regs;
 778
 779         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 780                                 &regs);
 781
 782         return regs.pp_stat;
 783 }
 784
 785 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 786    This function only applicable when panel PM state is not to be tracked */
 787 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 788                               void *unused)
 789 {
 790         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 791                                                  edp_notifier);
 792         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 793         struct drm_i915_private *dev_priv = to_i915(dev);
 794
 795         if (!is_edp(intel_dp) || code != SYS_RESTART)
 796                 return 0;
 797
 798         pps_lock(intel_dp);
 799
 800         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 801                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 802                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 803                 u32 pp_div;
 804
 805                 pp_ctrl_reg = PP_CONTROL(pipe);
 806                 pp_div_reg  = PP_DIVISOR(pipe);
 807                 pp_div = I915_READ(pp_div_reg);
 808                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 809
 810                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 811                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 812                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 813                 msleep(intel_dp->panel_power_cycle_delay);
 814         }
 815
 816         pps_unlock(intel_dp);
 817
 818         return 0;
 819 }
 820
 821 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 822 {
 823         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 824         struct drm_i915_private *dev_priv = to_i915(dev);
 825
 826         lockdep_assert_held(&dev_priv->pps_mutex);
 827
 828         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 829             intel_dp->pps_pipe == INVALID_PIPE)
 830                 return false;
 831
 832         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 833 }
 834
 835 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 836 {
 837         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 838         struct drm_i915_private *dev_priv = to_i915(dev);
 839
 840         lockdep_assert_held(&dev_priv->pps_mutex);
 841
 842         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 843             intel_dp->pps_pipe == INVALID_PIPE)
 844                 return false;
 845
 846         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 847 }
 848
 849 static void
 850 intel_dp_check_edp(struct intel_dp *intel_dp)
 851 {
 852         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 853         struct drm_i915_private *dev_priv = to_i915(dev);
 854
 855         if (!is_edp(intel_dp))
 856                 return;
 857
 858         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 859                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 860                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 861                               I915_READ(_pp_stat_reg(intel_dp)),
 862                               I915_READ(_pp_ctrl_reg(intel_dp)));
 863         }
 864 }
 865
 866 static uint32_t
 867 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 868 {
 869         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 870         struct drm_device *dev = intel_dig_port->base.base.dev;
 871         struct drm_i915_private *dev_priv = to_i915(dev);
 872         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 873         uint32_t status;
 874         bool done;
 875
 876 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 877         if (has_aux_irq)
 878                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 879                                           msecs_to_jiffies_timeout(10));
 880         else
 881                 done = wait_for(C, 10) == 0;
 882         if (!done)
 883                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 884                           has_aux_irq);
 885 #undef C
 886
 887         return status;
 888 }
 889
 890 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 891 {
 892         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 893         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 894
 895         if (index)
 896                 return 0;
 897
 898         /*
 899          * The clock divider is based off the hrawclk, and would like to run at
 900          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 901          */
 902         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 903 }
 904
 905 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 906 {
 907         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 908         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 909
 910         if (index)
 911                 return 0;
 912
 913         /*
 914          * The clock divider is based off the cdclk or PCH rawclk, and would
 915          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 916          * divide by 2000 and use that
 917          */
 918         if (intel_dig_port->port == PORT_A)
 919                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 920         else
 921                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 922 }
 923
 924 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 925 {
 926         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 927         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 928
 929         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 930                 /* Workaround for non-ULT HSW */
 931                 switch (index) {
 932                 case 0: return 63;
 933                 case 1: return 72;
 934                 default: return 0;
 935                 }
 936         }
 937
 938         return ilk_get_aux_clock_divider(intel_dp, index);
 939 }
 940
 941 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 942 {
 943         /*
 944          * SKL doesn't need us to program the AUX clock divider (Hardware will
 945          * derive the clock from CDCLK automatically). We still implement the
 946          * get_aux_clock_divider vfunc to plug-in into the existing code.
 947          */
 948         return index ? 0 : 1;
 949 }
 950
 951 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 952                                      bool has_aux_irq,
 953                                      int send_bytes,
 954                                      uint32_t aux_clock_divider)
 955 {
 956         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 957         struct drm_i915_private *dev_priv =
 958                         to_i915(intel_dig_port->base.base.dev);
 959         uint32_t precharge, timeout;
 960
 961         if (IS_GEN6(dev_priv))
 962                 precharge = 3;
 963         else
 964                 precharge = 5;
 965
 966         if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
 967                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 968         else
 969                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 970
 971         return DP_AUX_CH_CTL_SEND_BUSY |
 972                DP_AUX_CH_CTL_DONE |
 973                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 974                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 975                timeout |
 976                DP_AUX_CH_CTL_RECEIVE_ERROR |
 977                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 978                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 979                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 980 }
 981
 982 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 983                                       bool has_aux_irq,
 984                                       int send_bytes,
 985                                       uint32_t unused)
 986 {
 987         return DP_AUX_CH_CTL_SEND_BUSY |
 988                DP_AUX_CH_CTL_DONE |
 989                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 990                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 991                DP_AUX_CH_CTL_TIME_OUT_1600us |
 992                DP_AUX_CH_CTL_RECEIVE_ERROR |
 993                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 994                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
 995                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 996 }
 997
 998 static int
 999 intel_dp_aux_ch(struct intel_dp *intel_dp,
1000                 const uint8_t *send, int send_bytes,
1001                 uint8_t *recv, int recv_size)
1002 {
1003         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1004         struct drm_i915_private *dev_priv =
1005                         to_i915(intel_dig_port->base.base.dev);
1006         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1007         uint32_t aux_clock_divider;
1008         int i, ret, recv_bytes;
1009         uint32_t status;
1010         int try, clock = 0;
1011         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1012         bool vdd;
1013
1014         pps_lock(intel_dp);
1015
1016         /*
1017          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1018          * In such cases we want to leave VDD enabled and it's up to upper layers
1019          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1020          * ourselves.
1021          */
1022         vdd = edp_panel_vdd_on(intel_dp);
1023
1024         /* dp aux is extremely sensitive to irq latency, hence request the
1025          * lowest possible wakeup latency and so prevent the cpu from going into
1026          * deep sleep states.
1027          */
1028         pm_qos_update_request(&dev_priv->pm_qos, 0);
1029
1030         intel_dp_check_edp(intel_dp);
1031
1032         /* Try to wait for any previous AUX channel activity */
1033         for (try = 0; try < 3; try++) {
1034                 status = I915_READ_NOTRACE(ch_ctl);
1035                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1036                         break;
1037                 msleep(1);
1038         }
1039
1040         if (try == 3) {
1041                 static u32 last_status = -1;
1042                 const u32 status = I915_READ(ch_ctl);
1043
1044                 if (status != last_status) {
1045                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1046                              status);
1047                         last_status = status;
1048                 }
1049
1050                 ret = -EBUSY;
1051                 goto out;
1052         }
1053
1054         /* Only 5 data registers! */
1055         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1056                 ret = -E2BIG;
1057                 goto out;
1058         }
1059
1060         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1061                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1062                                                           has_aux_irq,
1063                                                           send_bytes,
1064                                                           aux_clock_divider);
1065
1066                 /* Must try at least 3 times according to DP spec */
1067                 for (try = 0; try < 5; try++) {
1068                         /* Load the send data into the aux channel data registers */
1069                         for (i = 0; i < send_bytes; i += 4)
1070                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1071                                            intel_dp_pack_aux(send + i,
1072                                                              send_bytes - i));
1073
1074                         /* Send the command and wait for it to complete */
1075                         I915_WRITE(ch_ctl, send_ctl);
1076
1077                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1078
1079                         /* Clear done status and any errors */
1080                         I915_WRITE(ch_ctl,
1081                                    status |
1082                                    DP_AUX_CH_CTL_DONE |
1083                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1084                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1085
1086                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1087                                 continue;
1088
1089                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1090                          *   400us delay required for errors and timeouts
1091                          *   Timeout errors from the HW already meet this
1092                          *   requirement so skip to next iteration
1093                          */
1094                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1095                                 usleep_range(400, 500);
1096                                 continue;
1097                         }
1098                         if (status & DP_AUX_CH_CTL_DONE)
1099                                 goto done;
1100                 }
1101         }
1102
1103         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1104                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1105                 ret = -EBUSY;
1106                 goto out;
1107         }
1108
1109 done:
1110         /* Check for timeout or receive error.
1111          * Timeouts occur when the sink is not connected
1112          */
1113         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1114                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1115                 ret = -EIO;
1116                 goto out;
1117         }
1118
1119         /* Timeouts occur when the device isn't connected, so they're
1120          * "normal" -- don't fill the kernel log with these */
1121         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1122                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1123                 ret = -ETIMEDOUT;
1124                 goto out;
1125         }
1126
1127         /* Unload any bytes sent back from the other side */
1128         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1129                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1130
1131         /*
1132          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1133          * We have no idea of what happened so we return -EBUSY so
1134          * drm layer takes care for the necessary retries.
1135          */
1136         if (recv_bytes == 0 || recv_bytes > 20) {
1137                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1138                               recv_bytes);
1139                 /*
1140                  * FIXME: This patch was created on top of a series that
1141                  * organize the retries at drm level. There EBUSY should
1142                  * also take care for 1ms wait before retrying.
1143                  * That aux retries re-org is still needed and after that is
1144                  * merged we remove this sleep from here.
1145                  */
1146                 usleep_range(1000, 1500);
1147                 ret = -EBUSY;
1148                 goto out;
1149         }
1150
1151         if (recv_bytes > recv_size)
1152                 recv_bytes = recv_size;
1153
1154         for (i = 0; i < recv_bytes; i += 4)
1155                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1156                                     recv + i, recv_bytes - i);
1157
1158         ret = recv_bytes;
1159 out:
1160         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1161
1162         if (vdd)
1163                 edp_panel_vdd_off(intel_dp, false);
1164
1165         pps_unlock(intel_dp);
1166
1167         return ret;
1168 }
1169
1170 #define BARE_ADDRESS_SIZE       3
1171 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1172 static ssize_t
1173 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1174 {
1175         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1176         uint8_t txbuf[20], rxbuf[20];
1177         size_t txsize, rxsize;
1178         int ret;
1179
1180         txbuf[0] = (msg->request << 4) |
1181                 ((msg->address >> 16) & 0xf);
1182         txbuf[1] = (msg->address >> 8) & 0xff;
1183         txbuf[2] = msg->address & 0xff;
1184         txbuf[3] = msg->size - 1;
1185
1186         switch (msg->request & ~DP_AUX_I2C_MOT) {
1187         case DP_AUX_NATIVE_WRITE:
1188         case DP_AUX_I2C_WRITE:
1189         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1190                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1191                 rxsize = 2; /* 0 or 1 data bytes */
1192
1193                 if (WARN_ON(txsize > 20))
1194                         return -E2BIG;
1195
1196                 WARN_ON(!msg->buffer != !msg->size);
1197
1198                 if (msg->buffer)
1199                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1200
1201                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1202                 if (ret > 0) {
1203                         msg->reply = rxbuf[0] >> 4;
1204
1205                         if (ret > 1) {
1206                                 /* Number of bytes written in a short write. */
1207                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1208                         } else {
1209                                 /* Return payload size. */
1210                                 ret = msg->size;
1211                         }
1212                 }
1213                 break;
1214
1215         case DP_AUX_NATIVE_READ:
1216         case DP_AUX_I2C_READ:
1217                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1218                 rxsize = msg->size + 1;
1219
1220                 if (WARN_ON(rxsize > 20))
1221                         return -E2BIG;
1222
1223                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1224                 if (ret > 0) {
1225                         msg->reply = rxbuf[0] >> 4;
1226                         /*
1227                          * Assume happy day, and copy the data. The caller is
1228                          * expected to check msg->reply before touching it.
1229                          *
1230                          * Return payload size.
1231                          */
1232                         ret--;
1233                         memcpy(msg->buffer, rxbuf + 1, ret);
1234                 }
1235                 break;
1236
1237         default:
1238                 ret = -EINVAL;
1239                 break;
1240         }
1241
1242         return ret;
1243 }
1244
1245 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1246                                 enum port port)
1247 {
1248         const struct ddi_vbt_port_info *info =
1249                 &dev_priv->vbt.ddi_port_info[port];
1250         enum port aux_port;
1251
1252         if (!info->alternate_aux_channel) {
1253                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1254                               port_name(port), port_name(port));
1255                 return port;
1256         }
1257
1258         switch (info->alternate_aux_channel) {
1259         case DP_AUX_A:
1260                 aux_port = PORT_A;
1261                 break;
1262         case DP_AUX_B:
1263                 aux_port = PORT_B;
1264                 break;
1265         case DP_AUX_C:
1266                 aux_port = PORT_C;
1267                 break;
1268         case DP_AUX_D:
1269                 aux_port = PORT_D;
1270                 break;
1271         default:
1272                 MISSING_CASE(info->alternate_aux_channel);
1273                 aux_port = PORT_A;
1274                 break;
1275         }
1276
1277         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1278                       port_name(aux_port), port_name(port));
1279
1280         return aux_port;
1281 }
1282
1283 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1284                                   enum port port)
1285 {
1286         switch (port) {
1287         case PORT_B:
1288         case PORT_C:
1289         case PORT_D:
1290                 return DP_AUX_CH_CTL(port);
1291         default:
1292                 MISSING_CASE(port);
1293                 return DP_AUX_CH_CTL(PORT_B);
1294         }
1295 }
1296
1297 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1298                                    enum port port, int index)
1299 {
1300         switch (port) {
1301         case PORT_B:
1302         case PORT_C:
1303         case PORT_D:
1304                 return DP_AUX_CH_DATA(port, index);
1305         default:
1306                 MISSING_CASE(port);
1307                 return DP_AUX_CH_DATA(PORT_B, index);
1308         }
1309 }
1310
1311 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1312                                   enum port port)
1313 {
1314         switch (port) {
1315         case PORT_A:
1316                 return DP_AUX_CH_CTL(port);
1317         case PORT_B:
1318         case PORT_C:
1319         case PORT_D:
1320                 return PCH_DP_AUX_CH_CTL(port);
1321         default:
1322                 MISSING_CASE(port);
1323                 return DP_AUX_CH_CTL(PORT_A);
1324         }
1325 }
1326
1327 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1328                                    enum port port, int index)
1329 {
1330         switch (port) {
1331         case PORT_A:
1332                 return DP_AUX_CH_DATA(port, index);
1333         case PORT_B:
1334         case PORT_C:
1335         case PORT_D:
1336                 return PCH_DP_AUX_CH_DATA(port, index);
1337         default:
1338                 MISSING_CASE(port);
1339                 return DP_AUX_CH_DATA(PORT_A, index);
1340         }
1341 }
1342
1343 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1344                                   enum port port)
1345 {
1346         switch (port) {
1347         case PORT_A:
1348         case PORT_B:
1349         case PORT_C:
1350         case PORT_D:
1351                 return DP_AUX_CH_CTL(port);
1352         default:
1353                 MISSING_CASE(port);
1354                 return DP_AUX_CH_CTL(PORT_A);
1355         }
1356 }
1357
1358 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1359                                    enum port port, int index)
1360 {
1361         switch (port) {
1362         case PORT_A:
1363         case PORT_B:
1364         case PORT_C:
1365         case PORT_D:
1366                 return DP_AUX_CH_DATA(port, index);
1367         default:
1368                 MISSING_CASE(port);
1369                 return DP_AUX_CH_DATA(PORT_A, index);
1370         }
1371 }
1372
1373 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1374                                     enum port port)
1375 {
1376         if (INTEL_INFO(dev_priv)->gen >= 9)
1377                 return skl_aux_ctl_reg(dev_priv, port);
1378         else if (HAS_PCH_SPLIT(dev_priv))
1379                 return ilk_aux_ctl_reg(dev_priv, port);
1380         else
1381                 return g4x_aux_ctl_reg(dev_priv, port);
1382 }
1383
1384 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1385                                      enum port port, int index)
1386 {
1387         if (INTEL_INFO(dev_priv)->gen >= 9)
1388                 return skl_aux_data_reg(dev_priv, port, index);
1389         else if (HAS_PCH_SPLIT(dev_priv))
1390                 return ilk_aux_data_reg(dev_priv, port, index);
1391         else
1392                 return g4x_aux_data_reg(dev_priv, port, index);
1393 }
1394
1395 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1396 {
1397         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1398         enum port port = intel_aux_port(dev_priv,
1399                                         dp_to_dig_port(intel_dp)->port);
1400         int i;
1401
1402         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1403         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1404                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1405 }
1406
1407 static void
1408 intel_dp_aux_fini(struct intel_dp *intel_dp)
1409 {
1410         kfree(intel_dp->aux.name);
1411 }
1412
1413 static void
1414 intel_dp_aux_init(struct intel_dp *intel_dp)
1415 {
1416         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1417         enum port port = intel_dig_port->port;
1418
1419         intel_aux_reg_init(intel_dp);
1420         drm_dp_aux_init(&intel_dp->aux);
1421
1422         /* Failure to allocate our preferred name is not critical */
1423         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1424         intel_dp->aux.transfer = intel_dp_aux_transfer;
1425 }
1426
1427 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1428 {
1429         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1430         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1431
1432         if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1433             IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1434                 return true;
1435         else
1436                 return false;
1437 }
1438
1439 static void
1440 intel_dp_set_clock(struct intel_encoder *encoder,
1441                    struct intel_crtc_state *pipe_config)
1442 {
1443         struct drm_device *dev = encoder->base.dev;
1444         struct drm_i915_private *dev_priv = to_i915(dev);
1445         const struct dp_link_dpll *divisor = NULL;
1446         int i, count = 0;
1447
1448         if (IS_G4X(dev_priv)) {
1449                 divisor = gen4_dpll;
1450                 count = ARRAY_SIZE(gen4_dpll);
1451         } else if (HAS_PCH_SPLIT(dev_priv)) {
1452                 divisor = pch_dpll;
1453                 count = ARRAY_SIZE(pch_dpll);
1454         } else if (IS_CHERRYVIEW(dev_priv)) {
1455                 divisor = chv_dpll;
1456                 count = ARRAY_SIZE(chv_dpll);
1457         } else if (IS_VALLEYVIEW(dev_priv)) {
1458                 divisor = vlv_dpll;
1459                 count = ARRAY_SIZE(vlv_dpll);
1460         }
1461
1462         if (divisor && count) {
1463                 for (i = 0; i < count; i++) {
1464                         if (pipe_config->port_clock == divisor[i].clock) {
1465                                 pipe_config->dpll = divisor[i].dpll;
1466                                 pipe_config->clock_set = true;
1467                                 break;
1468                         }
1469                 }
1470         }
1471 }
1472
1473 static void snprintf_int_array(char *str, size_t len,
1474                                const int *array, int nelem)
1475 {
1476         int i;
1477
1478         str[0] = '\0';
1479
1480         for (i = 0; i < nelem; i++) {
1481                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1482                 if (r >= len)
1483                         return;
1484                 str += r;
1485                 len -= r;
1486         }
1487 }
1488
1489 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1490 {
1491         const int *source_rates, *sink_rates;
1492         int source_len, sink_len, common_len;
1493         int common_rates[DP_MAX_SUPPORTED_RATES];
1494         char str[128]; /* FIXME: too big for stack? */
1495
1496         if ((drm_debug & DRM_UT_KMS) == 0)
1497                 return;
1498
1499         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1500         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1501         DRM_DEBUG_KMS("source rates: %s\n", str);
1502
1503         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1504         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1505         DRM_DEBUG_KMS("sink rates: %s\n", str);
1506
1507         common_len = intel_dp_common_rates(intel_dp, common_rates);
1508         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1509         DRM_DEBUG_KMS("common rates: %s\n", str);
1510 }
1511
1512 bool
1513 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1514 {
1515         u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1516                                                       DP_SINK_OUI;
1517
1518         return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1519                sizeof(*desc);
1520 }
1521
1522 bool intel_dp_read_desc(struct intel_dp *intel_dp)
1523 {
1524         struct intel_dp_desc *desc = &intel_dp->desc;
1525         bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1526                        DP_OUI_SUPPORT;
1527         int dev_id_len;
1528
1529         if (!__intel_dp_read_desc(intel_dp, desc))
1530                 return false;
1531
1532         dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1533         DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1534                       drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1535                       (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1536                       dev_id_len, desc->device_id,
1537                       desc->hw_rev >> 4, desc->hw_rev & 0xf,
1538                       desc->sw_major_rev, desc->sw_minor_rev);
1539
1540         return true;
1541 }
1542
1543 static int rate_to_index(int find, const int *rates)
1544 {
1545         int i = 0;
1546
1547         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1548                 if (find == rates[i])
1549                         break;
1550
1551         return i;
1552 }
1553
1554 int
1555 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1556 {
1557         int rates[DP_MAX_SUPPORTED_RATES] = {};
1558         int len;
1559
1560         len = intel_dp_common_rates(intel_dp, rates);
1561         if (WARN_ON(len <= 0))
1562                 return 162000;
1563
1564         return rates[len - 1];
1565 }
1566
1567 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1568 {
1569         return rate_to_index(rate, intel_dp->sink_rates);
1570 }
1571
1572 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1573                            uint8_t *link_bw, uint8_t *rate_select)
1574 {
1575         if (intel_dp->num_sink_rates) {
1576                 *link_bw = 0;
1577                 *rate_select =
1578                         intel_dp_rate_select(intel_dp, port_clock);
1579         } else {
1580                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1581                 *rate_select = 0;
1582         }
1583 }
1584
1585 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1586                                 struct intel_crtc_state *pipe_config)
1587 {
1588         int bpp, bpc;
1589
1590         bpp = pipe_config->pipe_bpp;
1591         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1592
1593         if (bpc > 0)
1594                 bpp = min(bpp, 3*bpc);
1595
1596         return bpp;
1597 }
1598
1599 bool
1600 intel_dp_compute_config(struct intel_encoder *encoder,
1601                         struct intel_crtc_state *pipe_config,
1602                         struct drm_connector_state *conn_state)
1603 {
1604         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1605         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1606         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1607         enum port port = dp_to_dig_port(intel_dp)->port;
1608         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1609         struct intel_connector *intel_connector = intel_dp->attached_connector;
1610         int lane_count, clock;
1611         int min_lane_count = 1;
1612         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1613         /* Conveniently, the link BW constants become indices with a shift...*/
1614         int min_clock = 0;
1615         int max_clock;
1616         int bpp, mode_rate;
1617         int link_avail, link_clock;
1618         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1619         int common_len;
1620         uint8_t link_bw, rate_select;
1621
1622         common_len = intel_dp_common_rates(intel_dp, common_rates);
1623
1624         /* No common link rates between source and sink */
1625         WARN_ON(common_len <= 0);
1626
1627         max_clock = common_len - 1;
1628
1629         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1630                 pipe_config->has_pch_encoder = true;
1631
1632         pipe_config->has_drrs = false;
1633         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1634
1635         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1636                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1637                                        adjusted_mode);
1638
1639                 if (INTEL_GEN(dev_priv) >= 9) {
1640                         int ret;
1641                         ret = skl_update_scaler_crtc(pipe_config);
1642                         if (ret)
1643                                 return ret;
1644                 }
1645
1646                 if (HAS_GMCH_DISPLAY(dev_priv))
1647                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1648                                                  intel_connector->panel.fitting_mode);
1649                 else
1650                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1651                                                 intel_connector->panel.fitting_mode);
1652         }
1653
1654         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1655                 return false;
1656
1657         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1658                       "max bw %d pixel clock %iKHz\n",
1659                       max_lane_count, common_rates[max_clock],
1660                       adjusted_mode->crtc_clock);
1661
1662         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1663          * bpc in between. */
1664         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1665         if (is_edp(intel_dp)) {
1666
1667                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1668                 if (intel_connector->base.display_info.bpc == 0 &&
1669                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1670                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1671                                       dev_priv->vbt.edp.bpp);
1672                         bpp = dev_priv->vbt.edp.bpp;
1673                 }
1674
1675                 /*
1676                  * Use the maximum clock and number of lanes the eDP panel
1677                  * advertizes being capable of. The panels are generally
1678                  * designed to support only a single clock and lane
1679                  * configuration, and typically these values correspond to the
1680                  * native resolution of the panel.
1681                  */
1682                 min_lane_count = max_lane_count;
1683                 min_clock = max_clock;
1684         }
1685
1686         for (; bpp >= 6*3; bpp -= 2*3) {
1687                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1688                                                    bpp);
1689
1690                 for (clock = min_clock; clock <= max_clock; clock++) {
1691                         for (lane_count = min_lane_count;
1692                                 lane_count <= max_lane_count;
1693                                 lane_count <<= 1) {
1694
1695                                 link_clock = common_rates[clock];
1696                                 link_avail = intel_dp_max_data_rate(link_clock,
1697                                                                     lane_count);
1698
1699                                 if (mode_rate <= link_avail) {
1700                                         goto found;
1701                                 }
1702                         }
1703                 }
1704         }
1705
1706         return false;
1707
1708 found:
1709         if (intel_dp->color_range_auto) {
1710                 /*
1711                  * See:
1712                  * CEA-861-E - 5.1 Default Encoding Parameters
1713                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1714                  */
1715                 pipe_config->limited_color_range =
1716                         bpp != 18 &&
1717                         drm_default_rgb_quant_range(adjusted_mode) ==
1718                         HDMI_QUANTIZATION_RANGE_LIMITED;
1719         } else {
1720                 pipe_config->limited_color_range =
1721                         intel_dp->limited_color_range;
1722         }
1723
1724         pipe_config->lane_count = lane_count;
1725
1726         pipe_config->pipe_bpp = bpp;
1727         pipe_config->port_clock = common_rates[clock];
1728
1729         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1730                               &link_bw, &rate_select);
1731
1732         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1733                       link_bw, rate_select, pipe_config->lane_count,
1734                       pipe_config->port_clock, bpp);
1735         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1736                       mode_rate, link_avail);
1737
1738         intel_link_compute_m_n(bpp, lane_count,
1739                                adjusted_mode->crtc_clock,
1740                                pipe_config->port_clock,
1741                                &pipe_config->dp_m_n);
1742
1743         if (intel_connector->panel.downclock_mode != NULL &&
1744                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1745                         pipe_config->has_drrs = true;
1746                         intel_link_compute_m_n(bpp, lane_count,
1747                                 intel_connector->panel.downclock_mode->clock,
1748                                 pipe_config->port_clock,
1749                                 &pipe_config->dp_m2_n2);
1750         }
1751
1752         /*
1753          * DPLL0 VCO may need to be adjusted to get the correct
1754          * clock for eDP. This will affect cdclk as well.
1755          */
1756         if (is_edp(intel_dp) &&
1757             (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1758                 int vco;
1759
1760                 switch (pipe_config->port_clock / 2) {
1761                 case 108000:
1762                 case 216000:
1763                         vco = 8640000;
1764                         break;
1765                 default:
1766                         vco = 8100000;
1767                         break;
1768                 }
1769
1770                 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1771         }
1772
1773         if (!HAS_DDI(dev_priv))
1774                 intel_dp_set_clock(encoder, pipe_config);
1775
1776         return true;
1777 }
1778
1779 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1780                               int link_rate, uint8_t lane_count,
1781                               bool link_mst)
1782 {
1783         intel_dp->link_rate = link_rate;
1784         intel_dp->lane_count = lane_count;
1785         intel_dp->link_mst = link_mst;
1786 }
1787
1788 static void intel_dp_prepare(struct intel_encoder *encoder,
1789                              struct intel_crtc_state *pipe_config)
1790 {
1791         struct drm_device *dev = encoder->base.dev;
1792         struct drm_i915_private *dev_priv = to_i915(dev);
1793         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1794         enum port port = dp_to_dig_port(intel_dp)->port;
1795         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1796         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1797
1798         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1799                                  pipe_config->lane_count,
1800                                  intel_crtc_has_type(pipe_config,
1801                                                      INTEL_OUTPUT_DP_MST));
1802
1803         /*
1804          * There are four kinds of DP registers:
1805          *
1806          *      IBX PCH
1807          *      SNB CPU
1808          *      IVB CPU
1809          *      CPT PCH
1810          *
1811          * IBX PCH and CPU are the same for almost everything,
1812          * except that the CPU DP PLL is configured in this
1813          * register
1814          *
1815          * CPT PCH is quite different, having many bits moved
1816          * to the TRANS_DP_CTL register instead. That
1817          * configuration happens (oddly) in ironlake_pch_enable
1818          */
1819
1820         /* Preserve the BIOS-computed detected bit. This is
1821          * supposed to be read-only.
1822          */
1823         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1824
1825         /* Handle DP bits in common between all three register formats */
1826         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1827         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1828
1829         /* Split out the IBX/CPU vs CPT settings */
1830
1831         if (IS_GEN7(dev_priv) && port == PORT_A) {
1832                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1833                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1834                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1835                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1836                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1837
1838                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1839                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1840
1841                 intel_dp->DP |= crtc->pipe << 29;
1842         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1843                 u32 trans_dp;
1844
1845                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1846
1847                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1848                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1849                         trans_dp |= TRANS_DP_ENH_FRAMING;
1850                 else
1851                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1852                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1853         } else {
1854                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1855                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1856
1857                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1858                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1859                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1860                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1861                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1862
1863                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1864                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1865
1866                 if (IS_CHERRYVIEW(dev_priv))
1867                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1868                 else if (crtc->pipe == PIPE_B)
1869                         intel_dp->DP |= DP_PIPEB_SELECT;
1870         }
1871 }
1872
1873 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1874 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1875
1876 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1877 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1878
1879 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1880 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1881
1882 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1883                                    struct intel_dp *intel_dp);
1884
1885 static void wait_panel_status(struct intel_dp *intel_dp,
1886                                        u32 mask,
1887                                        u32 value)
1888 {
1889         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1890         struct drm_i915_private *dev_priv = to_i915(dev);
1891         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1892
1893         lockdep_assert_held(&dev_priv->pps_mutex);
1894
1895         intel_pps_verify_state(dev_priv, intel_dp);
1896
1897         pp_stat_reg = _pp_stat_reg(intel_dp);
1898         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1899
1900         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1901                         mask, value,
1902                         I915_READ(pp_stat_reg),
1903                         I915_READ(pp_ctrl_reg));
1904
1905         if (intel_wait_for_register(dev_priv,
1906                                     pp_stat_reg, mask, value,
1907                                     5000))
1908                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1909                                 I915_READ(pp_stat_reg),
1910                                 I915_READ(pp_ctrl_reg));
1911
1912         DRM_DEBUG_KMS("Wait complete\n");
1913 }
1914
1915 static void wait_panel_on(struct intel_dp *intel_dp)
1916 {
1917         DRM_DEBUG_KMS("Wait for panel power on\n");
1918         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1919 }
1920
1921 static void wait_panel_off(struct intel_dp *intel_dp)
1922 {
1923         DRM_DEBUG_KMS("Wait for panel power off time\n");
1924         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1925 }
1926
1927 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1928 {
1929         ktime_t panel_power_on_time;
1930         s64 panel_power_off_duration;
1931
1932         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1933
1934         /* take the difference of currrent time and panel power off time
1935          * and then make panel wait for t11_t12 if needed. */
1936         panel_power_on_time = ktime_get_boottime();
1937         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1938
1939         /* When we disable the VDD override bit last we have to do the manual
1940          * wait. */
1941         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1942                 wait_remaining_ms_from_jiffies(jiffies,
1943                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1944
1945         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1946 }
1947
1948 static void wait_backlight_on(struct intel_dp *intel_dp)
1949 {
1950         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1951                                        intel_dp->backlight_on_delay);
1952 }
1953
1954 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1955 {
1956         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1957                                        intel_dp->backlight_off_delay);
1958 }
1959
1960 /* Read the current pp_control value, unlocking the register if it
1961  * is locked
1962  */
1963
1964 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1965 {
1966         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1967         struct drm_i915_private *dev_priv = to_i915(dev);
1968         u32 control;
1969
1970         lockdep_assert_held(&dev_priv->pps_mutex);
1971
1972         control = I915_READ(_pp_ctrl_reg(intel_dp));
1973         if (WARN_ON(!HAS_DDI(dev_priv) &&
1974                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1975                 control &= ~PANEL_UNLOCK_MASK;
1976                 control |= PANEL_UNLOCK_REGS;
1977         }
1978         return control;
1979 }
1980
1981 /*
1982  * Must be paired with edp_panel_vdd_off().
1983  * Must hold pps_mutex around the whole on/off sequence.
1984  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1985  */
1986 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1987 {
1988         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1989         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1990         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1991         struct drm_i915_private *dev_priv = to_i915(dev);
1992         enum intel_display_power_domain power_domain;
1993         u32 pp;
1994         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1995         bool need_to_disable = !intel_dp->want_panel_vdd;
1996
1997         lockdep_assert_held(&dev_priv->pps_mutex);
1998
1999         if (!is_edp(intel_dp))
2000                 return false;
2001
2002         cancel_delayed_work(&intel_dp->panel_vdd_work);
2003         intel_dp->want_panel_vdd = true;
2004
2005         if (edp_have_panel_vdd(intel_dp))
2006                 return need_to_disable;
2007
2008         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2009         intel_display_power_get(dev_priv, power_domain);
2010
2011         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2012                       port_name(intel_dig_port->port));
2013
2014         if (!edp_have_panel_power(intel_dp))
2015                 wait_panel_power_cycle(intel_dp);
2016
2017         pp = ironlake_get_pp_control(intel_dp);
2018         pp |= EDP_FORCE_VDD;
2019
2020         pp_stat_reg = _pp_stat_reg(intel_dp);
2021         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2022
2023         I915_WRITE(pp_ctrl_reg, pp);
2024         POSTING_READ(pp_ctrl_reg);
2025         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2026                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2027         /*
2028          * If the panel wasn't on, delay before accessing aux channel
2029          */
2030         if (!edp_have_panel_power(intel_dp)) {
2031                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2032                               port_name(intel_dig_port->port));
2033                 msleep(intel_dp->panel_power_up_delay);
2034         }
2035
2036         return need_to_disable;
2037 }
2038
2039 /*
2040  * Must be paired with intel_edp_panel_vdd_off() or
2041  * intel_edp_panel_off().
2042  * Nested calls to these functions are not allowed since
2043  * we drop the lock. Caller must use some higher level
2044  * locking to prevent nested calls from other threads.
2045  */
2046 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2047 {
2048         bool vdd;
2049
2050         if (!is_edp(intel_dp))
2051                 return;
2052
2053         pps_lock(intel_dp);
2054         vdd = edp_panel_vdd_on(intel_dp);
2055         pps_unlock(intel_dp);
2056
2057         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2058              port_name(dp_to_dig_port(intel_dp)->port));
2059 }
2060
2061 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2062 {
2063         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2064         struct drm_i915_private *dev_priv = to_i915(dev);
2065         struct intel_digital_port *intel_dig_port =
2066                 dp_to_dig_port(intel_dp);
2067         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2068         enum intel_display_power_domain power_domain;
2069         u32 pp;
2070         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2071
2072         lockdep_assert_held(&dev_priv->pps_mutex);
2073
2074         WARN_ON(intel_dp->want_panel_vdd);
2075
2076         if (!edp_have_panel_vdd(intel_dp))
2077                 return;
2078
2079         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2080                       port_name(intel_dig_port->port));
2081
2082         pp = ironlake_get_pp_control(intel_dp);
2083         pp &= ~EDP_FORCE_VDD;
2084
2085         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2086         pp_stat_reg = _pp_stat_reg(intel_dp);
2087
2088         I915_WRITE(pp_ctrl_reg, pp);
2089         POSTING_READ(pp_ctrl_reg);
2090
2091         /* Make sure sequencer is idle before allowing subsequent activity */
2092         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2093         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2094
2095         if ((pp & PANEL_POWER_ON) == 0)
2096                 intel_dp->panel_power_off_time = ktime_get_boottime();
2097
2098         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2099         intel_display_power_put(dev_priv, power_domain);
2100 }
2101
2102 static void edp_panel_vdd_work(struct work_struct *__work)
2103 {
2104         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2105                                                  struct intel_dp, panel_vdd_work);
2106
2107         pps_lock(intel_dp);
2108         if (!intel_dp->want_panel_vdd)
2109                 edp_panel_vdd_off_sync(intel_dp);
2110         pps_unlock(intel_dp);
2111 }
2112
2113 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2114 {
2115         unsigned long delay;
2116
2117         /*
2118          * Queue the timer to fire a long time from now (relative to the power
2119          * down delay) to keep the panel power up across a sequence of
2120          * operations.
2121          */
2122         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2123         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2124 }
2125
2126 /*
2127  * Must be paired with edp_panel_vdd_on().
2128  * Must hold pps_mutex around the whole on/off sequence.
2129  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2130  */
2131 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2132 {
2133         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2134
2135         lockdep_assert_held(&dev_priv->pps_mutex);
2136
2137         if (!is_edp(intel_dp))
2138                 return;
2139
2140         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2141              port_name(dp_to_dig_port(intel_dp)->port));
2142
2143         intel_dp->want_panel_vdd = false;
2144
2145         if (sync)
2146                 edp_panel_vdd_off_sync(intel_dp);
2147         else
2148                 edp_panel_vdd_schedule_off(intel_dp);
2149 }
2150
2151 static void edp_panel_on(struct intel_dp *intel_dp)
2152 {
2153         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2154         struct drm_i915_private *dev_priv = to_i915(dev);
2155         u32 pp;
2156         i915_reg_t pp_ctrl_reg;
2157
2158         lockdep_assert_held(&dev_priv->pps_mutex);
2159
2160         if (!is_edp(intel_dp))
2161                 return;
2162
2163         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2164                       port_name(dp_to_dig_port(intel_dp)->port));
2165
2166         if (WARN(edp_have_panel_power(intel_dp),
2167                  "eDP port %c panel power already on\n",
2168                  port_name(dp_to_dig_port(intel_dp)->port)))
2169                 return;
2170
2171         wait_panel_power_cycle(intel_dp);
2172
2173         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2174         pp = ironlake_get_pp_control(intel_dp);
2175         if (IS_GEN5(dev_priv)) {
2176                 /* ILK workaround: disable reset around power sequence */
2177                 pp &= ~PANEL_POWER_RESET;
2178                 I915_WRITE(pp_ctrl_reg, pp);
2179                 POSTING_READ(pp_ctrl_reg);
2180         }
2181
2182         pp |= PANEL_POWER_ON;
2183         if (!IS_GEN5(dev_priv))
2184                 pp |= PANEL_POWER_RESET;
2185
2186         I915_WRITE(pp_ctrl_reg, pp);
2187         POSTING_READ(pp_ctrl_reg);
2188
2189         wait_panel_on(intel_dp);
2190         intel_dp->last_power_on = jiffies;
2191
2192         if (IS_GEN5(dev_priv)) {
2193                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2194                 I915_WRITE(pp_ctrl_reg, pp);
2195                 POSTING_READ(pp_ctrl_reg);
2196         }
2197 }
2198
2199 void intel_edp_panel_on(struct intel_dp *intel_dp)
2200 {
2201         if (!is_edp(intel_dp))
2202                 return;
2203
2204         pps_lock(intel_dp);
2205         edp_panel_on(intel_dp);
2206         pps_unlock(intel_dp);
2207 }
2208
2209
2210 static void edp_panel_off(struct intel_dp *intel_dp)
2211 {
2212         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2213         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2214         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2215         struct drm_i915_private *dev_priv = to_i915(dev);
2216         enum intel_display_power_domain power_domain;
2217         u32 pp;
2218         i915_reg_t pp_ctrl_reg;
2219
2220         lockdep_assert_held(&dev_priv->pps_mutex);
2221
2222         if (!is_edp(intel_dp))
2223                 return;
2224
2225         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2226                       port_name(dp_to_dig_port(intel_dp)->port));
2227
2228         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2229              port_name(dp_to_dig_port(intel_dp)->port));
2230
2231         pp = ironlake_get_pp_control(intel_dp);
2232         /* We need to switch off panel power _and_ force vdd, for otherwise some
2233          * panels get very unhappy and cease to work. */
2234         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2235                 EDP_BLC_ENABLE);
2236
2237         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2238
2239         intel_dp->want_panel_vdd = false;
2240
2241         I915_WRITE(pp_ctrl_reg, pp);
2242         POSTING_READ(pp_ctrl_reg);
2243
2244         intel_dp->panel_power_off_time = ktime_get_boottime();
2245         wait_panel_off(intel_dp);
2246
2247         /* We got a reference when we enabled the VDD. */
2248         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2249         intel_display_power_put(dev_priv, power_domain);
2250 }
2251
2252 void intel_edp_panel_off(struct intel_dp *intel_dp)
2253 {
2254         if (!is_edp(intel_dp))
2255                 return;
2256
2257         pps_lock(intel_dp);
2258         edp_panel_off(intel_dp);
2259         pps_unlock(intel_dp);
2260 }
2261
2262 /* Enable backlight in the panel power control. */
2263 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2264 {
2265         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2266         struct drm_device *dev = intel_dig_port->base.base.dev;
2267         struct drm_i915_private *dev_priv = to_i915(dev);
2268         u32 pp;
2269         i915_reg_t pp_ctrl_reg;
2270
2271         /*
2272          * If we enable the backlight right away following a panel power
2273          * on, we may see slight flicker as the panel syncs with the eDP
2274          * link.  So delay a bit to make sure the image is solid before
2275          * allowing it to appear.
2276          */
2277         wait_backlight_on(intel_dp);
2278
2279         pps_lock(intel_dp);
2280
2281         pp = ironlake_get_pp_control(intel_dp);
2282         pp |= EDP_BLC_ENABLE;
2283
2284         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2285
2286         I915_WRITE(pp_ctrl_reg, pp);
2287         POSTING_READ(pp_ctrl_reg);
2288
2289         pps_unlock(intel_dp);
2290 }
2291
2292 /* Enable backlight PWM and backlight PP control. */
2293 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2294 {
2295         if (!is_edp(intel_dp))
2296                 return;
2297
2298         DRM_DEBUG_KMS("\n");
2299
2300         intel_panel_enable_backlight(intel_dp->attached_connector);
2301         _intel_edp_backlight_on(intel_dp);
2302 }
2303
2304 /* Disable backlight in the panel power control. */
2305 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2306 {
2307         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2308         struct drm_i915_private *dev_priv = to_i915(dev);
2309         u32 pp;
2310         i915_reg_t pp_ctrl_reg;
2311
2312         if (!is_edp(intel_dp))
2313                 return;
2314
2315         pps_lock(intel_dp);
2316
2317         pp = ironlake_get_pp_control(intel_dp);
2318         pp &= ~EDP_BLC_ENABLE;
2319
2320         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2321
2322         I915_WRITE(pp_ctrl_reg, pp);
2323         POSTING_READ(pp_ctrl_reg);
2324
2325         pps_unlock(intel_dp);
2326
2327         intel_dp->last_backlight_off = jiffies;
2328         edp_wait_backlight_off(intel_dp);
2329 }
2330
2331 /* Disable backlight PP control and backlight PWM. */
2332 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2333 {
2334         if (!is_edp(intel_dp))
2335                 return;
2336
2337         DRM_DEBUG_KMS("\n");
2338
2339         _intel_edp_backlight_off(intel_dp);
2340         intel_panel_disable_backlight(intel_dp->attached_connector);
2341 }
2342
2343 /*
2344  * Hook for controlling the panel power control backlight through the bl_power
2345  * sysfs attribute. Take care to handle multiple calls.
2346  */
2347 static void intel_edp_backlight_power(struct intel_connector *connector,
2348                                       bool enable)
2349 {
2350         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2351         bool is_enabled;
2352
2353         pps_lock(intel_dp);
2354         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2355         pps_unlock(intel_dp);
2356
2357         if (is_enabled == enable)
2358                 return;
2359
2360         DRM_DEBUG_KMS("panel power control backlight %s\n",
2361                       enable ? "enable" : "disable");
2362
2363         if (enable)
2364                 _intel_edp_backlight_on(intel_dp);
2365         else
2366                 _intel_edp_backlight_off(intel_dp);
2367 }
2368
2369 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2370 {
2371         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2372         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2373         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2374
2375         I915_STATE_WARN(cur_state != state,
2376                         "DP port %c state assertion failure (expected %s, current %s)\n",
2377                         port_name(dig_port->port),
2378                         onoff(state), onoff(cur_state));
2379 }
2380 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2381
2382 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2383 {
2384         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2385
2386         I915_STATE_WARN(cur_state != state,
2387                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2388                         onoff(state), onoff(cur_state));
2389 }
2390 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2391 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2392
2393 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2394                                 struct intel_crtc_state *pipe_config)
2395 {
2396         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2397         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2398
2399         assert_pipe_disabled(dev_priv, crtc->pipe);
2400         assert_dp_port_disabled(intel_dp);
2401         assert_edp_pll_disabled(dev_priv);
2402
2403         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2404                       pipe_config->port_clock);
2405
2406         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2407
2408         if (pipe_config->port_clock == 162000)
2409                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2410         else
2411                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2412
2413         I915_WRITE(DP_A, intel_dp->DP);
2414         POSTING_READ(DP_A);
2415         udelay(500);
2416
2417         /*
2418          * [DevILK] Work around required when enabling DP PLL
2419          * while a pipe is enabled going to FDI:
2420          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2421          * 2. Program DP PLL enable
2422          */
2423         if (IS_GEN5(dev_priv))
2424                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2425
2426         intel_dp->DP |= DP_PLL_ENABLE;
2427
2428         I915_WRITE(DP_A, intel_dp->DP);
2429         POSTING_READ(DP_A);
2430         udelay(200);
2431 }
2432
2433 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2434 {
2435         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2436         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2437         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2438
2439         assert_pipe_disabled(dev_priv, crtc->pipe);
2440         assert_dp_port_disabled(intel_dp);
2441         assert_edp_pll_enabled(dev_priv);
2442
2443         DRM_DEBUG_KMS("disabling eDP PLL\n");
2444
2445         intel_dp->DP &= ~DP_PLL_ENABLE;
2446
2447         I915_WRITE(DP_A, intel_dp->DP);
2448         POSTING_READ(DP_A);
2449         udelay(200);
2450 }
2451
2452 /* If the sink supports it, try to set the power state appropriately */
2453 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2454 {
2455         int ret, i;
2456
2457         /* Should have a valid DPCD by this point */
2458         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2459                 return;
2460
2461         if (mode != DRM_MODE_DPMS_ON) {
2462                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2463                                          DP_SET_POWER_D3);
2464         } else {
2465                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2466
2467                 /*
2468                  * When turning on, we need to retry for 1ms to give the sink
2469                  * time to wake up.
2470                  */
2471                 for (i = 0; i < 3; i++) {
2472                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2473                                                  DP_SET_POWER_D0);
2474                         if (ret == 1)
2475                                 break;
2476                         msleep(1);
2477                 }
2478
2479                 if (ret == 1 && lspcon->active)
2480                         lspcon_wait_pcon_mode(lspcon);
2481         }
2482
2483         if (ret != 1)
2484                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2485                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2486 }
2487
2488 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2489                                   enum pipe *pipe)
2490 {
2491         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2492         enum port port = dp_to_dig_port(intel_dp)->port;
2493         struct drm_device *dev = encoder->base.dev;
2494         struct drm_i915_private *dev_priv = to_i915(dev);
2495         enum intel_display_power_domain power_domain;
2496         u32 tmp;
2497         bool ret;
2498
2499         power_domain = intel_display_port_power_domain(encoder);
2500         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2501                 return false;
2502
2503         ret = false;
2504
2505         tmp = I915_READ(intel_dp->output_reg);
2506
2507         if (!(tmp & DP_PORT_EN))
2508                 goto out;
2509
2510         if (IS_GEN7(dev_priv) && port == PORT_A) {
2511                 *pipe = PORT_TO_PIPE_CPT(tmp);
2512         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2513                 enum pipe p;
2514
2515                 for_each_pipe(dev_priv, p) {
2516                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2517                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2518                                 *pipe = p;
2519                                 ret = true;
2520
2521                                 goto out;
2522                         }
2523                 }
2524
2525                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2526                               i915_mmio_reg_offset(intel_dp->output_reg));
2527         } else if (IS_CHERRYVIEW(dev_priv)) {
2528                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2529         } else {
2530                 *pipe = PORT_TO_PIPE(tmp);
2531         }
2532
2533         ret = true;
2534
2535 out:
2536         intel_display_power_put(dev_priv, power_domain);
2537
2538         return ret;
2539 }
2540
2541 static void intel_dp_get_config(struct intel_encoder *encoder,
2542                                 struct intel_crtc_state *pipe_config)
2543 {
2544         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2545         u32 tmp, flags = 0;
2546         struct drm_device *dev = encoder->base.dev;
2547         struct drm_i915_private *dev_priv = to_i915(dev);
2548         enum port port = dp_to_dig_port(intel_dp)->port;
2549         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2550
2551         tmp = I915_READ(intel_dp->output_reg);
2552
2553         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2554
2555         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2556                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2557
2558                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2559                         flags |= DRM_MODE_FLAG_PHSYNC;
2560                 else
2561                         flags |= DRM_MODE_FLAG_NHSYNC;
2562
2563                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2564                         flags |= DRM_MODE_FLAG_PVSYNC;
2565                 else
2566                         flags |= DRM_MODE_FLAG_NVSYNC;
2567         } else {
2568                 if (tmp & DP_SYNC_HS_HIGH)
2569                         flags |= DRM_MODE_FLAG_PHSYNC;
2570                 else
2571                         flags |= DRM_MODE_FLAG_NHSYNC;
2572
2573                 if (tmp & DP_SYNC_VS_HIGH)
2574                         flags |= DRM_MODE_FLAG_PVSYNC;
2575                 else
2576                         flags |= DRM_MODE_FLAG_NVSYNC;
2577         }
2578
2579         pipe_config->base.adjusted_mode.flags |= flags;
2580
2581         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2582                 pipe_config->limited_color_range = true;
2583
2584         pipe_config->lane_count =
2585                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2586
2587         intel_dp_get_m_n(crtc, pipe_config);
2588
2589         if (port == PORT_A) {
2590                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2591                         pipe_config->port_clock = 162000;
2592                 else
2593                         pipe_config->port_clock = 270000;
2594         }
2595
2596         pipe_config->base.adjusted_mode.crtc_clock =
2597                 intel_dotclock_calculate(pipe_config->port_clock,
2598                                          &pipe_config->dp_m_n);
2599
2600         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2601             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2602                 /*
2603                  * This is a big fat ugly hack.
2604                  *
2605                  * Some machines in UEFI boot mode provide us a VBT that has 18
2606                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2607                  * unknown we fail to light up. Yet the same BIOS boots up with
2608                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2609                  * max, not what it tells us to use.
2610                  *
2611                  * Note: This will still be broken if the eDP panel is not lit
2612                  * up by the BIOS, and thus we can't get the mode at module
2613                  * load.
2614                  */
2615                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2616                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2617                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2618         }
2619 }
2620
2621 static void intel_disable_dp(struct intel_encoder *encoder,
2622                              struct intel_crtc_state *old_crtc_state,
2623                              struct drm_connector_state *old_conn_state)
2624 {
2625         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2626         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2627
2628         if (old_crtc_state->has_audio)
2629                 intel_audio_codec_disable(encoder);
2630
2631         if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2632                 intel_psr_disable(intel_dp);
2633
2634         /* Make sure the panel is off before trying to change the mode. But also
2635          * ensure that we have vdd while we switch off the panel. */
2636         intel_edp_panel_vdd_on(intel_dp);
2637         intel_edp_backlight_off(intel_dp);
2638         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2639         intel_edp_panel_off(intel_dp);
2640
2641         /* disable the port before the pipe on g4x */
2642         if (INTEL_GEN(dev_priv) < 5)
2643                 intel_dp_link_down(intel_dp);
2644 }
2645
2646 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2647                                 struct intel_crtc_state *old_crtc_state,
2648                                 struct drm_connector_state *old_conn_state)
2649 {
2650         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2651         enum port port = dp_to_dig_port(intel_dp)->port;
2652
2653         intel_dp_link_down(intel_dp);
2654
2655         /* Only ilk+ has port A */
2656         if (port == PORT_A)
2657                 ironlake_edp_pll_off(intel_dp);
2658 }
2659
2660 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2661                                 struct intel_crtc_state *old_crtc_state,
2662                                 struct drm_connector_state *old_conn_state)
2663 {
2664         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2665
2666         intel_dp_link_down(intel_dp);
2667 }
2668
2669 static void chv_post_disable_dp(struct intel_encoder *encoder,
2670                                 struct intel_crtc_state *old_crtc_state,
2671                                 struct drm_connector_state *old_conn_state)
2672 {
2673         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2674         struct drm_device *dev = encoder->base.dev;
2675         struct drm_i915_private *dev_priv = to_i915(dev);
2676
2677         intel_dp_link_down(intel_dp);
2678
2679         mutex_lock(&dev_priv->sb_lock);
2680
2681         /* Assert data lane reset */
2682         chv_data_lane_soft_reset(encoder, true);
2683
2684         mutex_unlock(&dev_priv->sb_lock);
2685 }
2686
2687 static void
2688 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2689                          uint32_t *DP,
2690                          uint8_t dp_train_pat)
2691 {
2692         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2693         struct drm_device *dev = intel_dig_port->base.base.dev;
2694         struct drm_i915_private *dev_priv = to_i915(dev);
2695         enum port port = intel_dig_port->port;
2696
2697         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2698                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2699                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2700
2701         if (HAS_DDI(dev_priv)) {
2702                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2703
2704                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2705                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2706                 else
2707                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2708
2709                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2710                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2711                 case DP_TRAINING_PATTERN_DISABLE:
2712                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2713
2714                         break;
2715                 case DP_TRAINING_PATTERN_1:
2716                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2717                         break;
2718                 case DP_TRAINING_PATTERN_2:
2719                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2720                         break;
2721                 case DP_TRAINING_PATTERN_3:
2722                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2723                         break;
2724                 }
2725                 I915_WRITE(DP_TP_CTL(port), temp);
2726
2727         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2728                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2729                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2730
2731                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2732                 case DP_TRAINING_PATTERN_DISABLE:
2733                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2734                         break;
2735                 case DP_TRAINING_PATTERN_1:
2736                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2737                         break;
2738                 case DP_TRAINING_PATTERN_2:
2739                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2740                         break;
2741                 case DP_TRAINING_PATTERN_3:
2742                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2743                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2744                         break;
2745                 }
2746
2747         } else {
2748                 if (IS_CHERRYVIEW(dev_priv))
2749                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2750                 else
2751                         *DP &= ~DP_LINK_TRAIN_MASK;
2752
2753                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2754                 case DP_TRAINING_PATTERN_DISABLE:
2755                         *DP |= DP_LINK_TRAIN_OFF;
2756                         break;
2757                 case DP_TRAINING_PATTERN_1:
2758                         *DP |= DP_LINK_TRAIN_PAT_1;
2759                         break;
2760                 case DP_TRAINING_PATTERN_2:
2761                         *DP |= DP_LINK_TRAIN_PAT_2;
2762                         break;
2763                 case DP_TRAINING_PATTERN_3:
2764                         if (IS_CHERRYVIEW(dev_priv)) {
2765                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2766                         } else {
2767                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2768                                 *DP |= DP_LINK_TRAIN_PAT_2;
2769                         }
2770                         break;
2771                 }
2772         }
2773 }
2774
2775 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2776                                  struct intel_crtc_state *old_crtc_state)
2777 {
2778         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2779         struct drm_i915_private *dev_priv = to_i915(dev);
2780
2781         /* enable with pattern 1 (as per spec) */
2782
2783         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2784
2785         /*
2786          * Magic for VLV/CHV. We _must_ first set up the register
2787          * without actually enabling the port, and then do another
2788          * write to enable the port. Otherwise link training will
2789          * fail when the power sequencer is freshly used for this port.
2790          */
2791         intel_dp->DP |= DP_PORT_EN;
2792         if (old_crtc_state->has_audio)
2793                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2794
2795         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2796         POSTING_READ(intel_dp->output_reg);
2797 }
2798
2799 static void intel_enable_dp(struct intel_encoder *encoder,
2800                             struct intel_crtc_state *pipe_config,
2801                             struct drm_connector_state *conn_state)
2802 {
2803         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2804         struct drm_device *dev = encoder->base.dev;
2805         struct drm_i915_private *dev_priv = to_i915(dev);
2806         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2807         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2808         enum pipe pipe = crtc->pipe;
2809
2810         if (WARN_ON(dp_reg & DP_PORT_EN))
2811                 return;
2812
2813         pps_lock(intel_dp);
2814
2815         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2816                 vlv_init_panel_power_sequencer(intel_dp);
2817
2818         intel_dp_enable_port(intel_dp, pipe_config);
2819
2820         edp_panel_vdd_on(intel_dp);
2821         edp_panel_on(intel_dp);
2822         edp_panel_vdd_off(intel_dp, true);
2823
2824         pps_unlock(intel_dp);
2825
2826         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2827                 unsigned int lane_mask = 0x0;
2828
2829                 if (IS_CHERRYVIEW(dev_priv))
2830                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2831
2832                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2833                                     lane_mask);
2834         }
2835
2836         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2837         intel_dp_start_link_train(intel_dp);
2838         intel_dp_stop_link_train(intel_dp);
2839
2840         if (pipe_config->has_audio) {
2841                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2842                                  pipe_name(pipe));
2843                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2844         }
2845 }
2846
2847 static void g4x_enable_dp(struct intel_encoder *encoder,
2848                           struct intel_crtc_state *pipe_config,
2849                           struct drm_connector_state *conn_state)
2850 {
2851         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2852
2853         intel_enable_dp(encoder, pipe_config, conn_state);
2854         intel_edp_backlight_on(intel_dp);
2855 }
2856
2857 static void vlv_enable_dp(struct intel_encoder *encoder,
2858                           struct intel_crtc_state *pipe_config,
2859                           struct drm_connector_state *conn_state)
2860 {
2861         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2862
2863         intel_edp_backlight_on(intel_dp);
2864         intel_psr_enable(intel_dp);
2865 }
2866
2867 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2868                               struct intel_crtc_state *pipe_config,
2869                               struct drm_connector_state *conn_state)
2870 {
2871         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2872         enum port port = dp_to_dig_port(intel_dp)->port;
2873
2874         intel_dp_prepare(encoder, pipe_config);
2875
2876         /* Only ilk+ has port A */
2877         if (port == PORT_A)
2878                 ironlake_edp_pll_on(intel_dp, pipe_config);
2879 }
2880
2881 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2882 {
2883         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2884         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2885         enum pipe pipe = intel_dp->pps_pipe;
2886         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2887
2888         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2889
2890         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2891                 return;
2892
2893         edp_panel_vdd_off_sync(intel_dp);
2894
2895         /*
2896          * VLV seems to get confused when multiple power seqeuencers
2897          * have the same port selected (even if only one has power/vdd
2898          * enabled). The failure manifests as vlv_wait_port_ready() failing
2899          * CHV on the other hand doesn't seem to mind having the same port
2900          * selected in multiple power seqeuencers, but let's clear the
2901          * port select always when logically disconnecting a power sequencer
2902          * from a port.
2903          */
2904         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2905                       pipe_name(pipe), port_name(intel_dig_port->port));
2906         I915_WRITE(pp_on_reg, 0);
2907         POSTING_READ(pp_on_reg);
2908
2909         intel_dp->pps_pipe = INVALID_PIPE;
2910 }
2911
2912 static void vlv_steal_power_sequencer(struct drm_device *dev,
2913                                       enum pipe pipe)
2914 {
2915         struct drm_i915_private *dev_priv = to_i915(dev);
2916         struct intel_encoder *encoder;
2917
2918         lockdep_assert_held(&dev_priv->pps_mutex);
2919
2920         for_each_intel_encoder(dev, encoder) {
2921                 struct intel_dp *intel_dp;
2922                 enum port port;
2923
2924                 if (encoder->type != INTEL_OUTPUT_DP &&
2925                     encoder->type != INTEL_OUTPUT_EDP)
2926                         continue;
2927
2928                 intel_dp = enc_to_intel_dp(&encoder->base);
2929                 port = dp_to_dig_port(intel_dp)->port;
2930
2931                 WARN(intel_dp->active_pipe == pipe,
2932                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
2933                      pipe_name(pipe), port_name(port));
2934
2935                 if (intel_dp->pps_pipe != pipe)
2936                         continue;
2937
2938                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2939                               pipe_name(pipe), port_name(port));
2940
2941                 /* make sure vdd is off before we steal it */
2942                 vlv_detach_power_sequencer(intel_dp);
2943         }
2944 }
2945
2946 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2947 {
2948         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2949         struct intel_encoder *encoder = &intel_dig_port->base;
2950         struct drm_device *dev = encoder->base.dev;
2951         struct drm_i915_private *dev_priv = to_i915(dev);
2952         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2953
2954         lockdep_assert_held(&dev_priv->pps_mutex);
2955
2956         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2957
2958         if (intel_dp->pps_pipe != INVALID_PIPE &&
2959             intel_dp->pps_pipe != crtc->pipe) {
2960                 /*
2961                  * If another power sequencer was being used on this
2962                  * port previously make sure to turn off vdd there while
2963                  * we still have control of it.
2964                  */
2965                 vlv_detach_power_sequencer(intel_dp);
2966         }
2967
2968         /*
2969          * We may be stealing the power
2970          * sequencer from another port.
2971          */
2972         vlv_steal_power_sequencer(dev, crtc->pipe);
2973
2974         intel_dp->active_pipe = crtc->pipe;
2975
2976         if (!is_edp(intel_dp))
2977                 return;
2978
2979         /* now it's all ours */
2980         intel_dp->pps_pipe = crtc->pipe;
2981
2982         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2983                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2984
2985         /* init power sequencer on this pipe and port */
2986         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2987         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
2988 }
2989
2990 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2991                               struct intel_crtc_state *pipe_config,
2992                               struct drm_connector_state *conn_state)
2993 {
2994         vlv_phy_pre_encoder_enable(encoder);
2995
2996         intel_enable_dp(encoder, pipe_config, conn_state);
2997 }
2998
2999 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3000                                   struct intel_crtc_state *pipe_config,
3001                                   struct drm_connector_state *conn_state)
3002 {
3003         intel_dp_prepare(encoder, pipe_config);
3004
3005         vlv_phy_pre_pll_enable(encoder);
3006 }
3007
3008 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3009                               struct intel_crtc_state *pipe_config,
3010                               struct drm_connector_state *conn_state)
3011 {
3012         chv_phy_pre_encoder_enable(encoder);
3013
3014         intel_enable_dp(encoder, pipe_config, conn_state);
3015
3016         /* Second common lane will stay alive on its own now */
3017         chv_phy_release_cl2_override(encoder);
3018 }
3019
3020 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3021                                   struct intel_crtc_state *pipe_config,
3022                                   struct drm_connector_state *conn_state)
3023 {
3024         intel_dp_prepare(encoder, pipe_config);
3025
3026         chv_phy_pre_pll_enable(encoder);
3027 }
3028
3029 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3030                                     struct intel_crtc_state *pipe_config,
3031                                     struct drm_connector_state *conn_state)
3032 {
3033         chv_phy_post_pll_disable(encoder);
3034 }
3035
3036 /*
3037  * Fetch AUX CH registers 0x202 - 0x207 which contain
3038  * link status information
3039  */
3040 bool
3041 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3042 {
3043         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3044                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3045 }
3046
3047 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3048 {
3049         uint8_t psr_caps = 0;
3050
3051         drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
3052         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3053 }
3054
3055 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3056 {
3057         uint8_t dprx = 0;
3058
3059         drm_dp_dpcd_readb(&intel_dp->aux,
3060                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3061                         &dprx);
3062         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3063 }
3064
3065 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3066 {
3067         uint8_t alpm_caps = 0;
3068
3069         drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
3070         return alpm_caps & DP_ALPM_CAP;
3071 }
3072
3073 /* These are source-specific values. */
3074 uint8_t
3075 intel_dp_voltage_max(struct intel_dp *intel_dp)
3076 {
3077         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3078         enum port port = dp_to_dig_port(intel_dp)->port;
3079
3080         if (IS_GEN9_LP(dev_priv))
3081                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3082         else if (INTEL_GEN(dev_priv) >= 9) {
3083                 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
3084                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3085                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3086         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3087                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3088         else if (IS_GEN7(dev_priv) && port == PORT_A)
3089                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3090         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3091                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3092         else
3093                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3094 }
3095
3096 uint8_t
3097 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3098 {
3099         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3100         enum port port = dp_to_dig_port(intel_dp)->port;
3101
3102         if (INTEL_GEN(dev_priv) >= 9) {
3103                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3104                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3105                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3106                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3107                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3108                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3109                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3110                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3111                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3112                 default:
3113                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3114                 }
3115         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3116                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3117                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3118                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3119                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3120                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3121                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3122                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3123                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3124                 default:
3125                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3126                 }
3127         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3128                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3129                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3130                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3131                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3132                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3133                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3134                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3135                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3136                 default:
3137                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3138                 }
3139         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3140                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3141                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3142                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3143                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3144                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3145                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3146                 default:
3147                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3148                 }
3149         } else {
3150                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3151                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3152                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3153                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3154                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3155                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3156                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3157                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3158                 default:
3159                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3160                 }
3161         }
3162 }
3163
3164 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3165 {
3166         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3167         unsigned long demph_reg_value, preemph_reg_value,
3168                 uniqtranscale_reg_value;
3169         uint8_t train_set = intel_dp->train_set[0];
3170
3171         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3172         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3173                 preemph_reg_value = 0x0004000;
3174                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3175                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3176                         demph_reg_value = 0x2B405555;
3177                         uniqtranscale_reg_value = 0x552AB83A;
3178                         break;
3179                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3180                         demph_reg_value = 0x2B404040;
3181                         uniqtranscale_reg_value = 0x5548B83A;
3182                         break;
3183                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3184                         demph_reg_value = 0x2B245555;
3185                         uniqtranscale_reg_value = 0x5560B83A;
3186                         break;
3187                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3188                         demph_reg_value = 0x2B405555;
3189                         uniqtranscale_reg_value = 0x5598DA3A;
3190                         break;
3191                 default:
3192                         return 0;
3193                 }
3194                 break;
3195         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3196                 preemph_reg_value = 0x0002000;
3197                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3198                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3199                         demph_reg_value = 0x2B404040;
3200                         uniqtranscale_reg_value = 0x5552B83A;
3201                         break;
3202                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3203                         demph_reg_value = 0x2B404848;
3204                         uniqtranscale_reg_value = 0x5580B83A;
3205                         break;
3206                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3207                         demph_reg_value = 0x2B404040;
3208                         uniqtranscale_reg_value = 0x55ADDA3A;
3209                         break;
3210                 default:
3211                         return 0;
3212                 }
3213                 break;
3214         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3215                 preemph_reg_value = 0x0000000;
3216                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3217                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3218                         demph_reg_value = 0x2B305555;
3219                         uniqtranscale_reg_value = 0x5570B83A;
3220                         break;
3221                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3222                         demph_reg_value = 0x2B2B4040;
3223                         uniqtranscale_reg_value = 0x55ADDA3A;
3224                         break;
3225                 default:
3226                         return 0;
3227                 }
3228                 break;
3229         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3230                 preemph_reg_value = 0x0006000;
3231                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3232                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3233                         demph_reg_value = 0x1B405555;
3234                         uniqtranscale_reg_value = 0x55ADDA3A;
3235                         break;
3236                 default:
3237                         return 0;
3238                 }
3239                 break;
3240         default:
3241                 return 0;
3242         }
3243
3244         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3245                                  uniqtranscale_reg_value, 0);
3246
3247         return 0;
3248 }
3249
3250 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3251 {
3252         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3253         u32 deemph_reg_value, margin_reg_value;
3254         bool uniq_trans_scale = false;
3255         uint8_t train_set = intel_dp->train_set[0];
3256
3257         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3258         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3259                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3260                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3261                         deemph_reg_value = 128;
3262                         margin_reg_value = 52;
3263                         break;
3264                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3265                         deemph_reg_value = 128;
3266                         margin_reg_value = 77;
3267                         break;
3268                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3269                         deemph_reg_value = 128;
3270                         margin_reg_value = 102;
3271                         break;
3272                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3273                         deemph_reg_value = 128;
3274                         margin_reg_value = 154;
3275                         uniq_trans_scale = true;
3276                         break;
3277                 default:
3278                         return 0;
3279                 }
3280                 break;
3281         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3282                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3283                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3284                         deemph_reg_value = 85;
3285                         margin_reg_value = 78;
3286                         break;
3287                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3288                         deemph_reg_value = 85;
3289                         margin_reg_value = 116;
3290                         break;
3291                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3292                         deemph_reg_value = 85;
3293                         margin_reg_value = 154;
3294                         break;
3295                 default:
3296                         return 0;
3297                 }
3298                 break;
3299         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3300                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3301                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3302                         deemph_reg_value = 64;
3303                         margin_reg_value = 104;
3304                         break;
3305                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3306                         deemph_reg_value = 64;
3307                         margin_reg_value = 154;
3308                         break;
3309                 default:
3310                         return 0;
3311                 }
3312                 break;
3313         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3314                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3315                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3316                         deemph_reg_value = 43;
3317                         margin_reg_value = 154;
3318                         break;
3319                 default:
3320                         return 0;
3321                 }
3322                 break;
3323         default:
3324                 return 0;
3325         }
3326
3327         chv_set_phy_signal_level(encoder, deemph_reg_value,
3328                                  margin_reg_value, uniq_trans_scale);
3329
3330         return 0;
3331 }
3332
3333 static uint32_t
3334 gen4_signal_levels(uint8_t train_set)
3335 {
3336         uint32_t        signal_levels = 0;
3337
3338         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3339         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3340         default:
3341                 signal_levels |= DP_VOLTAGE_0_4;
3342                 break;
3343         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3344                 signal_levels |= DP_VOLTAGE_0_6;
3345                 break;
3346         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3347                 signal_levels |= DP_VOLTAGE_0_8;
3348                 break;
3349         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3350                 signal_levels |= DP_VOLTAGE_1_2;
3351                 break;
3352         }
3353         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3354         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3355         default:
3356                 signal_levels |= DP_PRE_EMPHASIS_0;
3357                 break;
3358         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3359                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3360                 break;
3361         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3362                 signal_levels |= DP_PRE_EMPHASIS_6;
3363                 break;
3364         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3365                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3366                 break;
3367         }
3368         return signal_levels;
3369 }
3370
3371 /* Gen6's DP voltage swing and pre-emphasis control */
3372 static uint32_t
3373 gen6_edp_signal_levels(uint8_t train_set)
3374 {
3375         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3376                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3377         switch (signal_levels) {
3378         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3379         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3380                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3381         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3382                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3383         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3384         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3385                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3386         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3387         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3388                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3389         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3390         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3391                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3392         default:
3393                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3394                               "0x%x\n", signal_levels);
3395                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3396         }
3397 }
3398
3399 /* Gen7's DP voltage swing and pre-emphasis control */
3400 static uint32_t
3401 gen7_edp_signal_levels(uint8_t train_set)
3402 {
3403         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3404                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3405         switch (signal_levels) {
3406         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3407                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3408         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3409                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3410         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3411                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3412
3413         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3414                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3415         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3416                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3417
3418         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3419                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3420         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3421                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3422
3423         default:
3424                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3425                               "0x%x\n", signal_levels);
3426                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3427         }
3428 }
3429
3430 void
3431 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3432 {
3433         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3434         enum port port = intel_dig_port->port;
3435         struct drm_device *dev = intel_dig_port->base.base.dev;
3436         struct drm_i915_private *dev_priv = to_i915(dev);
3437         uint32_t signal_levels, mask = 0;
3438         uint8_t train_set = intel_dp->train_set[0];
3439
3440         if (HAS_DDI(dev_priv)) {
3441                 signal_levels = ddi_signal_levels(intel_dp);
3442
3443                 if (IS_GEN9_LP(dev_priv))
3444                         signal_levels = 0;
3445                 else
3446                         mask = DDI_BUF_EMP_MASK;
3447         } else if (IS_CHERRYVIEW(dev_priv)) {
3448                 signal_levels = chv_signal_levels(intel_dp);
3449         } else if (IS_VALLEYVIEW(dev_priv)) {
3450                 signal_levels = vlv_signal_levels(intel_dp);
3451         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3452                 signal_levels = gen7_edp_signal_levels(train_set);
3453                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3454         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3455                 signal_levels = gen6_edp_signal_levels(train_set);
3456                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3457         } else {
3458                 signal_levels = gen4_signal_levels(train_set);
3459                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3460         }
3461
3462         if (mask)
3463                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3464
3465         DRM_DEBUG_KMS("Using vswing level %d\n",
3466                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3467         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3468                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3469                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3470
3471         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3472
3473         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3474         POSTING_READ(intel_dp->output_reg);
3475 }
3476
3477 void
3478 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3479                                        uint8_t dp_train_pat)
3480 {
3481         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3482         struct drm_i915_private *dev_priv =
3483                 to_i915(intel_dig_port->base.base.dev);
3484
3485         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3486
3487         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3488         POSTING_READ(intel_dp->output_reg);
3489 }
3490
3491 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3492 {
3493         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3494         struct drm_device *dev = intel_dig_port->base.base.dev;
3495         struct drm_i915_private *dev_priv = to_i915(dev);
3496         enum port port = intel_dig_port->port;
3497         uint32_t val;
3498
3499         if (!HAS_DDI(dev_priv))
3500                 return;
3501
3502         val = I915_READ(DP_TP_CTL(port));
3503         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3504         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3505         I915_WRITE(DP_TP_CTL(port), val);
3506
3507         /*
3508          * On PORT_A we can have only eDP in SST mode. There the only reason
3509          * we need to set idle transmission mode is to work around a HW issue
3510          * where we enable the pipe while not in idle link-training mode.
3511          * In this case there is requirement to wait for a minimum number of
3512          * idle patterns to be sent.
3513          */
3514         if (port == PORT_A)
3515                 return;
3516
3517         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3518                                     DP_TP_STATUS_IDLE_DONE,
3519                                     DP_TP_STATUS_IDLE_DONE,
3520                                     1))
3521                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3522 }
3523
3524 static void
3525 intel_dp_link_down(struct intel_dp *intel_dp)
3526 {
3527         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3528         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3529         enum port port = intel_dig_port->port;
3530         struct drm_device *dev = intel_dig_port->base.base.dev;
3531         struct drm_i915_private *dev_priv = to_i915(dev);
3532         uint32_t DP = intel_dp->DP;
3533
3534         if (WARN_ON(HAS_DDI(dev_priv)))
3535                 return;
3536
3537         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3538                 return;
3539
3540         DRM_DEBUG_KMS("\n");
3541
3542         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3543             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3544                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3545                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3546         } else {
3547                 if (IS_CHERRYVIEW(dev_priv))
3548                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3549                 else
3550                         DP &= ~DP_LINK_TRAIN_MASK;
3551                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3552         }
3553         I915_WRITE(intel_dp->output_reg, DP);
3554         POSTING_READ(intel_dp->output_reg);
3555
3556         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3557         I915_WRITE(intel_dp->output_reg, DP);
3558         POSTING_READ(intel_dp->output_reg);
3559
3560         /*
3561          * HW workaround for IBX, we need to move the port
3562          * to transcoder A after disabling it to allow the
3563          * matching HDMI port to be enabled on transcoder A.
3564          */
3565         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3566                 /*
3567                  * We get CPU/PCH FIFO underruns on the other pipe when
3568                  * doing the workaround. Sweep them under the rug.
3569                  */
3570                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3571                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3572
3573                 /* always enable with pattern 1 (as per spec) */
3574                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3575                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3576                 I915_WRITE(intel_dp->output_reg, DP);
3577                 POSTING_READ(intel_dp->output_reg);
3578
3579                 DP &= ~DP_PORT_EN;
3580                 I915_WRITE(intel_dp->output_reg, DP);
3581                 POSTING_READ(intel_dp->output_reg);
3582
3583                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3584                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3585                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3586         }
3587
3588         msleep(intel_dp->panel_power_down_delay);
3589
3590         intel_dp->DP = DP;
3591
3592         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3593                 pps_lock(intel_dp);
3594                 intel_dp->active_pipe = INVALID_PIPE;
3595                 pps_unlock(intel_dp);
3596         }
3597 }
3598
3599 bool
3600 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3601 {
3602         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3603                              sizeof(intel_dp->dpcd)) < 0)
3604                 return false; /* aux transfer failed */
3605
3606         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3607
3608         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3609 }
3610
3611 static bool
3612 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3613 {
3614         struct drm_i915_private *dev_priv =
3615                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3616
3617         /* this function is meant to be called only once */
3618         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3619
3620         if (!intel_dp_read_dpcd(intel_dp))
3621                 return false;
3622
3623         intel_dp_read_desc(intel_dp);
3624
3625         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3626                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3627                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3628
3629         /* Check if the panel supports PSR */
3630         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3631                          intel_dp->psr_dpcd,
3632                          sizeof(intel_dp->psr_dpcd));
3633         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3634                 dev_priv->psr.sink_support = true;
3635                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3636         }
3637
3638         if (INTEL_GEN(dev_priv) >= 9 &&
3639             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3640                 uint8_t frame_sync_cap;
3641
3642                 dev_priv->psr.sink_support = true;
3643                 drm_dp_dpcd_read(&intel_dp->aux,
3644                                  DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3645                                  &frame_sync_cap, 1);
3646                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3647                 /* PSR2 needs frame sync as well */
3648                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3649                 DRM_DEBUG_KMS("PSR2 %s on sink",
3650                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3651
3652                 if (dev_priv->psr.psr2_support) {
3653                         dev_priv->psr.y_cord_support =
3654                                 intel_dp_get_y_cord_status(intel_dp);
3655                         dev_priv->psr.colorimetry_support =
3656                                 intel_dp_get_colorimetry_status(intel_dp);
3657                         dev_priv->psr.alpm =
3658                                 intel_dp_get_alpm_status(intel_dp);
3659                 }
3660
3661         }
3662
3663         /* Read the eDP Display control capabilities registers */
3664         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3665             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3666                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3667                              sizeof(intel_dp->edp_dpcd))
3668                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3669                               intel_dp->edp_dpcd);
3670
3671         /* Intermediate frequency support */
3672         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3673                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3674                 int i;
3675
3676                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3677                                 sink_rates, sizeof(sink_rates));
3678
3679                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3680                         int val = le16_to_cpu(sink_rates[i]);
3681
3682                         if (val == 0)
3683                                 break;
3684
3685                         /* Value read multiplied by 200kHz gives the per-lane
3686                          * link rate in kHz. The source rates are, however,
3687                          * stored in terms of LS_Clk kHz. The full conversion
3688                          * back to symbols is
3689                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3690                          */
3691                         intel_dp->sink_rates[i] = (val * 200) / 10;
3692                 }
3693                 intel_dp->num_sink_rates = i;
3694         }
3695
3696         return true;
3697 }
3698
3699
3700 static bool
3701 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3702 {
3703         if (!intel_dp_read_dpcd(intel_dp))
3704                 return false;
3705
3706         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3707                              &intel_dp->sink_count, 1) < 0)
3708                 return false;
3709
3710         /*
3711          * Sink count can change between short pulse hpd hence
3712          * a member variable in intel_dp will track any changes
3713          * between short pulse interrupts.
3714          */
3715         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3716
3717         /*
3718          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3719          * a dongle is present but no display. Unless we require to know
3720          * if a dongle is present or not, we don't need to update
3721          * downstream port information. So, an early return here saves
3722          * time from performing other operations which are not required.
3723          */
3724         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3725                 return false;
3726
3727         if (!drm_dp_is_branch(intel_dp->dpcd))
3728                 return true; /* native DP sink */
3729
3730         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3731                 return true; /* no per-port downstream info */
3732
3733         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3734                              intel_dp->downstream_ports,
3735                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3736                 return false; /* downstream port status fetch failed */
3737
3738         return true;
3739 }
3740
3741 static bool
3742 intel_dp_can_mst(struct intel_dp *intel_dp)
3743 {
3744         u8 buf[1];
3745
3746         if (!i915.enable_dp_mst)
3747                 return false;
3748
3749         if (!intel_dp->can_mst)
3750                 return false;
3751
3752         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3753                 return false;
3754
3755         if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3756                 return false;
3757
3758         return buf[0] & DP_MST_CAP;
3759 }
3760
3761 static void
3762 intel_dp_configure_mst(struct intel_dp *intel_dp)
3763 {
3764         if (!i915.enable_dp_mst)
3765                 return;
3766
3767         if (!intel_dp->can_mst)
3768                 return;
3769
3770         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3771
3772         if (intel_dp->is_mst)
3773                 DRM_DEBUG_KMS("Sink is MST capable\n");
3774         else
3775                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3776
3777         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3778                                         intel_dp->is_mst);
3779 }
3780
3781 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3782 {
3783         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3784         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3785         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3786         u8 buf;
3787         int ret = 0;
3788         int count = 0;
3789         int attempts = 10;
3790
3791         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3792                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3793                 ret = -EIO;
3794                 goto out;
3795         }
3796
3797         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3798                                buf & ~DP_TEST_SINK_START) < 0) {
3799                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3800                 ret = -EIO;
3801                 goto out;
3802         }
3803
3804         do {
3805                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3806
3807                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3808                                       DP_TEST_SINK_MISC, &buf) < 0) {
3809                         ret = -EIO;
3810                         goto out;
3811                 }
3812                 count = buf & DP_TEST_COUNT_MASK;
3813         } while (--attempts && count);
3814
3815         if (attempts == 0) {
3816                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3817                 ret = -ETIMEDOUT;
3818         }
3819
3820  out:
3821         hsw_enable_ips(intel_crtc);
3822         return ret;
3823 }
3824
3825 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3826 {
3827         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3828         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3829         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3830         u8 buf;
3831         int ret;
3832
3833         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3834                 return -EIO;
3835
3836         if (!(buf & DP_TEST_CRC_SUPPORTED))
3837                 return -ENOTTY;
3838
3839         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3840                 return -EIO;
3841
3842         if (buf & DP_TEST_SINK_START) {
3843                 ret = intel_dp_sink_crc_stop(intel_dp);
3844                 if (ret)
3845                         return ret;
3846         }
3847
3848         hsw_disable_ips(intel_crtc);
3849
3850         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3851                                buf | DP_TEST_SINK_START) < 0) {
3852                 hsw_enable_ips(intel_crtc);
3853                 return -EIO;
3854         }
3855
3856         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3857         return 0;
3858 }
3859
3860 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3861 {
3862         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3863         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3864         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3865         u8 buf;
3866         int count, ret;
3867         int attempts = 6;
3868
3869         ret = intel_dp_sink_crc_start(intel_dp);
3870         if (ret)
3871                 return ret;
3872
3873         do {
3874                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3875
3876                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3877                                       DP_TEST_SINK_MISC, &buf) < 0) {
3878                         ret = -EIO;
3879                         goto stop;
3880                 }
3881                 count = buf & DP_TEST_COUNT_MASK;
3882
3883         } while (--attempts && count == 0);
3884
3885         if (attempts == 0) {
3886                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3887                 ret = -ETIMEDOUT;
3888                 goto stop;
3889         }
3890
3891         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3892                 ret = -EIO;
3893                 goto stop;
3894         }
3895
3896 stop:
3897         intel_dp_sink_crc_stop(intel_dp);
3898         return ret;
3899 }
3900
3901 static bool
3902 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3903 {
3904         return drm_dp_dpcd_read(&intel_dp->aux,
3905                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3906                                        sink_irq_vector, 1) == 1;
3907 }
3908
3909 static bool
3910 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3911 {
3912         int ret;
3913
3914         ret = drm_dp_dpcd_read(&intel_dp->aux,
3915                                              DP_SINK_COUNT_ESI,
3916                                              sink_irq_vector, 14);
3917         if (ret != 14)
3918                 return false;
3919
3920         return true;
3921 }
3922
3923 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3924 {
3925         uint8_t test_result = DP_TEST_ACK;
3926         return test_result;
3927 }
3928
3929 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3930 {
3931         uint8_t test_result = DP_TEST_NAK;
3932         return test_result;
3933 }
3934
3935 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3936 {
3937         uint8_t test_result = DP_TEST_NAK;
3938         struct intel_connector *intel_connector = intel_dp->attached_connector;
3939         struct drm_connector *connector = &intel_connector->base;
3940
3941         if (intel_connector->detect_edid == NULL ||
3942             connector->edid_corrupt ||
3943             intel_dp->aux.i2c_defer_count > 6) {
3944                 /* Check EDID read for NACKs, DEFERs and corruption
3945                  * (DP CTS 1.2 Core r1.1)
3946                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3947                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3948                  *    4.2.2.6 : EDID corruption detected
3949                  * Use failsafe mode for all cases
3950                  */
3951                 if (intel_dp->aux.i2c_nack_count > 0 ||
3952                         intel_dp->aux.i2c_defer_count > 0)
3953                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3954                                       intel_dp->aux.i2c_nack_count,
3955                                       intel_dp->aux.i2c_defer_count);
3956                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3957         } else {
3958                 struct edid *block = intel_connector->detect_edid;
3959
3960                 /* We have to write the checksum
3961                  * of the last block read
3962                  */
3963                 block += intel_connector->detect_edid->extensions;
3964
3965                 if (!drm_dp_dpcd_write(&intel_dp->aux,
3966                                         DP_TEST_EDID_CHECKSUM,
3967                                         &block->checksum,
3968                                         1))
3969                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3970
3971                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3972                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_STANDARD;
3973         }
3974
3975         /* Set test active flag here so userspace doesn't interrupt things */
3976         intel_dp->compliance.test_active = 1;
3977
3978         return test_result;
3979 }
3980
3981 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3982 {
3983         uint8_t test_result = DP_TEST_NAK;
3984         return test_result;
3985 }
3986
3987 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3988 {
3989         uint8_t response = DP_TEST_NAK;
3990         uint8_t rxdata = 0;
3991         int status = 0;
3992
3993         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3994         if (status <= 0) {
3995                 DRM_DEBUG_KMS("Could not read test request from sink\n");
3996                 goto update_status;
3997         }
3998
3999         switch (rxdata) {
4000         case DP_TEST_LINK_TRAINING:
4001                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4002                 intel_dp->compliance.test_type = DP_TEST_LINK_TRAINING;
4003                 response = intel_dp_autotest_link_training(intel_dp);
4004                 break;
4005         case DP_TEST_LINK_VIDEO_PATTERN:
4006                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4007                 intel_dp->compliance.test_type = DP_TEST_LINK_VIDEO_PATTERN;
4008                 response = intel_dp_autotest_video_pattern(intel_dp);
4009                 break;
4010         case DP_TEST_LINK_EDID_READ:
4011                 DRM_DEBUG_KMS("EDID test requested\n");
4012                 intel_dp->compliance.test_type = DP_TEST_LINK_EDID_READ;
4013                 response = intel_dp_autotest_edid(intel_dp);
4014                 break;
4015         case DP_TEST_LINK_PHY_TEST_PATTERN:
4016                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4017                 intel_dp->compliance.test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4018                 response = intel_dp_autotest_phy_pattern(intel_dp);
4019                 break;
4020         default:
4021                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4022                 break;
4023         }
4024
4025 update_status:
4026         status = drm_dp_dpcd_write(&intel_dp->aux,
4027                                    DP_TEST_RESPONSE,
4028                                    &response, 1);
4029         if (status <= 0)
4030                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4031 }
4032
4033 static int
4034 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4035 {
4036         bool bret;
4037
4038         if (intel_dp->is_mst) {
4039                 u8 esi[16] = { 0 };
4040                 int ret = 0;
4041                 int retry;
4042                 bool handled;
4043                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4044 go_again:
4045                 if (bret == true) {
4046
4047                         /* check link status - esi[10] = 0x200c */
4048                         if (intel_dp->active_mst_links &&
4049                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4050                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4051                                 intel_dp_start_link_train(intel_dp);
4052                                 intel_dp_stop_link_train(intel_dp);
4053                         }
4054
4055                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4056                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4057
4058                         if (handled) {
4059                                 for (retry = 0; retry < 3; retry++) {
4060                                         int wret;
4061                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4062                                                                  DP_SINK_COUNT_ESI+1,
4063                                                                  &esi[1], 3);
4064                                         if (wret == 3) {
4065                                                 break;
4066                                         }
4067                                 }
4068
4069                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4070                                 if (bret == true) {
4071                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4072                                         goto go_again;
4073                                 }
4074                         } else
4075                                 ret = 0;
4076
4077                         return ret;
4078                 } else {
4079                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4080                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4081                         intel_dp->is_mst = false;
4082                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4083                         /* send a hotplug event */
4084                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4085                 }
4086         }
4087         return -EINVAL;
4088 }
4089
4090 static void
4091 intel_dp_retrain_link(struct intel_dp *intel_dp)
4092 {
4093         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4094         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4095         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4096
4097         /* Suppress underruns caused by re-training */
4098         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4099         if (crtc->config->has_pch_encoder)
4100                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4101                                                       intel_crtc_pch_transcoder(crtc), false);
4102
4103         intel_dp_start_link_train(intel_dp);
4104         intel_dp_stop_link_train(intel_dp);
4105
4106         /* Keep underrun reporting disabled until things are stable */
4107         intel_wait_for_vblank(dev_priv, crtc->pipe);
4108
4109         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4110         if (crtc->config->has_pch_encoder)
4111                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4112                                                       intel_crtc_pch_transcoder(crtc), true);
4113 }
4114
4115 static void
4116 intel_dp_check_link_status(struct intel_dp *intel_dp)
4117 {
4118         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4119         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4120         u8 link_status[DP_LINK_STATUS_SIZE];
4121
4122         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4123
4124         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4125                 DRM_ERROR("Failed to get link status\n");
4126                 return;
4127         }
4128
4129         if (!intel_encoder->base.crtc)
4130                 return;
4131
4132         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4133                 return;
4134
4135         /* FIXME: we need to synchronize this sort of stuff with hardware
4136          * readout. Currently fast link training doesn't work on boot-up. */
4137         if (!intel_dp->lane_count)
4138                 return;
4139
4140         /* if link training is requested we should perform it always */
4141         if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) ||
4142             (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4143                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4144                               intel_encoder->base.name);
4145
4146                 intel_dp_retrain_link(intel_dp);
4147         }
4148 }
4149
4150 /*
4151  * According to DP spec
4152  * 5.1.2:
4153  *  1. Read DPCD
4154  *  2. Configure link according to Receiver Capabilities
4155  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4156  *  4. Check link status on receipt of hot-plug interrupt
4157  *
4158  * intel_dp_short_pulse -  handles short pulse interrupts
4159  * when full detection is not required.
4160  * Returns %true if short pulse is handled and full detection
4161  * is NOT required and %false otherwise.
4162  */
4163 static bool
4164 intel_dp_short_pulse(struct intel_dp *intel_dp)
4165 {
4166         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4167         u8 sink_irq_vector = 0;
4168         u8 old_sink_count = intel_dp->sink_count;
4169         bool ret;
4170
4171         /*
4172          * Clearing compliance test variables to allow capturing
4173          * of values for next automated test request.
4174          */
4175         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4176
4177         /*
4178          * Now read the DPCD to see if it's actually running
4179          * If the current value of sink count doesn't match with
4180          * the value that was stored earlier or dpcd read failed
4181          * we need to do full detection
4182          */
4183         ret = intel_dp_get_dpcd(intel_dp);
4184
4185         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4186                 /* No need to proceed if we are going to do full detect */
4187                 return false;
4188         }
4189
4190         /* Try to read the source of the interrupt */
4191         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4192             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4193             sink_irq_vector != 0) {
4194                 /* Clear interrupt source */
4195                 drm_dp_dpcd_writeb(&intel_dp->aux,
4196                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4197                                    sink_irq_vector);
4198
4199                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4200                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4201                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4202                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4203         }
4204
4205         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4206         intel_dp_check_link_status(intel_dp);
4207         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4208
4209         return true;
4210 }
4211
4212 /* XXX this is probably wrong for multiple downstream ports */
4213 static enum drm_connector_status
4214 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4215 {
4216         uint8_t *dpcd = intel_dp->dpcd;
4217         uint8_t type;
4218
4219         if (!intel_dp_get_dpcd(intel_dp))
4220                 return connector_status_disconnected;
4221
4222         if (is_edp(intel_dp))
4223                 return connector_status_connected;
4224
4225         /* if there's no downstream port, we're done */
4226         if (!drm_dp_is_branch(dpcd))
4227                 return connector_status_connected;
4228
4229         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4230         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4231             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4232
4233                 return intel_dp->sink_count ?
4234                 connector_status_connected : connector_status_disconnected;
4235         }
4236
4237         if (intel_dp_can_mst(intel_dp))
4238                 return connector_status_connected;
4239
4240         /* If no HPD, poke DDC gently */
4241         if (drm_probe_ddc(&intel_dp->aux.ddc))
4242                 return connector_status_connected;
4243
4244         /* Well we tried, say unknown for unreliable port types */
4245         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4246                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4247                 if (type == DP_DS_PORT_TYPE_VGA ||
4248                     type == DP_DS_PORT_TYPE_NON_EDID)
4249                         return connector_status_unknown;
4250         } else {
4251                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4252                         DP_DWN_STRM_PORT_TYPE_MASK;
4253                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4254                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4255                         return connector_status_unknown;
4256         }
4257
4258         /* Anything else is out of spec, warn and ignore */
4259         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4260         return connector_status_disconnected;
4261 }
4262
4263 static enum drm_connector_status
4264 edp_detect(struct intel_dp *intel_dp)
4265 {
4266         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4267         struct drm_i915_private *dev_priv = to_i915(dev);
4268         enum drm_connector_status status;
4269
4270         status = intel_panel_detect(dev_priv);
4271         if (status == connector_status_unknown)
4272                 status = connector_status_connected;
4273
4274         return status;
4275 }
4276
4277 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4278                                        struct intel_digital_port *port)
4279 {
4280         u32 bit;
4281
4282         switch (port->port) {
4283         case PORT_A:
4284                 return true;
4285         case PORT_B:
4286                 bit = SDE_PORTB_HOTPLUG;
4287                 break;
4288         case PORT_C:
4289                 bit = SDE_PORTC_HOTPLUG;
4290                 break;
4291         case PORT_D:
4292                 bit = SDE_PORTD_HOTPLUG;
4293                 break;
4294         default:
4295                 MISSING_CASE(port->port);
4296                 return false;
4297         }
4298
4299         return I915_READ(SDEISR) & bit;
4300 }
4301
4302 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4303                                        struct intel_digital_port *port)
4304 {
4305         u32 bit;
4306
4307         switch (port->port) {
4308         case PORT_A:
4309                 return true;
4310         case PORT_B:
4311                 bit = SDE_PORTB_HOTPLUG_CPT;
4312                 break;
4313         case PORT_C:
4314                 bit = SDE_PORTC_HOTPLUG_CPT;
4315                 break;
4316         case PORT_D:
4317                 bit = SDE_PORTD_HOTPLUG_CPT;
4318                 break;
4319         case PORT_E:
4320                 bit = SDE_PORTE_HOTPLUG_SPT;
4321                 break;
4322         default:
4323                 MISSING_CASE(port->port);
4324                 return false;
4325         }
4326
4327         return I915_READ(SDEISR) & bit;
4328 }
4329
4330 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4331                                        struct intel_digital_port *port)
4332 {
4333         u32 bit;
4334
4335         switch (port->port) {
4336         case PORT_B:
4337                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4338                 break;
4339         case PORT_C:
4340                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4341                 break;
4342         case PORT_D:
4343                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4344                 break;
4345         default:
4346                 MISSING_CASE(port->port);
4347                 return false;
4348         }
4349
4350         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4351 }
4352
4353 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4354                                         struct intel_digital_port *port)
4355 {
4356         u32 bit;
4357
4358         switch (port->port) {
4359         case PORT_B:
4360                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4361                 break;
4362         case PORT_C:
4363                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4364                 break;
4365         case PORT_D:
4366                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4367                 break;
4368         default:
4369                 MISSING_CASE(port->port);
4370                 return false;
4371         }
4372
4373         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4374 }
4375
4376 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4377                                        struct intel_digital_port *intel_dig_port)
4378 {
4379         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4380         enum port port;
4381         u32 bit;
4382
4383         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4384         switch (port) {
4385         case PORT_A:
4386                 bit = BXT_DE_PORT_HP_DDIA;
4387                 break;
4388         case PORT_B:
4389                 bit = BXT_DE_PORT_HP_DDIB;
4390                 break;
4391         case PORT_C:
4392                 bit = BXT_DE_PORT_HP_DDIC;
4393                 break;
4394         default:
4395                 MISSING_CASE(port);
4396                 return false;
4397         }
4398
4399         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4400 }
4401
4402 /*
4403  * intel_digital_port_connected - is the specified port connected?
4404  * @dev_priv: i915 private structure
4405  * @port: the port to test
4406  *
4407  * Return %true if @port is connected, %false otherwise.
4408  */
4409 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4410                                   struct intel_digital_port *port)
4411 {
4412         if (HAS_PCH_IBX(dev_priv))
4413                 return ibx_digital_port_connected(dev_priv, port);
4414         else if (HAS_PCH_SPLIT(dev_priv))
4415                 return cpt_digital_port_connected(dev_priv, port);
4416         else if (IS_GEN9_LP(dev_priv))
4417                 return bxt_digital_port_connected(dev_priv, port);
4418         else if (IS_GM45(dev_priv))
4419                 return gm45_digital_port_connected(dev_priv, port);
4420         else
4421                 return g4x_digital_port_connected(dev_priv, port);
4422 }
4423
4424 static struct edid *
4425 intel_dp_get_edid(struct intel_dp *intel_dp)
4426 {
4427         struct intel_connector *intel_connector = intel_dp->attached_connector;
4428
4429         /* use cached edid if we have one */
4430         if (intel_connector->edid) {
4431                 /* invalid edid */
4432                 if (IS_ERR(intel_connector->edid))
4433                         return NULL;
4434
4435                 return drm_edid_duplicate(intel_connector->edid);
4436         } else
4437                 return drm_get_edid(&intel_connector->base,
4438                                     &intel_dp->aux.ddc);
4439 }
4440
4441 static void
4442 intel_dp_set_edid(struct intel_dp *intel_dp)
4443 {
4444         struct intel_connector *intel_connector = intel_dp->attached_connector;
4445         struct edid *edid;
4446
4447         intel_dp_unset_edid(intel_dp);
4448         edid = intel_dp_get_edid(intel_dp);
4449         intel_connector->detect_edid = edid;
4450
4451         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4452                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4453         else
4454                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4455 }
4456
4457 static void
4458 intel_dp_unset_edid(struct intel_dp *intel_dp)
4459 {
4460         struct intel_connector *intel_connector = intel_dp->attached_connector;
4461
4462         kfree(intel_connector->detect_edid);
4463         intel_connector->detect_edid = NULL;
4464
4465         intel_dp->has_audio = false;
4466 }
4467
4468 static enum drm_connector_status
4469 intel_dp_long_pulse(struct intel_connector *intel_connector)
4470 {
4471         struct drm_connector *connector = &intel_connector->base;
4472         struct intel_dp *intel_dp = intel_attached_dp(connector);
4473         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4474         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4475         struct drm_device *dev = connector->dev;
4476         enum drm_connector_status status;
4477         enum intel_display_power_domain power_domain;
4478         u8 sink_irq_vector = 0;
4479
4480         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4481         intel_display_power_get(to_i915(dev), power_domain);
4482
4483         /* Can't disconnect eDP, but you can close the lid... */
4484         if (is_edp(intel_dp))
4485                 status = edp_detect(intel_dp);
4486         else if (intel_digital_port_connected(to_i915(dev),
4487                                               dp_to_dig_port(intel_dp)))
4488                 status = intel_dp_detect_dpcd(intel_dp);
4489         else
4490                 status = connector_status_disconnected;
4491
4492         if (status == connector_status_disconnected) {
4493                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4494
4495                 if (intel_dp->is_mst) {
4496                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4497                                       intel_dp->is_mst,
4498                                       intel_dp->mst_mgr.mst_state);
4499                         intel_dp->is_mst = false;
4500                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4501                                                         intel_dp->is_mst);
4502                 }
4503
4504                 goto out;
4505         }
4506
4507         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4508                 intel_encoder->type = INTEL_OUTPUT_DP;
4509
4510         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4511                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
4512                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4513
4514         /* Set the max lane count for sink */
4515         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
4516
4517         /* Set the max link BW for sink */
4518         intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
4519
4520         intel_dp_print_rates(intel_dp);
4521
4522         intel_dp_read_desc(intel_dp);
4523
4524         intel_dp_configure_mst(intel_dp);
4525
4526         if (intel_dp->is_mst) {
4527                 /*
4528                  * If we are in MST mode then this connector
4529                  * won't appear connected or have anything
4530                  * with EDID on it
4531                  */
4532                 status = connector_status_disconnected;
4533                 goto out;
4534         } else if (connector->status == connector_status_connected) {
4535                 /*
4536                  * If display was connected already and is still connected
4537                  * check links status, there has been known issues of
4538                  * link loss triggerring long pulse!!!!
4539                  */
4540                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4541                 intel_dp_check_link_status(intel_dp);
4542                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4543                 goto out;
4544         }
4545
4546         /*
4547          * Clearing NACK and defer counts to get their exact values
4548          * while reading EDID which are required by Compliance tests
4549          * 4.2.2.4 and 4.2.2.5
4550          */
4551         intel_dp->aux.i2c_nack_count = 0;
4552         intel_dp->aux.i2c_defer_count = 0;
4553
4554         intel_dp_set_edid(intel_dp);
4555         if (is_edp(intel_dp) || intel_connector->detect_edid)
4556                 status = connector_status_connected;
4557         intel_dp->detect_done = true;
4558
4559         /* Try to read the source of the interrupt */
4560         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4561             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4562             sink_irq_vector != 0) {
4563                 /* Clear interrupt source */
4564                 drm_dp_dpcd_writeb(&intel_dp->aux,
4565                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4566                                    sink_irq_vector);
4567
4568                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4569                         intel_dp_handle_test_request(intel_dp);
4570                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4571                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4572         }
4573
4574 out:
4575         if (status != connector_status_connected && !intel_dp->is_mst)
4576                 intel_dp_unset_edid(intel_dp);
4577
4578         intel_display_power_put(to_i915(dev), power_domain);
4579         return status;
4580 }
4581
4582 static enum drm_connector_status
4583 intel_dp_detect(struct drm_connector *connector, bool force)
4584 {
4585         struct intel_dp *intel_dp = intel_attached_dp(connector);
4586         enum drm_connector_status status = connector->status;
4587
4588         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4589                       connector->base.id, connector->name);
4590
4591         /* If full detect is not performed yet, do a full detect */
4592         if (!intel_dp->detect_done)
4593                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4594
4595         intel_dp->detect_done = false;
4596
4597         return status;
4598 }
4599
4600 static void
4601 intel_dp_force(struct drm_connector *connector)
4602 {
4603         struct intel_dp *intel_dp = intel_attached_dp(connector);
4604         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4605         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4606         enum intel_display_power_domain power_domain;
4607
4608         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4609                       connector->base.id, connector->name);
4610         intel_dp_unset_edid(intel_dp);
4611
4612         if (connector->status != connector_status_connected)
4613                 return;
4614
4615         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4616         intel_display_power_get(dev_priv, power_domain);
4617
4618         intel_dp_set_edid(intel_dp);
4619
4620         intel_display_power_put(dev_priv, power_domain);
4621
4622         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4623                 intel_encoder->type = INTEL_OUTPUT_DP;
4624 }
4625
4626 static int intel_dp_get_modes(struct drm_connector *connector)
4627 {
4628         struct intel_connector *intel_connector = to_intel_connector(connector);
4629         struct edid *edid;
4630
4631         edid = intel_connector->detect_edid;
4632         if (edid) {
4633                 int ret = intel_connector_update_modes(connector, edid);
4634                 if (ret)
4635                         return ret;
4636         }
4637
4638         /* if eDP has no EDID, fall back to fixed mode */
4639         if (is_edp(intel_attached_dp(connector)) &&
4640             intel_connector->panel.fixed_mode) {
4641                 struct drm_display_mode *mode;
4642
4643                 mode = drm_mode_duplicate(connector->dev,
4644                                           intel_connector->panel.fixed_mode);
4645                 if (mode) {
4646                         drm_mode_probed_add(connector, mode);
4647                         return 1;
4648                 }
4649         }
4650
4651         return 0;
4652 }
4653
4654 static bool
4655 intel_dp_detect_audio(struct drm_connector *connector)
4656 {
4657         bool has_audio = false;
4658         struct edid *edid;
4659
4660         edid = to_intel_connector(connector)->detect_edid;
4661         if (edid)
4662                 has_audio = drm_detect_monitor_audio(edid);
4663
4664         return has_audio;
4665 }
4666
4667 static int
4668 intel_dp_set_property(struct drm_connector *connector,
4669                       struct drm_property *property,
4670                       uint64_t val)
4671 {
4672         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4673         struct intel_connector *intel_connector = to_intel_connector(connector);
4674         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4675         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4676         int ret;
4677
4678         ret = drm_object_property_set_value(&connector->base, property, val);
4679         if (ret)
4680                 return ret;
4681
4682         if (property == dev_priv->force_audio_property) {
4683                 int i = val;
4684                 bool has_audio;
4685
4686                 if (i == intel_dp->force_audio)
4687                         return 0;
4688
4689                 intel_dp->force_audio = i;
4690
4691                 if (i == HDMI_AUDIO_AUTO)
4692                         has_audio = intel_dp_detect_audio(connector);
4693                 else
4694                         has_audio = (i == HDMI_AUDIO_ON);
4695
4696                 if (has_audio == intel_dp->has_audio)
4697                         return 0;
4698
4699                 intel_dp->has_audio = has_audio;
4700                 goto done;
4701         }
4702
4703         if (property == dev_priv->broadcast_rgb_property) {
4704                 bool old_auto = intel_dp->color_range_auto;
4705                 bool old_range = intel_dp->limited_color_range;
4706
4707                 switch (val) {
4708                 case INTEL_BROADCAST_RGB_AUTO:
4709                         intel_dp->color_range_auto = true;
4710                         break;
4711                 case INTEL_BROADCAST_RGB_FULL:
4712                         intel_dp->color_range_auto = false;
4713                         intel_dp->limited_color_range = false;
4714                         break;
4715                 case INTEL_BROADCAST_RGB_LIMITED:
4716                         intel_dp->color_range_auto = false;
4717                         intel_dp->limited_color_range = true;
4718                         break;
4719                 default:
4720                         return -EINVAL;
4721                 }
4722
4723                 if (old_auto == intel_dp->color_range_auto &&
4724                     old_range == intel_dp->limited_color_range)
4725                         return 0;
4726
4727                 goto done;
4728         }
4729
4730         if (is_edp(intel_dp) &&
4731             property == connector->dev->mode_config.scaling_mode_property) {
4732                 if (val == DRM_MODE_SCALE_NONE) {
4733                         DRM_DEBUG_KMS("no scaling not supported\n");
4734                         return -EINVAL;
4735                 }
4736                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4737                     val == DRM_MODE_SCALE_CENTER) {
4738                         DRM_DEBUG_KMS("centering not supported\n");
4739                         return -EINVAL;
4740                 }
4741
4742                 if (intel_connector->panel.fitting_mode == val) {
4743                         /* the eDP scaling property is not changed */
4744                         return 0;
4745                 }
4746                 intel_connector->panel.fitting_mode = val;
4747
4748                 goto done;
4749         }
4750
4751         return -EINVAL;
4752
4753 done:
4754         if (intel_encoder->base.crtc)
4755                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4756
4757         return 0;
4758 }
4759
4760 static int
4761 intel_dp_connector_register(struct drm_connector *connector)
4762 {
4763         struct intel_dp *intel_dp = intel_attached_dp(connector);
4764         int ret;
4765
4766         ret = intel_connector_register(connector);
4767         if (ret)
4768                 return ret;
4769
4770         i915_debugfs_connector_add(connector);
4771
4772         DRM_DEBUG_KMS("registering %s bus for %s\n",
4773                       intel_dp->aux.name, connector->kdev->kobj.name);
4774
4775         intel_dp->aux.dev = connector->kdev;
4776         return drm_dp_aux_register(&intel_dp->aux);
4777 }
4778
4779 static void
4780 intel_dp_connector_unregister(struct drm_connector *connector)
4781 {
4782         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4783         intel_connector_unregister(connector);
4784 }
4785
4786 static void
4787 intel_dp_connector_destroy(struct drm_connector *connector)
4788 {
4789         struct intel_connector *intel_connector = to_intel_connector(connector);
4790
4791         kfree(intel_connector->detect_edid);
4792
4793         if (!IS_ERR_OR_NULL(intel_connector->edid))
4794                 kfree(intel_connector->edid);
4795
4796         /* Can't call is_edp() since the encoder may have been destroyed
4797          * already. */
4798         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4799                 intel_panel_fini(&intel_connector->panel);
4800
4801         drm_connector_cleanup(connector);
4802         kfree(connector);
4803 }
4804
4805 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4806 {
4807         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4808         struct intel_dp *intel_dp = &intel_dig_port->dp;
4809
4810         intel_dp_mst_encoder_cleanup(intel_dig_port);
4811         if (is_edp(intel_dp)) {
4812                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4813                 /*
4814                  * vdd might still be enabled do to the delayed vdd off.
4815                  * Make sure vdd is actually turned off here.
4816                  */
4817                 pps_lock(intel_dp);
4818                 edp_panel_vdd_off_sync(intel_dp);
4819                 pps_unlock(intel_dp);
4820
4821                 if (intel_dp->edp_notifier.notifier_call) {
4822                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4823                         intel_dp->edp_notifier.notifier_call = NULL;
4824                 }
4825         }
4826
4827         intel_dp_aux_fini(intel_dp);
4828
4829         drm_encoder_cleanup(encoder);
4830         kfree(intel_dig_port);
4831 }
4832
4833 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4834 {
4835         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4836
4837         if (!is_edp(intel_dp))
4838                 return;
4839
4840         /*
4841          * vdd might still be enabled do to the delayed vdd off.
4842          * Make sure vdd is actually turned off here.
4843          */
4844         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4845         pps_lock(intel_dp);
4846         edp_panel_vdd_off_sync(intel_dp);
4847         pps_unlock(intel_dp);
4848 }
4849
4850 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4851 {
4852         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4853         struct drm_device *dev = intel_dig_port->base.base.dev;
4854         struct drm_i915_private *dev_priv = to_i915(dev);
4855         enum intel_display_power_domain power_domain;
4856
4857         lockdep_assert_held(&dev_priv->pps_mutex);
4858
4859         if (!edp_have_panel_vdd(intel_dp))
4860                 return;
4861
4862         /*
4863          * The VDD bit needs a power domain reference, so if the bit is
4864          * already enabled when we boot or resume, grab this reference and
4865          * schedule a vdd off, so we don't hold on to the reference
4866          * indefinitely.
4867          */
4868         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4869         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4870         intel_display_power_get(dev_priv, power_domain);
4871
4872         edp_panel_vdd_schedule_off(intel_dp);
4873 }
4874
4875 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
4876 {
4877         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4878
4879         if ((intel_dp->DP & DP_PORT_EN) == 0)
4880                 return INVALID_PIPE;
4881
4882         if (IS_CHERRYVIEW(dev_priv))
4883                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4884         else
4885                 return PORT_TO_PIPE(intel_dp->DP);
4886 }
4887
4888 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4889 {
4890         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4891         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4892         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4893
4894         if (!HAS_DDI(dev_priv))
4895                 intel_dp->DP = I915_READ(intel_dp->output_reg);
4896
4897         if (lspcon->active)
4898                 lspcon_resume(lspcon);
4899
4900         pps_lock(intel_dp);
4901
4902         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4903                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
4904
4905         if (is_edp(intel_dp)) {
4906                 /* Reinit the power sequencer, in case BIOS did something with it. */
4907                 intel_dp_pps_init(encoder->dev, intel_dp);
4908                 intel_edp_panel_vdd_sanitize(intel_dp);
4909         }
4910
4911         pps_unlock(intel_dp);
4912 }
4913
4914 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4915         .dpms = drm_atomic_helper_connector_dpms,
4916         .detect = intel_dp_detect,
4917         .force = intel_dp_force,
4918         .fill_modes = drm_helper_probe_single_connector_modes,
4919         .set_property = intel_dp_set_property,
4920         .atomic_get_property = intel_connector_atomic_get_property,
4921         .late_register = intel_dp_connector_register,
4922         .early_unregister = intel_dp_connector_unregister,
4923         .destroy = intel_dp_connector_destroy,
4924         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4925         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4926 };
4927
4928 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4929         .get_modes = intel_dp_get_modes,
4930         .mode_valid = intel_dp_mode_valid,
4931 };
4932
4933 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4934         .reset = intel_dp_encoder_reset,
4935         .destroy = intel_dp_encoder_destroy,
4936 };
4937
4938 enum irqreturn
4939 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4940 {
4941         struct intel_dp *intel_dp = &intel_dig_port->dp;
4942         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4943         struct drm_device *dev = intel_dig_port->base.base.dev;
4944         struct drm_i915_private *dev_priv = to_i915(dev);
4945         enum intel_display_power_domain power_domain;
4946         enum irqreturn ret = IRQ_NONE;
4947
4948         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4949             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4950                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4951
4952         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4953                 /*
4954                  * vdd off can generate a long pulse on eDP which
4955                  * would require vdd on to handle it, and thus we
4956                  * would end up in an endless cycle of
4957                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4958                  */
4959                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4960                               port_name(intel_dig_port->port));
4961                 return IRQ_HANDLED;
4962         }
4963
4964         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4965                       port_name(intel_dig_port->port),
4966                       long_hpd ? "long" : "short");
4967
4968         if (long_hpd) {
4969                 intel_dp->detect_done = false;
4970                 return IRQ_NONE;
4971         }
4972
4973         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4974         intel_display_power_get(dev_priv, power_domain);
4975
4976         if (intel_dp->is_mst) {
4977                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4978                         /*
4979                          * If we were in MST mode, and device is not
4980                          * there, get out of MST mode
4981                          */
4982                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4983                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4984                         intel_dp->is_mst = false;
4985                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4986                                                         intel_dp->is_mst);
4987                         intel_dp->detect_done = false;
4988                         goto put_power;
4989                 }
4990         }
4991
4992         if (!intel_dp->is_mst) {
4993                 if (!intel_dp_short_pulse(intel_dp)) {
4994                         intel_dp->detect_done = false;
4995                         goto put_power;
4996                 }
4997         }
4998
4999         ret = IRQ_HANDLED;
5000
5001 put_power:
5002         intel_display_power_put(dev_priv, power_domain);
5003
5004         return ret;
5005 }
5006
5007 /* check the VBT to see whether the eDP is on another port */
5008 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5009 {
5010         /*
5011          * eDP not supported on g4x. so bail out early just
5012          * for a bit extra safety in case the VBT is bonkers.
5013          */
5014         if (INTEL_GEN(dev_priv) < 5)
5015                 return false;
5016
5017         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5018                 return true;
5019
5020         return intel_bios_is_port_edp(dev_priv, port);
5021 }
5022
5023 void
5024 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5025 {
5026         struct intel_connector *intel_connector = to_intel_connector(connector);
5027
5028         intel_attach_force_audio_property(connector);
5029         intel_attach_broadcast_rgb_property(connector);
5030         intel_dp->color_range_auto = true;
5031
5032         if (is_edp(intel_dp)) {
5033                 drm_mode_create_scaling_mode_property(connector->dev);
5034                 drm_object_attach_property(
5035                         &connector->base,
5036                         connector->dev->mode_config.scaling_mode_property,
5037                         DRM_MODE_SCALE_ASPECT);
5038                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5039         }
5040 }
5041
5042 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5043 {
5044         intel_dp->panel_power_off_time = ktime_get_boottime();
5045         intel_dp->last_power_on = jiffies;
5046         intel_dp->last_backlight_off = jiffies;
5047 }
5048
5049 static void
5050 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5051                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5052 {
5053         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5054         struct pps_registers regs;
5055
5056         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5057
5058         /* Workaround: Need to write PP_CONTROL with the unlock key as
5059          * the very first thing. */
5060         pp_ctl = ironlake_get_pp_control(intel_dp);
5061
5062         pp_on = I915_READ(regs.pp_on);
5063         pp_off = I915_READ(regs.pp_off);
5064         if (!IS_GEN9_LP(dev_priv)) {
5065                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5066                 pp_div = I915_READ(regs.pp_div);
5067         }
5068
5069         /* Pull timing values out of registers */
5070         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5071                      PANEL_POWER_UP_DELAY_SHIFT;
5072
5073         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5074                   PANEL_LIGHT_ON_DELAY_SHIFT;
5075
5076         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5077                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5078
5079         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5080                    PANEL_POWER_DOWN_DELAY_SHIFT;
5081
5082         if (IS_GEN9_LP(dev_priv)) {
5083                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5084                         BXT_POWER_CYCLE_DELAY_SHIFT;
5085                 if (tmp > 0)
5086                         seq->t11_t12 = (tmp - 1) * 1000;
5087                 else
5088                         seq->t11_t12 = 0;
5089         } else {
5090                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5091                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5092         }
5093 }
5094
5095 static void
5096 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5097 {
5098         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5099                       state_name,
5100                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5101 }
5102
5103 static void
5104 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5105                        struct intel_dp *intel_dp)
5106 {
5107         struct edp_power_seq hw;
5108         struct edp_power_seq *sw = &intel_dp->pps_delays;
5109
5110         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5111
5112         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5113             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5114                 DRM_ERROR("PPS state mismatch\n");
5115                 intel_pps_dump_state("sw", sw);
5116                 intel_pps_dump_state("hw", &hw);
5117         }
5118 }
5119
5120 static void
5121 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5122                                     struct intel_dp *intel_dp)
5123 {
5124         struct drm_i915_private *dev_priv = to_i915(dev);
5125         struct edp_power_seq cur, vbt, spec,
5126                 *final = &intel_dp->pps_delays;
5127
5128         lockdep_assert_held(&dev_priv->pps_mutex);
5129
5130         /* already initialized? */
5131         if (final->t11_t12 != 0)
5132                 return;
5133
5134         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5135
5136         intel_pps_dump_state("cur", &cur);
5137
5138         vbt = dev_priv->vbt.edp.pps;
5139
5140         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5141          * our hw here, which are all in 100usec. */
5142         spec.t1_t3 = 210 * 10;
5143         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5144         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5145         spec.t10 = 500 * 10;
5146         /* This one is special and actually in units of 100ms, but zero
5147          * based in the hw (so we need to add 100 ms). But the sw vbt
5148          * table multiplies it with 1000 to make it in units of 100usec,
5149          * too. */
5150         spec.t11_t12 = (510 + 100) * 10;
5151
5152         intel_pps_dump_state("vbt", &vbt);
5153
5154         /* Use the max of the register settings and vbt. If both are
5155          * unset, fall back to the spec limits. */
5156 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5157                                        spec.field : \
5158                                        max(cur.field, vbt.field))
5159         assign_final(t1_t3);
5160         assign_final(t8);
5161         assign_final(t9);
5162         assign_final(t10);
5163         assign_final(t11_t12);
5164 #undef assign_final
5165
5166 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5167         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5168         intel_dp->backlight_on_delay = get_delay(t8);
5169         intel_dp->backlight_off_delay = get_delay(t9);
5170         intel_dp->panel_power_down_delay = get_delay(t10);
5171         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5172 #undef get_delay
5173
5174         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5175                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5176                       intel_dp->panel_power_cycle_delay);
5177
5178         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5179                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5180
5181         /*
5182          * We override the HW backlight delays to 1 because we do manual waits
5183          * on them. For T8, even BSpec recommends doing it. For T9, if we
5184          * don't do this, we'll end up waiting for the backlight off delay
5185          * twice: once when we do the manual sleep, and once when we disable
5186          * the panel and wait for the PP_STATUS bit to become zero.
5187          */
5188         final->t8 = 1;
5189         final->t9 = 1;
5190 }
5191
5192 static void
5193 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5194                                               struct intel_dp *intel_dp,
5195                                               bool force_disable_vdd)
5196 {
5197         struct drm_i915_private *dev_priv = to_i915(dev);
5198         u32 pp_on, pp_off, pp_div, port_sel = 0;
5199         int div = dev_priv->rawclk_freq / 1000;
5200         struct pps_registers regs;
5201         enum port port = dp_to_dig_port(intel_dp)->port;
5202         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5203
5204         lockdep_assert_held(&dev_priv->pps_mutex);
5205
5206         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5207
5208         /*
5209          * On some VLV machines the BIOS can leave the VDD
5210          * enabled even on power seqeuencers which aren't
5211          * hooked up to any port. This would mess up the
5212          * power domain tracking the first time we pick
5213          * one of these power sequencers for use since
5214          * edp_panel_vdd_on() would notice that the VDD was
5215          * already on and therefore wouldn't grab the power
5216          * domain reference. Disable VDD first to avoid this.
5217          * This also avoids spuriously turning the VDD on as
5218          * soon as the new power seqeuencer gets initialized.
5219          */
5220         if (force_disable_vdd) {
5221                 u32 pp = ironlake_get_pp_control(intel_dp);
5222
5223                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5224
5225                 if (pp & EDP_FORCE_VDD)
5226                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5227
5228                 pp &= ~EDP_FORCE_VDD;
5229
5230                 I915_WRITE(regs.pp_ctrl, pp);
5231         }
5232
5233         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5234                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5235         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5236                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5237         /* Compute the divisor for the pp clock, simply match the Bspec
5238          * formula. */
5239         if (IS_GEN9_LP(dev_priv)) {
5240                 pp_div = I915_READ(regs.pp_ctrl);
5241                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5242                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5243                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5244         } else {
5245                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5246                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5247                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5248         }
5249
5250         /* Haswell doesn't have any port selection bits for the panel
5251          * power sequencer any more. */
5252         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5253                 port_sel = PANEL_PORT_SELECT_VLV(port);
5254         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5255                 if (port == PORT_A)
5256                         port_sel = PANEL_PORT_SELECT_DPA;
5257                 else
5258                         port_sel = PANEL_PORT_SELECT_DPD;
5259         }
5260
5261         pp_on |= port_sel;
5262
5263         I915_WRITE(regs.pp_on, pp_on);
5264         I915_WRITE(regs.pp_off, pp_off);
5265         if (IS_GEN9_LP(dev_priv))
5266                 I915_WRITE(regs.pp_ctrl, pp_div);
5267         else
5268                 I915_WRITE(regs.pp_div, pp_div);
5269
5270         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5271                       I915_READ(regs.pp_on),
5272                       I915_READ(regs.pp_off),
5273                       IS_GEN9_LP(dev_priv) ?
5274                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5275                       I915_READ(regs.pp_div));
5276 }
5277
5278 static void intel_dp_pps_init(struct drm_device *dev,
5279                               struct intel_dp *intel_dp)
5280 {
5281         struct drm_i915_private *dev_priv = to_i915(dev);
5282
5283         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5284                 vlv_initial_power_sequencer_setup(intel_dp);
5285         } else {
5286                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5287                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5288         }
5289 }
5290
5291 /**
5292  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5293  * @dev_priv: i915 device
5294  * @crtc_state: a pointer to the active intel_crtc_state
5295  * @refresh_rate: RR to be programmed
5296  *
5297  * This function gets called when refresh rate (RR) has to be changed from
5298  * one frequency to another. Switches can be between high and low RR
5299  * supported by the panel or to any other RR based on media playback (in
5300  * this case, RR value needs to be passed from user space).
5301  *
5302  * The caller of this function needs to take a lock on dev_priv->drrs.
5303  */
5304 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5305                                     struct intel_crtc_state *crtc_state,
5306                                     int refresh_rate)
5307 {
5308         struct intel_encoder *encoder;
5309         struct intel_digital_port *dig_port = NULL;
5310         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5312         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5313
5314         if (refresh_rate <= 0) {
5315                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5316                 return;
5317         }
5318
5319         if (intel_dp == NULL) {
5320                 DRM_DEBUG_KMS("DRRS not supported.\n");
5321                 return;
5322         }
5323
5324         /*
5325          * FIXME: This needs proper synchronization with psr state for some
5326          * platforms that cannot have PSR and DRRS enabled at the same time.
5327          */
5328
5329         dig_port = dp_to_dig_port(intel_dp);
5330         encoder = &dig_port->base;
5331         intel_crtc = to_intel_crtc(encoder->base.crtc);
5332
5333         if (!intel_crtc) {
5334                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5335                 return;
5336         }
5337
5338         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5339                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5340                 return;
5341         }
5342
5343         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5344                         refresh_rate)
5345                 index = DRRS_LOW_RR;
5346
5347         if (index == dev_priv->drrs.refresh_rate_type) {
5348                 DRM_DEBUG_KMS(
5349                         "DRRS requested for previously set RR...ignoring\n");
5350                 return;
5351         }
5352
5353         if (!crtc_state->base.active) {
5354                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5355                 return;
5356         }
5357
5358         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5359                 switch (index) {
5360                 case DRRS_HIGH_RR:
5361                         intel_dp_set_m_n(intel_crtc, M1_N1);
5362                         break;
5363                 case DRRS_LOW_RR:
5364                         intel_dp_set_m_n(intel_crtc, M2_N2);
5365                         break;
5366                 case DRRS_MAX_RR:
5367                 default:
5368                         DRM_ERROR("Unsupported refreshrate type\n");
5369                 }
5370         } else if (INTEL_GEN(dev_priv) > 6) {
5371                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5372                 u32 val;
5373
5374                 val = I915_READ(reg);
5375                 if (index > DRRS_HIGH_RR) {
5376                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5377                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5378                         else
5379                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5380                 } else {
5381                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5382                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5383                         else
5384                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5385                 }
5386                 I915_WRITE(reg, val);
5387         }
5388
5389         dev_priv->drrs.refresh_rate_type = index;
5390
5391         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5392 }
5393
5394 /**
5395  * intel_edp_drrs_enable - init drrs struct if supported
5396  * @intel_dp: DP struct
5397  * @crtc_state: A pointer to the active crtc state.
5398  *
5399  * Initializes frontbuffer_bits and drrs.dp
5400  */
5401 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5402                            struct intel_crtc_state *crtc_state)
5403 {
5404         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5405         struct drm_i915_private *dev_priv = to_i915(dev);
5406
5407         if (!crtc_state->has_drrs) {
5408                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5409                 return;
5410         }
5411
5412         mutex_lock(&dev_priv->drrs.mutex);
5413         if (WARN_ON(dev_priv->drrs.dp)) {
5414                 DRM_ERROR("DRRS already enabled\n");
5415                 goto unlock;
5416         }
5417
5418         dev_priv->drrs.busy_frontbuffer_bits = 0;
5419
5420         dev_priv->drrs.dp = intel_dp;
5421
5422 unlock:
5423         mutex_unlock(&dev_priv->drrs.mutex);
5424 }
5425
5426 /**
5427  * intel_edp_drrs_disable - Disable DRRS
5428  * @intel_dp: DP struct
5429  * @old_crtc_state: Pointer to old crtc_state.
5430  *
5431  */
5432 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5433                             struct intel_crtc_state *old_crtc_state)
5434 {
5435         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5436         struct drm_i915_private *dev_priv = to_i915(dev);
5437
5438         if (!old_crtc_state->has_drrs)
5439                 return;
5440
5441         mutex_lock(&dev_priv->drrs.mutex);
5442         if (!dev_priv->drrs.dp) {
5443                 mutex_unlock(&dev_priv->drrs.mutex);
5444                 return;
5445         }
5446
5447         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5448                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5449                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5450
5451         dev_priv->drrs.dp = NULL;
5452         mutex_unlock(&dev_priv->drrs.mutex);
5453
5454         cancel_delayed_work_sync(&dev_priv->drrs.work);
5455 }
5456
5457 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5458 {
5459         struct drm_i915_private *dev_priv =
5460                 container_of(work, typeof(*dev_priv), drrs.work.work);
5461         struct intel_dp *intel_dp;
5462
5463         mutex_lock(&dev_priv->drrs.mutex);
5464
5465         intel_dp = dev_priv->drrs.dp;
5466
5467         if (!intel_dp)
5468                 goto unlock;
5469
5470         /*
5471          * The delayed work can race with an invalidate hence we need to
5472          * recheck.
5473          */
5474
5475         if (dev_priv->drrs.busy_frontbuffer_bits)
5476                 goto unlock;
5477
5478         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5479                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5480
5481                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5482                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5483         }
5484
5485 unlock:
5486         mutex_unlock(&dev_priv->drrs.mutex);
5487 }
5488
5489 /**
5490  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5491  * @dev_priv: i915 device
5492  * @frontbuffer_bits: frontbuffer plane tracking bits
5493  *
5494  * This function gets called everytime rendering on the given planes start.
5495  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5496  *
5497  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5498  */
5499 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5500                                unsigned int frontbuffer_bits)
5501 {
5502         struct drm_crtc *crtc;
5503         enum pipe pipe;
5504
5505         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5506                 return;
5507
5508         cancel_delayed_work(&dev_priv->drrs.work);
5509
5510         mutex_lock(&dev_priv->drrs.mutex);
5511         if (!dev_priv->drrs.dp) {
5512                 mutex_unlock(&dev_priv->drrs.mutex);
5513                 return;
5514         }
5515
5516         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5517         pipe = to_intel_crtc(crtc)->pipe;
5518
5519         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5520         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5521
5522         /* invalidate means busy screen hence upclock */
5523         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5524                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5525                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5526
5527         mutex_unlock(&dev_priv->drrs.mutex);
5528 }
5529
5530 /**
5531  * intel_edp_drrs_flush - Restart Idleness DRRS
5532  * @dev_priv: i915 device
5533  * @frontbuffer_bits: frontbuffer plane tracking bits
5534  *
5535  * This function gets called every time rendering on the given planes has
5536  * completed or flip on a crtc is completed. So DRRS should be upclocked
5537  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5538  * if no other planes are dirty.
5539  *
5540  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5541  */
5542 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5543                           unsigned int frontbuffer_bits)
5544 {
5545         struct drm_crtc *crtc;
5546         enum pipe pipe;
5547
5548         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5549                 return;
5550
5551         cancel_delayed_work(&dev_priv->drrs.work);
5552
5553         mutex_lock(&dev_priv->drrs.mutex);
5554         if (!dev_priv->drrs.dp) {
5555                 mutex_unlock(&dev_priv->drrs.mutex);
5556                 return;
5557         }
5558
5559         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5560         pipe = to_intel_crtc(crtc)->pipe;
5561
5562         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5563         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5564
5565         /* flush means busy screen hence upclock */
5566         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5567                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5568                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5569
5570         /*
5571          * flush also means no more activity hence schedule downclock, if all
5572          * other fbs are quiescent too
5573          */
5574         if (!dev_priv->drrs.busy_frontbuffer_bits)
5575                 schedule_delayed_work(&dev_priv->drrs.work,
5576                                 msecs_to_jiffies(1000));
5577         mutex_unlock(&dev_priv->drrs.mutex);
5578 }
5579
5580 /**
5581  * DOC: Display Refresh Rate Switching (DRRS)
5582  *
5583  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5584  * which enables swtching between low and high refresh rates,
5585  * dynamically, based on the usage scenario. This feature is applicable
5586  * for internal panels.
5587  *
5588  * Indication that the panel supports DRRS is given by the panel EDID, which
5589  * would list multiple refresh rates for one resolution.
5590  *
5591  * DRRS is of 2 types - static and seamless.
5592  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5593  * (may appear as a blink on screen) and is used in dock-undock scenario.
5594  * Seamless DRRS involves changing RR without any visual effect to the user
5595  * and can be used during normal system usage. This is done by programming
5596  * certain registers.
5597  *
5598  * Support for static/seamless DRRS may be indicated in the VBT based on
5599  * inputs from the panel spec.
5600  *
5601  * DRRS saves power by switching to low RR based on usage scenarios.
5602  *
5603  * The implementation is based on frontbuffer tracking implementation.  When
5604  * there is a disturbance on the screen triggered by user activity or a periodic
5605  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5606  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5607  * made.
5608  *
5609  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5610  * and intel_edp_drrs_flush() are called.
5611  *
5612  * DRRS can be further extended to support other internal panels and also
5613  * the scenario of video playback wherein RR is set based on the rate
5614  * requested by userspace.
5615  */
5616
5617 /**
5618  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5619  * @intel_connector: eDP connector
5620  * @fixed_mode: preferred mode of panel
5621  *
5622  * This function is  called only once at driver load to initialize basic
5623  * DRRS stuff.
5624  *
5625  * Returns:
5626  * Downclock mode if panel supports it, else return NULL.
5627  * DRRS support is determined by the presence of downclock mode (apart
5628  * from VBT setting).
5629  */
5630 static struct drm_display_mode *
5631 intel_dp_drrs_init(struct intel_connector *intel_connector,
5632                 struct drm_display_mode *fixed_mode)
5633 {
5634         struct drm_connector *connector = &intel_connector->base;
5635         struct drm_device *dev = connector->dev;
5636         struct drm_i915_private *dev_priv = to_i915(dev);
5637         struct drm_display_mode *downclock_mode = NULL;
5638
5639         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5640         mutex_init(&dev_priv->drrs.mutex);
5641
5642         if (INTEL_GEN(dev_priv) <= 6) {
5643                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5644                 return NULL;
5645         }
5646
5647         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5648                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5649                 return NULL;
5650         }
5651
5652         downclock_mode = intel_find_panel_downclock
5653                                         (dev_priv, fixed_mode, connector);
5654
5655         if (!downclock_mode) {
5656                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5657                 return NULL;
5658         }
5659
5660         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5661
5662         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5663         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5664         return downclock_mode;
5665 }
5666
5667 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5668                                      struct intel_connector *intel_connector)
5669 {
5670         struct drm_connector *connector = &intel_connector->base;
5671         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5672         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5673         struct drm_device *dev = intel_encoder->base.dev;
5674         struct drm_i915_private *dev_priv = to_i915(dev);
5675         struct drm_display_mode *fixed_mode = NULL;
5676         struct drm_display_mode *downclock_mode = NULL;
5677         bool has_dpcd;
5678         struct drm_display_mode *scan;
5679         struct edid *edid;
5680         enum pipe pipe = INVALID_PIPE;
5681
5682         if (!is_edp(intel_dp))
5683                 return true;
5684
5685         /*
5686          * On IBX/CPT we may get here with LVDS already registered. Since the
5687          * driver uses the only internal power sequencer available for both
5688          * eDP and LVDS bail out early in this case to prevent interfering
5689          * with an already powered-on LVDS power sequencer.
5690          */
5691         if (intel_get_lvds_encoder(dev)) {
5692                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5693                 DRM_INFO("LVDS was detected, not registering eDP\n");
5694
5695                 return false;
5696         }
5697
5698         pps_lock(intel_dp);
5699
5700         intel_dp_init_panel_power_timestamps(intel_dp);
5701         intel_dp_pps_init(dev, intel_dp);
5702         intel_edp_panel_vdd_sanitize(intel_dp);
5703
5704         pps_unlock(intel_dp);
5705
5706         /* Cache DPCD and EDID for edp. */
5707         has_dpcd = intel_edp_init_dpcd(intel_dp);
5708
5709         if (!has_dpcd) {
5710                 /* if this fails, presume the device is a ghost */
5711                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5712                 goto out_vdd_off;
5713         }
5714
5715         mutex_lock(&dev->mode_config.mutex);
5716         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5717         if (edid) {
5718                 if (drm_add_edid_modes(connector, edid)) {
5719                         drm_mode_connector_update_edid_property(connector,
5720                                                                 edid);
5721                         drm_edid_to_eld(connector, edid);
5722                 } else {
5723                         kfree(edid);
5724                         edid = ERR_PTR(-EINVAL);
5725                 }
5726         } else {
5727                 edid = ERR_PTR(-ENOENT);
5728         }
5729         intel_connector->edid = edid;
5730
5731         /* prefer fixed mode from EDID if available */
5732         list_for_each_entry(scan, &connector->probed_modes, head) {
5733                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5734                         fixed_mode = drm_mode_duplicate(dev, scan);
5735                         downclock_mode = intel_dp_drrs_init(
5736                                                 intel_connector, fixed_mode);
5737                         break;
5738                 }
5739         }
5740
5741         /* fallback to VBT if available for eDP */
5742         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5743                 fixed_mode = drm_mode_duplicate(dev,
5744                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5745                 if (fixed_mode) {
5746                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5747                         connector->display_info.width_mm = fixed_mode->width_mm;
5748                         connector->display_info.height_mm = fixed_mode->height_mm;
5749                 }
5750         }
5751         mutex_unlock(&dev->mode_config.mutex);
5752
5753         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5754                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5755                 register_reboot_notifier(&intel_dp->edp_notifier);
5756
5757                 /*
5758                  * Figure out the current pipe for the initial backlight setup.
5759                  * If the current pipe isn't valid, try the PPS pipe, and if that
5760                  * fails just assume pipe A.
5761                  */
5762                 pipe = vlv_active_pipe(intel_dp);
5763
5764                 if (pipe != PIPE_A && pipe != PIPE_B)
5765                         pipe = intel_dp->pps_pipe;
5766
5767                 if (pipe != PIPE_A && pipe != PIPE_B)
5768                         pipe = PIPE_A;
5769
5770                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5771                               pipe_name(pipe));
5772         }
5773
5774         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5775         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5776         intel_panel_setup_backlight(connector, pipe);
5777
5778         return true;
5779
5780 out_vdd_off:
5781         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5782         /*
5783          * vdd might still be enabled do to the delayed vdd off.
5784          * Make sure vdd is actually turned off here.
5785          */
5786         pps_lock(intel_dp);
5787         edp_panel_vdd_off_sync(intel_dp);
5788         pps_unlock(intel_dp);
5789
5790         return false;
5791 }
5792
5793 bool
5794 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5795                         struct intel_connector *intel_connector)
5796 {
5797         struct drm_connector *connector = &intel_connector->base;
5798         struct intel_dp *intel_dp = &intel_dig_port->dp;
5799         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5800         struct drm_device *dev = intel_encoder->base.dev;
5801         struct drm_i915_private *dev_priv = to_i915(dev);
5802         enum port port = intel_dig_port->port;
5803         int type;
5804
5805         if (WARN(intel_dig_port->max_lanes < 1,
5806                  "Not enough lanes (%d) for DP on port %c\n",
5807                  intel_dig_port->max_lanes, port_name(port)))
5808                 return false;
5809
5810         intel_dp->pps_pipe = INVALID_PIPE;
5811         intel_dp->active_pipe = INVALID_PIPE;
5812
5813         /* intel_dp vfuncs */
5814         if (INTEL_GEN(dev_priv) >= 9)
5815                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5816         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5817                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5818         else if (HAS_PCH_SPLIT(dev_priv))
5819                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5820         else
5821                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5822
5823         if (INTEL_GEN(dev_priv) >= 9)
5824                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5825         else
5826                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5827
5828         if (HAS_DDI(dev_priv))
5829                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5830
5831         /* Preserve the current hw state. */
5832         intel_dp->DP = I915_READ(intel_dp->output_reg);
5833         intel_dp->attached_connector = intel_connector;
5834
5835         if (intel_dp_is_edp(dev_priv, port))
5836                 type = DRM_MODE_CONNECTOR_eDP;
5837         else
5838                 type = DRM_MODE_CONNECTOR_DisplayPort;
5839
5840         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5841                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5842
5843         /*
5844          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5845          * for DP the encoder type can be set by the caller to
5846          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5847          */
5848         if (type == DRM_MODE_CONNECTOR_eDP)
5849                 intel_encoder->type = INTEL_OUTPUT_EDP;
5850
5851         /* eDP only on port B and/or C on vlv/chv */
5852         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5853                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5854                 return false;
5855
5856         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5857                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5858                         port_name(port));
5859
5860         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5861         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5862
5863         connector->interlace_allowed = true;
5864         connector->doublescan_allowed = 0;
5865
5866         intel_dp_aux_init(intel_dp);
5867
5868         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5869                           edp_panel_vdd_work);
5870
5871         intel_connector_attach_encoder(intel_connector, intel_encoder);
5872
5873         if (HAS_DDI(dev_priv))
5874                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5875         else
5876                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5877
5878         /* Set up the hotplug pin. */
5879         switch (port) {
5880         case PORT_A:
5881                 intel_encoder->hpd_pin = HPD_PORT_A;
5882                 break;
5883         case PORT_B:
5884                 intel_encoder->hpd_pin = HPD_PORT_B;
5885                 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
5886                         intel_encoder->hpd_pin = HPD_PORT_A;
5887                 break;
5888         case PORT_C:
5889                 intel_encoder->hpd_pin = HPD_PORT_C;
5890                 break;
5891         case PORT_D:
5892                 intel_encoder->hpd_pin = HPD_PORT_D;
5893                 break;
5894         case PORT_E:
5895                 intel_encoder->hpd_pin = HPD_PORT_E;
5896                 break;
5897         default:
5898                 BUG();
5899         }
5900
5901         /* init MST on ports that can support it */
5902         if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
5903             (port == PORT_B || port == PORT_C || port == PORT_D))
5904                 intel_dp_mst_encoder_init(intel_dig_port,
5905                                           intel_connector->base.base.id);
5906
5907         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5908                 intel_dp_aux_fini(intel_dp);
5909                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5910                 goto fail;
5911         }
5912
5913         intel_dp_add_properties(intel_dp, connector);
5914
5915         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5916          * 0xd.  Failure to do so will result in spurious interrupts being
5917          * generated on the port when a cable is not attached.
5918          */
5919         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
5920                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5921                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5922         }
5923
5924         return true;
5925
5926 fail:
5927         drm_connector_cleanup(connector);
5928
5929         return false;
5930 }
5931
5932 bool intel_dp_init(struct drm_i915_private *dev_priv,
5933                    i915_reg_t output_reg,
5934                    enum port port)
5935 {
5936         struct intel_digital_port *intel_dig_port;
5937         struct intel_encoder *intel_encoder;
5938         struct drm_encoder *encoder;
5939         struct intel_connector *intel_connector;
5940
5941         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5942         if (!intel_dig_port)
5943                 return false;
5944
5945         intel_connector = intel_connector_alloc();
5946         if (!intel_connector)
5947                 goto err_connector_alloc;
5948
5949         intel_encoder = &intel_dig_port->base;
5950         encoder = &intel_encoder->base;
5951
5952         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
5953                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
5954                              "DP %c", port_name(port)))
5955                 goto err_encoder_init;
5956
5957         intel_encoder->compute_config = intel_dp_compute_config;
5958         intel_encoder->disable = intel_disable_dp;
5959         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5960         intel_encoder->get_config = intel_dp_get_config;
5961         intel_encoder->suspend = intel_dp_encoder_suspend;
5962         if (IS_CHERRYVIEW(dev_priv)) {
5963                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5964                 intel_encoder->pre_enable = chv_pre_enable_dp;
5965                 intel_encoder->enable = vlv_enable_dp;
5966                 intel_encoder->post_disable = chv_post_disable_dp;
5967                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5968         } else if (IS_VALLEYVIEW(dev_priv)) {
5969                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5970                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5971                 intel_encoder->enable = vlv_enable_dp;
5972                 intel_encoder->post_disable = vlv_post_disable_dp;
5973         } else {
5974                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5975                 intel_encoder->enable = g4x_enable_dp;
5976                 if (INTEL_GEN(dev_priv) >= 5)
5977                         intel_encoder->post_disable = ilk_post_disable_dp;
5978         }
5979
5980         intel_dig_port->port = port;
5981         intel_dig_port->dp.output_reg = output_reg;
5982         intel_dig_port->max_lanes = 4;
5983
5984         intel_encoder->type = INTEL_OUTPUT_DP;
5985         if (IS_CHERRYVIEW(dev_priv)) {
5986                 if (port == PORT_D)
5987                         intel_encoder->crtc_mask = 1 << 2;
5988                 else
5989                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5990         } else {
5991                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5992         }
5993         intel_encoder->cloneable = 0;
5994         intel_encoder->port = port;
5995
5996         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5997         dev_priv->hotplug.irq_port[port] = intel_dig_port;
5998
5999         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6000                 goto err_init_connector;
6001
6002         return true;
6003
6004 err_init_connector:
6005         drm_encoder_cleanup(encoder);
6006 err_encoder_init:
6007         kfree(intel_connector);
6008 err_connector_alloc:
6009         kfree(intel_dig_port);
6010         return false;
6011 }
6012
6013 void intel_dp_mst_suspend(struct drm_device *dev)
6014 {
6015         struct drm_i915_private *dev_priv = to_i915(dev);
6016         int i;
6017
6018         /* disable MST */
6019         for (i = 0; i < I915_MAX_PORTS; i++) {
6020                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6021
6022                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6023                         continue;
6024
6025                 if (intel_dig_port->dp.is_mst)
6026                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6027         }
6028 }
6029
6030 void intel_dp_mst_resume(struct drm_device *dev)
6031 {
6032         struct drm_i915_private *dev_priv = to_i915(dev);
6033         int i;
6034
6035         for (i = 0; i < I915_MAX_PORTS; i++) {
6036                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6037                 int ret;
6038
6039                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6040                         continue;
6041
6042                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6043                 if (ret)
6044                         intel_dp_check_mst_status(&intel_dig_port->dp);
6045         }
6046 }