2 * Copyright © 2014-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_DEVICE_INFO_H_
26 #define _INTEL_DEVICE_INFO_H_
28 #include "intel_display.h"
31 struct drm_i915_private;
33 /* Keep in gen based order, and chronological order within a gen */
35 INTEL_PLATFORM_UNINITIALIZED = 0,
77 #define DEV_INFO_FOR_EACH_FLAG(func) \
80 func(is_alpha_support); \
81 /* Keep has_* in alphabetical order */ \
82 func(has_64bit_reloc); \
83 func(has_aliasing_ppgtt); \
87 func(has_reset_engine); \
90 func(has_full_ppgtt); \
91 func(has_full_48bit_ppgtt); \
92 func(has_gmch_display); \
98 func(has_logical_ring_contexts); \
99 func(has_logical_ring_preemption); \
101 func(has_pooled_eu); \
105 func(has_resource_streamer); \
106 func(has_runtime_pm); \
108 func(unfenced_needs_alignment); \
109 func(cursor_needs_physical); \
110 func(hws_needs_physical); \
111 func(overlay_needs_physical); \
115 struct sseu_dev_info {
121 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
124 u8 has_subslice_pg:1;
128 struct intel_device_info {
133 u8 gt; /* GT number, 0 if undefined */
135 u8 ring_mask; /* Rings supported by the HW */
137 enum intel_platform platform;
140 unsigned int page_sizes; /* page sizes supported by the HW */
142 u32 display_mmio_offset;
145 u8 num_sprites[I915_MAX_PIPES];
146 u8 num_scalers[I915_MAX_PIPES];
148 #define DEFINE_FLAG(name) u8 name:1
149 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
151 u16 ddb_size; /* in blocks */
153 /* Register offsets for the various display pipes and transcoders */
154 int pipe_offsets[I915_MAX_TRANSCODERS];
155 int trans_offsets[I915_MAX_TRANSCODERS];
156 int palette_offsets[I915_MAX_PIPES];
157 int cursor_offsets[I915_MAX_PIPES];
159 /* Slice/subslice/EU info */
160 struct sseu_dev_info sseu;
162 u32 cs_timestamp_frequency_khz;
165 u16 degamma_lut_size;
170 struct intel_driver_caps {
171 unsigned int scheduler;
174 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
176 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
179 const char *intel_platform_name(enum intel_platform platform);
181 void intel_device_info_runtime_init(struct intel_device_info *info);
182 void intel_device_info_dump(const struct intel_device_info *info,
183 struct drm_printer *p);
184 void intel_device_info_dump_flags(const struct intel_device_info *info,
185 struct drm_printer *p);
186 void intel_device_info_dump_runtime(const struct intel_device_info *info,
187 struct drm_printer *p);
189 void intel_driver_caps_print(const struct intel_driver_caps *caps,
190 struct drm_printer *p);