drivers/gpu/drm/i915/intel_device_info.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "i915_drv.h"
  26
  27 #define PLATFORM_NAME(x) [INTEL_##x] = #x
  28 static const char * const platform_names[] = {
  29         PLATFORM_NAME(I830),
  30         PLATFORM_NAME(I845G),
  31         PLATFORM_NAME(I85X),
  32         PLATFORM_NAME(I865G),
  33         PLATFORM_NAME(I915G),
  34         PLATFORM_NAME(I915GM),
  35         PLATFORM_NAME(I945G),
  36         PLATFORM_NAME(I945GM),
  37         PLATFORM_NAME(G33),
  38         PLATFORM_NAME(PINEVIEW),
  39         PLATFORM_NAME(I965G),
  40         PLATFORM_NAME(I965GM),
  41         PLATFORM_NAME(G45),
  42         PLATFORM_NAME(GM45),
  43         PLATFORM_NAME(IRONLAKE),
  44         PLATFORM_NAME(SANDYBRIDGE),
  45         PLATFORM_NAME(IVYBRIDGE),
  46         PLATFORM_NAME(VALLEYVIEW),
  47         PLATFORM_NAME(HASWELL),
  48         PLATFORM_NAME(BROADWELL),
  49         PLATFORM_NAME(CHERRYVIEW),
  50         PLATFORM_NAME(SKYLAKE),
  51         PLATFORM_NAME(BROXTON),
  52         PLATFORM_NAME(KABYLAKE),
  53         PLATFORM_NAME(GEMINILAKE),
  54         PLATFORM_NAME(COFFEELAKE),
  55         PLATFORM_NAME(CANNONLAKE),
  56 };
  57 #undef PLATFORM_NAME
  58
  59 const char *intel_platform_name(enum intel_platform platform)
  60 {
  61         BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
  62
  63         if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
  64                          platform_names[platform] == NULL))
  65                 return "<unknown>";
  66
  67         return platform_names[platform];
  68 }
  69
  70 void intel_device_info_dump(struct drm_i915_private *dev_priv)
  71 {
  72         const struct intel_device_info *info = &dev_priv->info;
  73
  74         DRM_DEBUG_DRIVER("i915 device info: platform=%s gen=%i pciid=0x%04x rev=0x%02x",
  75                          intel_platform_name(info->platform),
  76                          info->gen,
  77                          dev_priv->drm.pdev->device,
  78                          dev_priv->drm.pdev->revision);
  79 #define PRINT_FLAG(name) \
  80         DRM_DEBUG_DRIVER("i915 device info: " #name ": %s", yesno(info->name))
  81         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  82 #undef PRINT_FLAG
  83 }
  84
  85 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
  86 {
  87         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
  88         const u32 fuse2 = I915_READ(GEN8_FUSE2);
  89
  90         sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
  91                             GEN10_F2_S_ENA_SHIFT;
  92         sseu->subslice_mask = (1 << 4) - 1;
  93         sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
  94                                  GEN10_F2_SS_DIS_SHIFT);
  95
  96         sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
  97         sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
  98         sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
  99         sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
 100                                      GEN10_EU_DIS_SS_MASK));
 101
 102         /*
 103          * CNL is expected to always have a uniform distribution
 104          * of EU across subslices with the exception that any one
 105          * EU in any one subslice may be fused off for die
 106          * recovery.
 107          */
 108         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 109                                 DIV_ROUND_UP(sseu->eu_total,
 110                                              sseu_subslice_total(sseu)) : 0;
 111
 112         /* No restrictions on Power Gating */
 113         sseu->has_slice_pg = 1;
 114         sseu->has_subslice_pg = 1;
 115         sseu->has_eu_pg = 1;
 116 }
 117
 118 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 119 {
 120         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 121         u32 fuse, eu_dis;
 122
 123         fuse = I915_READ(CHV_FUSE_GT);
 124
 125         sseu->slice_mask = BIT(0);
 126
 127         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 128                 sseu->subslice_mask |= BIT(0);
 129                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 130                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 131                 sseu->eu_total += 8 - hweight32(eu_dis);
 132         }
 133
 134         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 135                 sseu->subslice_mask |= BIT(1);
 136                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 137                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 138                 sseu->eu_total += 8 - hweight32(eu_dis);
 139         }
 140
 141         /*
 142          * CHV expected to always have a uniform distribution of EU
 143          * across subslices.
 144         */
 145         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 146                                 sseu->eu_total / sseu_subslice_total(sseu) :
 147                                 0;
 148         /*
 149          * CHV supports subslice power gating on devices with more than
 150          * one subslice, and supports EU power gating on devices with
 151          * more than one EU pair per subslice.
 152         */
 153         sseu->has_slice_pg = 0;
 154         sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
 155         sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
 156 }
 157
 158 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 159 {
 160         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 161         struct sseu_dev_info *sseu = &info->sseu;
 162         int s_max = 3, ss_max = 4, eu_max = 8;
 163         int s, ss;
 164         u32 fuse2, eu_disable;
 165         u8 eu_mask = 0xff;
 166
 167         fuse2 = I915_READ(GEN8_FUSE2);
 168         sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 169
 170         /*
 171          * The subslice disable field is global, i.e. it applies
 172          * to each of the enabled slices.
 173         */
 174         sseu->subslice_mask = (1 << ss_max) - 1;
 175         sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
 176                                  GEN9_F2_SS_DIS_SHIFT);
 177
 178         /*
 179          * Iterate through enabled slices and subslices to
 180          * count the total enabled EU.
 181         */
 182         for (s = 0; s < s_max; s++) {
 183                 if (!(sseu->slice_mask & BIT(s)))
 184                         /* skip disabled slice */
 185                         continue;
 186
 187                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 188                 for (ss = 0; ss < ss_max; ss++) {
 189                         int eu_per_ss;
 190
 191                         if (!(sseu->subslice_mask & BIT(ss)))
 192                                 /* skip disabled subslice */
 193                                 continue;
 194
 195                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 196                                                       eu_mask);
 197
 198                         /*
 199                          * Record which subslice(s) has(have) 7 EUs. we
 200                          * can tune the hash used to spread work among
 201                          * subslices if they are unbalanced.
 202                          */
 203                         if (eu_per_ss == 7)
 204                                 sseu->subslice_7eu[s] |= BIT(ss);
 205
 206                         sseu->eu_total += eu_per_ss;
 207                 }
 208         }
 209
 210         /*
 211          * SKL is expected to always have a uniform distribution
 212          * of EU across subslices with the exception that any one
 213          * EU in any one subslice may be fused off for die
 214          * recovery. BXT is expected to be perfectly uniform in EU
 215          * distribution.
 216         */
 217         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 218                                 DIV_ROUND_UP(sseu->eu_total,
 219                                              sseu_subslice_total(sseu)) : 0;
 220         /*
 221          * SKL+ supports slice power gating on devices with more than
 222          * one slice, and supports EU power gating on devices with
 223          * more than one EU pair per subslice. BXT+ supports subslice
 224          * power gating on devices with more than one subslice, and
 225          * supports EU power gating on devices with more than one EU
 226          * pair per subslice.
 227         */
 228         sseu->has_slice_pg =
 229                 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
 230         sseu->has_subslice_pg =
 231                 IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
 232         sseu->has_eu_pg = sseu->eu_per_subslice > 2;
 233
 234         if (IS_GEN9_LP(dev_priv)) {
 235 #define IS_SS_DISABLED(ss)      (!(sseu->subslice_mask & BIT(ss)))
 236                 info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
 237
 238                 /*
 239                  * There is a HW issue in 2x6 fused down parts that requires
 240                  * Pooled EU to be enabled as a WA. The pool configuration
 241                  * changes depending upon which subslice is fused down. This
 242                  * doesn't affect if the device has all 3 subslices enabled.
 243                  */
 244                 /* WaEnablePooledEuFor2x6:bxt */
 245                 info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
 246                                         IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
 247
 248                 sseu->min_eu_in_pool = 0;
 249                 if (info->has_pooled_eu) {
 250                         if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
 251                                 sseu->min_eu_in_pool = 3;
 252                         else if (IS_SS_DISABLED(1))
 253                                 sseu->min_eu_in_pool = 6;
 254                         else
 255                                 sseu->min_eu_in_pool = 9;
 256                 }
 257 #undef IS_SS_DISABLED
 258         }
 259 }
 260
 261 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 262 {
 263         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 264         const int s_max = 3, ss_max = 3, eu_max = 8;
 265         int s, ss;
 266         u32 fuse2, eu_disable[3]; /* s_max */
 267
 268         fuse2 = I915_READ(GEN8_FUSE2);
 269         sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 270         /*
 271          * The subslice disable field is global, i.e. it applies
 272          * to each of the enabled slices.
 273          */
 274         sseu->subslice_mask = GENMASK(ss_max - 1, 0);
 275         sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
 276                                  GEN8_F2_SS_DIS_SHIFT);
 277
 278         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 279         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 280                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 281                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 282         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 283                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 284                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 285
 286         /*
 287          * Iterate through enabled slices and subslices to
 288          * count the total enabled EU.
 289          */
 290         for (s = 0; s < s_max; s++) {
 291                 if (!(sseu->slice_mask & BIT(s)))
 292                         /* skip disabled slice */
 293                         continue;
 294
 295                 for (ss = 0; ss < ss_max; ss++) {
 296                         u32 n_disabled;
 297
 298                         if (!(sseu->subslice_mask & BIT(ss)))
 299                                 /* skip disabled subslice */
 300                                 continue;
 301
 302                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 303
 304                         /*
 305                          * Record which subslices have 7 EUs.
 306                          */
 307                         if (eu_max - n_disabled == 7)
 308                                 sseu->subslice_7eu[s] |= 1 << ss;
 309
 310                         sseu->eu_total += eu_max - n_disabled;
 311                 }
 312         }
 313
 314         /*
 315          * BDW is expected to always have a uniform distribution of EU across
 316          * subslices with the exception that any one EU in any one subslice may
 317          * be fused off for die recovery.
 318          */
 319         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 320                                 DIV_ROUND_UP(sseu->eu_total,
 321                                              sseu_subslice_total(sseu)) : 0;
 322
 323         /*
 324          * BDW supports slice power gating on devices with more than
 325          * one slice.
 326          */
 327         sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
 328         sseu->has_subslice_pg = 0;
 329         sseu->has_eu_pg = 0;
 330 }
 331
 332 /*
 333  * Determine various intel_device_info fields at runtime.
 334  *
 335  * Use it when either:
 336  *   - it's judged too laborious to fill n static structures with the limit
 337  *     when a simple if statement does the job,
 338  *   - run-time checks (eg read fuse/strap registers) are needed.
 339  *
 340  * This function needs to be called:
 341  *   - after the MMIO has been setup as we are reading registers,
 342  *   - after the PCH has been detected,
 343  *   - before the first usage of the fields it can tweak.
 344  */
 345 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 346 {
 347         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 348         enum pipe pipe;
 349
 350         if (INTEL_GEN(dev_priv) >= 9) {
 351                 info->num_scalers[PIPE_A] = 2;
 352                 info->num_scalers[PIPE_B] = 2;
 353                 info->num_scalers[PIPE_C] = 1;
 354         }
 355
 356         /*
 357          * Skylake and Broxton currently don't expose the topmost plane as its
 358          * use is exclusive with the legacy cursor and we only want to expose
 359          * one of those, not both. Until we can safely expose the topmost plane
 360          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 361          * we don't expose the topmost plane at all to prevent ABI breakage
 362          * down the line.
 363          */
 364         if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
 365                 for_each_pipe(dev_priv, pipe)
 366                         info->num_sprites[pipe] = 3;
 367         else if (IS_BROXTON(dev_priv)) {
 368                 info->num_sprites[PIPE_A] = 2;
 369                 info->num_sprites[PIPE_B] = 2;
 370                 info->num_sprites[PIPE_C] = 1;
 371         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 372                 for_each_pipe(dev_priv, pipe)
 373                         info->num_sprites[pipe] = 2;
 374         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 375                 for_each_pipe(dev_priv, pipe)
 376                         info->num_sprites[pipe] = 1;
 377         }
 378
 379         if (i915_modparams.disable_display) {
 380                 DRM_INFO("Display disabled (module parameter)\n");
 381                 info->num_pipes = 0;
 382         } else if (info->num_pipes > 0 &&
 383                    (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
 384                    HAS_PCH_SPLIT(dev_priv)) {
 385                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 386                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 387
 388                 /*
 389                  * SFUSE_STRAP is supposed to have a bit signalling the display
 390                  * is fused off. Unfortunately it seems that, at least in
 391                  * certain cases, fused off display means that PCH display
 392                  * reads don't land anywhere. In that case, we read 0s.
 393                  *
 394                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 395                  * should be set when taking over after the firmware.
 396                  */
 397                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 398                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 399                     (HAS_PCH_CPT(dev_priv) &&
 400                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 401                         DRM_INFO("Display fused off, disabling\n");
 402                         info->num_pipes = 0;
 403                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 404                         DRM_INFO("PipeC fused off\n");
 405                         info->num_pipes -= 1;
 406                 }
 407         } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
 408                 u32 dfsm = I915_READ(SKL_DFSM);
 409                 u8 disabled_mask = 0;
 410                 bool invalid;
 411                 int num_bits;
 412
 413                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
 414                         disabled_mask |= BIT(PIPE_A);
 415                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
 416                         disabled_mask |= BIT(PIPE_B);
 417                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
 418                         disabled_mask |= BIT(PIPE_C);
 419
 420                 num_bits = hweight8(disabled_mask);
 421
 422                 switch (disabled_mask) {
 423                 case BIT(PIPE_A):
 424                 case BIT(PIPE_B):
 425                 case BIT(PIPE_A) | BIT(PIPE_B):
 426                 case BIT(PIPE_A) | BIT(PIPE_C):
 427                         invalid = true;
 428                         break;
 429                 default:
 430                         invalid = false;
 431                 }
 432
 433                 if (num_bits > info->num_pipes || invalid)
 434                         DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
 435                                   disabled_mask);
 436                 else
 437                         info->num_pipes -= num_bits;
 438         }
 439
 440         /* Initialize slice/subslice/EU info */
 441         if (IS_CHERRYVIEW(dev_priv))
 442                 cherryview_sseu_info_init(dev_priv);
 443         else if (IS_BROADWELL(dev_priv))
 444                 broadwell_sseu_info_init(dev_priv);
 445         else if (INTEL_GEN(dev_priv) == 9)
 446                 gen9_sseu_info_init(dev_priv);
 447         else if (INTEL_GEN(dev_priv) >= 10)
 448                 gen10_sseu_info_init(dev_priv);
 449
 450         DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
 451         DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
 452         DRM_DEBUG_DRIVER("subslice total: %u\n",
 453                          sseu_subslice_total(&info->sseu));
 454         DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask);
 455         DRM_DEBUG_DRIVER("subslice per slice: %u\n",
 456                          hweight8(info->sseu.subslice_mask));
 457         DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total);
 458         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice);
 459         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 460                          info->sseu.has_slice_pg ? "y" : "n");
 461         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 462                          info->sseu.has_subslice_pg ? "y" : "n");
 463         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 464                          info->sseu.has_eu_pg ? "y" : "n");
 465 }