drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_connector.h"
  33 #include "intel_ddi.h"
  34 #include "intel_dp.h"
  35 #include "intel_drv.h"
  36 #include "intel_dsi.h"
  37 #include "intel_hdcp.h"
  38 #include "intel_hdmi.h"
  39 #include "intel_lspcon.h"
  40 #include "intel_panel.h"
  41 #include "intel_psr.h"
  42
  43 struct ddi_buf_trans {
  44         u32 trans1;     /* balance leg enable, de-emph level */
  45         u32 trans2;     /* vref sel, vswing */
  46         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  47 };
  48
  49 static const u8 index_to_dp_signal_levels[] = {
  50         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  51         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  52         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  53         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  54         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  55         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  56         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  57         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  58         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  59         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  60 };
  61
  62 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  63  * them for both DP and FDI transports, allowing those ports to
  64  * automatically adapt to HDMI connections as well
  65  */
  66 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  67         { 0x00FFFFFF, 0x0006000E, 0x0 },
  68         { 0x00D75FFF, 0x0005000A, 0x0 },
  69         { 0x00C30FFF, 0x00040006, 0x0 },
  70         { 0x80AAAFFF, 0x000B0000, 0x0 },
  71         { 0x00FFFFFF, 0x0005000A, 0x0 },
  72         { 0x00D75FFF, 0x000C0004, 0x0 },
  73         { 0x80C30FFF, 0x000B0000, 0x0 },
  74         { 0x00FFFFFF, 0x00040006, 0x0 },
  75         { 0x80D75FFF, 0x000B0000, 0x0 },
  76 };
  77
  78 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  79         { 0x00FFFFFF, 0x0007000E, 0x0 },
  80         { 0x00D75FFF, 0x000F000A, 0x0 },
  81         { 0x00C30FFF, 0x00060006, 0x0 },
  82         { 0x00AAAFFF, 0x001E0000, 0x0 },
  83         { 0x00FFFFFF, 0x000F000A, 0x0 },
  84         { 0x00D75FFF, 0x00160004, 0x0 },
  85         { 0x00C30FFF, 0x001E0000, 0x0 },
  86         { 0x00FFFFFF, 0x00060006, 0x0 },
  87         { 0x00D75FFF, 0x001E0000, 0x0 },
  88 };
  89
  90 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  91                                         /* Idx  NT mV d T mV d  db      */
  92         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  93         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  94         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  95         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  96         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  97         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  98         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  99         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 100         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 101         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 102         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 103         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 104 };
 105
 106 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 107         { 0x00FFFFFF, 0x00000012, 0x0 },
 108         { 0x00EBAFFF, 0x00020011, 0x0 },
 109         { 0x00C71FFF, 0x0006000F, 0x0 },
 110         { 0x00AAAFFF, 0x000E000A, 0x0 },
 111         { 0x00FFFFFF, 0x00020011, 0x0 },
 112         { 0x00DB6FFF, 0x0005000F, 0x0 },
 113         { 0x00BEEFFF, 0x000A000C, 0x0 },
 114         { 0x00FFFFFF, 0x0005000F, 0x0 },
 115         { 0x00DB6FFF, 0x000A000C, 0x0 },
 116 };
 117
 118 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 119         { 0x00FFFFFF, 0x0007000E, 0x0 },
 120         { 0x00D75FFF, 0x000E000A, 0x0 },
 121         { 0x00BEFFFF, 0x00140006, 0x0 },
 122         { 0x80B2CFFF, 0x001B0002, 0x0 },
 123         { 0x00FFFFFF, 0x000E000A, 0x0 },
 124         { 0x00DB6FFF, 0x00160005, 0x0 },
 125         { 0x80C71FFF, 0x001A0002, 0x0 },
 126         { 0x00F7DFFF, 0x00180004, 0x0 },
 127         { 0x80D75FFF, 0x001B0002, 0x0 },
 128 };
 129
 130 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 131         { 0x00FFFFFF, 0x0001000E, 0x0 },
 132         { 0x00D75FFF, 0x0004000A, 0x0 },
 133         { 0x00C30FFF, 0x00070006, 0x0 },
 134         { 0x00AAAFFF, 0x000C0000, 0x0 },
 135         { 0x00FFFFFF, 0x0004000A, 0x0 },
 136         { 0x00D75FFF, 0x00090004, 0x0 },
 137         { 0x00C30FFF, 0x000C0000, 0x0 },
 138         { 0x00FFFFFF, 0x00070006, 0x0 },
 139         { 0x00D75FFF, 0x000C0000, 0x0 },
 140 };
 141
 142 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 143                                         /* Idx  NT mV d T mV df db      */
 144         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 145         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 146         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 147         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 148         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 149         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 150         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 151         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 152         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 153         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 154 };
 155
 156 /* Skylake H and S */
 157 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 158         { 0x00002016, 0x000000A0, 0x0 },
 159         { 0x00005012, 0x0000009B, 0x0 },
 160         { 0x00007011, 0x00000088, 0x0 },
 161         { 0x80009010, 0x000000C0, 0x1 },
 162         { 0x00002016, 0x0000009B, 0x0 },
 163         { 0x00005012, 0x00000088, 0x0 },
 164         { 0x80007011, 0x000000C0, 0x1 },
 165         { 0x00002016, 0x000000DF, 0x0 },
 166         { 0x80005012, 0x000000C0, 0x1 },
 167 };
 168
 169 /* Skylake U */
 170 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 171         { 0x0000201B, 0x000000A2, 0x0 },
 172         { 0x00005012, 0x00000088, 0x0 },
 173         { 0x80007011, 0x000000CD, 0x1 },
 174         { 0x80009010, 0x000000C0, 0x1 },
 175         { 0x0000201B, 0x0000009D, 0x0 },
 176         { 0x80005012, 0x000000C0, 0x1 },
 177         { 0x80007011, 0x000000C0, 0x1 },
 178         { 0x00002016, 0x00000088, 0x0 },
 179         { 0x80005012, 0x000000C0, 0x1 },
 180 };
 181
 182 /* Skylake Y */
 183 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 184         { 0x00000018, 0x000000A2, 0x0 },
 185         { 0x00005012, 0x00000088, 0x0 },
 186         { 0x80007011, 0x000000CD, 0x3 },
 187         { 0x80009010, 0x000000C0, 0x3 },
 188         { 0x00000018, 0x0000009D, 0x0 },
 189         { 0x80005012, 0x000000C0, 0x3 },
 190         { 0x80007011, 0x000000C0, 0x3 },
 191         { 0x00000018, 0x00000088, 0x0 },
 192         { 0x80005012, 0x000000C0, 0x3 },
 193 };
 194
 195 /* Kabylake H and S */
 196 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 197         { 0x00002016, 0x000000A0, 0x0 },
 198         { 0x00005012, 0x0000009B, 0x0 },
 199         { 0x00007011, 0x00000088, 0x0 },
 200         { 0x80009010, 0x000000C0, 0x1 },
 201         { 0x00002016, 0x0000009B, 0x0 },
 202         { 0x00005012, 0x00000088, 0x0 },
 203         { 0x80007011, 0x000000C0, 0x1 },
 204         { 0x00002016, 0x00000097, 0x0 },
 205         { 0x80005012, 0x000000C0, 0x1 },
 206 };
 207
 208 /* Kabylake U */
 209 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 210         { 0x0000201B, 0x000000A1, 0x0 },
 211         { 0x00005012, 0x00000088, 0x0 },
 212         { 0x80007011, 0x000000CD, 0x3 },
 213         { 0x80009010, 0x000000C0, 0x3 },
 214         { 0x0000201B, 0x0000009D, 0x0 },
 215         { 0x80005012, 0x000000C0, 0x3 },
 216         { 0x80007011, 0x000000C0, 0x3 },
 217         { 0x00002016, 0x0000004F, 0x0 },
 218         { 0x80005012, 0x000000C0, 0x3 },
 219 };
 220
 221 /* Kabylake Y */
 222 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 223         { 0x00001017, 0x000000A1, 0x0 },
 224         { 0x00005012, 0x00000088, 0x0 },
 225         { 0x80007011, 0x000000CD, 0x3 },
 226         { 0x8000800F, 0x000000C0, 0x3 },
 227         { 0x00001017, 0x0000009D, 0x0 },
 228         { 0x80005012, 0x000000C0, 0x3 },
 229         { 0x80007011, 0x000000C0, 0x3 },
 230         { 0x00001017, 0x0000004C, 0x0 },
 231         { 0x80005012, 0x000000C0, 0x3 },
 232 };
 233
 234 /*
 235  * Skylake/Kabylake H and S
 236  * eDP 1.4 low vswing translation parameters
 237  */
 238 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 239         { 0x00000018, 0x000000A8, 0x0 },
 240         { 0x00004013, 0x000000A9, 0x0 },
 241         { 0x00007011, 0x000000A2, 0x0 },
 242         { 0x00009010, 0x0000009C, 0x0 },
 243         { 0x00000018, 0x000000A9, 0x0 },
 244         { 0x00006013, 0x000000A2, 0x0 },
 245         { 0x00007011, 0x000000A6, 0x0 },
 246         { 0x00000018, 0x000000AB, 0x0 },
 247         { 0x00007013, 0x0000009F, 0x0 },
 248         { 0x00000018, 0x000000DF, 0x0 },
 249 };
 250
 251 /*
 252  * Skylake/Kabylake U
 253  * eDP 1.4 low vswing translation parameters
 254  */
 255 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 256         { 0x00000018, 0x000000A8, 0x0 },
 257         { 0x00004013, 0x000000A9, 0x0 },
 258         { 0x00007011, 0x000000A2, 0x0 },
 259         { 0x00009010, 0x0000009C, 0x0 },
 260         { 0x00000018, 0x000000A9, 0x0 },
 261         { 0x00006013, 0x000000A2, 0x0 },
 262         { 0x00007011, 0x000000A6, 0x0 },
 263         { 0x00002016, 0x000000AB, 0x0 },
 264         { 0x00005013, 0x0000009F, 0x0 },
 265         { 0x00000018, 0x000000DF, 0x0 },
 266 };
 267
 268 /*
 269  * Skylake/Kabylake Y
 270  * eDP 1.4 low vswing translation parameters
 271  */
 272 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 273         { 0x00000018, 0x000000A8, 0x0 },
 274         { 0x00004013, 0x000000AB, 0x0 },
 275         { 0x00007011, 0x000000A4, 0x0 },
 276         { 0x00009010, 0x000000DF, 0x0 },
 277         { 0x00000018, 0x000000AA, 0x0 },
 278         { 0x00006013, 0x000000A4, 0x0 },
 279         { 0x00007011, 0x0000009D, 0x0 },
 280         { 0x00000018, 0x000000A0, 0x0 },
 281         { 0x00006012, 0x000000DF, 0x0 },
 282         { 0x00000018, 0x0000008A, 0x0 },
 283 };
 284
 285 /* Skylake/Kabylake U, H and S */
 286 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 287         { 0x00000018, 0x000000AC, 0x0 },
 288         { 0x00005012, 0x0000009D, 0x0 },
 289         { 0x00007011, 0x00000088, 0x0 },
 290         { 0x00000018, 0x000000A1, 0x0 },
 291         { 0x00000018, 0x00000098, 0x0 },
 292         { 0x00004013, 0x00000088, 0x0 },
 293         { 0x80006012, 0x000000CD, 0x1 },
 294         { 0x00000018, 0x000000DF, 0x0 },
 295         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 296         { 0x80003015, 0x000000C0, 0x1 },
 297         { 0x80000018, 0x000000C0, 0x1 },
 298 };
 299
 300 /* Skylake/Kabylake Y */
 301 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 302         { 0x00000018, 0x000000A1, 0x0 },
 303         { 0x00005012, 0x000000DF, 0x0 },
 304         { 0x80007011, 0x000000CB, 0x3 },
 305         { 0x00000018, 0x000000A4, 0x0 },
 306         { 0x00000018, 0x0000009D, 0x0 },
 307         { 0x00004013, 0x00000080, 0x0 },
 308         { 0x80006013, 0x000000C0, 0x3 },
 309         { 0x00000018, 0x0000008A, 0x0 },
 310         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 311         { 0x80003015, 0x000000C0, 0x3 },
 312         { 0x80000018, 0x000000C0, 0x3 },
 313 };
 314
 315 struct bxt_ddi_buf_trans {
 316         u8 margin;      /* swing value */
 317         u8 scale;       /* scale value */
 318         u8 enable;      /* scale enable */
 319         u8 deemphasis;
 320 };
 321
 322 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 323                                         /* Idx  NT mV diff      db  */
 324         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 325         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 326         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 327         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 328         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 329         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 330         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 331         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 332         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 333         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 334 };
 335
 336 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 337                                         /* Idx  NT mV diff      db  */
 338         { 26, 0, 0, 128, },     /* 0:   200             0   */
 339         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 340         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 341         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 342         { 32, 0, 0, 128, },     /* 4:   250             0   */
 343         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 344         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 345         { 43, 0, 0, 128, },     /* 7:   300             0   */
 346         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 347         { 48, 0, 0, 128, },     /* 9:   300             0   */
 348 };
 349
 350 /* BSpec has 2 recommended values - entries 0 and 8.
 351  * Using the entry with higher vswing.
 352  */
 353 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 354                                         /* Idx  NT mV diff      db  */
 355         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 356         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 357         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 358         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 359         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 360         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 361         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 362         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 363         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 364         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 365 };
 366
 367 struct cnl_ddi_buf_trans {
 368         u8 dw2_swing_sel;
 369         u8 dw7_n_scalar;
 370         u8 dw4_cursor_coeff;
 371         u8 dw4_post_cursor_2;
 372         u8 dw4_post_cursor_1;
 373 };
 374
 375 /* Voltage Swing Programming for VccIO 0.85V for DP */
 376 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 377                                                 /* NT mV Trans mV db    */
 378         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 379         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 380         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 381         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 382         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 383         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 384         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 385         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 386         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 387         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 388 };
 389
 390 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 391 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 392                                                 /* NT mV Trans mV db    */
 393         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 394         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 395         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 396         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 397         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 398         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 399         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 400 };
 401
 402 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 403 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 404                                                 /* NT mV Trans mV db    */
 405         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 406         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 407         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 408         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 409         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 410         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 411         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 412         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 413         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 414 };
 415
 416 /* Voltage Swing Programming for VccIO 0.95V for DP */
 417 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 418                                                 /* NT mV Trans mV db    */
 419         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 420         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 421         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 422         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 423         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 424         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 425         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 426         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 427         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 428         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 429 };
 430
 431 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 432 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 433                                                 /* NT mV Trans mV db    */
 434         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 435         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 436         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 437         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 438         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 439         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 440         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 441         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 442         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 443         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 444         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 445 };
 446
 447 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 448 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 449                                                 /* NT mV Trans mV db    */
 450         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 451         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 452         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 453         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 454         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 455         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 456         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 457         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 458         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 459         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 460 };
 461
 462 /* Voltage Swing Programming for VccIO 1.05V for DP */
 463 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 464                                                 /* NT mV Trans mV db    */
 465         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 466         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 467         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 468         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 469         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 470         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 471         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 472         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 473         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 474         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 475 };
 476
 477 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 478 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 479                                                 /* NT mV Trans mV db    */
 480         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 481         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 482         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 483         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 484         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 485         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 486         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 487         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 488         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 489         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 490         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 491 };
 492
 493 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 494 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 495                                                 /* NT mV Trans mV db    */
 496         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 497         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 498         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 499         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 500         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 501         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 502         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 503         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 504         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 505 };
 506
 507 /* icl_combo_phy_ddi_translations */
 508 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 509                                                 /* NT mV Trans mV db    */
 510         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 511         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 512         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 513         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 514         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 515         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 516         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 517         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 518         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 519         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 520 };
 521
 522 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 523                                                 /* NT mV Trans mV db    */
 524         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 525         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 526         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 527         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 528         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 529         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 530         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 531         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 532         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 533         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 534 };
 535
 536 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 537                                                 /* NT mV Trans mV db    */
 538         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 539         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 540         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 541         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 542         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 543         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 544         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 545         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 546         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 547         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 548 };
 549
 550 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 551                                                 /* NT mV Trans mV db    */
 552         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 553         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 554         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 555         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 556         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 557         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 558         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 559 };
 560
 561 struct icl_mg_phy_ddi_buf_trans {
 562         u32 cri_txdeemph_override_5_0;
 563         u32 cri_txdeemph_override_11_6;
 564         u32 cri_txdeemph_override_17_12;
 565 };
 566
 567 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 568                                 /* Voltage swing  pre-emphasis */
 569         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 570         { 0x0, 0x23, 0x08 },    /* 0              1   */
 571         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 572         { 0x0, 0x00, 0x00 },    /* 0              3   */
 573         { 0x0, 0x23, 0x00 },    /* 1              0   */
 574         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 575         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 576         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 577         { 0x0, 0x33, 0x0C },    /* 2              1   */
 578         { 0x0, 0x00, 0x00 },    /* 3              0   */
 579 };
 580
 581 static const struct ddi_buf_trans *
 582 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 583 {
 584         if (dev_priv->vbt.edp.low_vswing) {
 585                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 586                 return bdw_ddi_translations_edp;
 587         } else {
 588                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 589                 return bdw_ddi_translations_dp;
 590         }
 591 }
 592
 593 static const struct ddi_buf_trans *
 594 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 595 {
 596         if (IS_SKL_ULX(dev_priv)) {
 597                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 598                 return skl_y_ddi_translations_dp;
 599         } else if (IS_SKL_ULT(dev_priv)) {
 600                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 601                 return skl_u_ddi_translations_dp;
 602         } else {
 603                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 604                 return skl_ddi_translations_dp;
 605         }
 606 }
 607
 608 static const struct ddi_buf_trans *
 609 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 610 {
 611         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 612                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 613                 return kbl_y_ddi_translations_dp;
 614         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 615                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 616                 return kbl_u_ddi_translations_dp;
 617         } else {
 618                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 619                 return kbl_ddi_translations_dp;
 620         }
 621 }
 622
 623 static const struct ddi_buf_trans *
 624 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 625 {
 626         if (dev_priv->vbt.edp.low_vswing) {
 627                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 628                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 629                         return skl_y_ddi_translations_edp;
 630                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 631                            IS_CFL_ULT(dev_priv)) {
 632                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 633                         return skl_u_ddi_translations_edp;
 634                 } else {
 635                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 636                         return skl_ddi_translations_edp;
 637                 }
 638         }
 639
 640         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 641                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 642         else
 643                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 644 }
 645
 646 static const struct ddi_buf_trans *
 647 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 648 {
 649         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 650                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 651                 return skl_y_ddi_translations_hdmi;
 652         } else {
 653                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 654                 return skl_ddi_translations_hdmi;
 655         }
 656 }
 657
 658 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 659 {
 660         /* Only DDIA and DDIE can select the 10th register with DP */
 661         if (port == PORT_A || port == PORT_E)
 662                 return min(n_entries, 10);
 663         else
 664                 return min(n_entries, 9);
 665 }
 666
 667 static const struct ddi_buf_trans *
 668 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 669                            enum port port, int *n_entries)
 670 {
 671         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 672                 const struct ddi_buf_trans *ddi_translations =
 673                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 674                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 675                 return ddi_translations;
 676         } else if (IS_SKYLAKE(dev_priv)) {
 677                 const struct ddi_buf_trans *ddi_translations =
 678                         skl_get_buf_trans_dp(dev_priv, n_entries);
 679                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 680                 return ddi_translations;
 681         } else if (IS_BROADWELL(dev_priv)) {
 682                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 683                 return  bdw_ddi_translations_dp;
 684         } else if (IS_HASWELL(dev_priv)) {
 685                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 686                 return hsw_ddi_translations_dp;
 687         }
 688
 689         *n_entries = 0;
 690         return NULL;
 691 }
 692
 693 static const struct ddi_buf_trans *
 694 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 695                             enum port port, int *n_entries)
 696 {
 697         if (IS_GEN9_BC(dev_priv)) {
 698                 const struct ddi_buf_trans *ddi_translations =
 699                         skl_get_buf_trans_edp(dev_priv, n_entries);
 700                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 701                 return ddi_translations;
 702         } else if (IS_BROADWELL(dev_priv)) {
 703                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 704         } else if (IS_HASWELL(dev_priv)) {
 705                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 706                 return hsw_ddi_translations_dp;
 707         }
 708
 709         *n_entries = 0;
 710         return NULL;
 711 }
 712
 713 static const struct ddi_buf_trans *
 714 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 715                             int *n_entries)
 716 {
 717         if (IS_BROADWELL(dev_priv)) {
 718                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 719                 return bdw_ddi_translations_fdi;
 720         } else if (IS_HASWELL(dev_priv)) {
 721                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 722                 return hsw_ddi_translations_fdi;
 723         }
 724
 725         *n_entries = 0;
 726         return NULL;
 727 }
 728
 729 static const struct ddi_buf_trans *
 730 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 731                              int *n_entries)
 732 {
 733         if (IS_GEN9_BC(dev_priv)) {
 734                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 735         } else if (IS_BROADWELL(dev_priv)) {
 736                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 737                 return bdw_ddi_translations_hdmi;
 738         } else if (IS_HASWELL(dev_priv)) {
 739                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 740                 return hsw_ddi_translations_hdmi;
 741         }
 742
 743         *n_entries = 0;
 744         return NULL;
 745 }
 746
 747 static const struct bxt_ddi_buf_trans *
 748 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 749 {
 750         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 751         return bxt_ddi_translations_dp;
 752 }
 753
 754 static const struct bxt_ddi_buf_trans *
 755 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 756 {
 757         if (dev_priv->vbt.edp.low_vswing) {
 758                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 759                 return bxt_ddi_translations_edp;
 760         }
 761
 762         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 763 }
 764
 765 static const struct bxt_ddi_buf_trans *
 766 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 767 {
 768         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 769         return bxt_ddi_translations_hdmi;
 770 }
 771
 772 static const struct cnl_ddi_buf_trans *
 773 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 774 {
 775         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 776
 777         if (voltage == VOLTAGE_INFO_0_85V) {
 778                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 779                 return cnl_ddi_translations_hdmi_0_85V;
 780         } else if (voltage == VOLTAGE_INFO_0_95V) {
 781                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 782                 return cnl_ddi_translations_hdmi_0_95V;
 783         } else if (voltage == VOLTAGE_INFO_1_05V) {
 784                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 785                 return cnl_ddi_translations_hdmi_1_05V;
 786         } else {
 787                 *n_entries = 1; /* shut up gcc */
 788                 MISSING_CASE(voltage);
 789         }
 790         return NULL;
 791 }
 792
 793 static const struct cnl_ddi_buf_trans *
 794 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 795 {
 796         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 797
 798         if (voltage == VOLTAGE_INFO_0_85V) {
 799                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 800                 return cnl_ddi_translations_dp_0_85V;
 801         } else if (voltage == VOLTAGE_INFO_0_95V) {
 802                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 803                 return cnl_ddi_translations_dp_0_95V;
 804         } else if (voltage == VOLTAGE_INFO_1_05V) {
 805                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 806                 return cnl_ddi_translations_dp_1_05V;
 807         } else {
 808                 *n_entries = 1; /* shut up gcc */
 809                 MISSING_CASE(voltage);
 810         }
 811         return NULL;
 812 }
 813
 814 static const struct cnl_ddi_buf_trans *
 815 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 816 {
 817         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 818
 819         if (dev_priv->vbt.edp.low_vswing) {
 820                 if (voltage == VOLTAGE_INFO_0_85V) {
 821                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 822                         return cnl_ddi_translations_edp_0_85V;
 823                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 824                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 825                         return cnl_ddi_translations_edp_0_95V;
 826                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 827                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 828                         return cnl_ddi_translations_edp_1_05V;
 829                 } else {
 830                         *n_entries = 1; /* shut up gcc */
 831                         MISSING_CASE(voltage);
 832                 }
 833                 return NULL;
 834         } else {
 835                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 836         }
 837 }
 838
 839 static const struct cnl_ddi_buf_trans *
 840 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 841                         int type, int rate, int *n_entries)
 842 {
 843         if (type == INTEL_OUTPUT_HDMI) {
 844                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 845                 return icl_combo_phy_ddi_translations_hdmi;
 846         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 847                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 848                 return icl_combo_phy_ddi_translations_edp_hbr3;
 849         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 850                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 851                 return icl_combo_phy_ddi_translations_edp_hbr2;
 852         }
 853
 854         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 855         return icl_combo_phy_ddi_translations_dp_hbr2;
 856 }
 857
 858 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 859 {
 860         int n_entries, level, default_entry;
 861
 862         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 863
 864         if (INTEL_GEN(dev_priv) >= 11) {
 865                 if (intel_port_is_combophy(dev_priv, port))
 866                         icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 867                                                 0, &n_entries);
 868                 else
 869                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 870                 default_entry = n_entries - 1;
 871         } else if (IS_CANNONLAKE(dev_priv)) {
 872                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 873                 default_entry = n_entries - 1;
 874         } else if (IS_GEN9_LP(dev_priv)) {
 875                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 876                 default_entry = n_entries - 1;
 877         } else if (IS_GEN9_BC(dev_priv)) {
 878                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 879                 default_entry = 8;
 880         } else if (IS_BROADWELL(dev_priv)) {
 881                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 882                 default_entry = 7;
 883         } else if (IS_HASWELL(dev_priv)) {
 884                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 885                 default_entry = 6;
 886         } else {
 887                 WARN(1, "ddi translation table missing\n");
 888                 return 0;
 889         }
 890
 891         /* Choose a good default if VBT is badly populated */
 892         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 893                 level = default_entry;
 894
 895         if (WARN_ON_ONCE(n_entries == 0))
 896                 return 0;
 897         if (WARN_ON_ONCE(level >= n_entries))
 898                 level = n_entries - 1;
 899
 900         return level;
 901 }
 902
 903 /*
 904  * Starting with Haswell, DDI port buffers must be programmed with correct
 905  * values in advance. This function programs the correct values for
 906  * DP/eDP/FDI use cases.
 907  */
 908 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 909                                          const struct intel_crtc_state *crtc_state)
 910 {
 911         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 912         u32 iboost_bit = 0;
 913         int i, n_entries;
 914         enum port port = encoder->port;
 915         const struct ddi_buf_trans *ddi_translations;
 916
 917         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 918                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 919                                                                &n_entries);
 920         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 921                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 922                                                                &n_entries);
 923         else
 924                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 925                                                               &n_entries);
 926
 927         /* If we're boosting the current, set bit 31 of trans1 */
 928         if (IS_GEN9_BC(dev_priv) &&
 929             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 930                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 931
 932         for (i = 0; i < n_entries; i++) {
 933                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 934                            ddi_translations[i].trans1 | iboost_bit);
 935                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 936                            ddi_translations[i].trans2);
 937         }
 938 }
 939
 940 /*
 941  * Starting with Haswell, DDI port buffers must be programmed with correct
 942  * values in advance. This function programs the correct values for
 943  * HDMI/DVI use cases.
 944  */
 945 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 946                                            int level)
 947 {
 948         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 949         u32 iboost_bit = 0;
 950         int n_entries;
 951         enum port port = encoder->port;
 952         const struct ddi_buf_trans *ddi_translations;
 953
 954         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 955
 956         if (WARN_ON_ONCE(!ddi_translations))
 957                 return;
 958         if (WARN_ON_ONCE(level >= n_entries))
 959                 level = n_entries - 1;
 960
 961         /* If we're boosting the current, set bit 31 of trans1 */
 962         if (IS_GEN9_BC(dev_priv) &&
 963             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 964                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 965
 966         /* Entry 9 is for HDMI: */
 967         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 968                    ddi_translations[level].trans1 | iboost_bit);
 969         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 970                    ddi_translations[level].trans2);
 971 }
 972
 973 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 974                                     enum port port)
 975 {
 976         i915_reg_t reg = DDI_BUF_CTL(port);
 977         int i;
 978
 979         for (i = 0; i < 16; i++) {
 980                 udelay(1);
 981                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 982                         return;
 983         }
 984         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 985 }
 986
 987 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 988 {
 989         switch (pll->info->id) {
 990         case DPLL_ID_WRPLL1:
 991                 return PORT_CLK_SEL_WRPLL1;
 992         case DPLL_ID_WRPLL2:
 993                 return PORT_CLK_SEL_WRPLL2;
 994         case DPLL_ID_SPLL:
 995                 return PORT_CLK_SEL_SPLL;
 996         case DPLL_ID_LCPLL_810:
 997                 return PORT_CLK_SEL_LCPLL_810;
 998         case DPLL_ID_LCPLL_1350:
 999                 return PORT_CLK_SEL_LCPLL_1350;
1000         case DPLL_ID_LCPLL_2700:
1001                 return PORT_CLK_SEL_LCPLL_2700;
1002         default:
1003                 MISSING_CASE(pll->info->id);
1004                 return PORT_CLK_SEL_NONE;
1005         }
1006 }
1007
1008 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1009                                   const struct intel_crtc_state *crtc_state)
1010 {
1011         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1012         int clock = crtc_state->port_clock;
1013         const enum intel_dpll_id id = pll->info->id;
1014
1015         switch (id) {
1016         default:
1017                 /*
1018                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1019                  * here, so do warn if this get passed in
1020                  */
1021                 MISSING_CASE(id);
1022                 return DDI_CLK_SEL_NONE;
1023         case DPLL_ID_ICL_TBTPLL:
1024                 switch (clock) {
1025                 case 162000:
1026                         return DDI_CLK_SEL_TBT_162;
1027                 case 270000:
1028                         return DDI_CLK_SEL_TBT_270;
1029                 case 540000:
1030                         return DDI_CLK_SEL_TBT_540;
1031                 case 810000:
1032                         return DDI_CLK_SEL_TBT_810;
1033                 default:
1034                         MISSING_CASE(clock);
1035                         return DDI_CLK_SEL_NONE;
1036                 }
1037         case DPLL_ID_ICL_MGPLL1:
1038         case DPLL_ID_ICL_MGPLL2:
1039         case DPLL_ID_ICL_MGPLL3:
1040         case DPLL_ID_ICL_MGPLL4:
1041                 return DDI_CLK_SEL_MG;
1042         }
1043 }
1044
1045 /* Starting with Haswell, different DDI ports can work in FDI mode for
1046  * connection to the PCH-located connectors. For this, it is necessary to train
1047  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1048  *
1049  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1050  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1051  * DDI A (which is used for eDP)
1052  */
1053
1054 void hsw_fdi_link_train(struct intel_crtc *crtc,
1055                         const struct intel_crtc_state *crtc_state)
1056 {
1057         struct drm_device *dev = crtc->base.dev;
1058         struct drm_i915_private *dev_priv = to_i915(dev);
1059         struct intel_encoder *encoder;
1060         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1061
1062         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1063                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1064                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1065         }
1066
1067         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1068          * mode set "sequence for CRT port" document:
1069          * - TP1 to TP2 time with the default value
1070          * - FDI delay to 90h
1071          *
1072          * WaFDIAutoLinkSetTimingOverrride:hsw
1073          */
1074         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1075                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1076                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1077
1078         /* Enable the PCH Receiver FDI PLL */
1079         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1080                      FDI_RX_PLL_ENABLE |
1081                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1082         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1083         POSTING_READ(FDI_RX_CTL(PIPE_A));
1084         udelay(220);
1085
1086         /* Switch from Rawclk to PCDclk */
1087         rx_ctl_val |= FDI_PCDCLK;
1088         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1089
1090         /* Configure Port Clock Select */
1091         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1092         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1093         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1094
1095         /* Start the training iterating through available voltages and emphasis,
1096          * testing each value twice. */
1097         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1098                 /* Configure DP_TP_CTL with auto-training */
1099                 I915_WRITE(DP_TP_CTL(PORT_E),
1100                                         DP_TP_CTL_FDI_AUTOTRAIN |
1101                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1102                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1103                                         DP_TP_CTL_ENABLE);
1104
1105                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1106                  * DDI E does not support port reversal, the functionality is
1107                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1108                  * port reversal bit */
1109                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1110                            DDI_BUF_CTL_ENABLE |
1111                            ((crtc_state->fdi_lanes - 1) << 1) |
1112                            DDI_BUF_TRANS_SELECT(i / 2));
1113                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1114
1115                 udelay(600);
1116
1117                 /* Program PCH FDI Receiver TU */
1118                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1119
1120                 /* Enable PCH FDI Receiver with auto-training */
1121                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1122                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1123                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1124
1125                 /* Wait for FDI receiver lane calibration */
1126                 udelay(30);
1127
1128                 /* Unset FDI_RX_MISC pwrdn lanes */
1129                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1130                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1131                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1132                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1133
1134                 /* Wait for FDI auto training time */
1135                 udelay(5);
1136
1137                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1138                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1139                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1140                         break;
1141                 }
1142
1143                 /*
1144                  * Leave things enabled even if we failed to train FDI.
1145                  * Results in less fireworks from the state checker.
1146                  */
1147                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1148                         DRM_ERROR("FDI link training failed!\n");
1149                         break;
1150                 }
1151
1152                 rx_ctl_val &= ~FDI_RX_ENABLE;
1153                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1154                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1155
1156                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1157                 temp &= ~DDI_BUF_CTL_ENABLE;
1158                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1159                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1160
1161                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1162                 temp = I915_READ(DP_TP_CTL(PORT_E));
1163                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1164                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1165                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1166                 POSTING_READ(DP_TP_CTL(PORT_E));
1167
1168                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1169
1170                 /* Reset FDI_RX_MISC pwrdn lanes */
1171                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1172                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1173                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1174                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1175                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1176         }
1177
1178         /* Enable normal pixel sending for FDI */
1179         I915_WRITE(DP_TP_CTL(PORT_E),
1180                    DP_TP_CTL_FDI_AUTOTRAIN |
1181                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1182                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1183                    DP_TP_CTL_ENABLE);
1184 }
1185
1186 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1187 {
1188         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1189         struct intel_digital_port *intel_dig_port =
1190                 enc_to_dig_port(&encoder->base);
1191
1192         intel_dp->DP = intel_dig_port->saved_port_bits |
1193                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1194         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1195 }
1196
1197 static struct intel_encoder *
1198 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1199 {
1200         struct drm_device *dev = crtc->base.dev;
1201         struct intel_encoder *encoder, *ret = NULL;
1202         int num_encoders = 0;
1203
1204         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1205                 ret = encoder;
1206                 num_encoders++;
1207         }
1208
1209         if (num_encoders != 1)
1210                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1211                      pipe_name(crtc->pipe));
1212
1213         BUG_ON(ret == NULL);
1214         return ret;
1215 }
1216
1217 #define LC_FREQ 2700
1218
1219 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1220                                    i915_reg_t reg)
1221 {
1222         int refclk = LC_FREQ;
1223         int n, p, r;
1224         u32 wrpll;
1225
1226         wrpll = I915_READ(reg);
1227         switch (wrpll & WRPLL_PLL_REF_MASK) {
1228         case WRPLL_PLL_SSC:
1229         case WRPLL_PLL_NON_SSC:
1230                 /*
1231                  * We could calculate spread here, but our checking
1232                  * code only cares about 5% accuracy, and spread is a max of
1233                  * 0.5% downspread.
1234                  */
1235                 refclk = 135;
1236                 break;
1237         case WRPLL_PLL_LCPLL:
1238                 refclk = LC_FREQ;
1239                 break;
1240         default:
1241                 WARN(1, "bad wrpll refclk\n");
1242                 return 0;
1243         }
1244
1245         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1246         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1247         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1248
1249         /* Convert to KHz, p & r have a fixed point portion */
1250         return (refclk * n * 100) / (p * r);
1251 }
1252
1253 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1254 {
1255         u32 p0, p1, p2, dco_freq;
1256
1257         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1258         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1259
1260         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1261                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1262         else
1263                 p1 = 1;
1264
1265
1266         switch (p0) {
1267         case DPLL_CFGCR2_PDIV_1:
1268                 p0 = 1;
1269                 break;
1270         case DPLL_CFGCR2_PDIV_2:
1271                 p0 = 2;
1272                 break;
1273         case DPLL_CFGCR2_PDIV_3:
1274                 p0 = 3;
1275                 break;
1276         case DPLL_CFGCR2_PDIV_7:
1277                 p0 = 7;
1278                 break;
1279         }
1280
1281         switch (p2) {
1282         case DPLL_CFGCR2_KDIV_5:
1283                 p2 = 5;
1284                 break;
1285         case DPLL_CFGCR2_KDIV_2:
1286                 p2 = 2;
1287                 break;
1288         case DPLL_CFGCR2_KDIV_3:
1289                 p2 = 3;
1290                 break;
1291         case DPLL_CFGCR2_KDIV_1:
1292                 p2 = 1;
1293                 break;
1294         }
1295
1296         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1297                 * 24 * 1000;
1298
1299         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1300                      * 24 * 1000) / 0x8000;
1301
1302         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1303                 return 0;
1304
1305         return dco_freq / (p0 * p1 * p2 * 5);
1306 }
1307
1308 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1309                         struct intel_dpll_hw_state *pll_state)
1310 {
1311         u32 p0, p1, p2, dco_freq, ref_clock;
1312
1313         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1314         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1315
1316         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1317                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1318                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1319         else
1320                 p1 = 1;
1321
1322
1323         switch (p0) {
1324         case DPLL_CFGCR1_PDIV_2:
1325                 p0 = 2;
1326                 break;
1327         case DPLL_CFGCR1_PDIV_3:
1328                 p0 = 3;
1329                 break;
1330         case DPLL_CFGCR1_PDIV_5:
1331                 p0 = 5;
1332                 break;
1333         case DPLL_CFGCR1_PDIV_7:
1334                 p0 = 7;
1335                 break;
1336         }
1337
1338         switch (p2) {
1339         case DPLL_CFGCR1_KDIV_1:
1340                 p2 = 1;
1341                 break;
1342         case DPLL_CFGCR1_KDIV_2:
1343                 p2 = 2;
1344                 break;
1345         case DPLL_CFGCR1_KDIV_3:
1346                 p2 = 3;
1347                 break;
1348         }
1349
1350         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1351
1352         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1353                 * ref_clock;
1354
1355         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1356                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1357
1358         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1359                 return 0;
1360
1361         return dco_freq / (p0 * p1 * p2 * 5);
1362 }
1363
1364 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1365                                  enum port port)
1366 {
1367         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1368
1369         switch (val) {
1370         case DDI_CLK_SEL_NONE:
1371                 return 0;
1372         case DDI_CLK_SEL_TBT_162:
1373                 return 162000;
1374         case DDI_CLK_SEL_TBT_270:
1375                 return 270000;
1376         case DDI_CLK_SEL_TBT_540:
1377                 return 540000;
1378         case DDI_CLK_SEL_TBT_810:
1379                 return 810000;
1380         default:
1381                 MISSING_CASE(val);
1382                 return 0;
1383         }
1384 }
1385
1386 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1387                                 const struct intel_dpll_hw_state *pll_state)
1388 {
1389         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1390         u64 tmp;
1391
1392         ref_clock = dev_priv->cdclk.hw.ref;
1393
1394         m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1395         m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1396         m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1397                 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1398                 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1399
1400         switch (pll_state->mg_clktop2_hsclkctl &
1401                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1402         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1403                 div1 = 2;
1404                 break;
1405         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1406                 div1 = 3;
1407                 break;
1408         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1409                 div1 = 5;
1410                 break;
1411         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1412                 div1 = 7;
1413                 break;
1414         default:
1415                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1416                 return 0;
1417         }
1418
1419         div2 = (pll_state->mg_clktop2_hsclkctl &
1420                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1421                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1422
1423         /* div2 value of 0 is same as 1 means no div */
1424         if (div2 == 0)
1425                 div2 = 1;
1426
1427         /*
1428          * Adjust the original formula to delay the division by 2^22 in order to
1429          * minimize possible rounding errors.
1430          */
1431         tmp = (u64)m1 * m2_int * ref_clock +
1432               (((u64)m1 * m2_frac * ref_clock) >> 22);
1433         tmp = div_u64(tmp, 5 * div1 * div2);
1434
1435         return tmp;
1436 }
1437
1438 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1439 {
1440         int dotclock;
1441
1442         if (pipe_config->has_pch_encoder)
1443                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1444                                                     &pipe_config->fdi_m_n);
1445         else if (intel_crtc_has_dp_encoder(pipe_config))
1446                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1447                                                     &pipe_config->dp_m_n);
1448         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1449                 dotclock = pipe_config->port_clock * 2 / 3;
1450         else
1451                 dotclock = pipe_config->port_clock;
1452
1453         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1454                 dotclock *= 2;
1455
1456         if (pipe_config->pixel_multiplier)
1457                 dotclock /= pipe_config->pixel_multiplier;
1458
1459         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1460 }
1461
1462 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1463                               struct intel_crtc_state *pipe_config)
1464 {
1465         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1466         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1467         enum port port = encoder->port;
1468         int link_clock;
1469
1470         if (intel_port_is_combophy(dev_priv, port)) {
1471                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1472         } else {
1473                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1474                                                 pipe_config->shared_dpll);
1475
1476                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1477                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1478                 else
1479                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1480         }
1481
1482         pipe_config->port_clock = link_clock;
1483
1484         ddi_dotclock_get(pipe_config);
1485 }
1486
1487 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1488                               struct intel_crtc_state *pipe_config)
1489 {
1490         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1491         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1492         int link_clock;
1493
1494         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1495                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1496         } else {
1497                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1498
1499                 switch (link_clock) {
1500                 case DPLL_CFGCR0_LINK_RATE_810:
1501                         link_clock = 81000;
1502                         break;
1503                 case DPLL_CFGCR0_LINK_RATE_1080:
1504                         link_clock = 108000;
1505                         break;
1506                 case DPLL_CFGCR0_LINK_RATE_1350:
1507                         link_clock = 135000;
1508                         break;
1509                 case DPLL_CFGCR0_LINK_RATE_1620:
1510                         link_clock = 162000;
1511                         break;
1512                 case DPLL_CFGCR0_LINK_RATE_2160:
1513                         link_clock = 216000;
1514                         break;
1515                 case DPLL_CFGCR0_LINK_RATE_2700:
1516                         link_clock = 270000;
1517                         break;
1518                 case DPLL_CFGCR0_LINK_RATE_3240:
1519                         link_clock = 324000;
1520                         break;
1521                 case DPLL_CFGCR0_LINK_RATE_4050:
1522                         link_clock = 405000;
1523                         break;
1524                 default:
1525                         WARN(1, "Unsupported link rate\n");
1526                         break;
1527                 }
1528                 link_clock *= 2;
1529         }
1530
1531         pipe_config->port_clock = link_clock;
1532
1533         ddi_dotclock_get(pipe_config);
1534 }
1535
1536 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1537                               struct intel_crtc_state *pipe_config)
1538 {
1539         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1540         int link_clock;
1541
1542         /*
1543          * ctrl1 register is already shifted for each pll, just use 0 to get
1544          * the internal shift for each field
1545          */
1546         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1547                 link_clock = skl_calc_wrpll_link(pll_state);
1548         } else {
1549                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1550                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1551
1552                 switch (link_clock) {
1553                 case DPLL_CTRL1_LINK_RATE_810:
1554                         link_clock = 81000;
1555                         break;
1556                 case DPLL_CTRL1_LINK_RATE_1080:
1557                         link_clock = 108000;
1558                         break;
1559                 case DPLL_CTRL1_LINK_RATE_1350:
1560                         link_clock = 135000;
1561                         break;
1562                 case DPLL_CTRL1_LINK_RATE_1620:
1563                         link_clock = 162000;
1564                         break;
1565                 case DPLL_CTRL1_LINK_RATE_2160:
1566                         link_clock = 216000;
1567                         break;
1568                 case DPLL_CTRL1_LINK_RATE_2700:
1569                         link_clock = 270000;
1570                         break;
1571                 default:
1572                         WARN(1, "Unsupported link rate\n");
1573                         break;
1574                 }
1575                 link_clock *= 2;
1576         }
1577
1578         pipe_config->port_clock = link_clock;
1579
1580         ddi_dotclock_get(pipe_config);
1581 }
1582
1583 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1584                               struct intel_crtc_state *pipe_config)
1585 {
1586         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1587         int link_clock = 0;
1588         u32 val, pll;
1589
1590         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1591         switch (val & PORT_CLK_SEL_MASK) {
1592         case PORT_CLK_SEL_LCPLL_810:
1593                 link_clock = 81000;
1594                 break;
1595         case PORT_CLK_SEL_LCPLL_1350:
1596                 link_clock = 135000;
1597                 break;
1598         case PORT_CLK_SEL_LCPLL_2700:
1599                 link_clock = 270000;
1600                 break;
1601         case PORT_CLK_SEL_WRPLL1:
1602                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1603                 break;
1604         case PORT_CLK_SEL_WRPLL2:
1605                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1606                 break;
1607         case PORT_CLK_SEL_SPLL:
1608                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1609                 if (pll == SPLL_PLL_FREQ_810MHz)
1610                         link_clock = 81000;
1611                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1612                         link_clock = 135000;
1613                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1614                         link_clock = 270000;
1615                 else {
1616                         WARN(1, "bad spll freq\n");
1617                         return;
1618                 }
1619                 break;
1620         default:
1621                 WARN(1, "bad port clock sel\n");
1622                 return;
1623         }
1624
1625         pipe_config->port_clock = link_clock * 2;
1626
1627         ddi_dotclock_get(pipe_config);
1628 }
1629
1630 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1631 {
1632         struct dpll clock;
1633
1634         clock.m1 = 2;
1635         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1636         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1637                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1638         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1639         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1640         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1641
1642         return chv_calc_dpll_params(100000, &clock);
1643 }
1644
1645 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1646                               struct intel_crtc_state *pipe_config)
1647 {
1648         pipe_config->port_clock =
1649                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1650
1651         ddi_dotclock_get(pipe_config);
1652 }
1653
1654 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1655                                 struct intel_crtc_state *pipe_config)
1656 {
1657         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1658
1659         if (INTEL_GEN(dev_priv) >= 11)
1660                 icl_ddi_clock_get(encoder, pipe_config);
1661         else if (IS_CANNONLAKE(dev_priv))
1662                 cnl_ddi_clock_get(encoder, pipe_config);
1663         else if (IS_GEN9_LP(dev_priv))
1664                 bxt_ddi_clock_get(encoder, pipe_config);
1665         else if (IS_GEN9_BC(dev_priv))
1666                 skl_ddi_clock_get(encoder, pipe_config);
1667         else if (INTEL_GEN(dev_priv) <= 8)
1668                 hsw_ddi_clock_get(encoder, pipe_config);
1669 }
1670
1671 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1672 {
1673         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1674         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1675         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1676         u32 temp;
1677
1678         if (!intel_crtc_has_dp_encoder(crtc_state))
1679                 return;
1680
1681         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1682
1683         temp = TRANS_MSA_SYNC_CLK;
1684
1685         if (crtc_state->limited_color_range)
1686                 temp |= TRANS_MSA_CEA_RANGE;
1687
1688         switch (crtc_state->pipe_bpp) {
1689         case 18:
1690                 temp |= TRANS_MSA_6_BPC;
1691                 break;
1692         case 24:
1693                 temp |= TRANS_MSA_8_BPC;
1694                 break;
1695         case 30:
1696                 temp |= TRANS_MSA_10_BPC;
1697                 break;
1698         case 36:
1699                 temp |= TRANS_MSA_12_BPC;
1700                 break;
1701         default:
1702                 MISSING_CASE(crtc_state->pipe_bpp);
1703                 break;
1704         }
1705
1706         /*
1707          * As per DP 1.2 spec section 2.3.4.3 while sending
1708          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1709          * colorspace information. The output colorspace encoding is BT601.
1710          */
1711         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1712                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1713         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1714 }
1715
1716 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1717                                     bool state)
1718 {
1719         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1720         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1721         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1722         u32 temp;
1723
1724         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1725         if (state == true)
1726                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1727         else
1728                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1729         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1730 }
1731
1732 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1733 {
1734         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1735         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1736         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1737         enum pipe pipe = crtc->pipe;
1738         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1739         enum port port = encoder->port;
1740         u32 temp;
1741
1742         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1743         temp = TRANS_DDI_FUNC_ENABLE;
1744         temp |= TRANS_DDI_SELECT_PORT(port);
1745
1746         switch (crtc_state->pipe_bpp) {
1747         case 18:
1748                 temp |= TRANS_DDI_BPC_6;
1749                 break;
1750         case 24:
1751                 temp |= TRANS_DDI_BPC_8;
1752                 break;
1753         case 30:
1754                 temp |= TRANS_DDI_BPC_10;
1755                 break;
1756         case 36:
1757                 temp |= TRANS_DDI_BPC_12;
1758                 break;
1759         default:
1760                 BUG();
1761         }
1762
1763         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1764                 temp |= TRANS_DDI_PVSYNC;
1765         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1766                 temp |= TRANS_DDI_PHSYNC;
1767
1768         if (cpu_transcoder == TRANSCODER_EDP) {
1769                 switch (pipe) {
1770                 case PIPE_A:
1771                         /* On Haswell, can only use the always-on power well for
1772                          * eDP when not using the panel fitter, and when not
1773                          * using motion blur mitigation (which we don't
1774                          * support). */
1775                         if (IS_HASWELL(dev_priv) &&
1776                             (crtc_state->pch_pfit.enabled ||
1777                              crtc_state->pch_pfit.force_thru))
1778                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1779                         else
1780                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1781                         break;
1782                 case PIPE_B:
1783                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1784                         break;
1785                 case PIPE_C:
1786                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1787                         break;
1788                 default:
1789                         BUG();
1790                         break;
1791                 }
1792         }
1793
1794         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1795                 if (crtc_state->has_hdmi_sink)
1796                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1797                 else
1798                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1799
1800                 if (crtc_state->hdmi_scrambling)
1801                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1802                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1803                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1804         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1805                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1806                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1807         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1808                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1809                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1810         } else {
1811                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1812                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1813         }
1814
1815         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1816 }
1817
1818 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1819 {
1820         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1821         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1822         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1823         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1824         u32 val = I915_READ(reg);
1825
1826         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1827         val |= TRANS_DDI_PORT_NONE;
1828         I915_WRITE(reg, val);
1829
1830         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1831             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1832                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1833                 /* Quirk time at 100ms for reliable operation */
1834                 msleep(100);
1835         }
1836 }
1837
1838 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1839                                      bool enable)
1840 {
1841         struct drm_device *dev = intel_encoder->base.dev;
1842         struct drm_i915_private *dev_priv = to_i915(dev);
1843         intel_wakeref_t wakeref;
1844         enum pipe pipe = 0;
1845         int ret = 0;
1846         u32 tmp;
1847
1848         wakeref = intel_display_power_get_if_enabled(dev_priv,
1849                                                      intel_encoder->power_domain);
1850         if (WARN_ON(!wakeref))
1851                 return -ENXIO;
1852
1853         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1854                 ret = -EIO;
1855                 goto out;
1856         }
1857
1858         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1859         if (enable)
1860                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1861         else
1862                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1863         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1864 out:
1865         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1866         return ret;
1867 }
1868
1869 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1870 {
1871         struct drm_device *dev = intel_connector->base.dev;
1872         struct drm_i915_private *dev_priv = to_i915(dev);
1873         struct intel_encoder *encoder = intel_connector->encoder;
1874         int type = intel_connector->base.connector_type;
1875         enum port port = encoder->port;
1876         enum transcoder cpu_transcoder;
1877         intel_wakeref_t wakeref;
1878         enum pipe pipe = 0;
1879         u32 tmp;
1880         bool ret;
1881
1882         wakeref = intel_display_power_get_if_enabled(dev_priv,
1883                                                      encoder->power_domain);
1884         if (!wakeref)
1885                 return false;
1886
1887         if (!encoder->get_hw_state(encoder, &pipe)) {
1888                 ret = false;
1889                 goto out;
1890         }
1891
1892         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1893                 cpu_transcoder = TRANSCODER_EDP;
1894         else
1895                 cpu_transcoder = (enum transcoder) pipe;
1896
1897         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1898
1899         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1900         case TRANS_DDI_MODE_SELECT_HDMI:
1901         case TRANS_DDI_MODE_SELECT_DVI:
1902                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1903                 break;
1904
1905         case TRANS_DDI_MODE_SELECT_DP_SST:
1906                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1907                       type == DRM_MODE_CONNECTOR_DisplayPort;
1908                 break;
1909
1910         case TRANS_DDI_MODE_SELECT_DP_MST:
1911                 /* if the transcoder is in MST state then
1912                  * connector isn't connected */
1913                 ret = false;
1914                 break;
1915
1916         case TRANS_DDI_MODE_SELECT_FDI:
1917                 ret = type == DRM_MODE_CONNECTOR_VGA;
1918                 break;
1919
1920         default:
1921                 ret = false;
1922                 break;
1923         }
1924
1925 out:
1926         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1927
1928         return ret;
1929 }
1930
1931 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1932                                         u8 *pipe_mask, bool *is_dp_mst)
1933 {
1934         struct drm_device *dev = encoder->base.dev;
1935         struct drm_i915_private *dev_priv = to_i915(dev);
1936         enum port port = encoder->port;
1937         intel_wakeref_t wakeref;
1938         enum pipe p;
1939         u32 tmp;
1940         u8 mst_pipe_mask;
1941
1942         *pipe_mask = 0;
1943         *is_dp_mst = false;
1944
1945         wakeref = intel_display_power_get_if_enabled(dev_priv,
1946                                                      encoder->power_domain);
1947         if (!wakeref)
1948                 return;
1949
1950         tmp = I915_READ(DDI_BUF_CTL(port));
1951         if (!(tmp & DDI_BUF_CTL_ENABLE))
1952                 goto out;
1953
1954         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1955                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1956
1957                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1958                 default:
1959                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1960                         /* fallthrough */
1961                 case TRANS_DDI_EDP_INPUT_A_ON:
1962                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1963                         *pipe_mask = BIT(PIPE_A);
1964                         break;
1965                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1966                         *pipe_mask = BIT(PIPE_B);
1967                         break;
1968                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1969                         *pipe_mask = BIT(PIPE_C);
1970                         break;
1971                 }
1972
1973                 goto out;
1974         }
1975
1976         mst_pipe_mask = 0;
1977         for_each_pipe(dev_priv, p) {
1978                 enum transcoder cpu_transcoder = (enum transcoder)p;
1979
1980                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1981
1982                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1983                         continue;
1984
1985                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1986                     TRANS_DDI_MODE_SELECT_DP_MST)
1987                         mst_pipe_mask |= BIT(p);
1988
1989                 *pipe_mask |= BIT(p);
1990         }
1991
1992         if (!*pipe_mask)
1993                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
1994                               port_name(port));
1995
1996         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1997                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
1998                               port_name(port), *pipe_mask);
1999                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2000         }
2001
2002         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2003                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2004                               port_name(port), *pipe_mask, mst_pipe_mask);
2005         else
2006                 *is_dp_mst = mst_pipe_mask;
2007
2008 out:
2009         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2010                 tmp = I915_READ(BXT_PHY_CTL(port));
2011                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2012                             BXT_PHY_LANE_POWERDOWN_ACK |
2013                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2014                         DRM_ERROR("Port %c enabled but PHY powered down? "
2015                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2016         }
2017
2018         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2019 }
2020
2021 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2022                             enum pipe *pipe)
2023 {
2024         u8 pipe_mask;
2025         bool is_mst;
2026
2027         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2028
2029         if (is_mst || !pipe_mask)
2030                 return false;
2031
2032         *pipe = ffs(pipe_mask) - 1;
2033
2034         return true;
2035 }
2036
2037 static inline enum intel_display_power_domain
2038 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2039 {
2040         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2041          * DC states enabled at the same time, while for driver initiated AUX
2042          * transfers we need the same AUX IOs to be powered but with DC states
2043          * disabled. Accordingly use the AUX power domain here which leaves DC
2044          * states enabled.
2045          * However, for non-A AUX ports the corresponding non-EDP transcoders
2046          * would have already enabled power well 2 and DC_OFF. This means we can
2047          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2048          * specific AUX_IO reference without powering up any extra wells.
2049          * Note that PSR is enabled only on Port A even though this function
2050          * returns the correct domain for other ports too.
2051          */
2052         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2053                                               intel_aux_power_domain(dig_port);
2054 }
2055
2056 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2057                                         struct intel_crtc_state *crtc_state)
2058 {
2059         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2060         struct intel_digital_port *dig_port;
2061
2062         /*
2063          * TODO: Add support for MST encoders. Atm, the following should never
2064          * happen since fake-MST encoders don't set their get_power_domains()
2065          * hook.
2066          */
2067         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2068                 return;
2069
2070         dig_port = enc_to_dig_port(&encoder->base);
2071         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2072
2073         /*
2074          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2075          * ports.
2076          */
2077         if (intel_crtc_has_dp_encoder(crtc_state) ||
2078             intel_port_is_tc(dev_priv, encoder->port))
2079                 intel_display_power_get(dev_priv,
2080                                         intel_ddi_main_link_aux_domain(dig_port));
2081
2082         /*
2083          * VDSC power is needed when DSC is enabled
2084          */
2085         if (crtc_state->dsc_params.compression_enable)
2086                 intel_display_power_get(dev_priv,
2087                                         intel_dsc_power_domain(crtc_state));
2088 }
2089
2090 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2091 {
2092         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2093         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2094         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2095         enum port port = encoder->port;
2096         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2097
2098         if (cpu_transcoder != TRANSCODER_EDP)
2099                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2100                            TRANS_CLK_SEL_PORT(port));
2101 }
2102
2103 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2104 {
2105         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2106         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2107
2108         if (cpu_transcoder != TRANSCODER_EDP)
2109                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2110                            TRANS_CLK_SEL_DISABLED);
2111 }
2112
2113 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2114                                 enum port port, u8 iboost)
2115 {
2116         u32 tmp;
2117
2118         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2119         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2120         if (iboost)
2121                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2122         else
2123                 tmp |= BALANCE_LEG_DISABLE(port);
2124         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2125 }
2126
2127 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2128                                int level, enum intel_output_type type)
2129 {
2130         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2131         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2132         enum port port = encoder->port;
2133         u8 iboost;
2134
2135         if (type == INTEL_OUTPUT_HDMI)
2136                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2137         else
2138                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2139
2140         if (iboost == 0) {
2141                 const struct ddi_buf_trans *ddi_translations;
2142                 int n_entries;
2143
2144                 if (type == INTEL_OUTPUT_HDMI)
2145                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2146                 else if (type == INTEL_OUTPUT_EDP)
2147                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2148                 else
2149                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2150
2151                 if (WARN_ON_ONCE(!ddi_translations))
2152                         return;
2153                 if (WARN_ON_ONCE(level >= n_entries))
2154                         level = n_entries - 1;
2155
2156                 iboost = ddi_translations[level].i_boost;
2157         }
2158
2159         /* Make sure that the requested I_boost is valid */
2160         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2161                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2162                 return;
2163         }
2164
2165         _skl_ddi_set_iboost(dev_priv, port, iboost);
2166
2167         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2168                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2169 }
2170
2171 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2172                                     int level, enum intel_output_type type)
2173 {
2174         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2175         const struct bxt_ddi_buf_trans *ddi_translations;
2176         enum port port = encoder->port;
2177         int n_entries;
2178
2179         if (type == INTEL_OUTPUT_HDMI)
2180                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2181         else if (type == INTEL_OUTPUT_EDP)
2182                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2183         else
2184                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2185
2186         if (WARN_ON_ONCE(!ddi_translations))
2187                 return;
2188         if (WARN_ON_ONCE(level >= n_entries))
2189                 level = n_entries - 1;
2190
2191         bxt_ddi_phy_set_signal_level(dev_priv, port,
2192                                      ddi_translations[level].margin,
2193                                      ddi_translations[level].scale,
2194                                      ddi_translations[level].enable,
2195                                      ddi_translations[level].deemphasis);
2196 }
2197
2198 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2199 {
2200         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2201         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2202         enum port port = encoder->port;
2203         int n_entries;
2204
2205         if (INTEL_GEN(dev_priv) >= 11) {
2206                 if (intel_port_is_combophy(dev_priv, port))
2207                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2208                                                 intel_dp->link_rate, &n_entries);
2209                 else
2210                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2211         } else if (IS_CANNONLAKE(dev_priv)) {
2212                 if (encoder->type == INTEL_OUTPUT_EDP)
2213                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2214                 else
2215                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2216         } else if (IS_GEN9_LP(dev_priv)) {
2217                 if (encoder->type == INTEL_OUTPUT_EDP)
2218                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2219                 else
2220                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2221         } else {
2222                 if (encoder->type == INTEL_OUTPUT_EDP)
2223                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2224                 else
2225                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2226         }
2227
2228         if (WARN_ON(n_entries < 1))
2229                 n_entries = 1;
2230         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2231                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2232
2233         return index_to_dp_signal_levels[n_entries - 1] &
2234                 DP_TRAIN_VOLTAGE_SWING_MASK;
2235 }
2236
2237 /*
2238  * We assume that the full set of pre-emphasis values can be
2239  * used on all DDI platforms. Should that change we need to
2240  * rethink this code.
2241  */
2242 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2243 {
2244         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2245         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2246                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2247         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2248                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2249         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2250                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2251         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2252         default:
2253                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2254         }
2255 }
2256
2257 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2258                                    int level, enum intel_output_type type)
2259 {
2260         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2261         const struct cnl_ddi_buf_trans *ddi_translations;
2262         enum port port = encoder->port;
2263         int n_entries, ln;
2264         u32 val;
2265
2266         if (type == INTEL_OUTPUT_HDMI)
2267                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2268         else if (type == INTEL_OUTPUT_EDP)
2269                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2270         else
2271                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2272
2273         if (WARN_ON_ONCE(!ddi_translations))
2274                 return;
2275         if (WARN_ON_ONCE(level >= n_entries))
2276                 level = n_entries - 1;
2277
2278         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2279         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2280         val &= ~SCALING_MODE_SEL_MASK;
2281         val |= SCALING_MODE_SEL(2);
2282         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2283
2284         /* Program PORT_TX_DW2 */
2285         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2286         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2287                  RCOMP_SCALAR_MASK);
2288         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2289         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2290         /* Rcomp scalar is fixed as 0x98 for every table entry */
2291         val |= RCOMP_SCALAR(0x98);
2292         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2293
2294         /* Program PORT_TX_DW4 */
2295         /* We cannot write to GRP. It would overrite individual loadgen */
2296         for (ln = 0; ln < 4; ln++) {
2297                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2298                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2299                          CURSOR_COEFF_MASK);
2300                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2301                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2302                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2303                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2304         }
2305
2306         /* Program PORT_TX_DW5 */
2307         /* All DW5 values are fixed for every table entry */
2308         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2309         val &= ~RTERM_SELECT_MASK;
2310         val |= RTERM_SELECT(6);
2311         val |= TAP3_DISABLE;
2312         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2313
2314         /* Program PORT_TX_DW7 */
2315         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2316         val &= ~N_SCALAR_MASK;
2317         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2318         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2319 }
2320
2321 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2322                                     int level, enum intel_output_type type)
2323 {
2324         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2325         enum port port = encoder->port;
2326         int width, rate, ln;
2327         u32 val;
2328
2329         if (type == INTEL_OUTPUT_HDMI) {
2330                 width = 4;
2331                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2332         } else {
2333                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2334
2335                 width = intel_dp->lane_count;
2336                 rate = intel_dp->link_rate;
2337         }
2338
2339         /*
2340          * 1. If port type is eDP or DP,
2341          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2342          * else clear to 0b.
2343          */
2344         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2345         if (type != INTEL_OUTPUT_HDMI)
2346                 val |= COMMON_KEEPER_EN;
2347         else
2348                 val &= ~COMMON_KEEPER_EN;
2349         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2350
2351         /* 2. Program loadgen select */
2352         /*
2353          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2354          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2355          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2356          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2357          */
2358         for (ln = 0; ln <= 3; ln++) {
2359                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2360                 val &= ~LOADGEN_SELECT;
2361
2362                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2363                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2364                         val |= LOADGEN_SELECT;
2365                 }
2366                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2367         }
2368
2369         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2370         val = I915_READ(CNL_PORT_CL1CM_DW5);
2371         val |= SUS_CLOCK_CONFIG;
2372         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2373
2374         /* 4. Clear training enable to change swing values */
2375         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2376         val &= ~TX_TRAINING_EN;
2377         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2378
2379         /* 5. Program swing and de-emphasis */
2380         cnl_ddi_vswing_program(encoder, level, type);
2381
2382         /* 6. Set training enable to trigger update */
2383         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2384         val |= TX_TRAINING_EN;
2385         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2386 }
2387
2388 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2389                                         u32 level, enum port port, int type,
2390                                         int rate)
2391 {
2392         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2393         u32 n_entries, val;
2394         int ln;
2395
2396         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2397                                                    rate, &n_entries);
2398         if (!ddi_translations)
2399                 return;
2400
2401         if (level >= n_entries) {
2402                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2403                 level = n_entries - 1;
2404         }
2405
2406         /* Set PORT_TX_DW5 */
2407         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2408         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2409                   TAP2_DISABLE | TAP3_DISABLE);
2410         val |= SCALING_MODE_SEL(0x2);
2411         val |= RTERM_SELECT(0x6);
2412         val |= TAP3_DISABLE;
2413         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2414
2415         /* Program PORT_TX_DW2 */
2416         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2417         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2418                  RCOMP_SCALAR_MASK);
2419         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2420         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2421         /* Program Rcomp scalar for every table entry */
2422         val |= RCOMP_SCALAR(0x98);
2423         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2424
2425         /* Program PORT_TX_DW4 */
2426         /* We cannot write to GRP. It would overwrite individual loadgen. */
2427         for (ln = 0; ln <= 3; ln++) {
2428                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2429                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2430                          CURSOR_COEFF_MASK);
2431                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2432                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2433                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2434                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2435         }
2436
2437         /* Program PORT_TX_DW7 */
2438         val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2439         val &= ~N_SCALAR_MASK;
2440         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2441         I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2442 }
2443
2444 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2445                                               u32 level,
2446                                               enum intel_output_type type)
2447 {
2448         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2449         enum port port = encoder->port;
2450         int width = 0;
2451         int rate = 0;
2452         u32 val;
2453         int ln = 0;
2454
2455         if (type == INTEL_OUTPUT_HDMI) {
2456                 width = 4;
2457                 /* Rate is always < than 6GHz for HDMI */
2458         } else {
2459                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2460
2461                 width = intel_dp->lane_count;
2462                 rate = intel_dp->link_rate;
2463         }
2464
2465         /*
2466          * 1. If port type is eDP or DP,
2467          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2468          * else clear to 0b.
2469          */
2470         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2471         if (type == INTEL_OUTPUT_HDMI)
2472                 val &= ~COMMON_KEEPER_EN;
2473         else
2474                 val |= COMMON_KEEPER_EN;
2475         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2476
2477         /* 2. Program loadgen select */
2478         /*
2479          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2480          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2481          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2482          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2483          */
2484         for (ln = 0; ln <= 3; ln++) {
2485                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2486                 val &= ~LOADGEN_SELECT;
2487
2488                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2489                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2490                         val |= LOADGEN_SELECT;
2491                 }
2492                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2493         }
2494
2495         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2496         val = I915_READ(ICL_PORT_CL_DW5(port));
2497         val |= SUS_CLOCK_CONFIG;
2498         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2499
2500         /* 4. Clear training enable to change swing values */
2501         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2502         val &= ~TX_TRAINING_EN;
2503         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2504
2505         /* 5. Program swing and de-emphasis */
2506         icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2507
2508         /* 6. Set training enable to trigger update */
2509         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2510         val |= TX_TRAINING_EN;
2511         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2512 }
2513
2514 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2515                                            int link_clock,
2516                                            u32 level)
2517 {
2518         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2519         enum port port = encoder->port;
2520         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2521         u32 n_entries, val;
2522         int ln;
2523
2524         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2525         ddi_translations = icl_mg_phy_ddi_translations;
2526         /* The table does not have values for level 3 and level 9. */
2527         if (level >= n_entries || level == 3 || level == 9) {
2528                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2529                               level, n_entries - 2);
2530                 level = n_entries - 2;
2531         }
2532
2533         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2534         for (ln = 0; ln < 2; ln++) {
2535                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2536                 val &= ~CRI_USE_FS32;
2537                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2538
2539                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2540                 val &= ~CRI_USE_FS32;
2541                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2542         }
2543
2544         /* Program MG_TX_SWINGCTRL with values from vswing table */
2545         for (ln = 0; ln < 2; ln++) {
2546                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2547                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2548                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2549                         ddi_translations[level].cri_txdeemph_override_17_12);
2550                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2551
2552                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2553                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2554                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2555                         ddi_translations[level].cri_txdeemph_override_17_12);
2556                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2557         }
2558
2559         /* Program MG_TX_DRVCTRL with values from vswing table */
2560         for (ln = 0; ln < 2; ln++) {
2561                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2562                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2563                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2564                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2565                         ddi_translations[level].cri_txdeemph_override_5_0) |
2566                         CRI_TXDEEMPH_OVERRIDE_11_6(
2567                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2568                         CRI_TXDEEMPH_OVERRIDE_EN;
2569                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2570
2571                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2572                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2573                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2574                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2575                         ddi_translations[level].cri_txdeemph_override_5_0) |
2576                         CRI_TXDEEMPH_OVERRIDE_11_6(
2577                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2578                         CRI_TXDEEMPH_OVERRIDE_EN;
2579                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2580
2581                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2582         }
2583
2584         /*
2585          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2586          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2587          * values from table for which TX1 and TX2 enabled.
2588          */
2589         for (ln = 0; ln < 2; ln++) {
2590                 val = I915_READ(MG_CLKHUB(ln, port));
2591                 if (link_clock < 300000)
2592                         val |= CFG_LOW_RATE_LKREN_EN;
2593                 else
2594                         val &= ~CFG_LOW_RATE_LKREN_EN;
2595                 I915_WRITE(MG_CLKHUB(ln, port), val);
2596         }
2597
2598         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2599         for (ln = 0; ln < 2; ln++) {
2600                 val = I915_READ(MG_TX1_DCC(ln, port));
2601                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2602                 if (link_clock <= 500000) {
2603                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2604                 } else {
2605                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2606                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2607                 }
2608                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2609
2610                 val = I915_READ(MG_TX2_DCC(ln, port));
2611                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2612                 if (link_clock <= 500000) {
2613                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2614                 } else {
2615                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2616                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2617                 }
2618                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2619         }
2620
2621         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2622         for (ln = 0; ln < 2; ln++) {
2623                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2624                 val |= CRI_CALCINIT;
2625                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2626
2627                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2628                 val |= CRI_CALCINIT;
2629                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2630         }
2631 }
2632
2633 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2634                                     int link_clock,
2635                                     u32 level,
2636                                     enum intel_output_type type)
2637 {
2638         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2639         enum port port = encoder->port;
2640
2641         if (intel_port_is_combophy(dev_priv, port))
2642                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2643         else
2644                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2645 }
2646
2647 static u32 translate_signal_level(int signal_levels)
2648 {
2649         int i;
2650
2651         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2652                 if (index_to_dp_signal_levels[i] == signal_levels)
2653                         return i;
2654         }
2655
2656         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2657              signal_levels);
2658
2659         return 0;
2660 }
2661
2662 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2663 {
2664         u8 train_set = intel_dp->train_set[0];
2665         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2666                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2667
2668         return translate_signal_level(signal_levels);
2669 }
2670
2671 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2672 {
2673         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2674         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2675         struct intel_encoder *encoder = &dport->base;
2676         int level = intel_ddi_dp_level(intel_dp);
2677
2678         if (INTEL_GEN(dev_priv) >= 11)
2679                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2680                                         level, encoder->type);
2681         else if (IS_CANNONLAKE(dev_priv))
2682                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2683         else
2684                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2685
2686         return 0;
2687 }
2688
2689 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2690 {
2691         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2692         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2693         struct intel_encoder *encoder = &dport->base;
2694         int level = intel_ddi_dp_level(intel_dp);
2695
2696         if (IS_GEN9_BC(dev_priv))
2697                 skl_ddi_set_iboost(encoder, level, encoder->type);
2698
2699         return DDI_BUF_TRANS_SELECT(level);
2700 }
2701
2702 static inline
2703 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2704                               enum port port)
2705 {
2706         if (intel_port_is_combophy(dev_priv, port)) {
2707                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2708         } else if (intel_port_is_tc(dev_priv, port)) {
2709                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2710
2711                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2712         }
2713
2714         return 0;
2715 }
2716
2717 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2718                                   const struct intel_crtc_state *crtc_state)
2719 {
2720         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2721         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2722         enum port port = encoder->port;
2723         u32 val;
2724
2725         mutex_lock(&dev_priv->dpll_lock);
2726
2727         val = I915_READ(DPCLKA_CFGCR0_ICL);
2728         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2729
2730         if (intel_port_is_combophy(dev_priv, port)) {
2731                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2732                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2733                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2734                 POSTING_READ(DPCLKA_CFGCR0_ICL);
2735         }
2736
2737         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2738         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2739
2740         mutex_unlock(&dev_priv->dpll_lock);
2741 }
2742
2743 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2744 {
2745         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2746         enum port port = encoder->port;
2747         u32 val;
2748
2749         mutex_lock(&dev_priv->dpll_lock);
2750
2751         val = I915_READ(DPCLKA_CFGCR0_ICL);
2752         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2753         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2754
2755         mutex_unlock(&dev_priv->dpll_lock);
2756 }
2757
2758 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2759 {
2760         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2761         u32 val;
2762         enum port port;
2763         u32 port_mask;
2764         bool ddi_clk_needed;
2765
2766         /*
2767          * In case of DP MST, we sanitize the primary encoder only, not the
2768          * virtual ones.
2769          */
2770         if (encoder->type == INTEL_OUTPUT_DP_MST)
2771                 return;
2772
2773         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2774                 u8 pipe_mask;
2775                 bool is_mst;
2776
2777                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2778                 /*
2779                  * In the unlikely case that BIOS enables DP in MST mode, just
2780                  * warn since our MST HW readout is incomplete.
2781                  */
2782                 if (WARN_ON(is_mst))
2783                         return;
2784         }
2785
2786         port_mask = BIT(encoder->port);
2787         ddi_clk_needed = encoder->base.crtc;
2788
2789         if (encoder->type == INTEL_OUTPUT_DSI) {
2790                 struct intel_encoder *other_encoder;
2791
2792                 port_mask = intel_dsi_encoder_ports(encoder);
2793                 /*
2794                  * Sanity check that we haven't incorrectly registered another
2795                  * encoder using any of the ports of this DSI encoder.
2796                  */
2797                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2798                         if (other_encoder == encoder)
2799                                 continue;
2800
2801                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2802                                 return;
2803                 }
2804                 /*
2805                  * For DSI we keep the ddi clocks gated
2806                  * except during enable/disable sequence.
2807                  */
2808                 ddi_clk_needed = false;
2809         }
2810
2811         val = I915_READ(DPCLKA_CFGCR0_ICL);
2812         for_each_port_masked(port, port_mask) {
2813                 bool ddi_clk_ungated = !(val &
2814                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2815                                                                    port));
2816
2817                 if (ddi_clk_needed == ddi_clk_ungated)
2818                         continue;
2819
2820                 /*
2821                  * Punt on the case now where clock is gated, but it would
2822                  * be needed by the port. Something else is really broken then.
2823                  */
2824                 if (WARN_ON(ddi_clk_needed))
2825                         continue;
2826
2827                 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2828                          port_name(port));
2829                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2830                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2831         }
2832 }
2833
2834 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2835                                  const struct intel_crtc_state *crtc_state)
2836 {
2837         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2838         enum port port = encoder->port;
2839         u32 val;
2840         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2841
2842         if (WARN_ON(!pll))
2843                 return;
2844
2845         mutex_lock(&dev_priv->dpll_lock);
2846
2847         if (INTEL_GEN(dev_priv) >= 11) {
2848                 if (!intel_port_is_combophy(dev_priv, port))
2849                         I915_WRITE(DDI_CLK_SEL(port),
2850                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2851         } else if (IS_CANNONLAKE(dev_priv)) {
2852                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2853                 val = I915_READ(DPCLKA_CFGCR0);
2854                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2855                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2856                 I915_WRITE(DPCLKA_CFGCR0, val);
2857
2858                 /*
2859                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2860                  * This step and the step before must be done with separate
2861                  * register writes.
2862                  */
2863                 val = I915_READ(DPCLKA_CFGCR0);
2864                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2865                 I915_WRITE(DPCLKA_CFGCR0, val);
2866         } else if (IS_GEN9_BC(dev_priv)) {
2867                 /* DDI -> PLL mapping  */
2868                 val = I915_READ(DPLL_CTRL2);
2869
2870                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2871                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2872                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2873                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2874
2875                 I915_WRITE(DPLL_CTRL2, val);
2876
2877         } else if (INTEL_GEN(dev_priv) < 9) {
2878                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2879         }
2880
2881         mutex_unlock(&dev_priv->dpll_lock);
2882 }
2883
2884 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2885 {
2886         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2887         enum port port = encoder->port;
2888
2889         if (INTEL_GEN(dev_priv) >= 11) {
2890                 if (!intel_port_is_combophy(dev_priv, port))
2891                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2892         } else if (IS_CANNONLAKE(dev_priv)) {
2893                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2894                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2895         } else if (IS_GEN9_BC(dev_priv)) {
2896                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2897                            DPLL_CTRL2_DDI_CLK_OFF(port));
2898         } else if (INTEL_GEN(dev_priv) < 9) {
2899                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2900         }
2901 }
2902
2903 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2904 {
2905         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2906         enum port port = dig_port->base.port;
2907         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2908         i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
2909         u32 val;
2910         int i;
2911
2912         if (tc_port == PORT_TC_NONE)
2913                 return;
2914
2915         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2916                 val = I915_READ(mg_regs[i]);
2917                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2918                        MG_DP_MODE_CFG_TRPWR_GATING |
2919                        MG_DP_MODE_CFG_CLNPWR_GATING |
2920                        MG_DP_MODE_CFG_DIGPWR_GATING |
2921                        MG_DP_MODE_CFG_GAONPWR_GATING;
2922                 I915_WRITE(mg_regs[i], val);
2923         }
2924
2925         val = I915_READ(MG_MISC_SUS0(tc_port));
2926         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2927                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2928                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2929                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2930                MG_MISC_SUS0_CFG_TRPWR_GATING |
2931                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2932                MG_MISC_SUS0_CFG_DGPWR_GATING;
2933         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2934 }
2935
2936 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2937 {
2938         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2939         enum port port = dig_port->base.port;
2940         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2941         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2942         u32 val;
2943         int i;
2944
2945         if (tc_port == PORT_TC_NONE)
2946                 return;
2947
2948         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2949                 val = I915_READ(mg_regs[i]);
2950                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2951                          MG_DP_MODE_CFG_TRPWR_GATING |
2952                          MG_DP_MODE_CFG_CLNPWR_GATING |
2953                          MG_DP_MODE_CFG_DIGPWR_GATING |
2954                          MG_DP_MODE_CFG_GAONPWR_GATING);
2955                 I915_WRITE(mg_regs[i], val);
2956         }
2957
2958         val = I915_READ(MG_MISC_SUS0(tc_port));
2959         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2960                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
2961                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
2962                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
2963                  MG_MISC_SUS0_CFG_TRPWR_GATING |
2964                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
2965                  MG_MISC_SUS0_CFG_DGPWR_GATING);
2966         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2967 }
2968
2969 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2970 {
2971         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2972         enum port port = intel_dig_port->base.port;
2973         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2974         u32 ln0, ln1, lane_info;
2975
2976         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2977                 return;
2978
2979         ln0 = I915_READ(MG_DP_MODE(0, port));
2980         ln1 = I915_READ(MG_DP_MODE(1, port));
2981
2982         switch (intel_dig_port->tc_type) {
2983         case TC_PORT_TYPEC:
2984                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2985                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2986
2987                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
2988                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
2989                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
2990
2991                 switch (lane_info) {
2992                 case 0x1:
2993                 case 0x4:
2994                         break;
2995                 case 0x2:
2996                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2997                         break;
2998                 case 0x3:
2999                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3000                                MG_DP_MODE_CFG_DP_X2_MODE;
3001                         break;
3002                 case 0x8:
3003                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3004                         break;
3005                 case 0xC:
3006                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3007                                MG_DP_MODE_CFG_DP_X2_MODE;
3008                         break;
3009                 case 0xF:
3010                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3011                                MG_DP_MODE_CFG_DP_X2_MODE;
3012                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3013                                MG_DP_MODE_CFG_DP_X2_MODE;
3014                         break;
3015                 default:
3016                         MISSING_CASE(lane_info);
3017                 }
3018                 break;
3019
3020         case TC_PORT_LEGACY:
3021                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3022                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3023                 break;
3024
3025         default:
3026                 MISSING_CASE(intel_dig_port->tc_type);
3027                 return;
3028         }
3029
3030         I915_WRITE(MG_DP_MODE(0, port), ln0);
3031         I915_WRITE(MG_DP_MODE(1, port), ln1);
3032 }
3033
3034 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3035                                         const struct intel_crtc_state *crtc_state)
3036 {
3037         if (!crtc_state->fec_enable)
3038                 return;
3039
3040         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3041                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3042 }
3043
3044 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3045                                  const struct intel_crtc_state *crtc_state)
3046 {
3047         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3048         enum port port = encoder->port;
3049         u32 val;
3050
3051         if (!crtc_state->fec_enable)
3052                 return;
3053
3054         val = I915_READ(DP_TP_CTL(port));
3055         val |= DP_TP_CTL_FEC_ENABLE;
3056         I915_WRITE(DP_TP_CTL(port), val);
3057
3058         if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
3059                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3060                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3061                                     1))
3062                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3063 }
3064
3065 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3066                                         const struct intel_crtc_state *crtc_state)
3067 {
3068         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3069         enum port port = encoder->port;
3070         u32 val;
3071
3072         if (!crtc_state->fec_enable)
3073                 return;
3074
3075         val = I915_READ(DP_TP_CTL(port));
3076         val &= ~DP_TP_CTL_FEC_ENABLE;
3077         I915_WRITE(DP_TP_CTL(port), val);
3078         POSTING_READ(DP_TP_CTL(port));
3079 }
3080
3081 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3082                                     const struct intel_crtc_state *crtc_state,
3083                                     const struct drm_connector_state *conn_state)
3084 {
3085         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3086         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3087         enum port port = encoder->port;
3088         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3089         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3090         int level = intel_ddi_dp_level(intel_dp);
3091
3092         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3093
3094         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3095                                  crtc_state->lane_count, is_mst);
3096
3097         intel_edp_panel_on(intel_dp);
3098
3099         intel_ddi_clk_select(encoder, crtc_state);
3100
3101         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3102
3103         icl_program_mg_dp_mode(dig_port);
3104         icl_disable_phy_clock_gating(dig_port);
3105
3106         if (INTEL_GEN(dev_priv) >= 11)
3107                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3108                                         level, encoder->type);
3109         else if (IS_CANNONLAKE(dev_priv))
3110                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3111         else if (IS_GEN9_LP(dev_priv))
3112                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3113         else
3114                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3115
3116         intel_ddi_init_dp_buf_reg(encoder);
3117         if (!is_mst)
3118                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3119         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3120                                               true);
3121         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3122         intel_dp_start_link_train(intel_dp);
3123         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3124                 intel_dp_stop_link_train(intel_dp);
3125
3126         intel_ddi_enable_fec(encoder, crtc_state);
3127
3128         icl_enable_phy_clock_gating(dig_port);
3129
3130         if (!is_mst)
3131                 intel_ddi_enable_pipe_clock(crtc_state);
3132
3133         intel_dsc_enable(encoder, crtc_state);
3134 }
3135
3136 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3137                                       const struct intel_crtc_state *crtc_state,
3138                                       const struct drm_connector_state *conn_state)
3139 {
3140         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3141         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3142         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3143         enum port port = encoder->port;
3144         int level = intel_ddi_hdmi_level(dev_priv, port);
3145         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3146
3147         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3148         intel_ddi_clk_select(encoder, crtc_state);
3149
3150         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3151
3152         icl_program_mg_dp_mode(dig_port);
3153         icl_disable_phy_clock_gating(dig_port);
3154
3155         if (INTEL_GEN(dev_priv) >= 11)
3156                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3157                                         level, INTEL_OUTPUT_HDMI);
3158         else if (IS_CANNONLAKE(dev_priv))
3159                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3160         else if (IS_GEN9_LP(dev_priv))
3161                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3162         else
3163                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3164
3165         icl_enable_phy_clock_gating(dig_port);
3166
3167         if (IS_GEN9_BC(dev_priv))
3168                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3169
3170         intel_ddi_enable_pipe_clock(crtc_state);
3171
3172         intel_dig_port->set_infoframes(encoder,
3173                                        crtc_state->has_infoframe,
3174                                        crtc_state, conn_state);
3175 }
3176
3177 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3178                                  const struct intel_crtc_state *crtc_state,
3179                                  const struct drm_connector_state *conn_state)
3180 {
3181         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3182         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3183         enum pipe pipe = crtc->pipe;
3184
3185         /*
3186          * When called from DP MST code:
3187          * - conn_state will be NULL
3188          * - encoder will be the main encoder (ie. mst->primary)
3189          * - the main connector associated with this port
3190          *   won't be active or linked to a crtc
3191          * - crtc_state will be the state of the first stream to
3192          *   be activated on this port, and it may not be the same
3193          *   stream that will be deactivated last, but each stream
3194          *   should have a state that is identical when it comes to
3195          *   the DP link parameteres
3196          */
3197
3198         WARN_ON(crtc_state->has_pch_encoder);
3199
3200         if (INTEL_GEN(dev_priv) >= 11)
3201                 icl_map_plls_to_ports(encoder, crtc_state);
3202
3203         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3204
3205         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3206                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3207         } else {
3208                 struct intel_lspcon *lspcon =
3209                                 enc_to_intel_lspcon(&encoder->base);
3210
3211                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3212                 if (lspcon->active) {
3213                         struct intel_digital_port *dig_port =
3214                                         enc_to_dig_port(&encoder->base);
3215
3216                         dig_port->set_infoframes(encoder,
3217                                                  crtc_state->has_infoframe,
3218                                                  crtc_state, conn_state);
3219                 }
3220         }
3221 }
3222
3223 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3224                                   const struct intel_crtc_state *crtc_state)
3225 {
3226         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3227         enum port port = encoder->port;
3228         bool wait = false;
3229         u32 val;
3230
3231         val = I915_READ(DDI_BUF_CTL(port));
3232         if (val & DDI_BUF_CTL_ENABLE) {
3233                 val &= ~DDI_BUF_CTL_ENABLE;
3234                 I915_WRITE(DDI_BUF_CTL(port), val);
3235                 wait = true;
3236         }
3237
3238         val = I915_READ(DP_TP_CTL(port));
3239         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3240         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3241         I915_WRITE(DP_TP_CTL(port), val);
3242
3243         /* Disable FEC in DP Sink */
3244         intel_ddi_disable_fec_state(encoder, crtc_state);
3245
3246         if (wait)
3247                 intel_wait_ddi_buf_idle(dev_priv, port);
3248 }
3249
3250 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3251                                       const struct intel_crtc_state *old_crtc_state,
3252                                       const struct drm_connector_state *old_conn_state)
3253 {
3254         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3255         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3256         struct intel_dp *intel_dp = &dig_port->dp;
3257         bool is_mst = intel_crtc_has_type(old_crtc_state,
3258                                           INTEL_OUTPUT_DP_MST);
3259
3260         if (!is_mst) {
3261                 intel_ddi_disable_pipe_clock(old_crtc_state);
3262                 /*
3263                  * Power down sink before disabling the port, otherwise we end
3264                  * up getting interrupts from the sink on detecting link loss.
3265                  */
3266                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3267         }
3268
3269         intel_disable_ddi_buf(encoder, old_crtc_state);
3270
3271         intel_edp_panel_vdd_on(intel_dp);
3272         intel_edp_panel_off(intel_dp);
3273
3274         intel_display_power_put_unchecked(dev_priv,
3275                                           dig_port->ddi_io_power_domain);
3276
3277         intel_ddi_clk_disable(encoder);
3278 }
3279
3280 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3281                                         const struct intel_crtc_state *old_crtc_state,
3282                                         const struct drm_connector_state *old_conn_state)
3283 {
3284         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3285         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3286         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3287
3288         dig_port->set_infoframes(encoder, false,
3289                                  old_crtc_state, old_conn_state);
3290
3291         intel_ddi_disable_pipe_clock(old_crtc_state);
3292
3293         intel_disable_ddi_buf(encoder, old_crtc_state);
3294
3295         intel_display_power_put_unchecked(dev_priv,
3296                                           dig_port->ddi_io_power_domain);
3297
3298         intel_ddi_clk_disable(encoder);
3299
3300         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3301 }
3302
3303 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3304                                    const struct intel_crtc_state *old_crtc_state,
3305                                    const struct drm_connector_state *old_conn_state)
3306 {
3307         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3308
3309         /*
3310          * When called from DP MST code:
3311          * - old_conn_state will be NULL
3312          * - encoder will be the main encoder (ie. mst->primary)
3313          * - the main connector associated with this port
3314          *   won't be active or linked to a crtc
3315          * - old_crtc_state will be the state of the last stream to
3316          *   be deactivated on this port, and it may not be the same
3317          *   stream that was activated last, but each stream
3318          *   should have a state that is identical when it comes to
3319          *   the DP link parameteres
3320          */
3321
3322         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3323                 intel_ddi_post_disable_hdmi(encoder,
3324                                             old_crtc_state, old_conn_state);
3325         else
3326                 intel_ddi_post_disable_dp(encoder,
3327                                           old_crtc_state, old_conn_state);
3328
3329         if (INTEL_GEN(dev_priv) >= 11)
3330                 icl_unmap_plls_to_ports(encoder);
3331 }
3332
3333 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3334                                 const struct intel_crtc_state *old_crtc_state,
3335                                 const struct drm_connector_state *old_conn_state)
3336 {
3337         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3338         u32 val;
3339
3340         /*
3341          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3342          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3343          * step 13 is the correct place for it. Step 18 is where it was
3344          * originally before the BUN.
3345          */
3346         val = I915_READ(FDI_RX_CTL(PIPE_A));
3347         val &= ~FDI_RX_ENABLE;
3348         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3349
3350         intel_disable_ddi_buf(encoder, old_crtc_state);
3351         intel_ddi_clk_disable(encoder);
3352
3353         val = I915_READ(FDI_RX_MISC(PIPE_A));
3354         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3355         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3356         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3357
3358         val = I915_READ(FDI_RX_CTL(PIPE_A));
3359         val &= ~FDI_PCDCLK;
3360         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3361
3362         val = I915_READ(FDI_RX_CTL(PIPE_A));
3363         val &= ~FDI_RX_PLL_ENABLE;
3364         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3365 }
3366
3367 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3368                                 const struct intel_crtc_state *crtc_state,
3369                                 const struct drm_connector_state *conn_state)
3370 {
3371         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3372         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3373         enum port port = encoder->port;
3374
3375         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3376                 intel_dp_stop_link_train(intel_dp);
3377
3378         intel_edp_backlight_on(crtc_state, conn_state);
3379         intel_psr_enable(intel_dp, crtc_state);
3380         intel_edp_drrs_enable(intel_dp, crtc_state);
3381
3382         if (crtc_state->has_audio)
3383                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3384 }
3385
3386 static i915_reg_t
3387 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3388                                enum port port)
3389 {
3390         static const i915_reg_t regs[] = {
3391                 [PORT_A] = CHICKEN_TRANS_EDP,
3392                 [PORT_B] = CHICKEN_TRANS_A,
3393                 [PORT_C] = CHICKEN_TRANS_B,
3394                 [PORT_D] = CHICKEN_TRANS_C,
3395                 [PORT_E] = CHICKEN_TRANS_A,
3396         };
3397
3398         WARN_ON(INTEL_GEN(dev_priv) < 9);
3399
3400         if (WARN_ON(port < PORT_A || port > PORT_E))
3401                 port = PORT_A;
3402
3403         return regs[port];
3404 }
3405
3406 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3407                                   const struct intel_crtc_state *crtc_state,
3408                                   const struct drm_connector_state *conn_state)
3409 {
3410         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3411         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3412         struct drm_connector *connector = conn_state->connector;
3413         enum port port = encoder->port;
3414
3415         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3416                                                crtc_state->hdmi_high_tmds_clock_ratio,
3417                                                crtc_state->hdmi_scrambling))
3418                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3419                           connector->base.id, connector->name);
3420
3421         /* Display WA #1143: skl,kbl,cfl */
3422         if (IS_GEN9_BC(dev_priv)) {
3423                 /*
3424                  * For some reason these chicken bits have been
3425                  * stuffed into a transcoder register, event though
3426                  * the bits affect a specific DDI port rather than
3427                  * a specific transcoder.
3428                  */
3429                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3430                 u32 val;
3431
3432                 val = I915_READ(reg);
3433
3434                 if (port == PORT_E)
3435                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3436                                 DDIE_TRAINING_OVERRIDE_VALUE;
3437                 else
3438                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3439                                 DDI_TRAINING_OVERRIDE_VALUE;
3440
3441                 I915_WRITE(reg, val);
3442                 POSTING_READ(reg);
3443
3444                 udelay(1);
3445
3446                 if (port == PORT_E)
3447                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3448                                  DDIE_TRAINING_OVERRIDE_VALUE);
3449                 else
3450                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3451                                  DDI_TRAINING_OVERRIDE_VALUE);
3452
3453                 I915_WRITE(reg, val);
3454         }
3455
3456         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3457          * are ignored so nothing special needs to be done besides
3458          * enabling the port.
3459          */
3460         I915_WRITE(DDI_BUF_CTL(port),
3461                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3462
3463         if (crtc_state->has_audio)
3464                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3465 }
3466
3467 static void intel_enable_ddi(struct intel_encoder *encoder,
3468                              const struct intel_crtc_state *crtc_state,
3469                              const struct drm_connector_state *conn_state)
3470 {
3471         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3472                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3473         else
3474                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3475
3476         /* Enable hdcp if it's desired */
3477         if (conn_state->content_protection ==
3478             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3479                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3480 }
3481
3482 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3483                                  const struct intel_crtc_state *old_crtc_state,
3484                                  const struct drm_connector_state *old_conn_state)
3485 {
3486         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3487
3488         intel_dp->link_trained = false;
3489
3490         if (old_crtc_state->has_audio)
3491                 intel_audio_codec_disable(encoder,
3492                                           old_crtc_state, old_conn_state);
3493
3494         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3495         intel_psr_disable(intel_dp, old_crtc_state);
3496         intel_edp_backlight_off(old_conn_state);
3497         /* Disable the decompression in DP Sink */
3498         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3499                                               false);
3500 }
3501
3502 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3503                                    const struct intel_crtc_state *old_crtc_state,
3504                                    const struct drm_connector_state *old_conn_state)
3505 {
3506         struct drm_connector *connector = old_conn_state->connector;
3507
3508         if (old_crtc_state->has_audio)
3509                 intel_audio_codec_disable(encoder,
3510                                           old_crtc_state, old_conn_state);
3511
3512         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3513                                                false, false))
3514                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3515                               connector->base.id, connector->name);
3516 }
3517
3518 static void intel_disable_ddi(struct intel_encoder *encoder,
3519                               const struct intel_crtc_state *old_crtc_state,
3520                               const struct drm_connector_state *old_conn_state)
3521 {
3522         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3523
3524         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3525                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3526         else
3527                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3528 }
3529
3530 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3531                                      const struct intel_crtc_state *crtc_state,
3532                                      const struct drm_connector_state *conn_state)
3533 {
3534         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3535
3536         intel_ddi_set_pipe_settings(crtc_state);
3537
3538         intel_psr_update(intel_dp, crtc_state);
3539         intel_edp_drrs_enable(intel_dp, crtc_state);
3540
3541         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3542 }
3543
3544 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3545                                   const struct intel_crtc_state *crtc_state,
3546                                   const struct drm_connector_state *conn_state)
3547 {
3548         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3549                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3550
3551         if (conn_state->content_protection ==
3552             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3553                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3554         else if (conn_state->content_protection ==
3555                  DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3556                 intel_hdcp_disable(to_intel_connector(conn_state->connector));
3557 }
3558
3559 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3560                                          const struct intel_crtc_state *pipe_config,
3561                                          enum port port)
3562 {
3563         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3564         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3565         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3566         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3567         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3568
3569         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3570         switch (pipe_config->lane_count) {
3571         case 1:
3572                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3573                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3574                 break;
3575         case 2:
3576                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3577                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3578                 break;
3579         case 4:
3580                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3581                 break;
3582         default:
3583                 MISSING_CASE(pipe_config->lane_count);
3584         }
3585         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3586 }
3587
3588 static void
3589 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3590                          const struct intel_crtc_state *crtc_state,
3591                          const struct drm_connector_state *conn_state)
3592 {
3593         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3594         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3595         enum port port = encoder->port;
3596
3597         if (intel_crtc_has_dp_encoder(crtc_state) ||
3598             intel_port_is_tc(dev_priv, encoder->port))
3599                 intel_display_power_get(dev_priv,
3600                                         intel_ddi_main_link_aux_domain(dig_port));
3601
3602         if (IS_GEN9_LP(dev_priv))
3603                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3604                                                 crtc_state->lane_lat_optim_mask);
3605
3606         /*
3607          * Program the lane count for static/dynamic connections on Type-C ports.
3608          * Skip this step for TBT.
3609          */
3610         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3611             dig_port->tc_type == TC_PORT_TBT)
3612                 return;
3613
3614         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3615 }
3616
3617 static void
3618 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3619                            const struct intel_crtc_state *crtc_state,
3620                            const struct drm_connector_state *conn_state)
3621 {
3622         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3623         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3624
3625         if (intel_crtc_has_dp_encoder(crtc_state) ||
3626             intel_port_is_tc(dev_priv, encoder->port))
3627                 intel_display_power_put_unchecked(dev_priv,
3628                                                   intel_ddi_main_link_aux_domain(dig_port));
3629 }
3630
3631 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3632 {
3633         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3634         struct drm_i915_private *dev_priv =
3635                 to_i915(intel_dig_port->base.base.dev);
3636         enum port port = intel_dig_port->base.port;
3637         u32 val;
3638         bool wait = false;
3639
3640         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3641                 val = I915_READ(DDI_BUF_CTL(port));
3642                 if (val & DDI_BUF_CTL_ENABLE) {
3643                         val &= ~DDI_BUF_CTL_ENABLE;
3644                         I915_WRITE(DDI_BUF_CTL(port), val);
3645                         wait = true;
3646                 }
3647
3648                 val = I915_READ(DP_TP_CTL(port));
3649                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3650                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3651                 I915_WRITE(DP_TP_CTL(port), val);
3652                 POSTING_READ(DP_TP_CTL(port));
3653
3654                 if (wait)
3655                         intel_wait_ddi_buf_idle(dev_priv, port);
3656         }
3657
3658         val = DP_TP_CTL_ENABLE |
3659               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3660         if (intel_dp->link_mst)
3661                 val |= DP_TP_CTL_MODE_MST;
3662         else {
3663                 val |= DP_TP_CTL_MODE_SST;
3664                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3665                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3666         }
3667         I915_WRITE(DP_TP_CTL(port), val);
3668         POSTING_READ(DP_TP_CTL(port));
3669
3670         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3671         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3672         POSTING_READ(DDI_BUF_CTL(port));
3673
3674         udelay(600);
3675 }
3676
3677 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3678                                        enum transcoder cpu_transcoder)
3679 {
3680         if (cpu_transcoder == TRANSCODER_EDP)
3681                 return false;
3682
3683         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3684                 return false;
3685
3686         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3687                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3688 }
3689
3690 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3691                                          struct intel_crtc_state *crtc_state)
3692 {
3693         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3694                 crtc_state->min_voltage_level = 1;
3695         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3696                 crtc_state->min_voltage_level = 2;
3697 }
3698
3699 void intel_ddi_get_config(struct intel_encoder *encoder,
3700                           struct intel_crtc_state *pipe_config)
3701 {
3702         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3703         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3704         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3705         struct intel_digital_port *intel_dig_port;
3706         u32 temp, flags = 0;
3707
3708         /* XXX: DSI transcoder paranoia */
3709         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3710                 return;
3711
3712         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3713         if (temp & TRANS_DDI_PHSYNC)
3714                 flags |= DRM_MODE_FLAG_PHSYNC;
3715         else
3716                 flags |= DRM_MODE_FLAG_NHSYNC;
3717         if (temp & TRANS_DDI_PVSYNC)
3718                 flags |= DRM_MODE_FLAG_PVSYNC;
3719         else
3720                 flags |= DRM_MODE_FLAG_NVSYNC;
3721
3722         pipe_config->base.adjusted_mode.flags |= flags;
3723
3724         switch (temp & TRANS_DDI_BPC_MASK) {
3725         case TRANS_DDI_BPC_6:
3726                 pipe_config->pipe_bpp = 18;
3727                 break;
3728         case TRANS_DDI_BPC_8:
3729                 pipe_config->pipe_bpp = 24;
3730                 break;
3731         case TRANS_DDI_BPC_10:
3732                 pipe_config->pipe_bpp = 30;
3733                 break;
3734         case TRANS_DDI_BPC_12:
3735                 pipe_config->pipe_bpp = 36;
3736                 break;
3737         default:
3738                 break;
3739         }
3740
3741         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3742         case TRANS_DDI_MODE_SELECT_HDMI:
3743                 pipe_config->has_hdmi_sink = true;
3744                 intel_dig_port = enc_to_dig_port(&encoder->base);
3745
3746                 pipe_config->infoframes.enable |=
3747                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3748
3749                 if (pipe_config->infoframes.enable)
3750                         pipe_config->has_infoframe = true;
3751
3752                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3753                         pipe_config->hdmi_scrambling = true;
3754                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3755                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3756                 /* fall through */
3757         case TRANS_DDI_MODE_SELECT_DVI:
3758                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3759                 pipe_config->lane_count = 4;
3760                 break;
3761         case TRANS_DDI_MODE_SELECT_FDI:
3762                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3763                 break;
3764         case TRANS_DDI_MODE_SELECT_DP_SST:
3765                 if (encoder->type == INTEL_OUTPUT_EDP)
3766                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3767                 else
3768                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3769                 pipe_config->lane_count =
3770                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3771                 intel_dp_get_m_n(intel_crtc, pipe_config);
3772                 break;
3773         case TRANS_DDI_MODE_SELECT_DP_MST:
3774                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3775                 pipe_config->lane_count =
3776                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3777                 intel_dp_get_m_n(intel_crtc, pipe_config);
3778                 break;
3779         default:
3780                 break;
3781         }
3782
3783         pipe_config->has_audio =
3784                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3785
3786         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3787             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3788                 /*
3789                  * This is a big fat ugly hack.
3790                  *
3791                  * Some machines in UEFI boot mode provide us a VBT that has 18
3792                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3793                  * unknown we fail to light up. Yet the same BIOS boots up with
3794                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3795                  * max, not what it tells us to use.
3796                  *
3797                  * Note: This will still be broken if the eDP panel is not lit
3798                  * up by the BIOS, and thus we can't get the mode at module
3799                  * load.
3800                  */
3801                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3802                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3803                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3804         }
3805
3806         intel_ddi_clock_get(encoder, pipe_config);
3807
3808         if (IS_GEN9_LP(dev_priv))
3809                 pipe_config->lane_lat_optim_mask =
3810                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3811
3812         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3813
3814         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3815
3816         intel_read_infoframe(encoder, pipe_config,
3817                              HDMI_INFOFRAME_TYPE_AVI,
3818                              &pipe_config->infoframes.avi);
3819         intel_read_infoframe(encoder, pipe_config,
3820                              HDMI_INFOFRAME_TYPE_SPD,
3821                              &pipe_config->infoframes.spd);
3822         intel_read_infoframe(encoder, pipe_config,
3823                              HDMI_INFOFRAME_TYPE_VENDOR,
3824                              &pipe_config->infoframes.hdmi);
3825 }
3826
3827 static enum intel_output_type
3828 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3829                               struct intel_crtc_state *crtc_state,
3830                               struct drm_connector_state *conn_state)
3831 {
3832         switch (conn_state->connector->connector_type) {
3833         case DRM_MODE_CONNECTOR_HDMIA:
3834                 return INTEL_OUTPUT_HDMI;
3835         case DRM_MODE_CONNECTOR_eDP:
3836                 return INTEL_OUTPUT_EDP;
3837         case DRM_MODE_CONNECTOR_DisplayPort:
3838                 return INTEL_OUTPUT_DP;
3839         default:
3840                 MISSING_CASE(conn_state->connector->connector_type);
3841                 return INTEL_OUTPUT_UNUSED;
3842         }
3843 }
3844
3845 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3846                                     struct intel_crtc_state *pipe_config,
3847                                     struct drm_connector_state *conn_state)
3848 {
3849         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3850         enum port port = encoder->port;
3851         int ret;
3852
3853         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3854                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3855
3856         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3857                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3858         else
3859                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3860         if (ret)
3861                 return ret;
3862
3863         if (IS_GEN9_LP(dev_priv))
3864                 pipe_config->lane_lat_optim_mask =
3865                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3866
3867         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3868
3869         return 0;
3870
3871 }
3872
3873 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3874 {
3875         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3876         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3877
3878         intel_dp_encoder_suspend(encoder);
3879
3880         /*
3881          * TODO: disconnect also from USB DP alternate mode once we have a
3882          * way to handle the modeset restore in that mode during resume
3883          * even if the sink has disappeared while being suspended.
3884          */
3885         if (dig_port->tc_legacy_port)
3886                 icl_tc_phy_disconnect(i915, dig_port);
3887 }
3888
3889 static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3890 {
3891         struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3892         struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3893
3894         if (intel_port_is_tc(i915, dig_port->base.port))
3895                 intel_digital_port_connected(&dig_port->base);
3896
3897         intel_dp_encoder_reset(drm_encoder);
3898 }
3899
3900 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3901 {
3902         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3903         struct drm_i915_private *i915 = to_i915(encoder->dev);
3904
3905         intel_dp_encoder_flush_work(encoder);
3906
3907         if (intel_port_is_tc(i915, dig_port->base.port))
3908                 icl_tc_phy_disconnect(i915, dig_port);
3909
3910         drm_encoder_cleanup(encoder);
3911         kfree(dig_port);
3912 }
3913
3914 static const struct drm_encoder_funcs intel_ddi_funcs = {
3915         .reset = intel_ddi_encoder_reset,
3916         .destroy = intel_ddi_encoder_destroy,
3917 };
3918
3919 static struct intel_connector *
3920 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3921 {
3922         struct intel_connector *connector;
3923         enum port port = intel_dig_port->base.port;
3924
3925         connector = intel_connector_alloc();
3926         if (!connector)
3927                 return NULL;
3928
3929         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3930         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3931                 kfree(connector);
3932                 return NULL;
3933         }
3934
3935         return connector;
3936 }
3937
3938 static int modeset_pipe(struct drm_crtc *crtc,
3939                         struct drm_modeset_acquire_ctx *ctx)
3940 {
3941         struct drm_atomic_state *state;
3942         struct drm_crtc_state *crtc_state;
3943         int ret;
3944
3945         state = drm_atomic_state_alloc(crtc->dev);
3946         if (!state)
3947                 return -ENOMEM;
3948
3949         state->acquire_ctx = ctx;
3950
3951         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3952         if (IS_ERR(crtc_state)) {
3953                 ret = PTR_ERR(crtc_state);
3954                 goto out;
3955         }
3956
3957         crtc_state->connectors_changed = true;
3958
3959         ret = drm_atomic_commit(state);
3960 out:
3961         drm_atomic_state_put(state);
3962
3963         return ret;
3964 }
3965
3966 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3967                                  struct drm_modeset_acquire_ctx *ctx)
3968 {
3969         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3970         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3971         struct intel_connector *connector = hdmi->attached_connector;
3972         struct i2c_adapter *adapter =
3973                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3974         struct drm_connector_state *conn_state;
3975         struct intel_crtc_state *crtc_state;
3976         struct intel_crtc *crtc;
3977         u8 config;
3978         int ret;
3979
3980         if (!connector || connector->base.status != connector_status_connected)
3981                 return 0;
3982
3983         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3984                                ctx);
3985         if (ret)
3986                 return ret;
3987
3988         conn_state = connector->base.state;
3989
3990         crtc = to_intel_crtc(conn_state->crtc);
3991         if (!crtc)
3992                 return 0;
3993
3994         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3995         if (ret)
3996                 return ret;
3997
3998         crtc_state = to_intel_crtc_state(crtc->base.state);
3999
4000         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4001
4002         if (!crtc_state->base.active)
4003                 return 0;
4004
4005         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4006             !crtc_state->hdmi_scrambling)
4007                 return 0;
4008
4009         if (conn_state->commit &&
4010             !try_wait_for_completion(&conn_state->commit->hw_done))
4011                 return 0;
4012
4013         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4014         if (ret < 0) {
4015                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4016                 return 0;
4017         }
4018
4019         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4020             crtc_state->hdmi_high_tmds_clock_ratio &&
4021             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4022             crtc_state->hdmi_scrambling)
4023                 return 0;
4024
4025         /*
4026          * HDMI 2.0 says that one should not send scrambled data
4027          * prior to configuring the sink scrambling, and that
4028          * TMDS clock/data transmission should be suspended when
4029          * changing the TMDS clock rate in the sink. So let's
4030          * just do a full modeset here, even though some sinks
4031          * would be perfectly happy if were to just reconfigure
4032          * the SCDC settings on the fly.
4033          */
4034         return modeset_pipe(&crtc->base, ctx);
4035 }
4036
4037 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4038                               struct intel_connector *connector)
4039 {
4040         struct drm_modeset_acquire_ctx ctx;
4041         bool changed;
4042         int ret;
4043
4044         changed = intel_encoder_hotplug(encoder, connector);
4045
4046         drm_modeset_acquire_init(&ctx, 0);
4047
4048         for (;;) {
4049                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4050                         ret = intel_hdmi_reset_link(encoder, &ctx);
4051                 else
4052                         ret = intel_dp_retrain_link(encoder, &ctx);
4053
4054                 if (ret == -EDEADLK) {
4055                         drm_modeset_backoff(&ctx);
4056                         continue;
4057                 }
4058
4059                 break;
4060         }
4061
4062         drm_modeset_drop_locks(&ctx);
4063         drm_modeset_acquire_fini(&ctx);
4064         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4065
4066         return changed;
4067 }
4068
4069 static struct intel_connector *
4070 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4071 {
4072         struct intel_connector *connector;
4073         enum port port = intel_dig_port->base.port;
4074
4075         connector = intel_connector_alloc();
4076         if (!connector)
4077                 return NULL;
4078
4079         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4080         intel_hdmi_init_connector(intel_dig_port, connector);
4081
4082         return connector;
4083 }
4084
4085 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4086 {
4087         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4088
4089         if (dport->base.port != PORT_A)
4090                 return false;
4091
4092         if (dport->saved_port_bits & DDI_A_4_LANES)
4093                 return false;
4094
4095         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4096          *                     supported configuration
4097          */
4098         if (IS_GEN9_LP(dev_priv))
4099                 return true;
4100
4101         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4102          *             one who does also have a full A/E split called
4103          *             DDI_F what makes DDI_E useless. However for this
4104          *             case let's trust VBT info.
4105          */
4106         if (IS_CANNONLAKE(dev_priv) &&
4107             !intel_bios_is_port_present(dev_priv, PORT_E))
4108                 return true;
4109
4110         return false;
4111 }
4112
4113 static int
4114 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4115 {
4116         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4117         enum port port = intel_dport->base.port;
4118         int max_lanes = 4;
4119
4120         if (INTEL_GEN(dev_priv) >= 11)
4121                 return max_lanes;
4122
4123         if (port == PORT_A || port == PORT_E) {
4124                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4125                         max_lanes = port == PORT_A ? 4 : 0;
4126                 else
4127                         /* Both A and E share 2 lanes */
4128                         max_lanes = 2;
4129         }
4130
4131         /*
4132          * Some BIOS might fail to set this bit on port A if eDP
4133          * wasn't lit up at boot.  Force this bit set when needed
4134          * so we use the proper lane count for our calculations.
4135          */
4136         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4137                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4138                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4139                 max_lanes = 4;
4140         }
4141
4142         return max_lanes;
4143 }
4144
4145 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4146 {
4147         struct ddi_vbt_port_info *port_info =
4148                 &dev_priv->vbt.ddi_port_info[port];
4149         struct intel_digital_port *intel_dig_port;
4150         struct intel_encoder *intel_encoder;
4151         struct drm_encoder *encoder;
4152         bool init_hdmi, init_dp, init_lspcon = false;
4153         enum pipe pipe;
4154
4155         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4156         init_dp = port_info->supports_dp;
4157
4158         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4159                 /*
4160                  * Lspcon device needs to be driven with DP connector
4161                  * with special detection sequence. So make sure DP
4162                  * is initialized before lspcon.
4163                  */
4164                 init_dp = true;
4165                 init_lspcon = true;
4166                 init_hdmi = false;
4167                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4168         }
4169
4170         if (!init_dp && !init_hdmi) {
4171                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4172                               port_name(port));
4173                 return;
4174         }
4175
4176         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4177         if (!intel_dig_port)
4178                 return;
4179
4180         intel_encoder = &intel_dig_port->base;
4181         encoder = &intel_encoder->base;
4182
4183         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4184                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4185
4186         intel_encoder->hotplug = intel_ddi_hotplug;
4187         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4188         intel_encoder->compute_config = intel_ddi_compute_config;
4189         intel_encoder->enable = intel_enable_ddi;
4190         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4191         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4192         intel_encoder->pre_enable = intel_ddi_pre_enable;
4193         intel_encoder->disable = intel_disable_ddi;
4194         intel_encoder->post_disable = intel_ddi_post_disable;
4195         intel_encoder->update_pipe = intel_ddi_update_pipe;
4196         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4197         intel_encoder->get_config = intel_ddi_get_config;
4198         intel_encoder->suspend = intel_ddi_encoder_suspend;
4199         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4200         intel_encoder->type = INTEL_OUTPUT_DDI;
4201         intel_encoder->power_domain = intel_port_to_power_domain(port);
4202         intel_encoder->port = port;
4203         intel_encoder->cloneable = 0;
4204         for_each_pipe(dev_priv, pipe)
4205                 intel_encoder->crtc_mask |= BIT(pipe);
4206
4207         if (INTEL_GEN(dev_priv) >= 11)
4208                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4209                         DDI_BUF_PORT_REVERSAL;
4210         else
4211                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4212                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4213         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4214         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4215         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4216
4217         intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4218                                          !port_info->supports_typec_usb &&
4219                                          !port_info->supports_tbt;
4220
4221         switch (port) {
4222         case PORT_A:
4223                 intel_dig_port->ddi_io_power_domain =
4224                         POWER_DOMAIN_PORT_DDI_A_IO;
4225                 break;
4226         case PORT_B:
4227                 intel_dig_port->ddi_io_power_domain =
4228                         POWER_DOMAIN_PORT_DDI_B_IO;
4229                 break;
4230         case PORT_C:
4231                 intel_dig_port->ddi_io_power_domain =
4232                         POWER_DOMAIN_PORT_DDI_C_IO;
4233                 break;
4234         case PORT_D:
4235                 intel_dig_port->ddi_io_power_domain =
4236                         POWER_DOMAIN_PORT_DDI_D_IO;
4237                 break;
4238         case PORT_E:
4239                 intel_dig_port->ddi_io_power_domain =
4240                         POWER_DOMAIN_PORT_DDI_E_IO;
4241                 break;
4242         case PORT_F:
4243                 intel_dig_port->ddi_io_power_domain =
4244                         POWER_DOMAIN_PORT_DDI_F_IO;
4245                 break;
4246         default:
4247                 MISSING_CASE(port);
4248         }
4249
4250         if (init_dp) {
4251                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4252                         goto err;
4253
4254                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4255         }
4256
4257         /* In theory we don't need the encoder->type check, but leave it just in
4258          * case we have some really bad VBTs... */
4259         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4260                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4261                         goto err;
4262         }
4263
4264         if (init_lspcon) {
4265                 if (lspcon_init(intel_dig_port))
4266                         /* TODO: handle hdmi info frame part */
4267                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4268                                 port_name(port));
4269                 else
4270                         /*
4271                          * LSPCON init faied, but DP init was success, so
4272                          * lets try to drive as DP++ port.
4273                          */
4274                         DRM_ERROR("LSPCON init failed on port %c\n",
4275                                 port_name(port));
4276         }
4277
4278         intel_infoframe_init(intel_dig_port);
4279
4280         if (intel_port_is_tc(dev_priv, port))
4281                 intel_digital_port_connected(intel_encoder);
4282
4283         return;
4284
4285 err:
4286         drm_encoder_cleanup(encoder);
4287         kfree(intel_dig_port);
4288 }