drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = to_i915(dev);
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         u32 tmp;
  73         bool ret;
  74
  75         if (!intel_display_power_get_if_enabled(dev_priv,
  76                                                 encoder->power_domain))
  77                 return false;
  78
  79         ret = false;
  80
  81         tmp = I915_READ(crt->adpa_reg);
  82
  83         if (!(tmp & ADPA_DAC_ENABLE))
  84                 goto out;
  85
  86         if (HAS_PCH_CPT(dev_priv))
  87                 *pipe = PORT_TO_PIPE_CPT(tmp);
  88         else
  89                 *pipe = PORT_TO_PIPE(tmp);
  90
  91         ret = true;
  92 out:
  93         intel_display_power_put(dev_priv, encoder->power_domain);
  94
  95         return ret;
  96 }
  97
  98 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  99 {
 100         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 101         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 102         u32 tmp, flags = 0;
 103
 104         tmp = I915_READ(crt->adpa_reg);
 105
 106         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 107                 flags |= DRM_MODE_FLAG_PHSYNC;
 108         else
 109                 flags |= DRM_MODE_FLAG_NHSYNC;
 110
 111         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 112                 flags |= DRM_MODE_FLAG_PVSYNC;
 113         else
 114                 flags |= DRM_MODE_FLAG_NVSYNC;
 115
 116         return flags;
 117 }
 118
 119 static void intel_crt_get_config(struct intel_encoder *encoder,
 120                                  struct intel_crtc_state *pipe_config)
 121 {
 122         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 123
 124         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 125
 126         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 127 }
 128
 129 static void hsw_crt_get_config(struct intel_encoder *encoder,
 130                                struct intel_crtc_state *pipe_config)
 131 {
 132         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 133
 134         intel_ddi_get_config(encoder, pipe_config);
 135
 136         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 137                                               DRM_MODE_FLAG_NHSYNC |
 138                                               DRM_MODE_FLAG_PVSYNC |
 139                                               DRM_MODE_FLAG_NVSYNC);
 140         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 141
 142         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 143 }
 144
 145 /* Note: The caller is required to filter out dpms modes not supported by the
 146  * platform. */
 147 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 148                                const struct intel_crtc_state *crtc_state,
 149                                int mode)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 152         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 153         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 154         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 155         u32 adpa;
 156
 157         if (INTEL_GEN(dev_priv) >= 5)
 158                 adpa = ADPA_HOTPLUG_BITS;
 159         else
 160                 adpa = 0;
 161
 162         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 163                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 164         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 165                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 166
 167         /* For CPT allow 3 pipe config, for others just use A or B */
 168         if (HAS_PCH_LPT(dev_priv))
 169                 ; /* Those bits don't exist here */
 170         else if (HAS_PCH_CPT(dev_priv))
 171                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 172         else if (crtc->pipe == 0)
 173                 adpa |= ADPA_PIPE_A_SELECT;
 174         else
 175                 adpa |= ADPA_PIPE_B_SELECT;
 176
 177         if (!HAS_PCH_SPLIT(dev_priv))
 178                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 179
 180         switch (mode) {
 181         case DRM_MODE_DPMS_ON:
 182                 adpa |= ADPA_DAC_ENABLE;
 183                 break;
 184         case DRM_MODE_DPMS_STANDBY:
 185                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 186                 break;
 187         case DRM_MODE_DPMS_SUSPEND:
 188                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 189                 break;
 190         case DRM_MODE_DPMS_OFF:
 191                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 192                 break;
 193         }
 194
 195         I915_WRITE(crt->adpa_reg, adpa);
 196 }
 197
 198 static void intel_disable_crt(struct intel_encoder *encoder,
 199                               const struct intel_crtc_state *old_crtc_state,
 200                               const struct drm_connector_state *old_conn_state)
 201 {
 202         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 203 }
 204
 205 static void pch_disable_crt(struct intel_encoder *encoder,
 206                             const struct intel_crtc_state *old_crtc_state,
 207                             const struct drm_connector_state *old_conn_state)
 208 {
 209 }
 210
 211 static void pch_post_disable_crt(struct intel_encoder *encoder,
 212                                  const struct intel_crtc_state *old_crtc_state,
 213                                  const struct drm_connector_state *old_conn_state)
 214 {
 215         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 216 }
 217
 218 static void hsw_disable_crt(struct intel_encoder *encoder,
 219                             const struct intel_crtc_state *old_crtc_state,
 220                             const struct drm_connector_state *old_conn_state)
 221 {
 222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 223
 224         WARN_ON(!old_crtc_state->has_pch_encoder);
 225
 226         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 227 }
 228
 229 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 230                                  const struct intel_crtc_state *old_crtc_state,
 231                                  const struct drm_connector_state *old_conn_state)
 232 {
 233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 234
 235         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 236
 237         lpt_disable_pch_transcoder(dev_priv);
 238         lpt_disable_iclkip(dev_priv);
 239
 240         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 241
 242         WARN_ON(!old_crtc_state->has_pch_encoder);
 243
 244         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 245 }
 246
 247 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 248                                    const struct intel_crtc_state *crtc_state,
 249                                    const struct drm_connector_state *conn_state)
 250 {
 251         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 252
 253         WARN_ON(!crtc_state->has_pch_encoder);
 254
 255         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 256 }
 257
 258 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 259                                const struct intel_crtc_state *crtc_state,
 260                                const struct drm_connector_state *conn_state)
 261 {
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 264         enum pipe pipe = crtc->pipe;
 265
 266         WARN_ON(!crtc_state->has_pch_encoder);
 267
 268         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 269
 270         dev_priv->display.fdi_link_train(crtc, crtc_state);
 271 }
 272
 273 static void hsw_enable_crt(struct intel_encoder *encoder,
 274                            const struct intel_crtc_state *crtc_state,
 275                            const struct drm_connector_state *conn_state)
 276 {
 277         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 278         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 279         enum pipe pipe = crtc->pipe;
 280
 281         WARN_ON(!crtc_state->has_pch_encoder);
 282
 283         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 284
 285         intel_wait_for_vblank(dev_priv, pipe);
 286         intel_wait_for_vblank(dev_priv, pipe);
 287         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 288         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 289 }
 290
 291 static void intel_enable_crt(struct intel_encoder *encoder,
 292                              const struct intel_crtc_state *crtc_state,
 293                              const struct drm_connector_state *conn_state)
 294 {
 295         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 296 }
 297
 298 static enum drm_mode_status
 299 intel_crt_mode_valid(struct drm_connector *connector,
 300                      struct drm_display_mode *mode)
 301 {
 302         struct drm_device *dev = connector->dev;
 303         struct drm_i915_private *dev_priv = to_i915(dev);
 304         int max_dotclk = dev_priv->max_dotclk_freq;
 305         int max_clock;
 306
 307         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 308                 return MODE_NO_DBLESCAN;
 309
 310         if (mode->clock < 25000)
 311                 return MODE_CLOCK_LOW;
 312
 313         if (HAS_PCH_LPT(dev_priv))
 314                 max_clock = 180000;
 315         else if (IS_VALLEYVIEW(dev_priv))
 316                 /*
 317                  * 270 MHz due to current DPLL limits,
 318                  * DAC limit supposedly 355 MHz.
 319                  */
 320                 max_clock = 270000;
 321         else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
 322                 max_clock = 400000;
 323         else
 324                 max_clock = 350000;
 325         if (mode->clock > max_clock)
 326                 return MODE_CLOCK_HIGH;
 327
 328         if (mode->clock > max_dotclk)
 329                 return MODE_CLOCK_HIGH;
 330
 331         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 332         if (HAS_PCH_LPT(dev_priv) &&
 333             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 334                 return MODE_CLOCK_HIGH;
 335
 336         return MODE_OK;
 337 }
 338
 339 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 340                                      struct intel_crtc_state *pipe_config,
 341                                      struct drm_connector_state *conn_state)
 342 {
 343         struct drm_display_mode *adjusted_mode =
 344                 &pipe_config->base.adjusted_mode;
 345
 346         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 347                 return false;
 348
 349         return true;
 350 }
 351
 352 static bool pch_crt_compute_config(struct intel_encoder *encoder,
 353                                    struct intel_crtc_state *pipe_config,
 354                                    struct drm_connector_state *conn_state)
 355 {
 356         struct drm_display_mode *adjusted_mode =
 357                 &pipe_config->base.adjusted_mode;
 358
 359         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 360                 return false;
 361
 362         pipe_config->has_pch_encoder = true;
 363
 364         return true;
 365 }
 366
 367 static bool hsw_crt_compute_config(struct intel_encoder *encoder,
 368                                    struct intel_crtc_state *pipe_config,
 369                                    struct drm_connector_state *conn_state)
 370 {
 371         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 372         struct drm_display_mode *adjusted_mode =
 373                 &pipe_config->base.adjusted_mode;
 374
 375         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 376                 return false;
 377
 378         pipe_config->has_pch_encoder = true;
 379
 380         /* LPT FDI RX only supports 8bpc. */
 381         if (HAS_PCH_LPT(dev_priv)) {
 382                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 383                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 384                         return false;
 385                 }
 386
 387                 pipe_config->pipe_bpp = 24;
 388         }
 389
 390         /* FDI must always be 2.7 GHz */
 391         pipe_config->port_clock = 135000 * 2;
 392
 393         return true;
 394 }
 395
 396 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 397 {
 398         struct drm_device *dev = connector->dev;
 399         struct intel_crt *crt = intel_attached_crt(connector);
 400         struct drm_i915_private *dev_priv = to_i915(dev);
 401         u32 adpa;
 402         bool ret;
 403
 404         /* The first time through, trigger an explicit detection cycle */
 405         if (crt->force_hotplug_required) {
 406                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 407                 u32 save_adpa;
 408
 409                 crt->force_hotplug_required = 0;
 410
 411                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 412                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 413
 414                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 415                 if (turn_off_dac)
 416                         adpa &= ~ADPA_DAC_ENABLE;
 417
 418                 I915_WRITE(crt->adpa_reg, adpa);
 419
 420                 if (intel_wait_for_register(dev_priv,
 421                                             crt->adpa_reg,
 422                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 423                                             1000))
 424                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 425
 426                 if (turn_off_dac) {
 427                         I915_WRITE(crt->adpa_reg, save_adpa);
 428                         POSTING_READ(crt->adpa_reg);
 429                 }
 430         }
 431
 432         /* Check the status to see if both blue and green are on now */
 433         adpa = I915_READ(crt->adpa_reg);
 434         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 435                 ret = true;
 436         else
 437                 ret = false;
 438         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 439
 440         return ret;
 441 }
 442
 443 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 444 {
 445         struct drm_device *dev = connector->dev;
 446         struct intel_crt *crt = intel_attached_crt(connector);
 447         struct drm_i915_private *dev_priv = to_i915(dev);
 448         bool reenable_hpd;
 449         u32 adpa;
 450         bool ret;
 451         u32 save_adpa;
 452
 453         /*
 454          * Doing a force trigger causes a hpd interrupt to get sent, which can
 455          * get us stuck in a loop if we're polling:
 456          *  - We enable power wells and reset the ADPA
 457          *  - output_poll_exec does force probe on VGA, triggering a hpd
 458          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 459          *  - output_poll_exec shuts off the ADPA, unlocks
 460          *    dev->mode_config.mutex
 461          *  - HPD handler runs, resets ADPA and brings us back to the start
 462          *
 463          * Just disable HPD interrupts here to prevent this
 464          */
 465         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 466
 467         save_adpa = adpa = I915_READ(crt->adpa_reg);
 468         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 469
 470         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 471
 472         I915_WRITE(crt->adpa_reg, adpa);
 473
 474         if (intel_wait_for_register(dev_priv,
 475                                     crt->adpa_reg,
 476                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 477                                     1000)) {
 478                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 479                 I915_WRITE(crt->adpa_reg, save_adpa);
 480         }
 481
 482         /* Check the status to see if both blue and green are on now */
 483         adpa = I915_READ(crt->adpa_reg);
 484         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 485                 ret = true;
 486         else
 487                 ret = false;
 488
 489         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 490
 491         if (reenable_hpd)
 492                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 493
 494         return ret;
 495 }
 496
 497 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 498 {
 499         struct drm_device *dev = connector->dev;
 500         struct drm_i915_private *dev_priv = to_i915(dev);
 501         u32 stat;
 502         bool ret = false;
 503         int i, tries = 0;
 504
 505         if (HAS_PCH_SPLIT(dev_priv))
 506                 return intel_ironlake_crt_detect_hotplug(connector);
 507
 508         if (IS_VALLEYVIEW(dev_priv))
 509                 return valleyview_crt_detect_hotplug(connector);
 510
 511         /*
 512          * On 4 series desktop, CRT detect sequence need to be done twice
 513          * to get a reliable result.
 514          */
 515
 516         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv))
 517                 tries = 2;
 518         else
 519                 tries = 1;
 520
 521         for (i = 0; i < tries ; i++) {
 522                 /* turn on the FORCE_DETECT */
 523                 i915_hotplug_interrupt_update(dev_priv,
 524                                               CRT_HOTPLUG_FORCE_DETECT,
 525                                               CRT_HOTPLUG_FORCE_DETECT);
 526                 /* wait for FORCE_DETECT to go off */
 527                 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
 528                                             CRT_HOTPLUG_FORCE_DETECT, 0,
 529                                             1000))
 530                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 531         }
 532
 533         stat = I915_READ(PORT_HOTPLUG_STAT);
 534         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 535                 ret = true;
 536
 537         /* clear the interrupt we just generated, if any */
 538         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 539
 540         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 541
 542         return ret;
 543 }
 544
 545 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 546                                 struct i2c_adapter *i2c)
 547 {
 548         struct edid *edid;
 549
 550         edid = drm_get_edid(connector, i2c);
 551
 552         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 553                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 554                 intel_gmbus_force_bit(i2c, true);
 555                 edid = drm_get_edid(connector, i2c);
 556                 intel_gmbus_force_bit(i2c, false);
 557         }
 558
 559         return edid;
 560 }
 561
 562 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 563 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 564                                 struct i2c_adapter *adapter)
 565 {
 566         struct edid *edid;
 567         int ret;
 568
 569         edid = intel_crt_get_edid(connector, adapter);
 570         if (!edid)
 571                 return 0;
 572
 573         ret = intel_connector_update_modes(connector, edid);
 574         kfree(edid);
 575
 576         return ret;
 577 }
 578
 579 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 580 {
 581         struct intel_crt *crt = intel_attached_crt(connector);
 582         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 583         struct edid *edid;
 584         struct i2c_adapter *i2c;
 585         bool ret = false;
 586
 587         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 588
 589         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 590         edid = intel_crt_get_edid(connector, i2c);
 591
 592         if (edid) {
 593                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 594
 595                 /*
 596                  * This may be a DVI-I connector with a shared DDC
 597                  * link between analog and digital outputs, so we
 598                  * have to check the EDID input spec of the attached device.
 599                  */
 600                 if (!is_digital) {
 601                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 602                         ret = true;
 603                 } else {
 604                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 605                 }
 606         } else {
 607                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 608         }
 609
 610         kfree(edid);
 611
 612         return ret;
 613 }
 614
 615 static enum drm_connector_status
 616 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
 617 {
 618         struct drm_device *dev = crt->base.base.dev;
 619         struct drm_i915_private *dev_priv = to_i915(dev);
 620         uint32_t save_bclrpat;
 621         uint32_t save_vtotal;
 622         uint32_t vtotal, vactive;
 623         uint32_t vsample;
 624         uint32_t vblank, vblank_start, vblank_end;
 625         uint32_t dsl;
 626         i915_reg_t bclrpat_reg, vtotal_reg,
 627                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 628         uint8_t st00;
 629         enum drm_connector_status status;
 630
 631         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 632
 633         bclrpat_reg = BCLRPAT(pipe);
 634         vtotal_reg = VTOTAL(pipe);
 635         vblank_reg = VBLANK(pipe);
 636         vsync_reg = VSYNC(pipe);
 637         pipeconf_reg = PIPECONF(pipe);
 638         pipe_dsl_reg = PIPEDSL(pipe);
 639
 640         save_bclrpat = I915_READ(bclrpat_reg);
 641         save_vtotal = I915_READ(vtotal_reg);
 642         vblank = I915_READ(vblank_reg);
 643
 644         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 645         vactive = (save_vtotal & 0x7ff) + 1;
 646
 647         vblank_start = (vblank & 0xfff) + 1;
 648         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 649
 650         /* Set the border color to purple. */
 651         I915_WRITE(bclrpat_reg, 0x500050);
 652
 653         if (!IS_GEN2(dev_priv)) {
 654                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 655                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 656                 POSTING_READ(pipeconf_reg);
 657                 /* Wait for next Vblank to substitue
 658                  * border color for Color info */
 659                 intel_wait_for_vblank(dev_priv, pipe);
 660                 st00 = I915_READ8(_VGA_MSR_WRITE);
 661                 status = ((st00 & (1 << 4)) != 0) ?
 662                         connector_status_connected :
 663                         connector_status_disconnected;
 664
 665                 I915_WRITE(pipeconf_reg, pipeconf);
 666         } else {
 667                 bool restore_vblank = false;
 668                 int count, detect;
 669
 670                 /*
 671                 * If there isn't any border, add some.
 672                 * Yes, this will flicker
 673                 */
 674                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 675                         uint32_t vsync = I915_READ(vsync_reg);
 676                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 677
 678                         vblank_start = vsync_start;
 679                         I915_WRITE(vblank_reg,
 680                                    (vblank_start - 1) |
 681                                    ((vblank_end - 1) << 16));
 682                         restore_vblank = true;
 683                 }
 684                 /* sample in the vertical border, selecting the larger one */
 685                 if (vblank_start - vactive >= vtotal - vblank_end)
 686                         vsample = (vblank_start + vactive) >> 1;
 687                 else
 688                         vsample = (vtotal + vblank_end) >> 1;
 689
 690                 /*
 691                  * Wait for the border to be displayed
 692                  */
 693                 while (I915_READ(pipe_dsl_reg) >= vactive)
 694                         ;
 695                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 696                         ;
 697                 /*
 698                  * Watch ST00 for an entire scanline
 699                  */
 700                 detect = 0;
 701                 count = 0;
 702                 do {
 703                         count++;
 704                         /* Read the ST00 VGA status register */
 705                         st00 = I915_READ8(_VGA_MSR_WRITE);
 706                         if (st00 & (1 << 4))
 707                                 detect++;
 708                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 709
 710                 /* restore vblank if necessary */
 711                 if (restore_vblank)
 712                         I915_WRITE(vblank_reg, vblank);
 713                 /*
 714                  * If more than 3/4 of the scanline detected a monitor,
 715                  * then it is assumed to be present. This works even on i830,
 716                  * where there isn't any way to force the border color across
 717                  * the screen
 718                  */
 719                 status = detect * 4 > count * 3 ?
 720                          connector_status_connected :
 721                          connector_status_disconnected;
 722         }
 723
 724         /* Restore previous settings */
 725         I915_WRITE(bclrpat_reg, save_bclrpat);
 726
 727         return status;
 728 }
 729
 730 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 731 {
 732         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 733         return 1;
 734 }
 735
 736 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 737         {
 738                 .callback = intel_spurious_crt_detect_dmi_callback,
 739                 .ident = "ACER ZGB",
 740                 .matches = {
 741                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 742                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 743                 },
 744         },
 745         {
 746                 .callback = intel_spurious_crt_detect_dmi_callback,
 747                 .ident = "Intel DZ77BH-55K",
 748                 .matches = {
 749                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 750                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 751                 },
 752         },
 753         { }
 754 };
 755
 756 static int
 757 intel_crt_detect(struct drm_connector *connector,
 758                  struct drm_modeset_acquire_ctx *ctx,
 759                  bool force)
 760 {
 761         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 762         struct intel_crt *crt = intel_attached_crt(connector);
 763         struct intel_encoder *intel_encoder = &crt->base;
 764         int status, ret;
 765         struct intel_load_detect_pipe tmp;
 766
 767         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 768                       connector->base.id, connector->name,
 769                       force);
 770
 771         if (i915_modparams.load_detect_test) {
 772                 intel_display_power_get(dev_priv, intel_encoder->power_domain);
 773                 goto load_detect;
 774         }
 775
 776         /* Skip machines without VGA that falsely report hotplug events */
 777         if (dmi_check_system(intel_spurious_crt_detect))
 778                 return connector_status_disconnected;
 779
 780         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 781
 782         if (I915_HAS_HOTPLUG(dev_priv)) {
 783                 /* We can not rely on the HPD pin always being correctly wired
 784                  * up, for example many KVM do not pass it through, and so
 785                  * only trust an assertion that the monitor is connected.
 786                  */
 787                 if (intel_crt_detect_hotplug(connector)) {
 788                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 789                         status = connector_status_connected;
 790                         goto out;
 791                 } else
 792                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 793         }
 794
 795         if (intel_crt_detect_ddc(connector)) {
 796                 status = connector_status_connected;
 797                 goto out;
 798         }
 799
 800         /* Load detection is broken on HPD capable machines. Whoever wants a
 801          * broken monitor (without edid) to work behind a broken kvm (that fails
 802          * to have the right resistors for HP detection) needs to fix this up.
 803          * For now just bail out. */
 804         if (I915_HAS_HOTPLUG(dev_priv)) {
 805                 status = connector_status_disconnected;
 806                 goto out;
 807         }
 808
 809 load_detect:
 810         if (!force) {
 811                 status = connector->status;
 812                 goto out;
 813         }
 814
 815         /* for pre-945g platforms use load detect */
 816         ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
 817         if (ret > 0) {
 818                 if (intel_crt_detect_ddc(connector))
 819                         status = connector_status_connected;
 820                 else if (INTEL_GEN(dev_priv) < 4)
 821                         status = intel_crt_load_detect(crt,
 822                                 to_intel_crtc(connector->state->crtc)->pipe);
 823                 else if (i915_modparams.load_detect_test)
 824                         status = connector_status_disconnected;
 825                 else
 826                         status = connector_status_unknown;
 827                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 828         } else if (ret == 0) {
 829                 status = connector_status_unknown;
 830         } else {
 831                 status = ret;
 832         }
 833
 834 out:
 835         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 836         return status;
 837 }
 838
 839 static void intel_crt_destroy(struct drm_connector *connector)
 840 {
 841         drm_connector_cleanup(connector);
 842         kfree(connector);
 843 }
 844
 845 static int intel_crt_get_modes(struct drm_connector *connector)
 846 {
 847         struct drm_device *dev = connector->dev;
 848         struct drm_i915_private *dev_priv = to_i915(dev);
 849         struct intel_crt *crt = intel_attached_crt(connector);
 850         struct intel_encoder *intel_encoder = &crt->base;
 851         int ret;
 852         struct i2c_adapter *i2c;
 853
 854         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 855
 856         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 857         ret = intel_crt_ddc_get_modes(connector, i2c);
 858         if (ret || !IS_G4X(dev_priv))
 859                 goto out;
 860
 861         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 862         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 863         ret = intel_crt_ddc_get_modes(connector, i2c);
 864
 865 out:
 866         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 867
 868         return ret;
 869 }
 870
 871 void intel_crt_reset(struct drm_encoder *encoder)
 872 {
 873         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 874         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 875
 876         if (INTEL_GEN(dev_priv) >= 5) {
 877                 u32 adpa;
 878
 879                 adpa = I915_READ(crt->adpa_reg);
 880                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 881                 adpa |= ADPA_HOTPLUG_BITS;
 882                 I915_WRITE(crt->adpa_reg, adpa);
 883                 POSTING_READ(crt->adpa_reg);
 884
 885                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 886                 crt->force_hotplug_required = 1;
 887         }
 888
 889 }
 890
 891 /*
 892  * Routines for controlling stuff on the analog port
 893  */
 894
 895 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 896         .fill_modes = drm_helper_probe_single_connector_modes,
 897         .late_register = intel_connector_register,
 898         .early_unregister = intel_connector_unregister,
 899         .destroy = intel_crt_destroy,
 900         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 901         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 902 };
 903
 904 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 905         .detect_ctx = intel_crt_detect,
 906         .mode_valid = intel_crt_mode_valid,
 907         .get_modes = intel_crt_get_modes,
 908 };
 909
 910 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 911         .reset = intel_crt_reset,
 912         .destroy = intel_encoder_destroy,
 913 };
 914
 915 void intel_crt_init(struct drm_i915_private *dev_priv)
 916 {
 917         struct drm_connector *connector;
 918         struct intel_crt *crt;
 919         struct intel_connector *intel_connector;
 920         i915_reg_t adpa_reg;
 921         u32 adpa;
 922
 923         if (HAS_PCH_SPLIT(dev_priv))
 924                 adpa_reg = PCH_ADPA;
 925         else if (IS_VALLEYVIEW(dev_priv))
 926                 adpa_reg = VLV_ADPA;
 927         else
 928                 adpa_reg = ADPA;
 929
 930         adpa = I915_READ(adpa_reg);
 931         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 932                 /*
 933                  * On some machines (some IVB at least) CRT can be
 934                  * fused off, but there's no known fuse bit to
 935                  * indicate that. On these machine the ADPA register
 936                  * works normally, except the DAC enable bit won't
 937                  * take. So the only way to tell is attempt to enable
 938                  * it and see what happens.
 939                  */
 940                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 941                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 942                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 943                         return;
 944                 I915_WRITE(adpa_reg, adpa);
 945         }
 946
 947         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 948         if (!crt)
 949                 return;
 950
 951         intel_connector = intel_connector_alloc();
 952         if (!intel_connector) {
 953                 kfree(crt);
 954                 return;
 955         }
 956
 957         connector = &intel_connector->base;
 958         crt->connector = intel_connector;
 959         drm_connector_init(&dev_priv->drm, &intel_connector->base,
 960                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 961
 962         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
 963                          DRM_MODE_ENCODER_DAC, "CRT");
 964
 965         intel_connector_attach_encoder(intel_connector, &crt->base);
 966
 967         crt->base.type = INTEL_OUTPUT_ANALOG;
 968         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 969         if (IS_I830(dev_priv))
 970                 crt->base.crtc_mask = (1 << 0);
 971         else
 972                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 973
 974         if (IS_GEN2(dev_priv))
 975                 connector->interlace_allowed = 0;
 976         else
 977                 connector->interlace_allowed = 1;
 978         connector->doublescan_allowed = 0;
 979
 980         crt->adpa_reg = adpa_reg;
 981
 982         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
 983
 984         if (I915_HAS_HOTPLUG(dev_priv) &&
 985             !dmi_check_system(intel_spurious_crt_detect)) {
 986                 crt->base.hpd_pin = HPD_CRT;
 987                 crt->base.hotplug = intel_encoder_hotplug;
 988         }
 989
 990         if (HAS_DDI(dev_priv)) {
 991                 crt->base.port = PORT_E;
 992                 crt->base.get_config = hsw_crt_get_config;
 993                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 994                 crt->base.compute_config = hsw_crt_compute_config;
 995                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
 996                 crt->base.pre_enable = hsw_pre_enable_crt;
 997                 crt->base.enable = hsw_enable_crt;
 998                 crt->base.disable = hsw_disable_crt;
 999                 crt->base.post_disable = hsw_post_disable_crt;
1000         } else {
1001                 if (HAS_PCH_SPLIT(dev_priv)) {
1002                         crt->base.compute_config = pch_crt_compute_config;
1003                         crt->base.disable = pch_disable_crt;
1004                         crt->base.post_disable = pch_post_disable_crt;
1005                 } else {
1006                         crt->base.compute_config = intel_crt_compute_config;
1007                         crt->base.disable = intel_disable_crt;
1008                 }
1009                 crt->base.port = PORT_NONE;
1010                 crt->base.get_config = intel_crt_get_config;
1011                 crt->base.get_hw_state = intel_crt_get_hw_state;
1012                 crt->base.enable = intel_enable_crt;
1013         }
1014         intel_connector->get_hw_state = intel_connector_get_hw_state;
1015
1016         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1017
1018         if (!I915_HAS_HOTPLUG(dev_priv))
1019                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1020
1021         /*
1022          * Configure the automatic hotplug detection stuff
1023          */
1024         crt->force_hotplug_required = 0;
1025
1026         /*
1027          * TODO: find a proper way to discover whether we need to set the the
1028          * polarity and link reversal bits or not, instead of relying on the
1029          * BIOS.
1030          */
1031         if (HAS_PCH_LPT(dev_priv)) {
1032                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1033                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1034
1035                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1036         }
1037
1038         intel_crt_reset(&crt->base.base);
1039 }