drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 421 {
 422         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 423                 333333 : 320000;
 424
 425         /*
 426          * We seem to get an unstable or solid color picture at 200MHz.
 427          * Not sure what's wrong. For now use 200MHz only when all pipes
 428          * are off.
 429          */
 430         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 431                 return 400000;
 432         else if (min_cdclk > 266667)
 433                 return freq_320;
 434         else if (min_cdclk > 0)
 435                 return 266667;
 436         else
 437                 return 200000;
 438 }
 439
 440 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 441                           struct intel_cdclk_state *cdclk_state)
 442 {
 443         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 444         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 445                                                CCK_DISPLAY_CLOCK_CONTROL,
 446                                                cdclk_state->vco);
 447 }
 448
 449 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 450 {
 451         unsigned int credits, default_credits;
 452
 453         if (IS_CHERRYVIEW(dev_priv))
 454                 default_credits = PFI_CREDIT(12);
 455         else
 456                 default_credits = PFI_CREDIT(8);
 457
 458         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 459                 /* CHV suggested value is 31 or 63 */
 460                 if (IS_CHERRYVIEW(dev_priv))
 461                         credits = PFI_CREDIT_63;
 462                 else
 463                         credits = PFI_CREDIT(15);
 464         } else {
 465                 credits = default_credits;
 466         }
 467
 468         /*
 469          * WA - write default credits before re-programming
 470          * FIXME: should we also set the resend bit here?
 471          */
 472         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 473                    default_credits);
 474
 475         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 476                    credits | PFI_CREDIT_RESEND);
 477
 478         /*
 479          * FIXME is this guaranteed to clear
 480          * immediately or should we poll for it?
 481          */
 482         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 483 }
 484
 485 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 486                           const struct intel_cdclk_state *cdclk_state)
 487 {
 488         int cdclk = cdclk_state->cdclk;
 489         u32 val, cmd;
 490
 491         /* There are cases where we can end up here with power domains
 492          * off and a CDCLK frequency other than the minimum, like when
 493          * issuing a modeset without actually changing any display after
 494          * a system suspend.  So grab the PIPE-A domain, which covers
 495          * the HW blocks needed for the following programming.
 496          */
 497         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 498
 499         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 500                 cmd = 2;
 501         else if (cdclk == 266667)
 502                 cmd = 1;
 503         else
 504                 cmd = 0;
 505
 506         mutex_lock(&dev_priv->pcu_lock);
 507         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 508         val &= ~DSPFREQGUAR_MASK;
 509         val |= (cmd << DSPFREQGUAR_SHIFT);
 510         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 511         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 512                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 513                      50)) {
 514                 DRM_ERROR("timed out waiting for CDclk change\n");
 515         }
 516         mutex_unlock(&dev_priv->pcu_lock);
 517
 518         mutex_lock(&dev_priv->sb_lock);
 519
 520         if (cdclk == 400000) {
 521                 u32 divider;
 522
 523                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 524                                             cdclk) - 1;
 525
 526                 /* adjust cdclk divider */
 527                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 528                 val &= ~CCK_FREQUENCY_VALUES;
 529                 val |= divider;
 530                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 531
 532                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 533                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 534                              50))
 535                         DRM_ERROR("timed out waiting for CDclk change\n");
 536         }
 537
 538         /* adjust self-refresh exit latency value */
 539         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 540         val &= ~0x7f;
 541
 542         /*
 543          * For high bandwidth configs, we set a higher latency in the bunit
 544          * so that the core display fetch happens in time to avoid underruns.
 545          */
 546         if (cdclk == 400000)
 547                 val |= 4500 / 250; /* 4.5 usec */
 548         else
 549                 val |= 3000 / 250; /* 3.0 usec */
 550         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 551
 552         mutex_unlock(&dev_priv->sb_lock);
 553
 554         intel_update_cdclk(dev_priv);
 555
 556         vlv_program_pfi_credits(dev_priv);
 557
 558         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 559 }
 560
 561 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 562                           const struct intel_cdclk_state *cdclk_state)
 563 {
 564         int cdclk = cdclk_state->cdclk;
 565         u32 val, cmd;
 566
 567         switch (cdclk) {
 568         case 333333:
 569         case 320000:
 570         case 266667:
 571         case 200000:
 572                 break;
 573         default:
 574                 MISSING_CASE(cdclk);
 575                 return;
 576         }
 577
 578         /* There are cases where we can end up here with power domains
 579          * off and a CDCLK frequency other than the minimum, like when
 580          * issuing a modeset without actually changing any display after
 581          * a system suspend.  So grab the PIPE-A domain, which covers
 582          * the HW blocks needed for the following programming.
 583          */
 584         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 585
 586         /*
 587          * Specs are full of misinformation, but testing on actual
 588          * hardware has shown that we just need to write the desired
 589          * CCK divider into the Punit register.
 590          */
 591         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 592
 593         mutex_lock(&dev_priv->pcu_lock);
 594         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 595         val &= ~DSPFREQGUAR_MASK_CHV;
 596         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 597         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 598         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 599                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 600                      50)) {
 601                 DRM_ERROR("timed out waiting for CDclk change\n");
 602         }
 603         mutex_unlock(&dev_priv->pcu_lock);
 604
 605         intel_update_cdclk(dev_priv);
 606
 607         vlv_program_pfi_credits(dev_priv);
 608
 609         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 610 }
 611
 612 static int bdw_calc_cdclk(int min_cdclk)
 613 {
 614         if (min_cdclk > 540000)
 615                 return 675000;
 616         else if (min_cdclk > 450000)
 617                 return 540000;
 618         else if (min_cdclk > 337500)
 619                 return 450000;
 620         else
 621                 return 337500;
 622 }
 623
 624 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 625                           struct intel_cdclk_state *cdclk_state)
 626 {
 627         uint32_t lcpll = I915_READ(LCPLL_CTL);
 628         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 629
 630         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 631                 cdclk_state->cdclk = 800000;
 632         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 633                 cdclk_state->cdclk = 450000;
 634         else if (freq == LCPLL_CLK_FREQ_450)
 635                 cdclk_state->cdclk = 450000;
 636         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 637                 cdclk_state->cdclk = 540000;
 638         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 639                 cdclk_state->cdclk = 337500;
 640         else
 641                 cdclk_state->cdclk = 675000;
 642 }
 643
 644 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 645                           const struct intel_cdclk_state *cdclk_state)
 646 {
 647         int cdclk = cdclk_state->cdclk;
 648         uint32_t val, data;
 649         int ret;
 650
 651         if (WARN((I915_READ(LCPLL_CTL) &
 652                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 653                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 654                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 655                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 656                  "trying to change cdclk frequency with cdclk not enabled\n"))
 657                 return;
 658
 659         mutex_lock(&dev_priv->pcu_lock);
 660         ret = sandybridge_pcode_write(dev_priv,
 661                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 662         mutex_unlock(&dev_priv->pcu_lock);
 663         if (ret) {
 664                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 665                 return;
 666         }
 667
 668         val = I915_READ(LCPLL_CTL);
 669         val |= LCPLL_CD_SOURCE_FCLK;
 670         I915_WRITE(LCPLL_CTL, val);
 671
 672         /*
 673          * According to the spec, it should be enough to poll for this 1 us.
 674          * However, extensive testing shows that this can take longer.
 675          */
 676         if (wait_for_us(I915_READ(LCPLL_CTL) &
 677                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 678                 DRM_ERROR("Switching to FCLK failed\n");
 679
 680         val = I915_READ(LCPLL_CTL);
 681         val &= ~LCPLL_CLK_FREQ_MASK;
 682
 683         switch (cdclk) {
 684         case 450000:
 685                 val |= LCPLL_CLK_FREQ_450;
 686                 data = 0;
 687                 break;
 688         case 540000:
 689                 val |= LCPLL_CLK_FREQ_54O_BDW;
 690                 data = 1;
 691                 break;
 692         case 337500:
 693                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 694                 data = 2;
 695                 break;
 696         case 675000:
 697                 val |= LCPLL_CLK_FREQ_675_BDW;
 698                 data = 3;
 699                 break;
 700         default:
 701                 WARN(1, "invalid cdclk frequency\n");
 702                 return;
 703         }
 704
 705         I915_WRITE(LCPLL_CTL, val);
 706
 707         val = I915_READ(LCPLL_CTL);
 708         val &= ~LCPLL_CD_SOURCE_FCLK;
 709         I915_WRITE(LCPLL_CTL, val);
 710
 711         if (wait_for_us((I915_READ(LCPLL_CTL) &
 712                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 713                 DRM_ERROR("Switching back to LCPLL failed\n");
 714
 715         mutex_lock(&dev_priv->pcu_lock);
 716         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
 717         mutex_unlock(&dev_priv->pcu_lock);
 718
 719         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 720
 721         intel_update_cdclk(dev_priv);
 722
 723         WARN(cdclk != dev_priv->cdclk.hw.cdclk,
 724              "cdclk requested %d kHz but got %d kHz\n",
 725              cdclk, dev_priv->cdclk.hw.cdclk);
 726 }
 727
 728 static int skl_calc_cdclk(int min_cdclk, int vco)
 729 {
 730         if (vco == 8640000) {
 731                 if (min_cdclk > 540000)
 732                         return 617143;
 733                 else if (min_cdclk > 432000)
 734                         return 540000;
 735                 else if (min_cdclk > 308571)
 736                         return 432000;
 737                 else
 738                         return 308571;
 739         } else {
 740                 if (min_cdclk > 540000)
 741                         return 675000;
 742                 else if (min_cdclk > 450000)
 743                         return 540000;
 744                 else if (min_cdclk > 337500)
 745                         return 450000;
 746                 else
 747                         return 337500;
 748         }
 749 }
 750
 751 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 752                              struct intel_cdclk_state *cdclk_state)
 753 {
 754         u32 val;
 755
 756         cdclk_state->ref = 24000;
 757         cdclk_state->vco = 0;
 758
 759         val = I915_READ(LCPLL1_CTL);
 760         if ((val & LCPLL_PLL_ENABLE) == 0)
 761                 return;
 762
 763         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 764                 return;
 765
 766         val = I915_READ(DPLL_CTRL1);
 767
 768         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 769                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 770                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 771                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 772                 return;
 773
 774         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 775         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 776         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 777         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 778         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 779                 cdclk_state->vco = 8100000;
 780                 break;
 781         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 782         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 783                 cdclk_state->vco = 8640000;
 784                 break;
 785         default:
 786                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 787                 break;
 788         }
 789 }
 790
 791 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 792                           struct intel_cdclk_state *cdclk_state)
 793 {
 794         u32 cdctl;
 795
 796         skl_dpll0_update(dev_priv, cdclk_state);
 797
 798         cdclk_state->cdclk = cdclk_state->ref;
 799
 800         if (cdclk_state->vco == 0)
 801                 return;
 802
 803         cdctl = I915_READ(CDCLK_CTL);
 804
 805         if (cdclk_state->vco == 8640000) {
 806                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 807                 case CDCLK_FREQ_450_432:
 808                         cdclk_state->cdclk = 432000;
 809                         break;
 810                 case CDCLK_FREQ_337_308:
 811                         cdclk_state->cdclk = 308571;
 812                         break;
 813                 case CDCLK_FREQ_540:
 814                         cdclk_state->cdclk = 540000;
 815                         break;
 816                 case CDCLK_FREQ_675_617:
 817                         cdclk_state->cdclk = 617143;
 818                         break;
 819                 default:
 820                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 821                         break;
 822                 }
 823         } else {
 824                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 825                 case CDCLK_FREQ_450_432:
 826                         cdclk_state->cdclk = 450000;
 827                         break;
 828                 case CDCLK_FREQ_337_308:
 829                         cdclk_state->cdclk = 337500;
 830                         break;
 831                 case CDCLK_FREQ_540:
 832                         cdclk_state->cdclk = 540000;
 833                         break;
 834                 case CDCLK_FREQ_675_617:
 835                         cdclk_state->cdclk = 675000;
 836                         break;
 837                 default:
 838                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 839                         break;
 840                 }
 841         }
 842 }
 843
 844 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 845 static int skl_cdclk_decimal(int cdclk)
 846 {
 847         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 848 }
 849
 850 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 851                                         int vco)
 852 {
 853         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 854
 855         dev_priv->skl_preferred_vco_freq = vco;
 856
 857         if (changed)
 858                 intel_update_max_cdclk(dev_priv);
 859 }
 860
 861 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 862 {
 863         int min_cdclk = skl_calc_cdclk(0, vco);
 864         u32 val;
 865
 866         WARN_ON(vco != 8100000 && vco != 8640000);
 867
 868         /* select the minimum CDCLK before enabling DPLL 0 */
 869         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
 870         I915_WRITE(CDCLK_CTL, val);
 871         POSTING_READ(CDCLK_CTL);
 872
 873         /*
 874          * We always enable DPLL0 with the lowest link rate possible, but still
 875          * taking into account the VCO required to operate the eDP panel at the
 876          * desired frequency. The usual DP link rates operate with a VCO of
 877          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 878          * The modeset code is responsible for the selection of the exact link
 879          * rate later on, with the constraint of choosing a frequency that
 880          * works with vco.
 881          */
 882         val = I915_READ(DPLL_CTRL1);
 883
 884         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 885                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 886         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 887         if (vco == 8640000)
 888                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 889                                             SKL_DPLL0);
 890         else
 891                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 892                                             SKL_DPLL0);
 893
 894         I915_WRITE(DPLL_CTRL1, val);
 895         POSTING_READ(DPLL_CTRL1);
 896
 897         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 898
 899         if (intel_wait_for_register(dev_priv,
 900                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 901                                     5))
 902                 DRM_ERROR("DPLL0 not locked\n");
 903
 904         dev_priv->cdclk.hw.vco = vco;
 905
 906         /* We'll want to keep using the current vco from now on. */
 907         skl_set_preferred_cdclk_vco(dev_priv, vco);
 908 }
 909
 910 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 911 {
 912         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 913         if (intel_wait_for_register(dev_priv,
 914                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 915                                    1))
 916                 DRM_ERROR("Couldn't disable DPLL0\n");
 917
 918         dev_priv->cdclk.hw.vco = 0;
 919 }
 920
 921 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 922                           const struct intel_cdclk_state *cdclk_state)
 923 {
 924         int cdclk = cdclk_state->cdclk;
 925         int vco = cdclk_state->vco;
 926         u32 freq_select, pcu_ack;
 927         int ret;
 928
 929         WARN_ON((cdclk == 24000) != (vco == 0));
 930
 931         mutex_lock(&dev_priv->pcu_lock);
 932         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 933                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 934                                 SKL_CDCLK_READY_FOR_CHANGE,
 935                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 936         mutex_unlock(&dev_priv->pcu_lock);
 937         if (ret) {
 938                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
 939                           ret);
 940                 return;
 941         }
 942
 943         /* set CDCLK_CTL */
 944         switch (cdclk) {
 945         case 450000:
 946         case 432000:
 947                 freq_select = CDCLK_FREQ_450_432;
 948                 pcu_ack = 1;
 949                 break;
 950         case 540000:
 951                 freq_select = CDCLK_FREQ_540;
 952                 pcu_ack = 2;
 953                 break;
 954         case 308571:
 955         case 337500:
 956         default:
 957                 freq_select = CDCLK_FREQ_337_308;
 958                 pcu_ack = 0;
 959                 break;
 960         case 617143:
 961         case 675000:
 962                 freq_select = CDCLK_FREQ_675_617;
 963                 pcu_ack = 3;
 964                 break;
 965         }
 966
 967         if (dev_priv->cdclk.hw.vco != 0 &&
 968             dev_priv->cdclk.hw.vco != vco)
 969                 skl_dpll0_disable(dev_priv);
 970
 971         if (dev_priv->cdclk.hw.vco != vco)
 972                 skl_dpll0_enable(dev_priv, vco);
 973
 974         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
 975         POSTING_READ(CDCLK_CTL);
 976
 977         /* inform PCU of the change */
 978         mutex_lock(&dev_priv->pcu_lock);
 979         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
 980         mutex_unlock(&dev_priv->pcu_lock);
 981
 982         intel_update_cdclk(dev_priv);
 983 }
 984
 985 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 986 {
 987         uint32_t cdctl, expected;
 988
 989         /*
 990          * check if the pre-os initialized the display
 991          * There is SWF18 scratchpad register defined which is set by the
 992          * pre-os which can be used by the OS drivers to check the status
 993          */
 994         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
 995                 goto sanitize;
 996
 997         intel_update_cdclk(dev_priv);
 998         /* Is PLL enabled and locked ? */
 999         if (dev_priv->cdclk.hw.vco == 0 ||
1000             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1001                 goto sanitize;
1002
1003         /* DPLL okay; verify the cdclock
1004          *
1005          * Noticed in some instances that the freq selection is correct but
1006          * decimal part is programmed wrong from BIOS where pre-os does not
1007          * enable display. Verify the same as well.
1008          */
1009         cdctl = I915_READ(CDCLK_CTL);
1010         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1011                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1012         if (cdctl == expected)
1013                 /* All well; nothing to sanitize */
1014                 return;
1015
1016 sanitize:
1017         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1018
1019         /* force cdclk programming */
1020         dev_priv->cdclk.hw.cdclk = 0;
1021         /* force full PLL disable + enable */
1022         dev_priv->cdclk.hw.vco = -1;
1023 }
1024
1025 /**
1026  * skl_init_cdclk - Initialize CDCLK on SKL
1027  * @dev_priv: i915 device
1028  *
1029  * Initialize CDCLK for SKL and derivatives. This is generally
1030  * done only during the display core initialization sequence,
1031  * after which the DMC will take care of turning CDCLK off/on
1032  * as needed.
1033  */
1034 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1035 {
1036         struct intel_cdclk_state cdclk_state;
1037
1038         skl_sanitize_cdclk(dev_priv);
1039
1040         if (dev_priv->cdclk.hw.cdclk != 0 &&
1041             dev_priv->cdclk.hw.vco != 0) {
1042                 /*
1043                  * Use the current vco as our initial
1044                  * guess as to what the preferred vco is.
1045                  */
1046                 if (dev_priv->skl_preferred_vco_freq == 0)
1047                         skl_set_preferred_cdclk_vco(dev_priv,
1048                                                     dev_priv->cdclk.hw.vco);
1049                 return;
1050         }
1051
1052         cdclk_state = dev_priv->cdclk.hw;
1053
1054         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1055         if (cdclk_state.vco == 0)
1056                 cdclk_state.vco = 8100000;
1057         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1058
1059         skl_set_cdclk(dev_priv, &cdclk_state);
1060 }
1061
1062 /**
1063  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1064  * @dev_priv: i915 device
1065  *
1066  * Uninitialize CDCLK for SKL and derivatives. This is done only
1067  * during the display core uninitialization sequence.
1068  */
1069 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1070 {
1071         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1072
1073         cdclk_state.cdclk = cdclk_state.ref;
1074         cdclk_state.vco = 0;
1075
1076         skl_set_cdclk(dev_priv, &cdclk_state);
1077 }
1078
1079 static int bxt_calc_cdclk(int min_cdclk)
1080 {
1081         if (min_cdclk > 576000)
1082                 return 624000;
1083         else if (min_cdclk > 384000)
1084                 return 576000;
1085         else if (min_cdclk > 288000)
1086                 return 384000;
1087         else if (min_cdclk > 144000)
1088                 return 288000;
1089         else
1090                 return 144000;
1091 }
1092
1093 static int glk_calc_cdclk(int min_cdclk)
1094 {
1095         if (min_cdclk > 158400)
1096                 return 316800;
1097         else if (min_cdclk > 79200)
1098                 return 158400;
1099         else
1100                 return 79200;
1101 }
1102
1103 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1104 {
1105         int ratio;
1106
1107         if (cdclk == dev_priv->cdclk.hw.ref)
1108                 return 0;
1109
1110         switch (cdclk) {
1111         default:
1112                 MISSING_CASE(cdclk);
1113         case 144000:
1114         case 288000:
1115         case 384000:
1116         case 576000:
1117                 ratio = 60;
1118                 break;
1119         case 624000:
1120                 ratio = 65;
1121                 break;
1122         }
1123
1124         return dev_priv->cdclk.hw.ref * ratio;
1125 }
1126
1127 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1128 {
1129         int ratio;
1130
1131         if (cdclk == dev_priv->cdclk.hw.ref)
1132                 return 0;
1133
1134         switch (cdclk) {
1135         default:
1136                 MISSING_CASE(cdclk);
1137         case  79200:
1138         case 158400:
1139         case 316800:
1140                 ratio = 33;
1141                 break;
1142         }
1143
1144         return dev_priv->cdclk.hw.ref * ratio;
1145 }
1146
1147 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1148                               struct intel_cdclk_state *cdclk_state)
1149 {
1150         u32 val;
1151
1152         cdclk_state->ref = 19200;
1153         cdclk_state->vco = 0;
1154
1155         val = I915_READ(BXT_DE_PLL_ENABLE);
1156         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1157                 return;
1158
1159         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1160                 return;
1161
1162         val = I915_READ(BXT_DE_PLL_CTL);
1163         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1164 }
1165
1166 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1167                           struct intel_cdclk_state *cdclk_state)
1168 {
1169         u32 divider;
1170         int div;
1171
1172         bxt_de_pll_update(dev_priv, cdclk_state);
1173
1174         cdclk_state->cdclk = cdclk_state->ref;
1175
1176         if (cdclk_state->vco == 0)
1177                 return;
1178
1179         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1180
1181         switch (divider) {
1182         case BXT_CDCLK_CD2X_DIV_SEL_1:
1183                 div = 2;
1184                 break;
1185         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1186                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1187                 div = 3;
1188                 break;
1189         case BXT_CDCLK_CD2X_DIV_SEL_2:
1190                 div = 4;
1191                 break;
1192         case BXT_CDCLK_CD2X_DIV_SEL_4:
1193                 div = 8;
1194                 break;
1195         default:
1196                 MISSING_CASE(divider);
1197                 return;
1198         }
1199
1200         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1201 }
1202
1203 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1204 {
1205         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1206
1207         /* Timeout 200us */
1208         if (intel_wait_for_register(dev_priv,
1209                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1210                                     1))
1211                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1212
1213         dev_priv->cdclk.hw.vco = 0;
1214 }
1215
1216 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1217 {
1218         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1219         u32 val;
1220
1221         val = I915_READ(BXT_DE_PLL_CTL);
1222         val &= ~BXT_DE_PLL_RATIO_MASK;
1223         val |= BXT_DE_PLL_RATIO(ratio);
1224         I915_WRITE(BXT_DE_PLL_CTL, val);
1225
1226         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1227
1228         /* Timeout 200us */
1229         if (intel_wait_for_register(dev_priv,
1230                                     BXT_DE_PLL_ENABLE,
1231                                     BXT_DE_PLL_LOCK,
1232                                     BXT_DE_PLL_LOCK,
1233                                     1))
1234                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1235
1236         dev_priv->cdclk.hw.vco = vco;
1237 }
1238
1239 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1240                           const struct intel_cdclk_state *cdclk_state)
1241 {
1242         int cdclk = cdclk_state->cdclk;
1243         int vco = cdclk_state->vco;
1244         u32 val, divider;
1245         int ret;
1246
1247         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1248         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1249         case 8:
1250                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1251                 break;
1252         case 4:
1253                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1254                 break;
1255         case 3:
1256                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1257                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1258                 break;
1259         case 2:
1260                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1261                 break;
1262         default:
1263                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1264                 WARN_ON(vco != 0);
1265
1266                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1267                 break;
1268         }
1269
1270         /* Inform power controller of upcoming frequency change */
1271         mutex_lock(&dev_priv->pcu_lock);
1272         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1273                                       0x80000000);
1274         mutex_unlock(&dev_priv->pcu_lock);
1275
1276         if (ret) {
1277                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1278                           ret, cdclk);
1279                 return;
1280         }
1281
1282         if (dev_priv->cdclk.hw.vco != 0 &&
1283             dev_priv->cdclk.hw.vco != vco)
1284                 bxt_de_pll_disable(dev_priv);
1285
1286         if (dev_priv->cdclk.hw.vco != vco)
1287                 bxt_de_pll_enable(dev_priv, vco);
1288
1289         val = divider | skl_cdclk_decimal(cdclk);
1290         /*
1291          * FIXME if only the cd2x divider needs changing, it could be done
1292          * without shutting off the pipe (if only one pipe is active).
1293          */
1294         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1295         /*
1296          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1297          * enable otherwise.
1298          */
1299         if (cdclk >= 500000)
1300                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1301         I915_WRITE(CDCLK_CTL, val);
1302
1303         mutex_lock(&dev_priv->pcu_lock);
1304         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1305                                       DIV_ROUND_UP(cdclk, 25000));
1306         mutex_unlock(&dev_priv->pcu_lock);
1307
1308         if (ret) {
1309                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1310                           ret, cdclk);
1311                 return;
1312         }
1313
1314         intel_update_cdclk(dev_priv);
1315 }
1316
1317 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1318 {
1319         u32 cdctl, expected;
1320
1321         intel_update_cdclk(dev_priv);
1322
1323         if (dev_priv->cdclk.hw.vco == 0 ||
1324             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1325                 goto sanitize;
1326
1327         /* DPLL okay; verify the cdclock
1328          *
1329          * Some BIOS versions leave an incorrect decimal frequency value and
1330          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1331          * so sanitize this register.
1332          */
1333         cdctl = I915_READ(CDCLK_CTL);
1334         /*
1335          * Let's ignore the pipe field, since BIOS could have configured the
1336          * dividers both synching to an active pipe, or asynchronously
1337          * (PIPE_NONE).
1338          */
1339         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1340
1341         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1342                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1343         /*
1344          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1345          * enable otherwise.
1346          */
1347         if (dev_priv->cdclk.hw.cdclk >= 500000)
1348                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1349
1350         if (cdctl == expected)
1351                 /* All well; nothing to sanitize */
1352                 return;
1353
1354 sanitize:
1355         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1356
1357         /* force cdclk programming */
1358         dev_priv->cdclk.hw.cdclk = 0;
1359
1360         /* force full PLL disable + enable */
1361         dev_priv->cdclk.hw.vco = -1;
1362 }
1363
1364 /**
1365  * bxt_init_cdclk - Initialize CDCLK on BXT
1366  * @dev_priv: i915 device
1367  *
1368  * Initialize CDCLK for BXT and derivatives. This is generally
1369  * done only during the display core initialization sequence,
1370  * after which the DMC will take care of turning CDCLK off/on
1371  * as needed.
1372  */
1373 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1374 {
1375         struct intel_cdclk_state cdclk_state;
1376
1377         bxt_sanitize_cdclk(dev_priv);
1378
1379         if (dev_priv->cdclk.hw.cdclk != 0 &&
1380             dev_priv->cdclk.hw.vco != 0)
1381                 return;
1382
1383         cdclk_state = dev_priv->cdclk.hw;
1384
1385         /*
1386          * FIXME:
1387          * - The initial CDCLK needs to be read from VBT.
1388          *   Need to make this change after VBT has changes for BXT.
1389          */
1390         if (IS_GEMINILAKE(dev_priv)) {
1391                 cdclk_state.cdclk = glk_calc_cdclk(0);
1392                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1393         } else {
1394                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1395                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1396         }
1397
1398         bxt_set_cdclk(dev_priv, &cdclk_state);
1399 }
1400
1401 /**
1402  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1403  * @dev_priv: i915 device
1404  *
1405  * Uninitialize CDCLK for BXT and derivatives. This is done only
1406  * during the display core uninitialization sequence.
1407  */
1408 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1409 {
1410         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1411
1412         cdclk_state.cdclk = cdclk_state.ref;
1413         cdclk_state.vco = 0;
1414
1415         bxt_set_cdclk(dev_priv, &cdclk_state);
1416 }
1417
1418 static int cnl_calc_cdclk(int min_cdclk)
1419 {
1420         if (min_cdclk > 336000)
1421                 return 528000;
1422         else if (min_cdclk > 168000)
1423                 return 336000;
1424         else
1425                 return 168000;
1426 }
1427
1428 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1429                                  struct intel_cdclk_state *cdclk_state)
1430 {
1431         u32 val;
1432
1433         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1434                 cdclk_state->ref = 24000;
1435         else
1436                 cdclk_state->ref = 19200;
1437
1438         cdclk_state->vco = 0;
1439
1440         val = I915_READ(BXT_DE_PLL_ENABLE);
1441         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1442                 return;
1443
1444         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1445                 return;
1446
1447         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1448 }
1449
1450 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1451                          struct intel_cdclk_state *cdclk_state)
1452 {
1453         u32 divider;
1454         int div;
1455
1456         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1457
1458         cdclk_state->cdclk = cdclk_state->ref;
1459
1460         if (cdclk_state->vco == 0)
1461                 return;
1462
1463         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1464
1465         switch (divider) {
1466         case BXT_CDCLK_CD2X_DIV_SEL_1:
1467                 div = 2;
1468                 break;
1469         case BXT_CDCLK_CD2X_DIV_SEL_2:
1470                 div = 4;
1471                 break;
1472         default:
1473                 MISSING_CASE(divider);
1474                 return;
1475         }
1476
1477         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1478 }
1479
1480 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1481 {
1482         u32 val;
1483
1484         val = I915_READ(BXT_DE_PLL_ENABLE);
1485         val &= ~BXT_DE_PLL_PLL_ENABLE;
1486         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1487
1488         /* Timeout 200us */
1489         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1490                 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1491
1492         dev_priv->cdclk.hw.vco = 0;
1493 }
1494
1495 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1496 {
1497         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1498         u32 val;
1499
1500         val = CNL_CDCLK_PLL_RATIO(ratio);
1501         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1502
1503         val |= BXT_DE_PLL_PLL_ENABLE;
1504         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1505
1506         /* Timeout 200us */
1507         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1508                 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1509
1510         dev_priv->cdclk.hw.vco = vco;
1511 }
1512
1513 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1514                           const struct intel_cdclk_state *cdclk_state)
1515 {
1516         int cdclk = cdclk_state->cdclk;
1517         int vco = cdclk_state->vco;
1518         u32 val, divider, pcu_ack;
1519         int ret;
1520
1521         mutex_lock(&dev_priv->pcu_lock);
1522         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1523                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1524                                 SKL_CDCLK_READY_FOR_CHANGE,
1525                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1526         mutex_unlock(&dev_priv->pcu_lock);
1527         if (ret) {
1528                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1529                           ret);
1530                 return;
1531         }
1532
1533         /* cdclk = vco / 2 / div{1,2} */
1534         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1535         case 4:
1536                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1537                 break;
1538         case 2:
1539                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1540                 break;
1541         default:
1542                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1543                 WARN_ON(vco != 0);
1544
1545                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1546                 break;
1547         }
1548
1549         switch (cdclk) {
1550         case 528000:
1551                 pcu_ack = 2;
1552                 break;
1553         case 336000:
1554                 pcu_ack = 1;
1555                 break;
1556         case 168000:
1557         default:
1558                 pcu_ack = 0;
1559                 break;
1560         }
1561
1562         if (dev_priv->cdclk.hw.vco != 0 &&
1563             dev_priv->cdclk.hw.vco != vco)
1564                 cnl_cdclk_pll_disable(dev_priv);
1565
1566         if (dev_priv->cdclk.hw.vco != vco)
1567                 cnl_cdclk_pll_enable(dev_priv, vco);
1568
1569         val = divider | skl_cdclk_decimal(cdclk);
1570         /*
1571          * FIXME if only the cd2x divider needs changing, it could be done
1572          * without shutting off the pipe (if only one pipe is active).
1573          */
1574         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1575         I915_WRITE(CDCLK_CTL, val);
1576
1577         /* inform PCU of the change */
1578         mutex_lock(&dev_priv->pcu_lock);
1579         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1580         mutex_unlock(&dev_priv->pcu_lock);
1581
1582         intel_update_cdclk(dev_priv);
1583 }
1584
1585 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1586 {
1587         int ratio;
1588
1589         if (cdclk == dev_priv->cdclk.hw.ref)
1590                 return 0;
1591
1592         switch (cdclk) {
1593         default:
1594                 MISSING_CASE(cdclk);
1595         case 168000:
1596         case 336000:
1597                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1598                 break;
1599         case 528000:
1600                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1601                 break;
1602         }
1603
1604         return dev_priv->cdclk.hw.ref * ratio;
1605 }
1606
1607 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1608 {
1609         u32 cdctl, expected;
1610
1611         intel_update_cdclk(dev_priv);
1612
1613         if (dev_priv->cdclk.hw.vco == 0 ||
1614             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1615                 goto sanitize;
1616
1617         /* DPLL okay; verify the cdclock
1618          *
1619          * Some BIOS versions leave an incorrect decimal frequency value and
1620          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1621          * so sanitize this register.
1622          */
1623         cdctl = I915_READ(CDCLK_CTL);
1624         /*
1625          * Let's ignore the pipe field, since BIOS could have configured the
1626          * dividers both synching to an active pipe, or asynchronously
1627          * (PIPE_NONE).
1628          */
1629         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1630
1631         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1632                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1633
1634         if (cdctl == expected)
1635                 /* All well; nothing to sanitize */
1636                 return;
1637
1638 sanitize:
1639         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1640
1641         /* force cdclk programming */
1642         dev_priv->cdclk.hw.cdclk = 0;
1643
1644         /* force full PLL disable + enable */
1645         dev_priv->cdclk.hw.vco = -1;
1646 }
1647
1648 /**
1649  * cnl_init_cdclk - Initialize CDCLK on CNL
1650  * @dev_priv: i915 device
1651  *
1652  * Initialize CDCLK for CNL. This is generally
1653  * done only during the display core initialization sequence,
1654  * after which the DMC will take care of turning CDCLK off/on
1655  * as needed.
1656  */
1657 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1658 {
1659         struct intel_cdclk_state cdclk_state;
1660
1661         cnl_sanitize_cdclk(dev_priv);
1662
1663         if (dev_priv->cdclk.hw.cdclk != 0 &&
1664             dev_priv->cdclk.hw.vco != 0)
1665                 return;
1666
1667         cdclk_state = dev_priv->cdclk.hw;
1668
1669         cdclk_state.cdclk = cnl_calc_cdclk(0);
1670         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1671
1672         cnl_set_cdclk(dev_priv, &cdclk_state);
1673 }
1674
1675 /**
1676  * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1677  * @dev_priv: i915 device
1678  *
1679  * Uninitialize CDCLK for CNL. This is done only
1680  * during the display core uninitialization sequence.
1681  */
1682 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1683 {
1684         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1685
1686         cdclk_state.cdclk = cdclk_state.ref;
1687         cdclk_state.vco = 0;
1688
1689         cnl_set_cdclk(dev_priv, &cdclk_state);
1690 }
1691
1692 /**
1693  * intel_cdclk_state_compare - Determine if two CDCLK states differ
1694  * @a: first CDCLK state
1695  * @b: second CDCLK state
1696  *
1697  * Returns:
1698  * True if the CDCLK states are identical, false if they differ.
1699  */
1700 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1701                                const struct intel_cdclk_state *b)
1702 {
1703         return memcmp(a, b, sizeof(*a)) == 0;
1704 }
1705
1706 /**
1707  * intel_set_cdclk - Push the CDCLK state to the hardware
1708  * @dev_priv: i915 device
1709  * @cdclk_state: new CDCLK state
1710  *
1711  * Program the hardware based on the passed in CDCLK state,
1712  * if necessary.
1713  */
1714 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1715                      const struct intel_cdclk_state *cdclk_state)
1716 {
1717         if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1718                 return;
1719
1720         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1721                 return;
1722
1723         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1724                          cdclk_state->cdclk, cdclk_state->vco,
1725                          cdclk_state->ref);
1726
1727         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1728 }
1729
1730 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
1731                                      int pixel_rate)
1732 {
1733         if (INTEL_GEN(dev_priv) >= 10)
1734                 /*
1735                  * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
1736                  * once DDI clock voltage requirements are
1737                  * handled correctly.
1738                  */
1739                 return pixel_rate;
1740         else if (IS_GEMINILAKE(dev_priv))
1741                 /*
1742                  * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1743                  * as a temporary workaround. Use a higher cdclk instead. (Note that
1744                  * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1745                  * cdclk.)
1746                  */
1747                 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
1748         else if (IS_GEN9(dev_priv) ||
1749                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1750                 return pixel_rate;
1751         else if (IS_CHERRYVIEW(dev_priv))
1752                 return DIV_ROUND_UP(pixel_rate * 100, 95);
1753         else
1754                 return DIV_ROUND_UP(pixel_rate * 100, 90);
1755 }
1756
1757 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
1758 {
1759         struct drm_i915_private *dev_priv =
1760                 to_i915(crtc_state->base.crtc->dev);
1761         int min_cdclk;
1762
1763         if (!crtc_state->base.enable)
1764                 return 0;
1765
1766         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
1767
1768         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1769         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1770                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
1771
1772         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1773          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1774          * there may be audio corruption or screen corruption." This cdclk
1775          * restriction for GLK is 316.8 MHz.
1776          */
1777         if (intel_crtc_has_dp_encoder(crtc_state) &&
1778             crtc_state->has_audio &&
1779             crtc_state->port_clock >= 540000 &&
1780             crtc_state->lane_count == 4) {
1781                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1782                         /* Display WA #1145: glk,cnl */
1783                         min_cdclk = max(316800, min_cdclk);
1784                 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
1785                         /* Display WA #1144: skl,bxt */
1786                         min_cdclk = max(432000, min_cdclk);
1787                 }
1788         }
1789
1790         /* According to BSpec, "The CD clock frequency must be at least twice
1791          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1792          */
1793         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
1794                 min_cdclk = max(2 * 96000, min_cdclk);
1795
1796         if (min_cdclk > dev_priv->max_cdclk_freq) {
1797                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
1798                               min_cdclk, dev_priv->max_cdclk_freq);
1799                 return -EINVAL;
1800         }
1801
1802         return min_cdclk;
1803 }
1804
1805 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
1806 {
1807         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1808         struct drm_i915_private *dev_priv = to_i915(state->dev);
1809         struct intel_crtc *crtc;
1810         struct intel_crtc_state *crtc_state;
1811         int min_cdclk, i;
1812         enum pipe pipe;
1813
1814         memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
1815                sizeof(intel_state->min_cdclk));
1816
1817         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
1818                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
1819                 if (min_cdclk < 0)
1820                         return min_cdclk;
1821
1822                 intel_state->min_cdclk[i] = min_cdclk;
1823         }
1824
1825         min_cdclk = 0;
1826         for_each_pipe(dev_priv, pipe)
1827                 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
1828
1829         return min_cdclk;
1830 }
1831
1832 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1833 {
1834         struct drm_i915_private *dev_priv = to_i915(state->dev);
1835         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1836         int min_cdclk, cdclk;
1837
1838         min_cdclk = intel_compute_min_cdclk(state);
1839         if (min_cdclk < 0)
1840                 return min_cdclk;
1841
1842         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
1843
1844         intel_state->cdclk.logical.cdclk = cdclk;
1845
1846         if (!intel_state->active_crtcs) {
1847                 cdclk = vlv_calc_cdclk(dev_priv, 0);
1848
1849                 intel_state->cdclk.actual.cdclk = cdclk;
1850         } else {
1851                 intel_state->cdclk.actual =
1852                         intel_state->cdclk.logical;
1853         }
1854
1855         return 0;
1856 }
1857
1858 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1859 {
1860         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1861         int min_cdclk, cdclk;
1862
1863         min_cdclk = intel_compute_min_cdclk(state);
1864         if (min_cdclk < 0)
1865                 return min_cdclk;
1866
1867         /*
1868          * FIXME should also account for plane ratio
1869          * once 64bpp pixel formats are supported.
1870          */
1871         cdclk = bdw_calc_cdclk(min_cdclk);
1872
1873         intel_state->cdclk.logical.cdclk = cdclk;
1874
1875         if (!intel_state->active_crtcs) {
1876                 cdclk = bdw_calc_cdclk(0);
1877
1878                 intel_state->cdclk.actual.cdclk = cdclk;
1879         } else {
1880                 intel_state->cdclk.actual =
1881                         intel_state->cdclk.logical;
1882         }
1883
1884         return 0;
1885 }
1886
1887 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1888 {
1889         struct drm_i915_private *dev_priv = to_i915(state->dev);
1890         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1891         int min_cdclk, cdclk, vco;
1892
1893         min_cdclk = intel_compute_min_cdclk(state);
1894         if (min_cdclk < 0)
1895                 return min_cdclk;
1896
1897         vco = intel_state->cdclk.logical.vco;
1898         if (!vco)
1899                 vco = dev_priv->skl_preferred_vco_freq;
1900
1901         /*
1902          * FIXME should also account for plane ratio
1903          * once 64bpp pixel formats are supported.
1904          */
1905         cdclk = skl_calc_cdclk(min_cdclk, vco);
1906
1907         intel_state->cdclk.logical.vco = vco;
1908         intel_state->cdclk.logical.cdclk = cdclk;
1909
1910         if (!intel_state->active_crtcs) {
1911                 cdclk = skl_calc_cdclk(0, vco);
1912
1913                 intel_state->cdclk.actual.vco = vco;
1914                 intel_state->cdclk.actual.cdclk = cdclk;
1915         } else {
1916                 intel_state->cdclk.actual =
1917                         intel_state->cdclk.logical;
1918         }
1919
1920         return 0;
1921 }
1922
1923 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1924 {
1925         struct drm_i915_private *dev_priv = to_i915(state->dev);
1926         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1927         int min_cdclk, cdclk, vco;
1928
1929         min_cdclk = intel_compute_min_cdclk(state);
1930         if (min_cdclk < 0)
1931                 return min_cdclk;
1932
1933         if (IS_GEMINILAKE(dev_priv)) {
1934                 cdclk = glk_calc_cdclk(min_cdclk);
1935                 vco = glk_de_pll_vco(dev_priv, cdclk);
1936         } else {
1937                 cdclk = bxt_calc_cdclk(min_cdclk);
1938                 vco = bxt_de_pll_vco(dev_priv, cdclk);
1939         }
1940
1941         intel_state->cdclk.logical.vco = vco;
1942         intel_state->cdclk.logical.cdclk = cdclk;
1943
1944         if (!intel_state->active_crtcs) {
1945                 if (IS_GEMINILAKE(dev_priv)) {
1946                         cdclk = glk_calc_cdclk(0);
1947                         vco = glk_de_pll_vco(dev_priv, cdclk);
1948                 } else {
1949                         cdclk = bxt_calc_cdclk(0);
1950                         vco = bxt_de_pll_vco(dev_priv, cdclk);
1951                 }
1952
1953                 intel_state->cdclk.actual.vco = vco;
1954                 intel_state->cdclk.actual.cdclk = cdclk;
1955         } else {
1956                 intel_state->cdclk.actual =
1957                         intel_state->cdclk.logical;
1958         }
1959
1960         return 0;
1961 }
1962
1963 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
1964 {
1965         struct drm_i915_private *dev_priv = to_i915(state->dev);
1966         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1967         int min_cdclk, cdclk, vco;
1968
1969         min_cdclk = intel_compute_min_cdclk(state);
1970         if (min_cdclk < 0)
1971                 return min_cdclk;
1972
1973         cdclk = cnl_calc_cdclk(min_cdclk);
1974         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
1975
1976         intel_state->cdclk.logical.vco = vco;
1977         intel_state->cdclk.logical.cdclk = cdclk;
1978
1979         if (!intel_state->active_crtcs) {
1980                 cdclk = cnl_calc_cdclk(0);
1981                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
1982
1983                 intel_state->cdclk.actual.vco = vco;
1984                 intel_state->cdclk.actual.cdclk = cdclk;
1985         } else {
1986                 intel_state->cdclk.actual =
1987                         intel_state->cdclk.logical;
1988         }
1989
1990         return 0;
1991 }
1992
1993 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
1994 {
1995         int max_cdclk_freq = dev_priv->max_cdclk_freq;
1996
1997         if (INTEL_GEN(dev_priv) >= 10)
1998                 /*
1999                  * FIXME: Allow '2 * max_cdclk_freq'
2000                  * once DDI clock voltage requirements are
2001                  * handled correctly.
2002                  */
2003                 return max_cdclk_freq;
2004         else if (IS_GEMINILAKE(dev_priv))
2005                 /*
2006                  * FIXME: Limiting to 99% as a temporary workaround. See
2007                  * intel_min_cdclk() for details.
2008                  */
2009                 return 2 * max_cdclk_freq * 99 / 100;
2010         else if (IS_GEN9(dev_priv) ||
2011                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2012                 return max_cdclk_freq;
2013         else if (IS_CHERRYVIEW(dev_priv))
2014                 return max_cdclk_freq*95/100;
2015         else if (INTEL_INFO(dev_priv)->gen < 4)
2016                 return 2*max_cdclk_freq*90/100;
2017         else
2018                 return max_cdclk_freq*90/100;
2019 }
2020
2021 /**
2022  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2023  * @dev_priv: i915 device
2024  *
2025  * Determine the maximum CDCLK frequency the platform supports, and also
2026  * derive the maximum dot clock frequency the maximum CDCLK frequency
2027  * allows.
2028  */
2029 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2030 {
2031         if (IS_CANNONLAKE(dev_priv)) {
2032                 dev_priv->max_cdclk_freq = 528000;
2033         } else if (IS_GEN9_BC(dev_priv)) {
2034                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2035                 int max_cdclk, vco;
2036
2037                 vco = dev_priv->skl_preferred_vco_freq;
2038                 WARN_ON(vco != 8100000 && vco != 8640000);
2039
2040                 /*
2041                  * Use the lower (vco 8640) cdclk values as a
2042                  * first guess. skl_calc_cdclk() will correct it
2043                  * if the preferred vco is 8100 instead.
2044                  */
2045                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2046                         max_cdclk = 617143;
2047                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2048                         max_cdclk = 540000;
2049                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2050                         max_cdclk = 432000;
2051                 else
2052                         max_cdclk = 308571;
2053
2054                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2055         } else if (IS_GEMINILAKE(dev_priv)) {
2056                 dev_priv->max_cdclk_freq = 316800;
2057         } else if (IS_BROXTON(dev_priv)) {
2058                 dev_priv->max_cdclk_freq = 624000;
2059         } else if (IS_BROADWELL(dev_priv))  {
2060                 /*
2061                  * FIXME with extra cooling we can allow
2062                  * 540 MHz for ULX and 675 Mhz for ULT.
2063                  * How can we know if extra cooling is
2064                  * available? PCI ID, VTB, something else?
2065                  */
2066                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2067                         dev_priv->max_cdclk_freq = 450000;
2068                 else if (IS_BDW_ULX(dev_priv))
2069                         dev_priv->max_cdclk_freq = 450000;
2070                 else if (IS_BDW_ULT(dev_priv))
2071                         dev_priv->max_cdclk_freq = 540000;
2072                 else
2073                         dev_priv->max_cdclk_freq = 675000;
2074         } else if (IS_CHERRYVIEW(dev_priv)) {
2075                 dev_priv->max_cdclk_freq = 320000;
2076         } else if (IS_VALLEYVIEW(dev_priv)) {
2077                 dev_priv->max_cdclk_freq = 400000;
2078         } else {
2079                 /* otherwise assume cdclk is fixed */
2080                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2081         }
2082
2083         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2084
2085         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2086                          dev_priv->max_cdclk_freq);
2087
2088         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2089                          dev_priv->max_dotclk_freq);
2090 }
2091
2092 /**
2093  * intel_update_cdclk - Determine the current CDCLK frequency
2094  * @dev_priv: i915 device
2095  *
2096  * Determine the current CDCLK frequency.
2097  */
2098 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2099 {
2100         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2101
2102         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2103                          dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2104                          dev_priv->cdclk.hw.ref);
2105
2106         /*
2107          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2108          * Programmng [sic] note: bit[9:2] should be programmed to the number
2109          * of cdclk that generates 4MHz reference clock freq which is used to
2110          * generate GMBus clock. This will vary with the cdclk freq.
2111          */
2112         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2113                 I915_WRITE(GMBUSFREQ_VLV,
2114                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2115 }
2116
2117 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2118 {
2119         u32 rawclk;
2120         int divider, fraction;
2121
2122         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2123                 /* 24 MHz */
2124                 divider = 24000;
2125                 fraction = 0;
2126         } else {
2127                 /* 19.2 MHz */
2128                 divider = 19000;
2129                 fraction = 200;
2130         }
2131
2132         rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2133         if (fraction)
2134                 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2135                                                             fraction) - 1);
2136
2137         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2138         return divider + fraction;
2139 }
2140
2141 static int pch_rawclk(struct drm_i915_private *dev_priv)
2142 {
2143         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2144 }
2145
2146 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2147 {
2148         /* RAWCLK_FREQ_VLV register updated from power well code */
2149         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2150                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2151 }
2152
2153 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2154 {
2155         uint32_t clkcfg;
2156
2157         /* hrawclock is 1/4 the FSB frequency */
2158         clkcfg = I915_READ(CLKCFG);
2159         switch (clkcfg & CLKCFG_FSB_MASK) {
2160         case CLKCFG_FSB_400:
2161                 return 100000;
2162         case CLKCFG_FSB_533:
2163                 return 133333;
2164         case CLKCFG_FSB_667:
2165                 return 166667;
2166         case CLKCFG_FSB_800:
2167                 return 200000;
2168         case CLKCFG_FSB_1067:
2169         case CLKCFG_FSB_1067_ALT:
2170                 return 266667;
2171         case CLKCFG_FSB_1333:
2172         case CLKCFG_FSB_1333_ALT:
2173                 return 333333;
2174         default:
2175                 return 133333;
2176         }
2177 }
2178
2179 /**
2180  * intel_update_rawclk - Determine the current RAWCLK frequency
2181  * @dev_priv: i915 device
2182  *
2183  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2184  * frequency clock so this needs to done only once.
2185  */
2186 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2187 {
2188
2189         if (HAS_PCH_CNP(dev_priv))
2190                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2191         else if (HAS_PCH_SPLIT(dev_priv))
2192                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2193         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2194                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2195         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2196                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2197         else
2198                 /* no rawclk on other platforms, or no need to know it */
2199                 return;
2200
2201         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2202 }
2203
2204 /**
2205  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2206  * @dev_priv: i915 device
2207  */
2208 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2209 {
2210         if (IS_CHERRYVIEW(dev_priv)) {
2211                 dev_priv->display.set_cdclk = chv_set_cdclk;
2212                 dev_priv->display.modeset_calc_cdclk =
2213                         vlv_modeset_calc_cdclk;
2214         } else if (IS_VALLEYVIEW(dev_priv)) {
2215                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2216                 dev_priv->display.modeset_calc_cdclk =
2217                         vlv_modeset_calc_cdclk;
2218         } else if (IS_BROADWELL(dev_priv)) {
2219                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2220                 dev_priv->display.modeset_calc_cdclk =
2221                         bdw_modeset_calc_cdclk;
2222         } else if (IS_GEN9_LP(dev_priv)) {
2223                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2224                 dev_priv->display.modeset_calc_cdclk =
2225                         bxt_modeset_calc_cdclk;
2226         } else if (IS_GEN9_BC(dev_priv)) {
2227                 dev_priv->display.set_cdclk = skl_set_cdclk;
2228                 dev_priv->display.modeset_calc_cdclk =
2229                         skl_modeset_calc_cdclk;
2230         } else if (IS_CANNONLAKE(dev_priv)) {
2231                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2232                 dev_priv->display.modeset_calc_cdclk =
2233                         cnl_modeset_calc_cdclk;
2234         }
2235
2236         if (IS_CANNONLAKE(dev_priv))
2237                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2238         else if (IS_GEN9_BC(dev_priv))
2239                 dev_priv->display.get_cdclk = skl_get_cdclk;
2240         else if (IS_GEN9_LP(dev_priv))
2241                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2242         else if (IS_BROADWELL(dev_priv))
2243                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2244         else if (IS_HASWELL(dev_priv))
2245                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2246         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2247                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2248         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2249                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2250         else if (IS_GEN5(dev_priv))
2251                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2252         else if (IS_GM45(dev_priv))
2253                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2254         else if (IS_G45(dev_priv))
2255                 dev_priv->display.get_cdclk = g33_get_cdclk;
2256         else if (IS_I965GM(dev_priv))
2257                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2258         else if (IS_I965G(dev_priv))
2259                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2260         else if (IS_PINEVIEW(dev_priv))
2261                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2262         else if (IS_G33(dev_priv))
2263                 dev_priv->display.get_cdclk = g33_get_cdclk;
2264         else if (IS_I945GM(dev_priv))
2265                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2266         else if (IS_I945G(dev_priv))
2267                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2268         else if (IS_I915GM(dev_priv))
2269                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2270         else if (IS_I915G(dev_priv))
2271                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2272         else if (IS_I865G(dev_priv))
2273                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2274         else if (IS_I85X(dev_priv))
2275                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2276         else if (IS_I845G(dev_priv))
2277                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2278         else { /* 830 */
2279                 WARN(!IS_I830(dev_priv),
2280                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2281                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2282         }
2283 }