2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
35 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
37 struct drm_minor *minor = dev_get_drvdata(kdev);
38 return to_i915(minor->dev);
42 static u32 calc_residency(struct drm_i915_private *dev_priv,
45 return DIV_ROUND_CLOSEST_ULL(intel_rc6_residency_us(dev_priv, reg),
50 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
52 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6());
56 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
58 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
59 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
60 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
64 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
66 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
67 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
68 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
72 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
74 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
75 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
76 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
80 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
82 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
83 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
84 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
87 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
88 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
89 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
90 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
91 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
93 static struct attribute *rc6_attrs[] = {
94 &dev_attr_rc6_enable.attr,
95 &dev_attr_rc6_residency_ms.attr,
99 static const struct attribute_group rc6_attr_group = {
100 .name = power_group_name,
104 static struct attribute *rc6p_attrs[] = {
105 &dev_attr_rc6p_residency_ms.attr,
106 &dev_attr_rc6pp_residency_ms.attr,
110 static const struct attribute_group rc6p_attr_group = {
111 .name = power_group_name,
115 static struct attribute *media_rc6_attrs[] = {
116 &dev_attr_media_rc6_residency_ms.attr,
120 static const struct attribute_group media_rc6_attr_group = {
121 .name = power_group_name,
122 .attrs = media_rc6_attrs
126 static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset)
128 if (!HAS_L3_DPF(dev_priv))
134 if (offset >= GEN7_L3LOG_SIZE)
141 i915_l3_read(struct file *filp, struct kobject *kobj,
142 struct bin_attribute *attr, char *buf,
143 loff_t offset, size_t count)
145 struct device *kdev = kobj_to_dev(kobj);
146 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
147 struct drm_device *dev = &dev_priv->drm;
148 int slice = (int)(uintptr_t)attr->private;
151 count = round_down(count, 4);
153 ret = l3_access_valid(dev_priv, offset);
157 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
159 ret = i915_mutex_lock_interruptible(dev);
163 if (dev_priv->l3_parity.remap_info[slice])
165 dev_priv->l3_parity.remap_info[slice] + (offset/4),
168 memset(buf, 0, count);
170 mutex_unlock(&dev->struct_mutex);
176 i915_l3_write(struct file *filp, struct kobject *kobj,
177 struct bin_attribute *attr, char *buf,
178 loff_t offset, size_t count)
180 struct device *kdev = kobj_to_dev(kobj);
181 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
182 struct drm_device *dev = &dev_priv->drm;
183 struct i915_gem_context *ctx;
184 int slice = (int)(uintptr_t)attr->private;
188 ret = l3_access_valid(dev_priv, offset);
192 ret = i915_mutex_lock_interruptible(dev);
196 remap_info = &dev_priv->l3_parity.remap_info[slice];
198 *remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
205 /* TODO: Ideally we really want a GPU reset here to make sure errors
206 * aren't propagated. Since I cannot find a stable way to reset the GPU
207 * at this point it is left as a TODO.
209 memcpy(*remap_info + (offset/4), buf, count);
211 /* NB: We defer the remapping until we switch to the context */
212 list_for_each_entry(ctx, &dev_priv->contexts.list, link)
213 ctx->remap_slice |= (1<<slice);
218 mutex_unlock(&dev->struct_mutex);
223 static const struct bin_attribute dpf_attrs = {
224 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
225 .size = GEN7_L3LOG_SIZE,
226 .read = i915_l3_read,
227 .write = i915_l3_write,
232 static const struct bin_attribute dpf_attrs_1 = {
233 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
234 .size = GEN7_L3LOG_SIZE,
235 .read = i915_l3_read,
236 .write = i915_l3_write,
241 static ssize_t gt_act_freq_mhz_show(struct device *kdev,
242 struct device_attribute *attr, char *buf)
244 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
247 intel_runtime_pm_get(dev_priv);
249 mutex_lock(&dev_priv->rps.hw_lock);
250 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
252 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
253 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
255 u32 rpstat = I915_READ(GEN6_RPSTAT1);
256 if (INTEL_GEN(dev_priv) >= 9)
257 ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
258 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
259 ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
261 ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
262 ret = intel_gpu_freq(dev_priv, ret);
264 mutex_unlock(&dev_priv->rps.hw_lock);
266 intel_runtime_pm_put(dev_priv);
268 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
271 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
272 struct device_attribute *attr, char *buf)
274 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
276 return snprintf(buf, PAGE_SIZE, "%d\n",
277 intel_gpu_freq(dev_priv,
278 dev_priv->rps.cur_freq));
281 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
283 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
285 return snprintf(buf, PAGE_SIZE, "%d\n",
286 intel_gpu_freq(dev_priv,
287 dev_priv->rps.boost_freq));
290 static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
291 struct device_attribute *attr,
292 const char *buf, size_t count)
294 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
298 ret = kstrtou32(buf, 0, &val);
302 /* Validate against (static) hardware limits */
303 val = intel_freq_opcode(dev_priv, val);
304 if (val < dev_priv->rps.min_freq || val > dev_priv->rps.max_freq)
307 mutex_lock(&dev_priv->rps.hw_lock);
308 dev_priv->rps.boost_freq = val;
309 mutex_unlock(&dev_priv->rps.hw_lock);
314 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
315 struct device_attribute *attr, char *buf)
317 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
319 return snprintf(buf, PAGE_SIZE, "%d\n",
320 intel_gpu_freq(dev_priv,
321 dev_priv->rps.efficient_freq));
324 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
326 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
328 return snprintf(buf, PAGE_SIZE, "%d\n",
329 intel_gpu_freq(dev_priv,
330 dev_priv->rps.max_freq_softlimit));
333 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
334 struct device_attribute *attr,
335 const char *buf, size_t count)
337 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
341 ret = kstrtou32(buf, 0, &val);
345 intel_runtime_pm_get(dev_priv);
347 mutex_lock(&dev_priv->rps.hw_lock);
349 val = intel_freq_opcode(dev_priv, val);
351 if (val < dev_priv->rps.min_freq ||
352 val > dev_priv->rps.max_freq ||
353 val < dev_priv->rps.min_freq_softlimit) {
354 mutex_unlock(&dev_priv->rps.hw_lock);
355 intel_runtime_pm_put(dev_priv);
359 if (val > dev_priv->rps.rp0_freq)
360 DRM_DEBUG("User requested overclocking to %d\n",
361 intel_gpu_freq(dev_priv, val));
363 dev_priv->rps.max_freq_softlimit = val;
365 val = clamp_t(int, dev_priv->rps.cur_freq,
366 dev_priv->rps.min_freq_softlimit,
367 dev_priv->rps.max_freq_softlimit);
369 /* We still need *_set_rps to process the new max_delay and
370 * update the interrupt limits and PMINTRMSK even though
371 * frequency request may be unchanged. */
372 ret = intel_set_rps(dev_priv, val);
374 mutex_unlock(&dev_priv->rps.hw_lock);
376 intel_runtime_pm_put(dev_priv);
381 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
383 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
385 return snprintf(buf, PAGE_SIZE, "%d\n",
386 intel_gpu_freq(dev_priv,
387 dev_priv->rps.min_freq_softlimit));
390 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
391 struct device_attribute *attr,
392 const char *buf, size_t count)
394 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
398 ret = kstrtou32(buf, 0, &val);
402 intel_runtime_pm_get(dev_priv);
404 mutex_lock(&dev_priv->rps.hw_lock);
406 val = intel_freq_opcode(dev_priv, val);
408 if (val < dev_priv->rps.min_freq ||
409 val > dev_priv->rps.max_freq ||
410 val > dev_priv->rps.max_freq_softlimit) {
411 mutex_unlock(&dev_priv->rps.hw_lock);
412 intel_runtime_pm_put(dev_priv);
416 dev_priv->rps.min_freq_softlimit = val;
418 val = clamp_t(int, dev_priv->rps.cur_freq,
419 dev_priv->rps.min_freq_softlimit,
420 dev_priv->rps.max_freq_softlimit);
422 /* We still need *_set_rps to process the new min_delay and
423 * update the interrupt limits and PMINTRMSK even though
424 * frequency request may be unchanged. */
425 ret = intel_set_rps(dev_priv, val);
427 mutex_unlock(&dev_priv->rps.hw_lock);
429 intel_runtime_pm_put(dev_priv);
434 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
435 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
436 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO | S_IWUSR, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
437 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
438 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
440 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
442 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
443 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
444 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
445 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
447 /* For now we have a static number of RP states */
448 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
450 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
453 if (attr == &dev_attr_gt_RP0_freq_mhz)
454 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
455 else if (attr == &dev_attr_gt_RP1_freq_mhz)
456 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
457 else if (attr == &dev_attr_gt_RPn_freq_mhz)
458 val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
462 return snprintf(buf, PAGE_SIZE, "%d\n", val);
465 static const struct attribute *gen6_attrs[] = {
466 &dev_attr_gt_act_freq_mhz.attr,
467 &dev_attr_gt_cur_freq_mhz.attr,
468 &dev_attr_gt_boost_freq_mhz.attr,
469 &dev_attr_gt_max_freq_mhz.attr,
470 &dev_attr_gt_min_freq_mhz.attr,
471 &dev_attr_gt_RP0_freq_mhz.attr,
472 &dev_attr_gt_RP1_freq_mhz.attr,
473 &dev_attr_gt_RPn_freq_mhz.attr,
477 static const struct attribute *vlv_attrs[] = {
478 &dev_attr_gt_act_freq_mhz.attr,
479 &dev_attr_gt_cur_freq_mhz.attr,
480 &dev_attr_gt_boost_freq_mhz.attr,
481 &dev_attr_gt_max_freq_mhz.attr,
482 &dev_attr_gt_min_freq_mhz.attr,
483 &dev_attr_gt_RP0_freq_mhz.attr,
484 &dev_attr_gt_RP1_freq_mhz.attr,
485 &dev_attr_gt_RPn_freq_mhz.attr,
486 &dev_attr_vlv_rpe_freq_mhz.attr,
490 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
492 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
493 struct bin_attribute *attr, char *buf,
494 loff_t off, size_t count)
497 struct device *kdev = kobj_to_dev(kobj);
498 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
499 struct drm_i915_error_state_buf error_str;
500 struct i915_gpu_state *gpu;
503 ret = i915_error_state_buf_init(&error_str, dev_priv, count, off);
507 gpu = i915_first_error_state(dev_priv);
508 ret = i915_error_state_to_str(&error_str, gpu);
512 ret = count < error_str.bytes ? count : error_str.bytes;
513 memcpy(buf, error_str.buf, ret);
516 i915_gpu_state_put(gpu);
517 i915_error_state_buf_release(&error_str);
522 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
523 struct bin_attribute *attr, char *buf,
524 loff_t off, size_t count)
526 struct device *kdev = kobj_to_dev(kobj);
527 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
529 DRM_DEBUG_DRIVER("Resetting error state\n");
530 i915_reset_error_state(dev_priv);
535 static const struct bin_attribute error_state_attr = {
536 .attr.name = "error",
537 .attr.mode = S_IRUSR | S_IWUSR,
539 .read = error_state_read,
540 .write = error_state_write,
543 static void i915_setup_error_capture(struct device *kdev)
545 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
546 DRM_ERROR("error_state sysfs setup failed\n");
549 static void i915_teardown_error_capture(struct device *kdev)
551 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
554 static void i915_setup_error_capture(struct device *kdev) {}
555 static void i915_teardown_error_capture(struct device *kdev) {}
558 void i915_setup_sysfs(struct drm_i915_private *dev_priv)
560 struct device *kdev = dev_priv->drm.primary->kdev;
564 if (HAS_RC6(dev_priv)) {
565 ret = sysfs_merge_group(&kdev->kobj,
568 DRM_ERROR("RC6 residency sysfs setup failed\n");
570 if (HAS_RC6p(dev_priv)) {
571 ret = sysfs_merge_group(&kdev->kobj,
574 DRM_ERROR("RC6p residency sysfs setup failed\n");
576 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
577 ret = sysfs_merge_group(&kdev->kobj,
578 &media_rc6_attr_group);
580 DRM_ERROR("Media RC6 residency sysfs setup failed\n");
583 if (HAS_L3_DPF(dev_priv)) {
584 ret = device_create_bin_file(kdev, &dpf_attrs);
586 DRM_ERROR("l3 parity sysfs setup failed\n");
588 if (NUM_L3_SLICES(dev_priv) > 1) {
589 ret = device_create_bin_file(kdev,
592 DRM_ERROR("l3 parity slice 1 setup failed\n");
597 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
598 ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
599 else if (INTEL_GEN(dev_priv) >= 6)
600 ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
602 DRM_ERROR("RPS sysfs setup failed\n");
604 i915_setup_error_capture(kdev);
607 void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
609 struct device *kdev = dev_priv->drm.primary->kdev;
611 i915_teardown_error_capture(kdev);
613 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
614 sysfs_remove_files(&kdev->kobj, vlv_attrs);
616 sysfs_remove_files(&kdev->kobj, gen6_attrs);
617 device_remove_bin_file(kdev, &dpf_attrs_1);
618 device_remove_bin_file(kdev, &dpf_attrs);
620 sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
621 sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);