drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30
  31 #define GEN_DEFAULT_PIPEOFFSETS \
  32         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  33                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  34         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  35                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  36         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  37
  38 #define GEN_CHV_PIPEOFFSETS \
  39         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  40                           CHV_PIPE_C_OFFSET }, \
  41         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  42                            CHV_TRANSCODER_C_OFFSET, }, \
  43         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  44                              CHV_PALETTE_C_OFFSET }
  45
  46 #define CURSOR_OFFSETS \
  47         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  48
  49 #define IVB_CURSOR_OFFSETS \
  50         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  51
  52 #define BDW_COLORS \
  53         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  54 #define CHV_COLORS \
  55         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  56
  57 #define GEN2_FEATURES \
  58         .gen = 2, .num_pipes = 1, \
  59         .has_overlay = 1, .overlay_needs_physical = 1, \
  60         .has_gmch_display = 1, \
  61         .ring_mask = RENDER_RING, \
  62         GEN_DEFAULT_PIPEOFFSETS, \
  63         CURSOR_OFFSETS
  64
  65 static const struct intel_device_info intel_i830_info = {
  66         GEN2_FEATURES,
  67         .is_mobile = 1, .cursor_needs_physical = 1,
  68         .num_pipes = 2, /* legal, last one wins */
  69 };
  70
  71 static const struct intel_device_info intel_845g_info = {
  72         GEN2_FEATURES,
  73 };
  74
  75 static const struct intel_device_info intel_i85x_info = {
  76         GEN2_FEATURES,
  77         .is_i85x = 1, .is_mobile = 1,
  78         .num_pipes = 2, /* legal, last one wins */
  79         .cursor_needs_physical = 1,
  80         .has_fbc = 1,
  81 };
  82
  83 static const struct intel_device_info intel_i865g_info = {
  84         GEN2_FEATURES,
  85 };
  86
  87 #define GEN3_FEATURES \
  88         .gen = 3, .num_pipes = 2, \
  89         .has_gmch_display = 1, \
  90         .ring_mask = RENDER_RING, \
  91         GEN_DEFAULT_PIPEOFFSETS, \
  92         CURSOR_OFFSETS
  93
  94 static const struct intel_device_info intel_i915g_info = {
  95         GEN3_FEATURES,
  96         .is_i915g = 1, .cursor_needs_physical = 1,
  97         .has_overlay = 1, .overlay_needs_physical = 1,
  98 };
  99 static const struct intel_device_info intel_i915gm_info = {
 100         GEN3_FEATURES,
 101         .is_mobile = 1,
 102         .cursor_needs_physical = 1,
 103         .has_overlay = 1, .overlay_needs_physical = 1,
 104         .supports_tv = 1,
 105         .has_fbc = 1,
 106 };
 107 static const struct intel_device_info intel_i945g_info = {
 108         GEN3_FEATURES,
 109         .has_hotplug = 1, .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111 };
 112 static const struct intel_device_info intel_i945gm_info = {
 113         GEN3_FEATURES,
 114         .is_i945gm = 1, .is_mobile = 1,
 115         .has_hotplug = 1, .cursor_needs_physical = 1,
 116         .has_overlay = 1, .overlay_needs_physical = 1,
 117         .supports_tv = 1,
 118         .has_fbc = 1,
 119 };
 120
 121 #define GEN4_FEATURES \
 122         .gen = 4, .num_pipes = 2, \
 123         .has_hotplug = 1, \
 124         .has_gmch_display = 1, \
 125         .ring_mask = RENDER_RING, \
 126         GEN_DEFAULT_PIPEOFFSETS, \
 127         CURSOR_OFFSETS
 128
 129 static const struct intel_device_info intel_i965g_info = {
 130         GEN4_FEATURES,
 131         .is_broadwater = 1,
 132         .has_overlay = 1,
 133 };
 134
 135 static const struct intel_device_info intel_i965gm_info = {
 136         GEN4_FEATURES,
 137         .is_crestline = 1,
 138         .is_mobile = 1, .has_fbc = 1,
 139         .has_overlay = 1,
 140         .supports_tv = 1,
 141 };
 142
 143 static const struct intel_device_info intel_g33_info = {
 144         GEN3_FEATURES,
 145         .is_g33 = 1,
 146         .need_gfx_hws = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148 };
 149
 150 static const struct intel_device_info intel_g45_info = {
 151         GEN4_FEATURES,
 152         .is_g4x = 1, .need_gfx_hws = 1,
 153         .has_pipe_cxsr = 1,
 154         .ring_mask = RENDER_RING | BSD_RING,
 155 };
 156
 157 static const struct intel_device_info intel_gm45_info = {
 158         GEN4_FEATURES,
 159         .is_g4x = 1,
 160         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 161         .has_pipe_cxsr = 1,
 162         .supports_tv = 1,
 163         .ring_mask = RENDER_RING | BSD_RING,
 164 };
 165
 166 static const struct intel_device_info intel_pineview_info = {
 167         GEN3_FEATURES,
 168         .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 169         .need_gfx_hws = 1, .has_hotplug = 1,
 170         .has_overlay = 1,
 171 };
 172
 173 #define GEN5_FEATURES \
 174         .gen = 5, .num_pipes = 2, \
 175         .need_gfx_hws = 1, .has_hotplug = 1, \
 176         .has_gmbus_irq = 1, \
 177         .ring_mask = RENDER_RING | BSD_RING, \
 178         GEN_DEFAULT_PIPEOFFSETS, \
 179         CURSOR_OFFSETS
 180
 181 static const struct intel_device_info intel_ironlake_d_info = {
 182         GEN5_FEATURES,
 183 };
 184
 185 static const struct intel_device_info intel_ironlake_m_info = {
 186         GEN5_FEATURES,
 187         .is_mobile = 1,
 188 };
 189
 190 #define GEN6_FEATURES \
 191         .gen = 6, .num_pipes = 2, \
 192         .need_gfx_hws = 1, .has_hotplug = 1, \
 193         .has_fbc = 1, \
 194         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 195         .has_llc = 1, \
 196         .has_rc6 = 1, \
 197         .has_rc6p = 1, \
 198         .has_gmbus_irq = 1, \
 199         .has_hw_contexts = 1, \
 200         GEN_DEFAULT_PIPEOFFSETS, \
 201         CURSOR_OFFSETS
 202
 203 static const struct intel_device_info intel_sandybridge_d_info = {
 204         GEN6_FEATURES,
 205 };
 206
 207 static const struct intel_device_info intel_sandybridge_m_info = {
 208         GEN6_FEATURES,
 209         .is_mobile = 1,
 210 };
 211
 212 #define GEN7_FEATURES  \
 213         .gen = 7, .num_pipes = 3, \
 214         .need_gfx_hws = 1, .has_hotplug = 1, \
 215         .has_fbc = 1, \
 216         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 217         .has_llc = 1, \
 218         .has_rc6 = 1, \
 219         .has_rc6p = 1, \
 220         .has_gmbus_irq = 1, \
 221         .has_hw_contexts = 1, \
 222         GEN_DEFAULT_PIPEOFFSETS, \
 223         IVB_CURSOR_OFFSETS
 224
 225 static const struct intel_device_info intel_ivybridge_d_info = {
 226         GEN7_FEATURES,
 227         .is_ivybridge = 1,
 228         .has_l3_dpf = 1,
 229 };
 230
 231 static const struct intel_device_info intel_ivybridge_m_info = {
 232         GEN7_FEATURES,
 233         .is_ivybridge = 1,
 234         .is_mobile = 1,
 235         .has_l3_dpf = 1,
 236 };
 237
 238 static const struct intel_device_info intel_ivybridge_q_info = {
 239         GEN7_FEATURES,
 240         .is_ivybridge = 1,
 241         .num_pipes = 0, /* legal, last one wins */
 242         .has_l3_dpf = 1,
 243 };
 244
 245 #define VLV_FEATURES  \
 246         .gen = 7, .num_pipes = 2, \
 247         .has_psr = 1, \
 248         .has_runtime_pm = 1, \
 249         .has_rc6 = 1, \
 250         .has_gmbus_irq = 1, \
 251         .has_hw_contexts = 1, \
 252         .has_gmch_display = 1, \
 253         .need_gfx_hws = 1, .has_hotplug = 1, \
 254         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 255         .display_mmio_offset = VLV_DISPLAY_BASE, \
 256         GEN_DEFAULT_PIPEOFFSETS, \
 257         CURSOR_OFFSETS
 258
 259 static const struct intel_device_info intel_valleyview_info = {
 260         VLV_FEATURES,
 261         .is_valleyview = 1,
 262 };
 263
 264 #define HSW_FEATURES  \
 265         GEN7_FEATURES, \
 266         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 267         .has_ddi = 1, \
 268         .has_fpga_dbg = 1, \
 269         .has_psr = 1, \
 270         .has_resource_streamer = 1, \
 271         .has_dp_mst = 1, \
 272         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 273         .has_runtime_pm = 1
 274
 275 static const struct intel_device_info intel_haswell_info = {
 276         HSW_FEATURES,
 277         .is_haswell = 1,
 278         .has_l3_dpf = 1,
 279 };
 280
 281 #define BDW_FEATURES \
 282         HSW_FEATURES, \
 283         BDW_COLORS, \
 284         .has_logical_ring_contexts = 1
 285
 286 static const struct intel_device_info intel_broadwell_info = {
 287         BDW_FEATURES,
 288         .gen = 8,
 289         .is_broadwell = 1,
 290 };
 291
 292 static const struct intel_device_info intel_broadwell_gt3_info = {
 293         BDW_FEATURES,
 294         .gen = 8,
 295         .is_broadwell = 1,
 296         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 297 };
 298
 299 static const struct intel_device_info intel_cherryview_info = {
 300         .gen = 8, .num_pipes = 3,
 301         .need_gfx_hws = 1, .has_hotplug = 1,
 302         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 303         .is_cherryview = 1,
 304         .has_psr = 1,
 305         .has_runtime_pm = 1,
 306         .has_resource_streamer = 1,
 307         .has_rc6 = 1,
 308         .has_gmbus_irq = 1,
 309         .has_hw_contexts = 1,
 310         .has_logical_ring_contexts = 1,
 311         .has_gmch_display = 1,
 312         .display_mmio_offset = VLV_DISPLAY_BASE,
 313         GEN_CHV_PIPEOFFSETS,
 314         CURSOR_OFFSETS,
 315         CHV_COLORS,
 316 };
 317
 318 static const struct intel_device_info intel_skylake_info = {
 319         BDW_FEATURES,
 320         .is_skylake = 1,
 321         .gen = 9,
 322         .has_csr = 1,
 323 };
 324
 325 static const struct intel_device_info intel_skylake_gt3_info = {
 326         BDW_FEATURES,
 327         .is_skylake = 1,
 328         .gen = 9,
 329         .has_csr = 1,
 330         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 331 };
 332
 333 static const struct intel_device_info intel_broxton_info = {
 334         .is_broxton = 1,
 335         .gen = 9,
 336         .need_gfx_hws = 1, .has_hotplug = 1,
 337         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 338         .num_pipes = 3,
 339         .has_ddi = 1,
 340         .has_fpga_dbg = 1,
 341         .has_fbc = 1,
 342         .has_runtime_pm = 1,
 343         .has_pooled_eu = 0,
 344         .has_csr = 1,
 345         .has_resource_streamer = 1,
 346         .has_rc6 = 1,
 347         .has_dp_mst = 1,
 348         .has_gmbus_irq = 1,
 349         .has_hw_contexts = 1,
 350         .has_logical_ring_contexts = 1,
 351         GEN_DEFAULT_PIPEOFFSETS,
 352         IVB_CURSOR_OFFSETS,
 353         BDW_COLORS,
 354 };
 355
 356 static const struct intel_device_info intel_kabylake_info = {
 357         BDW_FEATURES,
 358         .is_kabylake = 1,
 359         .gen = 9,
 360         .has_csr = 1,
 361 };
 362
 363 static const struct intel_device_info intel_kabylake_gt3_info = {
 364         BDW_FEATURES,
 365         .is_kabylake = 1,
 366         .gen = 9,
 367         .has_csr = 1,
 368         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 369 };
 370
 371 /*
 372  * Make sure any device matches here are from most specific to most
 373  * general.  For example, since the Quanta match is based on the subsystem
 374  * and subvendor IDs, we need it to come before the more general IVB
 375  * PCI ID matches, otherwise we'll use the wrong info struct above.
 376  */
 377 static const struct pci_device_id pciidlist[] = {
 378         INTEL_I830_IDS(&intel_i830_info),
 379         INTEL_I845G_IDS(&intel_845g_info),
 380         INTEL_I85X_IDS(&intel_i85x_info),
 381         INTEL_I865G_IDS(&intel_i865g_info),
 382         INTEL_I915G_IDS(&intel_i915g_info),
 383         INTEL_I915GM_IDS(&intel_i915gm_info),
 384         INTEL_I945G_IDS(&intel_i945g_info),
 385         INTEL_I945GM_IDS(&intel_i945gm_info),
 386         INTEL_I965G_IDS(&intel_i965g_info),
 387         INTEL_G33_IDS(&intel_g33_info),
 388         INTEL_I965GM_IDS(&intel_i965gm_info),
 389         INTEL_GM45_IDS(&intel_gm45_info),
 390         INTEL_G45_IDS(&intel_g45_info),
 391         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 392         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 393         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 394         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
 395         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
 396         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 397         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 398         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
 399         INTEL_HSW_IDS(&intel_haswell_info),
 400         INTEL_VLV_IDS(&intel_valleyview_info),
 401         INTEL_BDW_GT12_IDS(&intel_broadwell_info),
 402         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 403         INTEL_CHV_IDS(&intel_cherryview_info),
 404         INTEL_SKL_GT1_IDS(&intel_skylake_info),
 405         INTEL_SKL_GT2_IDS(&intel_skylake_info),
 406         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 407         INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
 408         INTEL_BXT_IDS(&intel_broxton_info),
 409         INTEL_KBL_GT1_IDS(&intel_kabylake_info),
 410         INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 411         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 412         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 413         {0, 0, 0}
 414 };
 415 MODULE_DEVICE_TABLE(pci, pciidlist);
 416
 417 extern int i915_driver_load(struct pci_dev *pdev,
 418                             const struct pci_device_id *ent);
 419
 420 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 421 {
 422         struct intel_device_info *intel_info =
 423                 (struct intel_device_info *) ent->driver_data;
 424
 425         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 426                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 427                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 428                 return -ENODEV;
 429         }
 430
 431         /* Only bind to function 0 of the device. Early generations
 432          * used function 1 as a placeholder for multi-head. This causes
 433          * us confusion instead, especially on the systems where both
 434          * functions have the same PCI-ID!
 435          */
 436         if (PCI_FUNC(pdev->devfn))
 437                 return -ENODEV;
 438
 439         /*
 440          * apple-gmux is needed on dual GPU MacBook Pro
 441          * to probe the panel if we're the inactive GPU.
 442          */
 443         if (vga_switcheroo_client_probe_defer(pdev))
 444                 return -EPROBE_DEFER;
 445
 446         return i915_driver_load(pdev, ent);
 447 }
 448
 449 extern void i915_driver_unload(struct drm_device *dev);
 450
 451 static void i915_pci_remove(struct pci_dev *pdev)
 452 {
 453         struct drm_device *dev = pci_get_drvdata(pdev);
 454
 455         i915_driver_unload(dev);
 456         drm_dev_unref(dev);
 457 }
 458
 459 extern const struct dev_pm_ops i915_pm_ops;
 460
 461 static struct pci_driver i915_pci_driver = {
 462         .name = DRIVER_NAME,
 463         .id_table = pciidlist,
 464         .probe = i915_pci_probe,
 465         .remove = i915_pci_remove,
 466         .driver.pm = &i915_pm_ops,
 467 };
 468
 469 static int __init i915_init(void)
 470 {
 471         bool use_kms = true;
 472
 473         /*
 474          * Enable KMS by default, unless explicitly overriden by
 475          * either the i915.modeset prarameter or by the
 476          * vga_text_mode_force boot option.
 477          */
 478
 479         if (i915.modeset == 0)
 480                 use_kms = false;
 481
 482         if (vgacon_text_force() && i915.modeset == -1)
 483                 use_kms = false;
 484
 485         if (!use_kms) {
 486                 /* Silently fail loading to not upset userspace. */
 487                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 488                 return 0;
 489         }
 490
 491         return pci_register_driver(&i915_pci_driver);
 492 }
 493
 494 static void __exit i915_exit(void)
 495 {
 496         if (!i915_pci_driver.driver.owner)
 497                 return;
 498
 499         pci_unregister_driver(&i915_pci_driver);
 500 }
 501
 502 module_init(i915_init);
 503 module_exit(i915_exit);
 504
 505 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 506 MODULE_AUTHOR("Intel Corporation");
 507
 508 MODULE_DESCRIPTION(DRIVER_DESC);
 509 MODULE_LICENSE("GPL and additional rights");