drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* For display hotplug interrupt */
  41 static void
  42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  43 {
  44         if ((dev_priv->irq_mask & mask) != 0) {
  45                 dev_priv->irq_mask &= ~mask;
  46                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  47                 POSTING_READ(DEIMR);
  48         }
  49 }
  50
  51 static inline void
  52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  53 {
  54         if ((dev_priv->irq_mask & mask) != mask) {
  55                 dev_priv->irq_mask |= mask;
  56                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  57                 POSTING_READ(DEIMR);
  58         }
  59 }
  60
  61 void
  62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  63 {
  64         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  65                 u32 reg = PIPESTAT(pipe);
  66
  67                 dev_priv->pipestat[pipe] |= mask;
  68                 /* Enable the interrupt, clear any pending status */
  69                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  70                 POSTING_READ(reg);
  71         }
  72 }
  73
  74 void
  75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  76 {
  77         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  78                 u32 reg = PIPESTAT(pipe);
  79
  80                 dev_priv->pipestat[pipe] &= ~mask;
  81                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  82                 POSTING_READ(reg);
  83         }
  84 }
  85
  86 /**
  87  * intel_enable_asle - enable ASLE interrupt for OpRegion
  88  */
  89 void intel_enable_asle(struct drm_device *dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         unsigned long irqflags;
  93
  94         /* FIXME: opregion/asle for VLV */
  95         if (IS_VALLEYVIEW(dev))
  96                 return;
  97
  98         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  99
 100         if (HAS_PCH_SPLIT(dev))
 101                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 102         else {
 103                 i915_enable_pipestat(dev_priv, 1,
 104                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 105                 if (INTEL_INFO(dev)->gen >= 4)
 106                         i915_enable_pipestat(dev_priv, 0,
 107                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 108         }
 109
 110         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 111 }
 112
 113 /**
 114  * i915_pipe_enabled - check if a pipe is enabled
 115  * @dev: DRM device
 116  * @pipe: pipe to check
 117  *
 118  * Reading certain registers when the pipe is disabled can hang the chip.
 119  * Use this routine to make sure the PLL is running and the pipe is active
 120  * before reading such registers if unsure.
 121  */
 122 static int
 123 i915_pipe_enabled(struct drm_device *dev, int pipe)
 124 {
 125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 126         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 127 }
 128
 129 /* Called from drm generic code, passed a 'crtc', which
 130  * we use as a pipe index
 131  */
 132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 133 {
 134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 135         unsigned long high_frame;
 136         unsigned long low_frame;
 137         u32 high1, high2, low;
 138
 139         if (!i915_pipe_enabled(dev, pipe)) {
 140                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 141                                 "pipe %c\n", pipe_name(pipe));
 142                 return 0;
 143         }
 144
 145         high_frame = PIPEFRAME(pipe);
 146         low_frame = PIPEFRAMEPIXEL(pipe);
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 155                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 156                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157         } while (high1 != high2);
 158
 159         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 160         low >>= PIPE_FRAME_LOW_SHIFT;
 161         return (high1 << 8) | low;
 162 }
 163
 164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 165 {
 166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 167         int reg = PIPE_FRMCOUNT_GM45(pipe);
 168
 169         if (!i915_pipe_enabled(dev, pipe)) {
 170                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 171                                  "pipe %c\n", pipe_name(pipe));
 172                 return 0;
 173         }
 174
 175         return I915_READ(reg);
 176 }
 177
 178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 179                              int *vpos, int *hpos)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         u32 vbl = 0, position = 0;
 183         int vbl_start, vbl_end, htotal, vtotal;
 184         bool in_vbl = true;
 185         int ret = 0;
 186
 187         if (!i915_pipe_enabled(dev, pipe)) {
 188                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 189                                  "pipe %c\n", pipe_name(pipe));
 190                 return 0;
 191         }
 192
 193         /* Get vtotal. */
 194         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 195
 196         if (INTEL_INFO(dev)->gen >= 4) {
 197                 /* No obvious pixelcount register. Only query vertical
 198                  * scanout position from Display scan line register.
 199                  */
 200                 position = I915_READ(PIPEDSL(pipe));
 201
 202                 /* Decode into vertical scanout position. Don't have
 203                  * horizontal scanout position.
 204                  */
 205                 *vpos = position & 0x1fff;
 206                 *hpos = 0;
 207         } else {
 208                 /* Have access to pixelcount since start of frame.
 209                  * We can split this into vertical and horizontal
 210                  * scanout position.
 211                  */
 212                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 213
 214                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 215                 *vpos = position / htotal;
 216                 *hpos = position - (*vpos * htotal);
 217         }
 218
 219         /* Query vblank area. */
 220         vbl = I915_READ(VBLANK(pipe));
 221
 222         /* Test position against vblank region. */
 223         vbl_start = vbl & 0x1fff;
 224         vbl_end = (vbl >> 16) & 0x1fff;
 225
 226         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 227                 in_vbl = false;
 228
 229         /* Inside "upper part" of vblank area? Apply corrective offset: */
 230         if (in_vbl && (*vpos >= vbl_start))
 231                 *vpos = *vpos - vtotal;
 232
 233         /* Readouts valid? */
 234         if (vbl > 0)
 235                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 236
 237         /* In vblank? */
 238         if (in_vbl)
 239                 ret |= DRM_SCANOUTPOS_INVBL;
 240
 241         return ret;
 242 }
 243
 244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 245                               int *max_error,
 246                               struct timeval *vblank_time,
 247                               unsigned flags)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         struct drm_crtc *crtc;
 251
 252         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 253                 DRM_ERROR("Invalid crtc %d\n", pipe);
 254                 return -EINVAL;
 255         }
 256
 257         /* Get drm_crtc to timestamp: */
 258         crtc = intel_get_crtc_for_pipe(dev, pipe);
 259         if (crtc == NULL) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         if (!crtc->enabled) {
 265                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 266                 return -EBUSY;
 267         }
 268
 269         /* Helper routine in DRM core does all the work: */
 270         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 271                                                      vblank_time, flags,
 272                                                      crtc);
 273 }
 274
 275 /*
 276  * Handle hotplug events outside the interrupt handler proper.
 277  */
 278 static void i915_hotplug_work_func(struct work_struct *work)
 279 {
 280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 281                                                     hotplug_work);
 282         struct drm_device *dev = dev_priv->dev;
 283         struct drm_mode_config *mode_config = &dev->mode_config;
 284         struct intel_encoder *encoder;
 285
 286         mutex_lock(&mode_config->mutex);
 287         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 288
 289         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 290                 if (encoder->hot_plug)
 291                         encoder->hot_plug(encoder);
 292
 293         mutex_unlock(&mode_config->mutex);
 294
 295         /* Just fire off a uevent and let userspace tell us what to do */
 296         drm_helper_hpd_irq_event(dev);
 297 }
 298
 299 static void i915_handle_rps_change(struct drm_device *dev)
 300 {
 301         drm_i915_private_t *dev_priv = dev->dev_private;
 302         u32 busy_up, busy_down, max_avg, min_avg;
 303         u8 new_delay = dev_priv->cur_delay;
 304
 305         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 306         busy_up = I915_READ(RCPREVBSYTUPAVG);
 307         busy_down = I915_READ(RCPREVBSYTDNAVG);
 308         max_avg = I915_READ(RCBMAXAVG);
 309         min_avg = I915_READ(RCBMINAVG);
 310
 311         /* Handle RCS change request from hw */
 312         if (busy_up > max_avg) {
 313                 if (dev_priv->cur_delay != dev_priv->max_delay)
 314                         new_delay = dev_priv->cur_delay - 1;
 315                 if (new_delay < dev_priv->max_delay)
 316                         new_delay = dev_priv->max_delay;
 317         } else if (busy_down < min_avg) {
 318                 if (dev_priv->cur_delay != dev_priv->min_delay)
 319                         new_delay = dev_priv->cur_delay + 1;
 320                 if (new_delay > dev_priv->min_delay)
 321                         new_delay = dev_priv->min_delay;
 322         }
 323
 324         if (ironlake_set_drps(dev, new_delay))
 325                 dev_priv->cur_delay = new_delay;
 326
 327         return;
 328 }
 329
 330 static void notify_ring(struct drm_device *dev,
 331                         struct intel_ring_buffer *ring)
 332 {
 333         struct drm_i915_private *dev_priv = dev->dev_private;
 334
 335         if (ring->obj == NULL)
 336                 return;
 337
 338         trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
 339
 340         wake_up_all(&ring->irq_queue);
 341         if (i915_enable_hangcheck) {
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer,
 344                           jiffies +
 345                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 346         }
 347 }
 348
 349 static void gen6_pm_rps_work(struct work_struct *work)
 350 {
 351         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 352                                                     rps_work);
 353         u32 pm_iir, pm_imr;
 354         u8 new_delay;
 355
 356         spin_lock_irq(&dev_priv->rps_lock);
 357         pm_iir = dev_priv->pm_iir;
 358         dev_priv->pm_iir = 0;
 359         pm_imr = I915_READ(GEN6_PMIMR);
 360         I915_WRITE(GEN6_PMIMR, 0);
 361         spin_unlock_irq(&dev_priv->rps_lock);
 362
 363         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 364                 return;
 365
 366         mutex_lock(&dev_priv->dev->struct_mutex);
 367
 368         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 369                 new_delay = dev_priv->cur_delay + 1;
 370         else
 371                 new_delay = dev_priv->cur_delay - 1;
 372
 373         gen6_set_rps(dev_priv->dev, new_delay);
 374
 375         mutex_unlock(&dev_priv->dev->struct_mutex);
 376 }
 377
 378
 379 /**
 380  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 381  * occurred.
 382  * @work: workqueue struct
 383  *
 384  * Doesn't actually do anything except notify userspace. As a consequence of
 385  * this event, userspace should try to remap the bad rows since statistically
 386  * it is likely the same row is more likely to go bad again.
 387  */
 388 static void ivybridge_parity_work(struct work_struct *work)
 389 {
 390         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 391                                                     parity_error_work);
 392         u32 error_status, row, bank, subbank;
 393         char *parity_event[5];
 394         uint32_t misccpctl;
 395         unsigned long flags;
 396
 397         /* We must turn off DOP level clock gating to access the L3 registers.
 398          * In order to prevent a get/put style interface, acquire struct mutex
 399          * any time we access those registers.
 400          */
 401         mutex_lock(&dev_priv->dev->struct_mutex);
 402
 403         misccpctl = I915_READ(GEN7_MISCCPCTL);
 404         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 405         POSTING_READ(GEN7_MISCCPCTL);
 406
 407         error_status = I915_READ(GEN7_L3CDERRST1);
 408         row = GEN7_PARITY_ERROR_ROW(error_status);
 409         bank = GEN7_PARITY_ERROR_BANK(error_status);
 410         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 411
 412         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 413                                     GEN7_L3CDERRST1_ENABLE);
 414         POSTING_READ(GEN7_L3CDERRST1);
 415
 416         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 417
 418         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 419         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 420         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 421         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 422
 423         mutex_unlock(&dev_priv->dev->struct_mutex);
 424
 425         parity_event[0] = "L3_PARITY_ERROR=1";
 426         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 427         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 428         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 429         parity_event[4] = NULL;
 430
 431         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 432                            KOBJ_CHANGE, parity_event);
 433
 434         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 435                   row, bank, subbank);
 436
 437         kfree(parity_event[3]);
 438         kfree(parity_event[2]);
 439         kfree(parity_event[1]);
 440 }
 441
 442 static void ivybridge_handle_parity_error(struct drm_device *dev)
 443 {
 444         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 445         unsigned long flags;
 446
 447         if (!IS_IVYBRIDGE(dev))
 448                 return;
 449
 450         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 451         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 452         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 453         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 454
 455         queue_work(dev_priv->wq, &dev_priv->parity_error_work);
 456 }
 457
 458 static void snb_gt_irq_handler(struct drm_device *dev,
 459                                struct drm_i915_private *dev_priv,
 460                                u32 gt_iir)
 461 {
 462
 463         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 464                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 465                 notify_ring(dev, &dev_priv->ring[RCS]);
 466         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 467                 notify_ring(dev, &dev_priv->ring[VCS]);
 468         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 469                 notify_ring(dev, &dev_priv->ring[BCS]);
 470
 471         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 472                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 473                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 474                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 475                 i915_handle_error(dev, false);
 476         }
 477
 478         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 479                 ivybridge_handle_parity_error(dev);
 480 }
 481
 482 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 483                                 u32 pm_iir)
 484 {
 485         unsigned long flags;
 486
 487         /*
 488          * IIR bits should never already be set because IMR should
 489          * prevent an interrupt from being shown in IIR. The warning
 490          * displays a case where we've unsafely cleared
 491          * dev_priv->pm_iir. Although missing an interrupt of the same
 492          * type is not a problem, it displays a problem in the logic.
 493          *
 494          * The mask bit in IMR is cleared by rps_work.
 495          */
 496
 497         spin_lock_irqsave(&dev_priv->rps_lock, flags);
 498         dev_priv->pm_iir |= pm_iir;
 499         I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 500         POSTING_READ(GEN6_PMIMR);
 501         spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 502
 503         queue_work(dev_priv->wq, &dev_priv->rps_work);
 504 }
 505
 506 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
 507 {
 508         struct drm_device *dev = (struct drm_device *) arg;
 509         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 510         u32 iir, gt_iir, pm_iir;
 511         irqreturn_t ret = IRQ_NONE;
 512         unsigned long irqflags;
 513         int pipe;
 514         u32 pipe_stats[I915_MAX_PIPES];
 515         bool blc_event;
 516
 517         atomic_inc(&dev_priv->irq_received);
 518
 519         while (true) {
 520                 iir = I915_READ(VLV_IIR);
 521                 gt_iir = I915_READ(GTIIR);
 522                 pm_iir = I915_READ(GEN6_PMIIR);
 523
 524                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 525                         goto out;
 526
 527                 ret = IRQ_HANDLED;
 528
 529                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 530
 531                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 532                 for_each_pipe(pipe) {
 533                         int reg = PIPESTAT(pipe);
 534                         pipe_stats[pipe] = I915_READ(reg);
 535
 536                         /*
 537                          * Clear the PIPE*STAT regs before the IIR
 538                          */
 539                         if (pipe_stats[pipe] & 0x8000ffff) {
 540                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 541                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 542                                                          pipe_name(pipe));
 543                                 I915_WRITE(reg, pipe_stats[pipe]);
 544                         }
 545                 }
 546                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 547
 548                 for_each_pipe(pipe) {
 549                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 550                                 drm_handle_vblank(dev, pipe);
 551
 552                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 553                                 intel_prepare_page_flip(dev, pipe);
 554                                 intel_finish_page_flip(dev, pipe);
 555                         }
 556                 }
 557
 558                 /* Consume port.  Then clear IIR or we'll miss events */
 559                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 560                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 561
 562                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 563                                          hotplug_status);
 564                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 565                                 queue_work(dev_priv->wq,
 566                                            &dev_priv->hotplug_work);
 567
 568                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 569                         I915_READ(PORT_HOTPLUG_STAT);
 570                 }
 571
 572                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 573                         blc_event = true;
 574
 575                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 576                         gen6_queue_rps_work(dev_priv, pm_iir);
 577
 578                 I915_WRITE(GTIIR, gt_iir);
 579                 I915_WRITE(GEN6_PMIIR, pm_iir);
 580                 I915_WRITE(VLV_IIR, iir);
 581         }
 582
 583 out:
 584         return ret;
 585 }
 586
 587 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 588 {
 589         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 590         int pipe;
 591
 592         if (pch_iir & SDE_AUDIO_POWER_MASK)
 593                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 594                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 595                                  SDE_AUDIO_POWER_SHIFT);
 596
 597         if (pch_iir & SDE_GMBUS)
 598                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 599
 600         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 601                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 602
 603         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 604                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 605
 606         if (pch_iir & SDE_POISON)
 607                 DRM_ERROR("PCH poison interrupt\n");
 608
 609         if (pch_iir & SDE_FDI_MASK)
 610                 for_each_pipe(pipe)
 611                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 612                                          pipe_name(pipe),
 613                                          I915_READ(FDI_RX_IIR(pipe)));
 614
 615         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 616                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 617
 618         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 619                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 620
 621         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 622                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 623         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 624                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 625 }
 626
 627 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 628 {
 629         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 630         int pipe;
 631
 632         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 633                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 634                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 635                                  SDE_AUDIO_POWER_SHIFT_CPT);
 636
 637         if (pch_iir & SDE_AUX_MASK_CPT)
 638                 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 639
 640         if (pch_iir & SDE_GMBUS_CPT)
 641                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 642
 643         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 644                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 645
 646         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 647                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 648
 649         if (pch_iir & SDE_FDI_MASK_CPT)
 650                 for_each_pipe(pipe)
 651                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 652                                          pipe_name(pipe),
 653                                          I915_READ(FDI_RX_IIR(pipe)));
 654 }
 655
 656 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 657 {
 658         struct drm_device *dev = (struct drm_device *) arg;
 659         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 660         u32 de_iir, gt_iir, de_ier, pm_iir;
 661         irqreturn_t ret = IRQ_NONE;
 662         int i;
 663
 664         atomic_inc(&dev_priv->irq_received);
 665
 666         /* disable master interrupt before clearing iir  */
 667         de_ier = I915_READ(DEIER);
 668         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 669
 670         gt_iir = I915_READ(GTIIR);
 671         if (gt_iir) {
 672                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 673                 I915_WRITE(GTIIR, gt_iir);
 674                 ret = IRQ_HANDLED;
 675         }
 676
 677         de_iir = I915_READ(DEIIR);
 678         if (de_iir) {
 679                 if (de_iir & DE_GSE_IVB)
 680                         intel_opregion_gse_intr(dev);
 681
 682                 for (i = 0; i < 3; i++) {
 683                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 684                                 intel_prepare_page_flip(dev, i);
 685                                 intel_finish_page_flip_plane(dev, i);
 686                         }
 687                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 688                                 drm_handle_vblank(dev, i);
 689                 }
 690
 691                 /* check event from PCH */
 692                 if (de_iir & DE_PCH_EVENT_IVB) {
 693                         u32 pch_iir = I915_READ(SDEIIR);
 694
 695                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 696                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 697                         cpt_irq_handler(dev, pch_iir);
 698
 699                         /* clear PCH hotplug event before clear CPU irq */
 700                         I915_WRITE(SDEIIR, pch_iir);
 701                 }
 702
 703                 I915_WRITE(DEIIR, de_iir);
 704                 ret = IRQ_HANDLED;
 705         }
 706
 707         pm_iir = I915_READ(GEN6_PMIIR);
 708         if (pm_iir) {
 709                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 710                         gen6_queue_rps_work(dev_priv, pm_iir);
 711                 I915_WRITE(GEN6_PMIIR, pm_iir);
 712                 ret = IRQ_HANDLED;
 713         }
 714
 715         I915_WRITE(DEIER, de_ier);
 716         POSTING_READ(DEIER);
 717
 718         return ret;
 719 }
 720
 721 static void ilk_gt_irq_handler(struct drm_device *dev,
 722                                struct drm_i915_private *dev_priv,
 723                                u32 gt_iir)
 724 {
 725         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 726                 notify_ring(dev, &dev_priv->ring[RCS]);
 727         if (gt_iir & GT_BSD_USER_INTERRUPT)
 728                 notify_ring(dev, &dev_priv->ring[VCS]);
 729 }
 730
 731 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 732 {
 733         struct drm_device *dev = (struct drm_device *) arg;
 734         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 735         int ret = IRQ_NONE;
 736         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 737         u32 hotplug_mask;
 738
 739         atomic_inc(&dev_priv->irq_received);
 740
 741         /* disable master interrupt before clearing iir  */
 742         de_ier = I915_READ(DEIER);
 743         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 744         POSTING_READ(DEIER);
 745
 746         de_iir = I915_READ(DEIIR);
 747         gt_iir = I915_READ(GTIIR);
 748         pch_iir = I915_READ(SDEIIR);
 749         pm_iir = I915_READ(GEN6_PMIIR);
 750
 751         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 752             (!IS_GEN6(dev) || pm_iir == 0))
 753                 goto done;
 754
 755         if (HAS_PCH_CPT(dev))
 756                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 757         else
 758                 hotplug_mask = SDE_HOTPLUG_MASK;
 759
 760         ret = IRQ_HANDLED;
 761
 762         if (IS_GEN5(dev))
 763                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 764         else
 765                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 766
 767         if (de_iir & DE_GSE)
 768                 intel_opregion_gse_intr(dev);
 769
 770         if (de_iir & DE_PLANEA_FLIP_DONE) {
 771                 intel_prepare_page_flip(dev, 0);
 772                 intel_finish_page_flip_plane(dev, 0);
 773         }
 774
 775         if (de_iir & DE_PLANEB_FLIP_DONE) {
 776                 intel_prepare_page_flip(dev, 1);
 777                 intel_finish_page_flip_plane(dev, 1);
 778         }
 779
 780         if (de_iir & DE_PIPEA_VBLANK)
 781                 drm_handle_vblank(dev, 0);
 782
 783         if (de_iir & DE_PIPEB_VBLANK)
 784                 drm_handle_vblank(dev, 1);
 785
 786         /* check event from PCH */
 787         if (de_iir & DE_PCH_EVENT) {
 788                 if (pch_iir & hotplug_mask)
 789                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 790                 if (HAS_PCH_CPT(dev))
 791                         cpt_irq_handler(dev, pch_iir);
 792                 else
 793                         ibx_irq_handler(dev, pch_iir);
 794         }
 795
 796         if (de_iir & DE_PCU_EVENT) {
 797                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 798                 i915_handle_rps_change(dev);
 799         }
 800
 801         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 802                 gen6_queue_rps_work(dev_priv, pm_iir);
 803
 804         /* should clear PCH hotplug event before clear CPU irq */
 805         I915_WRITE(SDEIIR, pch_iir);
 806         I915_WRITE(GTIIR, gt_iir);
 807         I915_WRITE(DEIIR, de_iir);
 808         I915_WRITE(GEN6_PMIIR, pm_iir);
 809
 810 done:
 811         I915_WRITE(DEIER, de_ier);
 812         POSTING_READ(DEIER);
 813
 814         return ret;
 815 }
 816
 817 /**
 818  * i915_error_work_func - do process context error handling work
 819  * @work: work struct
 820  *
 821  * Fire an error uevent so userspace can see that a hang or error
 822  * was detected.
 823  */
 824 static void i915_error_work_func(struct work_struct *work)
 825 {
 826         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 827                                                     error_work);
 828         struct drm_device *dev = dev_priv->dev;
 829         char *error_event[] = { "ERROR=1", NULL };
 830         char *reset_event[] = { "RESET=1", NULL };
 831         char *reset_done_event[] = { "ERROR=0", NULL };
 832
 833         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 834
 835         if (atomic_read(&dev_priv->mm.wedged)) {
 836                 DRM_DEBUG_DRIVER("resetting chip\n");
 837                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 838                 if (!i915_reset(dev)) {
 839                         atomic_set(&dev_priv->mm.wedged, 0);
 840                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 841                 }
 842                 complete_all(&dev_priv->error_completion);
 843         }
 844 }
 845
 846 #ifdef CONFIG_DEBUG_FS
 847 static struct drm_i915_error_object *
 848 i915_error_object_create(struct drm_i915_private *dev_priv,
 849                          struct drm_i915_gem_object *src)
 850 {
 851         struct drm_i915_error_object *dst;
 852         int page, page_count;
 853         u32 reloc_offset;
 854
 855         if (src == NULL || src->pages == NULL)
 856                 return NULL;
 857
 858         page_count = src->base.size / PAGE_SIZE;
 859
 860         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 861         if (dst == NULL)
 862                 return NULL;
 863
 864         reloc_offset = src->gtt_offset;
 865         for (page = 0; page < page_count; page++) {
 866                 unsigned long flags;
 867                 void *d;
 868
 869                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 870                 if (d == NULL)
 871                         goto unwind;
 872
 873                 local_irq_save(flags);
 874                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 875                     src->has_global_gtt_mapping) {
 876                         void __iomem *s;
 877
 878                         /* Simply ignore tiling or any overlapping fence.
 879                          * It's part of the error state, and this hopefully
 880                          * captures what the GPU read.
 881                          */
 882
 883                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 884                                                      reloc_offset);
 885                         memcpy_fromio(d, s, PAGE_SIZE);
 886                         io_mapping_unmap_atomic(s);
 887                 } else {
 888                         void *s;
 889
 890                         drm_clflush_pages(&src->pages[page], 1);
 891
 892                         s = kmap_atomic(src->pages[page]);
 893                         memcpy(d, s, PAGE_SIZE);
 894                         kunmap_atomic(s);
 895
 896                         drm_clflush_pages(&src->pages[page], 1);
 897                 }
 898                 local_irq_restore(flags);
 899
 900                 dst->pages[page] = d;
 901
 902                 reloc_offset += PAGE_SIZE;
 903         }
 904         dst->page_count = page_count;
 905         dst->gtt_offset = src->gtt_offset;
 906
 907         return dst;
 908
 909 unwind:
 910         while (page--)
 911                 kfree(dst->pages[page]);
 912         kfree(dst);
 913         return NULL;
 914 }
 915
 916 static void
 917 i915_error_object_free(struct drm_i915_error_object *obj)
 918 {
 919         int page;
 920
 921         if (obj == NULL)
 922                 return;
 923
 924         for (page = 0; page < obj->page_count; page++)
 925                 kfree(obj->pages[page]);
 926
 927         kfree(obj);
 928 }
 929
 930 void
 931 i915_error_state_free(struct kref *error_ref)
 932 {
 933         struct drm_i915_error_state *error = container_of(error_ref,
 934                                                           typeof(*error), ref);
 935         int i;
 936
 937         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 938                 i915_error_object_free(error->ring[i].batchbuffer);
 939                 i915_error_object_free(error->ring[i].ringbuffer);
 940                 kfree(error->ring[i].requests);
 941         }
 942
 943         kfree(error->active_bo);
 944         kfree(error->overlay);
 945         kfree(error);
 946 }
 947 static void capture_bo(struct drm_i915_error_buffer *err,
 948                        struct drm_i915_gem_object *obj)
 949 {
 950         err->size = obj->base.size;
 951         err->name = obj->base.name;
 952         err->seqno = obj->last_rendering_seqno;
 953         err->gtt_offset = obj->gtt_offset;
 954         err->read_domains = obj->base.read_domains;
 955         err->write_domain = obj->base.write_domain;
 956         err->fence_reg = obj->fence_reg;
 957         err->pinned = 0;
 958         if (obj->pin_count > 0)
 959                 err->pinned = 1;
 960         if (obj->user_pin_count > 0)
 961                 err->pinned = -1;
 962         err->tiling = obj->tiling_mode;
 963         err->dirty = obj->dirty;
 964         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 965         err->ring = obj->ring ? obj->ring->id : -1;
 966         err->cache_level = obj->cache_level;
 967 }
 968
 969 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 970                              int count, struct list_head *head)
 971 {
 972         struct drm_i915_gem_object *obj;
 973         int i = 0;
 974
 975         list_for_each_entry(obj, head, mm_list) {
 976                 capture_bo(err++, obj);
 977                 if (++i == count)
 978                         break;
 979         }
 980
 981         return i;
 982 }
 983
 984 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 985                              int count, struct list_head *head)
 986 {
 987         struct drm_i915_gem_object *obj;
 988         int i = 0;
 989
 990         list_for_each_entry(obj, head, gtt_list) {
 991                 if (obj->pin_count == 0)
 992                         continue;
 993
 994                 capture_bo(err++, obj);
 995                 if (++i == count)
 996                         break;
 997         }
 998
 999         return i;
1000 }
1001
1002 static void i915_gem_record_fences(struct drm_device *dev,
1003                                    struct drm_i915_error_state *error)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         int i;
1007
1008         /* Fences */
1009         switch (INTEL_INFO(dev)->gen) {
1010         case 7:
1011         case 6:
1012                 for (i = 0; i < 16; i++)
1013                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1014                 break;
1015         case 5:
1016         case 4:
1017                 for (i = 0; i < 16; i++)
1018                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1019                 break;
1020         case 3:
1021                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1022                         for (i = 0; i < 8; i++)
1023                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1024         case 2:
1025                 for (i = 0; i < 8; i++)
1026                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1027                 break;
1028
1029         }
1030 }
1031
1032 static struct drm_i915_error_object *
1033 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1034                              struct intel_ring_buffer *ring)
1035 {
1036         struct drm_i915_gem_object *obj;
1037         u32 seqno;
1038
1039         if (!ring->get_seqno)
1040                 return NULL;
1041
1042         seqno = ring->get_seqno(ring);
1043         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1044                 if (obj->ring != ring)
1045                         continue;
1046
1047                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
1048                         continue;
1049
1050                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1051                         continue;
1052
1053                 /* We need to copy these to an anonymous buffer as the simplest
1054                  * method to avoid being overwritten by userspace.
1055                  */
1056                 return i915_error_object_create(dev_priv, obj);
1057         }
1058
1059         return NULL;
1060 }
1061
1062 static void i915_record_ring_state(struct drm_device *dev,
1063                                    struct drm_i915_error_state *error,
1064                                    struct intel_ring_buffer *ring)
1065 {
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068         if (INTEL_INFO(dev)->gen >= 6) {
1069                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1070                 error->semaphore_mboxes[ring->id][0]
1071                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1072                 error->semaphore_mboxes[ring->id][1]
1073                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1074         }
1075
1076         if (INTEL_INFO(dev)->gen >= 4) {
1077                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1078                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1079                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1080                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1081                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1082                 if (ring->id == RCS) {
1083                         error->instdone1 = I915_READ(INSTDONE1);
1084                         error->bbaddr = I915_READ64(BB_ADDR);
1085                 }
1086         } else {
1087                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1088                 error->ipeir[ring->id] = I915_READ(IPEIR);
1089                 error->ipehr[ring->id] = I915_READ(IPEHR);
1090                 error->instdone[ring->id] = I915_READ(INSTDONE);
1091         }
1092
1093         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1094         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1095         error->seqno[ring->id] = ring->get_seqno(ring);
1096         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1097         error->head[ring->id] = I915_READ_HEAD(ring);
1098         error->tail[ring->id] = I915_READ_TAIL(ring);
1099
1100         error->cpu_ring_head[ring->id] = ring->head;
1101         error->cpu_ring_tail[ring->id] = ring->tail;
1102 }
1103
1104 static void i915_gem_record_rings(struct drm_device *dev,
1105                                   struct drm_i915_error_state *error)
1106 {
1107         struct drm_i915_private *dev_priv = dev->dev_private;
1108         struct intel_ring_buffer *ring;
1109         struct drm_i915_gem_request *request;
1110         int i, count;
1111
1112         for_each_ring(ring, dev_priv, i) {
1113                 i915_record_ring_state(dev, error, ring);
1114
1115                 error->ring[i].batchbuffer =
1116                         i915_error_first_batchbuffer(dev_priv, ring);
1117
1118                 error->ring[i].ringbuffer =
1119                         i915_error_object_create(dev_priv, ring->obj);
1120
1121                 count = 0;
1122                 list_for_each_entry(request, &ring->request_list, list)
1123                         count++;
1124
1125                 error->ring[i].num_requests = count;
1126                 error->ring[i].requests =
1127                         kmalloc(count*sizeof(struct drm_i915_error_request),
1128                                 GFP_ATOMIC);
1129                 if (error->ring[i].requests == NULL) {
1130                         error->ring[i].num_requests = 0;
1131                         continue;
1132                 }
1133
1134                 count = 0;
1135                 list_for_each_entry(request, &ring->request_list, list) {
1136                         struct drm_i915_error_request *erq;
1137
1138                         erq = &error->ring[i].requests[count++];
1139                         erq->seqno = request->seqno;
1140                         erq->jiffies = request->emitted_jiffies;
1141                         erq->tail = request->tail;
1142                 }
1143         }
1144 }
1145
1146 /**
1147  * i915_capture_error_state - capture an error record for later analysis
1148  * @dev: drm device
1149  *
1150  * Should be called when an error is detected (either a hang or an error
1151  * interrupt) to capture error state from the time of the error.  Fills
1152  * out a structure which becomes available in debugfs for user level tools
1153  * to pick up.
1154  */
1155 static void i915_capture_error_state(struct drm_device *dev)
1156 {
1157         struct drm_i915_private *dev_priv = dev->dev_private;
1158         struct drm_i915_gem_object *obj;
1159         struct drm_i915_error_state *error;
1160         unsigned long flags;
1161         int i, pipe;
1162
1163         spin_lock_irqsave(&dev_priv->error_lock, flags);
1164         error = dev_priv->first_error;
1165         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1166         if (error)
1167                 return;
1168
1169         /* Account for pipe specific data like PIPE*STAT */
1170         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1171         if (!error) {
1172                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1173                 return;
1174         }
1175
1176         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1177                  dev->primary->index);
1178
1179         kref_init(&error->ref);
1180         error->eir = I915_READ(EIR);
1181         error->pgtbl_er = I915_READ(PGTBL_ER);
1182         error->ccid = I915_READ(CCID);
1183
1184         if (HAS_PCH_SPLIT(dev))
1185                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1186         else if (IS_VALLEYVIEW(dev))
1187                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1188         else if (IS_GEN2(dev))
1189                 error->ier = I915_READ16(IER);
1190         else
1191                 error->ier = I915_READ(IER);
1192
1193         for_each_pipe(pipe)
1194                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1195
1196         if (INTEL_INFO(dev)->gen >= 6) {
1197                 error->error = I915_READ(ERROR_GEN6);
1198                 error->done_reg = I915_READ(DONE_REG);
1199         }
1200
1201         i915_gem_record_fences(dev, error);
1202         i915_gem_record_rings(dev, error);
1203
1204         /* Record buffers on the active and pinned lists. */
1205         error->active_bo = NULL;
1206         error->pinned_bo = NULL;
1207
1208         i = 0;
1209         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1210                 i++;
1211         error->active_bo_count = i;
1212         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1213                 if (obj->pin_count)
1214                         i++;
1215         error->pinned_bo_count = i - error->active_bo_count;
1216
1217         error->active_bo = NULL;
1218         error->pinned_bo = NULL;
1219         if (i) {
1220                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1221                                            GFP_ATOMIC);
1222                 if (error->active_bo)
1223                         error->pinned_bo =
1224                                 error->active_bo + error->active_bo_count;
1225         }
1226
1227         if (error->active_bo)
1228                 error->active_bo_count =
1229                         capture_active_bo(error->active_bo,
1230                                           error->active_bo_count,
1231                                           &dev_priv->mm.active_list);
1232
1233         if (error->pinned_bo)
1234                 error->pinned_bo_count =
1235                         capture_pinned_bo(error->pinned_bo,
1236                                           error->pinned_bo_count,
1237                                           &dev_priv->mm.gtt_list);
1238
1239         do_gettimeofday(&error->time);
1240
1241         error->overlay = intel_overlay_capture_error_state(dev);
1242         error->display = intel_display_capture_error_state(dev);
1243
1244         spin_lock_irqsave(&dev_priv->error_lock, flags);
1245         if (dev_priv->first_error == NULL) {
1246                 dev_priv->first_error = error;
1247                 error = NULL;
1248         }
1249         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1250
1251         if (error)
1252                 i915_error_state_free(&error->ref);
1253 }
1254
1255 void i915_destroy_error_state(struct drm_device *dev)
1256 {
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258         struct drm_i915_error_state *error;
1259         unsigned long flags;
1260
1261         spin_lock_irqsave(&dev_priv->error_lock, flags);
1262         error = dev_priv->first_error;
1263         dev_priv->first_error = NULL;
1264         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1265
1266         if (error)
1267                 kref_put(&error->ref, i915_error_state_free);
1268 }
1269 #else
1270 #define i915_capture_error_state(x)
1271 #endif
1272
1273 static void i915_report_and_clear_eir(struct drm_device *dev)
1274 {
1275         struct drm_i915_private *dev_priv = dev->dev_private;
1276         u32 eir = I915_READ(EIR);
1277         int pipe;
1278
1279         if (!eir)
1280                 return;
1281
1282         pr_err("render error detected, EIR: 0x%08x\n", eir);
1283
1284         if (IS_G4X(dev)) {
1285                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1286                         u32 ipeir = I915_READ(IPEIR_I965);
1287
1288                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1289                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1290                         pr_err("  INSTDONE: 0x%08x\n",
1291                                I915_READ(INSTDONE_I965));
1292                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1293                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1294                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1295                         I915_WRITE(IPEIR_I965, ipeir);
1296                         POSTING_READ(IPEIR_I965);
1297                 }
1298                 if (eir & GM45_ERROR_PAGE_TABLE) {
1299                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1300                         pr_err("page table error\n");
1301                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1302                         I915_WRITE(PGTBL_ER, pgtbl_err);
1303                         POSTING_READ(PGTBL_ER);
1304                 }
1305         }
1306
1307         if (!IS_GEN2(dev)) {
1308                 if (eir & I915_ERROR_PAGE_TABLE) {
1309                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1310                         pr_err("page table error\n");
1311                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1312                         I915_WRITE(PGTBL_ER, pgtbl_err);
1313                         POSTING_READ(PGTBL_ER);
1314                 }
1315         }
1316
1317         if (eir & I915_ERROR_MEMORY_REFRESH) {
1318                 pr_err("memory refresh error:\n");
1319                 for_each_pipe(pipe)
1320                         pr_err("pipe %c stat: 0x%08x\n",
1321                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1322                 /* pipestat has already been acked */
1323         }
1324         if (eir & I915_ERROR_INSTRUCTION) {
1325                 pr_err("instruction error\n");
1326                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1327                 if (INTEL_INFO(dev)->gen < 4) {
1328                         u32 ipeir = I915_READ(IPEIR);
1329
1330                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1331                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1332                         pr_err("  INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1333                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1334                         I915_WRITE(IPEIR, ipeir);
1335                         POSTING_READ(IPEIR);
1336                 } else {
1337                         u32 ipeir = I915_READ(IPEIR_I965);
1338
1339                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1340                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1341                         pr_err("  INSTDONE: 0x%08x\n",
1342                                I915_READ(INSTDONE_I965));
1343                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1344                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1345                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1346                         I915_WRITE(IPEIR_I965, ipeir);
1347                         POSTING_READ(IPEIR_I965);
1348                 }
1349         }
1350
1351         I915_WRITE(EIR, eir);
1352         POSTING_READ(EIR);
1353         eir = I915_READ(EIR);
1354         if (eir) {
1355                 /*
1356                  * some errors might have become stuck,
1357                  * mask them.
1358                  */
1359                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1360                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1361                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1362         }
1363 }
1364
1365 /**
1366  * i915_handle_error - handle an error interrupt
1367  * @dev: drm device
1368  *
1369  * Do some basic checking of regsiter state at error interrupt time and
1370  * dump it to the syslog.  Also call i915_capture_error_state() to make
1371  * sure we get a record and make it available in debugfs.  Fire a uevent
1372  * so userspace knows something bad happened (should trigger collection
1373  * of a ring dump etc.).
1374  */
1375 void i915_handle_error(struct drm_device *dev, bool wedged)
1376 {
1377         struct drm_i915_private *dev_priv = dev->dev_private;
1378         struct intel_ring_buffer *ring;
1379         int i;
1380
1381         i915_capture_error_state(dev);
1382         i915_report_and_clear_eir(dev);
1383
1384         if (wedged) {
1385                 INIT_COMPLETION(dev_priv->error_completion);
1386                 atomic_set(&dev_priv->mm.wedged, 1);
1387
1388                 /*
1389                  * Wakeup waiting processes so they don't hang
1390                  */
1391                 for_each_ring(ring, dev_priv, i)
1392                         wake_up_all(&ring->irq_queue);
1393         }
1394
1395         queue_work(dev_priv->wq, &dev_priv->error_work);
1396 }
1397
1398 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1399 {
1400         drm_i915_private_t *dev_priv = dev->dev_private;
1401         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1403         struct drm_i915_gem_object *obj;
1404         struct intel_unpin_work *work;
1405         unsigned long flags;
1406         bool stall_detected;
1407
1408         /* Ignore early vblank irqs */
1409         if (intel_crtc == NULL)
1410                 return;
1411
1412         spin_lock_irqsave(&dev->event_lock, flags);
1413         work = intel_crtc->unpin_work;
1414
1415         if (work == NULL || work->pending || !work->enable_stall_check) {
1416                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1417                 spin_unlock_irqrestore(&dev->event_lock, flags);
1418                 return;
1419         }
1420
1421         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1422         obj = work->pending_flip_obj;
1423         if (INTEL_INFO(dev)->gen >= 4) {
1424                 int dspsurf = DSPSURF(intel_crtc->plane);
1425                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1426                                         obj->gtt_offset;
1427         } else {
1428                 int dspaddr = DSPADDR(intel_crtc->plane);
1429                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1430                                                         crtc->y * crtc->fb->pitches[0] +
1431                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1432         }
1433
1434         spin_unlock_irqrestore(&dev->event_lock, flags);
1435
1436         if (stall_detected) {
1437                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1438                 intel_prepare_page_flip(dev, intel_crtc->plane);
1439         }
1440 }
1441
1442 /* Called from drm generic code, passed 'crtc' which
1443  * we use as a pipe index
1444  */
1445 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1446 {
1447         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1448         unsigned long irqflags;
1449
1450         if (!i915_pipe_enabled(dev, pipe))
1451                 return -EINVAL;
1452
1453         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1454         if (INTEL_INFO(dev)->gen >= 4)
1455                 i915_enable_pipestat(dev_priv, pipe,
1456                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1457         else
1458                 i915_enable_pipestat(dev_priv, pipe,
1459                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1460
1461         /* maintain vblank delivery even in deep C-states */
1462         if (dev_priv->info->gen == 3)
1463                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1464         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1465
1466         return 0;
1467 }
1468
1469 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1470 {
1471         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1472         unsigned long irqflags;
1473
1474         if (!i915_pipe_enabled(dev, pipe))
1475                 return -EINVAL;
1476
1477         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1478         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1479                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1480         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1481
1482         return 0;
1483 }
1484
1485 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1486 {
1487         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1488         unsigned long irqflags;
1489
1490         if (!i915_pipe_enabled(dev, pipe))
1491                 return -EINVAL;
1492
1493         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1494         ironlake_enable_display_irq(dev_priv,
1495                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1496         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1497
1498         return 0;
1499 }
1500
1501 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1502 {
1503         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1504         unsigned long irqflags;
1505         u32 imr;
1506
1507         if (!i915_pipe_enabled(dev, pipe))
1508                 return -EINVAL;
1509
1510         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1511         imr = I915_READ(VLV_IMR);
1512         if (pipe == 0)
1513                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1514         else
1515                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1516         I915_WRITE(VLV_IMR, imr);
1517         i915_enable_pipestat(dev_priv, pipe,
1518                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1519         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1520
1521         return 0;
1522 }
1523
1524 /* Called from drm generic code, passed 'crtc' which
1525  * we use as a pipe index
1526  */
1527 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1528 {
1529         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1530         unsigned long irqflags;
1531
1532         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1533         if (dev_priv->info->gen == 3)
1534                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1535
1536         i915_disable_pipestat(dev_priv, pipe,
1537                               PIPE_VBLANK_INTERRUPT_ENABLE |
1538                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1539         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1540 }
1541
1542 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1543 {
1544         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1545         unsigned long irqflags;
1546
1547         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1548         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1549                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1550         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1551 }
1552
1553 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1554 {
1555         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1556         unsigned long irqflags;
1557
1558         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1559         ironlake_disable_display_irq(dev_priv,
1560                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1561         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1562 }
1563
1564 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1565 {
1566         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1567         unsigned long irqflags;
1568         u32 imr;
1569
1570         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1571         i915_disable_pipestat(dev_priv, pipe,
1572                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1573         imr = I915_READ(VLV_IMR);
1574         if (pipe == 0)
1575                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1576         else
1577                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1578         I915_WRITE(VLV_IMR, imr);
1579         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1580 }
1581
1582 static u32
1583 ring_last_seqno(struct intel_ring_buffer *ring)
1584 {
1585         return list_entry(ring->request_list.prev,
1586                           struct drm_i915_gem_request, list)->seqno;
1587 }
1588
1589 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1590 {
1591         if (list_empty(&ring->request_list) ||
1592             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1593                 /* Issue a wake-up to catch stuck h/w. */
1594                 if (waitqueue_active(&ring->irq_queue)) {
1595                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1596                                   ring->name);
1597                         wake_up_all(&ring->irq_queue);
1598                         *err = true;
1599                 }
1600                 return true;
1601         }
1602         return false;
1603 }
1604
1605 static bool kick_ring(struct intel_ring_buffer *ring)
1606 {
1607         struct drm_device *dev = ring->dev;
1608         struct drm_i915_private *dev_priv = dev->dev_private;
1609         u32 tmp = I915_READ_CTL(ring);
1610         if (tmp & RING_WAIT) {
1611                 DRM_ERROR("Kicking stuck wait on %s\n",
1612                           ring->name);
1613                 I915_WRITE_CTL(ring, tmp);
1614                 return true;
1615         }
1616         return false;
1617 }
1618
1619 static bool i915_hangcheck_hung(struct drm_device *dev)
1620 {
1621         drm_i915_private_t *dev_priv = dev->dev_private;
1622
1623         if (dev_priv->hangcheck_count++ > 1) {
1624                 bool hung = true;
1625
1626                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1627                 i915_handle_error(dev, true);
1628
1629                 if (!IS_GEN2(dev)) {
1630                         struct intel_ring_buffer *ring;
1631                         int i;
1632
1633                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1634                          * If so we can simply poke the RB_WAIT bit
1635                          * and break the hang. This should work on
1636                          * all but the second generation chipsets.
1637                          */
1638                         for_each_ring(ring, dev_priv, i)
1639                                 hung &= !kick_ring(ring);
1640                 }
1641
1642                 return hung;
1643         }
1644
1645         return false;
1646 }
1647
1648 /**
1649  * This is called when the chip hasn't reported back with completed
1650  * batchbuffers in a long time. The first time this is called we simply record
1651  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1652  * again, we assume the chip is wedged and try to fix it.
1653  */
1654 void i915_hangcheck_elapsed(unsigned long data)
1655 {
1656         struct drm_device *dev = (struct drm_device *)data;
1657         drm_i915_private_t *dev_priv = dev->dev_private;
1658         uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1659         struct intel_ring_buffer *ring;
1660         bool err = false, idle;
1661         int i;
1662
1663         if (!i915_enable_hangcheck)
1664                 return;
1665
1666         memset(acthd, 0, sizeof(acthd));
1667         idle = true;
1668         for_each_ring(ring, dev_priv, i) {
1669             idle &= i915_hangcheck_ring_idle(ring, &err);
1670             acthd[i] = intel_ring_get_active_head(ring);
1671         }
1672
1673         /* If all work is done then ACTHD clearly hasn't advanced. */
1674         if (idle) {
1675                 if (err) {
1676                         if (i915_hangcheck_hung(dev))
1677                                 return;
1678
1679                         goto repeat;
1680                 }
1681
1682                 dev_priv->hangcheck_count = 0;
1683                 return;
1684         }
1685
1686         if (INTEL_INFO(dev)->gen < 4) {
1687                 instdone = I915_READ(INSTDONE);
1688                 instdone1 = 0;
1689         } else {
1690                 instdone = I915_READ(INSTDONE_I965);
1691                 instdone1 = I915_READ(INSTDONE1);
1692         }
1693
1694         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1695             dev_priv->last_instdone == instdone &&
1696             dev_priv->last_instdone1 == instdone1) {
1697                 if (i915_hangcheck_hung(dev))
1698                         return;
1699         } else {
1700                 dev_priv->hangcheck_count = 0;
1701
1702                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1703                 dev_priv->last_instdone = instdone;
1704                 dev_priv->last_instdone1 = instdone1;
1705         }
1706
1707 repeat:
1708         /* Reset timer case chip hangs without another request being added */
1709         mod_timer(&dev_priv->hangcheck_timer,
1710                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1711 }
1712
1713 /* drm_dma.h hooks
1714 */
1715 static void ironlake_irq_preinstall(struct drm_device *dev)
1716 {
1717         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1718
1719         atomic_set(&dev_priv->irq_received, 0);
1720
1721         I915_WRITE(HWSTAM, 0xeffe);
1722
1723         /* XXX hotplug from PCH */
1724
1725         I915_WRITE(DEIMR, 0xffffffff);
1726         I915_WRITE(DEIER, 0x0);
1727         POSTING_READ(DEIER);
1728
1729         /* and GT */
1730         I915_WRITE(GTIMR, 0xffffffff);
1731         I915_WRITE(GTIER, 0x0);
1732         POSTING_READ(GTIER);
1733
1734         /* south display irq */
1735         I915_WRITE(SDEIMR, 0xffffffff);
1736         I915_WRITE(SDEIER, 0x0);
1737         POSTING_READ(SDEIER);
1738 }
1739
1740 static void valleyview_irq_preinstall(struct drm_device *dev)
1741 {
1742         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1743         int pipe;
1744
1745         atomic_set(&dev_priv->irq_received, 0);
1746
1747         /* VLV magic */
1748         I915_WRITE(VLV_IMR, 0);
1749         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1750         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1751         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1752
1753         /* and GT */
1754         I915_WRITE(GTIIR, I915_READ(GTIIR));
1755         I915_WRITE(GTIIR, I915_READ(GTIIR));
1756         I915_WRITE(GTIMR, 0xffffffff);
1757         I915_WRITE(GTIER, 0x0);
1758         POSTING_READ(GTIER);
1759
1760         I915_WRITE(DPINVGTT, 0xff);
1761
1762         I915_WRITE(PORT_HOTPLUG_EN, 0);
1763         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1764         for_each_pipe(pipe)
1765                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1766         I915_WRITE(VLV_IIR, 0xffffffff);
1767         I915_WRITE(VLV_IMR, 0xffffffff);
1768         I915_WRITE(VLV_IER, 0x0);
1769         POSTING_READ(VLV_IER);
1770 }
1771
1772 /*
1773  * Enable digital hotplug on the PCH, and configure the DP short pulse
1774  * duration to 2ms (which is the minimum in the Display Port spec)
1775  *
1776  * This register is the same on all known PCH chips.
1777  */
1778
1779 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1780 {
1781         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1782         u32     hotplug;
1783
1784         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1785         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1786         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1787         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1788         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1789         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1790 }
1791
1792 static int ironlake_irq_postinstall(struct drm_device *dev)
1793 {
1794         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1795         /* enable kind of interrupts always enabled */
1796         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1797                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1798         u32 render_irqs;
1799         u32 hotplug_mask;
1800
1801         dev_priv->irq_mask = ~display_mask;
1802
1803         /* should always can generate irq */
1804         I915_WRITE(DEIIR, I915_READ(DEIIR));
1805         I915_WRITE(DEIMR, dev_priv->irq_mask);
1806         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1807         POSTING_READ(DEIER);
1808
1809         dev_priv->gt_irq_mask = ~0;
1810
1811         I915_WRITE(GTIIR, I915_READ(GTIIR));
1812         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1813
1814         if (IS_GEN6(dev))
1815                 render_irqs =
1816                         GT_USER_INTERRUPT |
1817                         GEN6_BSD_USER_INTERRUPT |
1818                         GEN6_BLITTER_USER_INTERRUPT;
1819         else
1820                 render_irqs =
1821                         GT_USER_INTERRUPT |
1822                         GT_PIPE_NOTIFY |
1823                         GT_BSD_USER_INTERRUPT;
1824         I915_WRITE(GTIER, render_irqs);
1825         POSTING_READ(GTIER);
1826
1827         if (HAS_PCH_CPT(dev)) {
1828                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1829                                 SDE_PORTB_HOTPLUG_CPT |
1830                                 SDE_PORTC_HOTPLUG_CPT |
1831                                 SDE_PORTD_HOTPLUG_CPT);
1832         } else {
1833                 hotplug_mask = (SDE_CRT_HOTPLUG |
1834                                 SDE_PORTB_HOTPLUG |
1835                                 SDE_PORTC_HOTPLUG |
1836                                 SDE_PORTD_HOTPLUG |
1837                                 SDE_AUX_MASK);
1838         }
1839
1840         dev_priv->pch_irq_mask = ~hotplug_mask;
1841
1842         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1843         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1844         I915_WRITE(SDEIER, hotplug_mask);
1845         POSTING_READ(SDEIER);
1846
1847         ironlake_enable_pch_hotplug(dev);
1848
1849         if (IS_IRONLAKE_M(dev)) {
1850                 /* Clear & enable PCU event interrupts */
1851                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1852                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1853                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1854         }
1855
1856         return 0;
1857 }
1858
1859 static int ivybridge_irq_postinstall(struct drm_device *dev)
1860 {
1861         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1862         /* enable kind of interrupts always enabled */
1863         u32 display_mask =
1864                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1865                 DE_PLANEC_FLIP_DONE_IVB |
1866                 DE_PLANEB_FLIP_DONE_IVB |
1867                 DE_PLANEA_FLIP_DONE_IVB;
1868         u32 render_irqs;
1869         u32 hotplug_mask;
1870
1871         dev_priv->irq_mask = ~display_mask;
1872
1873         /* should always can generate irq */
1874         I915_WRITE(DEIIR, I915_READ(DEIIR));
1875         I915_WRITE(DEIMR, dev_priv->irq_mask);
1876         I915_WRITE(DEIER,
1877                    display_mask |
1878                    DE_PIPEC_VBLANK_IVB |
1879                    DE_PIPEB_VBLANK_IVB |
1880                    DE_PIPEA_VBLANK_IVB);
1881         POSTING_READ(DEIER);
1882
1883         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1884
1885         I915_WRITE(GTIIR, I915_READ(GTIIR));
1886         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1887
1888         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1889                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1890         I915_WRITE(GTIER, render_irqs);
1891         POSTING_READ(GTIER);
1892
1893         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1894                         SDE_PORTB_HOTPLUG_CPT |
1895                         SDE_PORTC_HOTPLUG_CPT |
1896                         SDE_PORTD_HOTPLUG_CPT);
1897         dev_priv->pch_irq_mask = ~hotplug_mask;
1898
1899         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1900         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1901         I915_WRITE(SDEIER, hotplug_mask);
1902         POSTING_READ(SDEIER);
1903
1904         ironlake_enable_pch_hotplug(dev);
1905
1906         return 0;
1907 }
1908
1909 static int valleyview_irq_postinstall(struct drm_device *dev)
1910 {
1911         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1912         u32 enable_mask;
1913         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1914         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
1915         u16 msid;
1916
1917         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1918         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1919                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1920                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1921                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1922
1923         /*
1924          *Leave vblank interrupts masked initially.  enable/disable will
1925          * toggle them based on usage.
1926          */
1927         dev_priv->irq_mask = (~enable_mask) |
1928                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1929                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1930
1931         dev_priv->pipestat[0] = 0;
1932         dev_priv->pipestat[1] = 0;
1933
1934         /* Hack for broken MSIs on VLV */
1935         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1936         pci_read_config_word(dev->pdev, 0x98, &msid);
1937         msid &= 0xff; /* mask out delivery bits */
1938         msid |= (1<<14);
1939         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1940
1941         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1942         I915_WRITE(VLV_IER, enable_mask);
1943         I915_WRITE(VLV_IIR, 0xffffffff);
1944         I915_WRITE(PIPESTAT(0), 0xffff);
1945         I915_WRITE(PIPESTAT(1), 0xffff);
1946         POSTING_READ(VLV_IER);
1947
1948         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1949         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1950
1951         I915_WRITE(VLV_IIR, 0xffffffff);
1952         I915_WRITE(VLV_IIR, 0xffffffff);
1953
1954         dev_priv->gt_irq_mask = ~0;
1955
1956         I915_WRITE(GTIIR, I915_READ(GTIIR));
1957         I915_WRITE(GTIIR, I915_READ(GTIIR));
1958         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1959         I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1960                    GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1961                    GT_GEN6_BLT_USER_INTERRUPT |
1962                    GT_GEN6_BSD_USER_INTERRUPT |
1963                    GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1964                    GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1965                    GT_PIPE_NOTIFY |
1966                    GT_RENDER_CS_ERROR_INTERRUPT |
1967                    GT_SYNC_STATUS |
1968                    GT_USER_INTERRUPT);
1969         POSTING_READ(GTIER);
1970
1971         /* ack & enable invalid PTE error interrupts */
1972 #if 0 /* FIXME: add support to irq handler for checking these bits */
1973         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1974         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1975 #endif
1976
1977         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1978 #if 0 /* FIXME: check register definitions; some have moved */
1979         /* Note HDMI and DP share bits */
1980         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1981                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1982         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1983                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1984         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1985                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1986         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1987                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1988         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1989                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1990         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1991                 hotplug_en |= CRT_HOTPLUG_INT_EN;
1992                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1993         }
1994 #endif
1995
1996         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1997
1998         return 0;
1999 }
2000
2001 static void valleyview_irq_uninstall(struct drm_device *dev)
2002 {
2003         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2004         int pipe;
2005
2006         if (!dev_priv)
2007                 return;
2008
2009         for_each_pipe(pipe)
2010                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2011
2012         I915_WRITE(HWSTAM, 0xffffffff);
2013         I915_WRITE(PORT_HOTPLUG_EN, 0);
2014         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2015         for_each_pipe(pipe)
2016                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2017         I915_WRITE(VLV_IIR, 0xffffffff);
2018         I915_WRITE(VLV_IMR, 0xffffffff);
2019         I915_WRITE(VLV_IER, 0x0);
2020         POSTING_READ(VLV_IER);
2021 }
2022
2023 static void ironlake_irq_uninstall(struct drm_device *dev)
2024 {
2025         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2026
2027         if (!dev_priv)
2028                 return;
2029
2030         I915_WRITE(HWSTAM, 0xffffffff);
2031
2032         I915_WRITE(DEIMR, 0xffffffff);
2033         I915_WRITE(DEIER, 0x0);
2034         I915_WRITE(DEIIR, I915_READ(DEIIR));
2035
2036         I915_WRITE(GTIMR, 0xffffffff);
2037         I915_WRITE(GTIER, 0x0);
2038         I915_WRITE(GTIIR, I915_READ(GTIIR));
2039
2040         I915_WRITE(SDEIMR, 0xffffffff);
2041         I915_WRITE(SDEIER, 0x0);
2042         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2043 }
2044
2045 static void i8xx_irq_preinstall(struct drm_device * dev)
2046 {
2047         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2048         int pipe;
2049
2050         atomic_set(&dev_priv->irq_received, 0);
2051
2052         for_each_pipe(pipe)
2053                 I915_WRITE(PIPESTAT(pipe), 0);
2054         I915_WRITE16(IMR, 0xffff);
2055         I915_WRITE16(IER, 0x0);
2056         POSTING_READ16(IER);
2057 }
2058
2059 static int i8xx_irq_postinstall(struct drm_device *dev)
2060 {
2061         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2062
2063         dev_priv->pipestat[0] = 0;
2064         dev_priv->pipestat[1] = 0;
2065
2066         I915_WRITE16(EMR,
2067                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2068
2069         /* Unmask the interrupts that we always want on. */
2070         dev_priv->irq_mask =
2071                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2072                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2073                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2074                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2075                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2076         I915_WRITE16(IMR, dev_priv->irq_mask);
2077
2078         I915_WRITE16(IER,
2079                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2080                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2081                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2082                      I915_USER_INTERRUPT);
2083         POSTING_READ16(IER);
2084
2085         return 0;
2086 }
2087
2088 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2089 {
2090         struct drm_device *dev = (struct drm_device *) arg;
2091         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2092         u16 iir, new_iir;
2093         u32 pipe_stats[2];
2094         unsigned long irqflags;
2095         int irq_received;
2096         int pipe;
2097         u16 flip_mask =
2098                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2099                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2100
2101         atomic_inc(&dev_priv->irq_received);
2102
2103         iir = I915_READ16(IIR);
2104         if (iir == 0)
2105                 return IRQ_NONE;
2106
2107         while (iir & ~flip_mask) {
2108                 /* Can't rely on pipestat interrupt bit in iir as it might
2109                  * have been cleared after the pipestat interrupt was received.
2110                  * It doesn't set the bit in iir again, but it still produces
2111                  * interrupts (for non-MSI).
2112                  */
2113                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2114                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2115                         i915_handle_error(dev, false);
2116
2117                 for_each_pipe(pipe) {
2118                         int reg = PIPESTAT(pipe);
2119                         pipe_stats[pipe] = I915_READ(reg);
2120
2121                         /*
2122                          * Clear the PIPE*STAT regs before the IIR
2123                          */
2124                         if (pipe_stats[pipe] & 0x8000ffff) {
2125                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2126                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2127                                                          pipe_name(pipe));
2128                                 I915_WRITE(reg, pipe_stats[pipe]);
2129                                 irq_received = 1;
2130                         }
2131                 }
2132                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2133
2134                 I915_WRITE16(IIR, iir & ~flip_mask);
2135                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2136
2137                 i915_update_dri1_breadcrumb(dev);
2138
2139                 if (iir & I915_USER_INTERRUPT)
2140                         notify_ring(dev, &dev_priv->ring[RCS]);
2141
2142                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2143                     drm_handle_vblank(dev, 0)) {
2144                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2145                                 intel_prepare_page_flip(dev, 0);
2146                                 intel_finish_page_flip(dev, 0);
2147                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2148                         }
2149                 }
2150
2151                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2152                     drm_handle_vblank(dev, 1)) {
2153                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2154                                 intel_prepare_page_flip(dev, 1);
2155                                 intel_finish_page_flip(dev, 1);
2156                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2157                         }
2158                 }
2159
2160                 iir = new_iir;
2161         }
2162
2163         return IRQ_HANDLED;
2164 }
2165
2166 static void i8xx_irq_uninstall(struct drm_device * dev)
2167 {
2168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2169         int pipe;
2170
2171         for_each_pipe(pipe) {
2172                 /* Clear enable bits; then clear status bits */
2173                 I915_WRITE(PIPESTAT(pipe), 0);
2174                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2175         }
2176         I915_WRITE16(IMR, 0xffff);
2177         I915_WRITE16(IER, 0x0);
2178         I915_WRITE16(IIR, I915_READ16(IIR));
2179 }
2180
2181 static void i915_irq_preinstall(struct drm_device * dev)
2182 {
2183         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2184         int pipe;
2185
2186         atomic_set(&dev_priv->irq_received, 0);
2187
2188         if (I915_HAS_HOTPLUG(dev)) {
2189                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2190                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2191         }
2192
2193         I915_WRITE16(HWSTAM, 0xeffe);
2194         for_each_pipe(pipe)
2195                 I915_WRITE(PIPESTAT(pipe), 0);
2196         I915_WRITE(IMR, 0xffffffff);
2197         I915_WRITE(IER, 0x0);
2198         POSTING_READ(IER);
2199 }
2200
2201 static int i915_irq_postinstall(struct drm_device *dev)
2202 {
2203         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2204         u32 enable_mask;
2205
2206         dev_priv->pipestat[0] = 0;
2207         dev_priv->pipestat[1] = 0;
2208
2209         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2210
2211         /* Unmask the interrupts that we always want on. */
2212         dev_priv->irq_mask =
2213                 ~(I915_ASLE_INTERRUPT |
2214                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2215                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2216                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2217                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2218                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2219
2220         enable_mask =
2221                 I915_ASLE_INTERRUPT |
2222                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2223                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2224                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2225                 I915_USER_INTERRUPT;
2226
2227         if (I915_HAS_HOTPLUG(dev)) {
2228                 /* Enable in IER... */
2229                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2230                 /* and unmask in IMR */
2231                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2232         }
2233
2234         I915_WRITE(IMR, dev_priv->irq_mask);
2235         I915_WRITE(IER, enable_mask);
2236         POSTING_READ(IER);
2237
2238         if (I915_HAS_HOTPLUG(dev)) {
2239                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2240
2241                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2242                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2243                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2244                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2245                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2246                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2247                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2248                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2249                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2250                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2251                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2252                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2253                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2254                 }
2255
2256                 /* Ignore TV since it's buggy */
2257
2258                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2259         }
2260
2261         intel_opregion_enable_asle(dev);
2262
2263         return 0;
2264 }
2265
2266 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2267 {
2268         struct drm_device *dev = (struct drm_device *) arg;
2269         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2270         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2271         unsigned long irqflags;
2272         u32 flip_mask =
2273                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2274                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2275         u32 flip[2] = {
2276                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2277                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2278         };
2279         int pipe, ret = IRQ_NONE;
2280
2281         atomic_inc(&dev_priv->irq_received);
2282
2283         iir = I915_READ(IIR);
2284         do {
2285                 bool irq_received = (iir & ~flip_mask) != 0;
2286                 bool blc_event = false;
2287
2288                 /* Can't rely on pipestat interrupt bit in iir as it might
2289                  * have been cleared after the pipestat interrupt was received.
2290                  * It doesn't set the bit in iir again, but it still produces
2291                  * interrupts (for non-MSI).
2292                  */
2293                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2294                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2295                         i915_handle_error(dev, false);
2296
2297                 for_each_pipe(pipe) {
2298                         int reg = PIPESTAT(pipe);
2299                         pipe_stats[pipe] = I915_READ(reg);
2300
2301                         /* Clear the PIPE*STAT regs before the IIR */
2302                         if (pipe_stats[pipe] & 0x8000ffff) {
2303                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2304                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2305                                                          pipe_name(pipe));
2306                                 I915_WRITE(reg, pipe_stats[pipe]);
2307                                 irq_received = true;
2308                         }
2309                 }
2310                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2311
2312                 if (!irq_received)
2313                         break;
2314
2315                 /* Consume port.  Then clear IIR or we'll miss events */
2316                 if ((I915_HAS_HOTPLUG(dev)) &&
2317                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2318                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2319
2320                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2321                                   hotplug_status);
2322                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2323                                 queue_work(dev_priv->wq,
2324                                            &dev_priv->hotplug_work);
2325
2326                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2327                         POSTING_READ(PORT_HOTPLUG_STAT);
2328                 }
2329
2330                 I915_WRITE(IIR, iir & ~flip_mask);
2331                 new_iir = I915_READ(IIR); /* Flush posted writes */
2332
2333                 if (iir & I915_USER_INTERRUPT)
2334                         notify_ring(dev, &dev_priv->ring[RCS]);
2335
2336                 for_each_pipe(pipe) {
2337                         int plane = pipe;
2338                         if (IS_MOBILE(dev))
2339                                 plane = !plane;
2340                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2341                             drm_handle_vblank(dev, pipe)) {
2342                                 if (iir & flip[plane]) {
2343                                         intel_prepare_page_flip(dev, plane);
2344                                         intel_finish_page_flip(dev, pipe);
2345                                         flip_mask &= ~flip[plane];
2346                                 }
2347                         }
2348
2349                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2350                                 blc_event = true;
2351                 }
2352
2353                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2354                         intel_opregion_asle_intr(dev);
2355
2356                 /* With MSI, interrupts are only generated when iir
2357                  * transitions from zero to nonzero.  If another bit got
2358                  * set while we were handling the existing iir bits, then
2359                  * we would never get another interrupt.
2360                  *
2361                  * This is fine on non-MSI as well, as if we hit this path
2362                  * we avoid exiting the interrupt handler only to generate
2363                  * another one.
2364                  *
2365                  * Note that for MSI this could cause a stray interrupt report
2366                  * if an interrupt landed in the time between writing IIR and
2367                  * the posting read.  This should be rare enough to never
2368                  * trigger the 99% of 100,000 interrupts test for disabling
2369                  * stray interrupts.
2370                  */
2371                 ret = IRQ_HANDLED;
2372                 iir = new_iir;
2373         } while (iir & ~flip_mask);
2374
2375         i915_update_dri1_breadcrumb(dev);
2376
2377         return ret;
2378 }
2379
2380 static void i915_irq_uninstall(struct drm_device * dev)
2381 {
2382         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2383         int pipe;
2384
2385         if (I915_HAS_HOTPLUG(dev)) {
2386                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2387                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2388         }
2389
2390         I915_WRITE16(HWSTAM, 0xffff);
2391         for_each_pipe(pipe) {
2392                 /* Clear enable bits; then clear status bits */
2393                 I915_WRITE(PIPESTAT(pipe), 0);
2394                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2395         }
2396         I915_WRITE(IMR, 0xffffffff);
2397         I915_WRITE(IER, 0x0);
2398
2399         I915_WRITE(IIR, I915_READ(IIR));
2400 }
2401
2402 static void i965_irq_preinstall(struct drm_device * dev)
2403 {
2404         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2405         int pipe;
2406
2407         atomic_set(&dev_priv->irq_received, 0);
2408
2409         I915_WRITE(PORT_HOTPLUG_EN, 0);
2410         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2411
2412         I915_WRITE(HWSTAM, 0xeffe);
2413         for_each_pipe(pipe)
2414                 I915_WRITE(PIPESTAT(pipe), 0);
2415         I915_WRITE(IMR, 0xffffffff);
2416         I915_WRITE(IER, 0x0);
2417         POSTING_READ(IER);
2418 }
2419
2420 static int i965_irq_postinstall(struct drm_device *dev)
2421 {
2422         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2423         u32 hotplug_en;
2424         u32 enable_mask;
2425         u32 error_mask;
2426
2427         /* Unmask the interrupts that we always want on. */
2428         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2429                                I915_DISPLAY_PORT_INTERRUPT |
2430                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2431                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2432                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2433                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2434                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2435
2436         enable_mask = ~dev_priv->irq_mask;
2437         enable_mask |= I915_USER_INTERRUPT;
2438
2439         if (IS_G4X(dev))
2440                 enable_mask |= I915_BSD_USER_INTERRUPT;
2441
2442         dev_priv->pipestat[0] = 0;
2443         dev_priv->pipestat[1] = 0;
2444
2445         /*
2446          * Enable some error detection, note the instruction error mask
2447          * bit is reserved, so we leave it masked.
2448          */
2449         if (IS_G4X(dev)) {
2450                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2451                                GM45_ERROR_MEM_PRIV |
2452                                GM45_ERROR_CP_PRIV |
2453                                I915_ERROR_MEMORY_REFRESH);
2454         } else {
2455                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2456                                I915_ERROR_MEMORY_REFRESH);
2457         }
2458         I915_WRITE(EMR, error_mask);
2459
2460         I915_WRITE(IMR, dev_priv->irq_mask);
2461         I915_WRITE(IER, enable_mask);
2462         POSTING_READ(IER);
2463
2464         /* Note HDMI and DP share hotplug bits */
2465         hotplug_en = 0;
2466         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2467                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2468         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2469                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2470         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2471                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2472         if (IS_G4X(dev)) {
2473                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2474                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2475                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2476                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2477         } else {
2478                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2479                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2480                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2481                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2482         }
2483         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2484                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2485
2486                 /* Programming the CRT detection parameters tends
2487                    to generate a spurious hotplug event about three
2488                    seconds later.  So just do it once.
2489                    */
2490                 if (IS_G4X(dev))
2491                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2492                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2493         }
2494
2495         /* Ignore TV since it's buggy */
2496
2497         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2498
2499         intel_opregion_enable_asle(dev);
2500
2501         return 0;
2502 }
2503
2504 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2505 {
2506         struct drm_device *dev = (struct drm_device *) arg;
2507         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2508         u32 iir, new_iir;
2509         u32 pipe_stats[I915_MAX_PIPES];
2510         unsigned long irqflags;
2511         int irq_received;
2512         int ret = IRQ_NONE, pipe;
2513
2514         atomic_inc(&dev_priv->irq_received);
2515
2516         iir = I915_READ(IIR);
2517
2518         for (;;) {
2519                 bool blc_event = false;
2520
2521                 irq_received = iir != 0;
2522
2523                 /* Can't rely on pipestat interrupt bit in iir as it might
2524                  * have been cleared after the pipestat interrupt was received.
2525                  * It doesn't set the bit in iir again, but it still produces
2526                  * interrupts (for non-MSI).
2527                  */
2528                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2529                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2530                         i915_handle_error(dev, false);
2531
2532                 for_each_pipe(pipe) {
2533                         int reg = PIPESTAT(pipe);
2534                         pipe_stats[pipe] = I915_READ(reg);
2535
2536                         /*
2537                          * Clear the PIPE*STAT regs before the IIR
2538                          */
2539                         if (pipe_stats[pipe] & 0x8000ffff) {
2540                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2541                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2542                                                          pipe_name(pipe));
2543                                 I915_WRITE(reg, pipe_stats[pipe]);
2544                                 irq_received = 1;
2545                         }
2546                 }
2547                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2548
2549                 if (!irq_received)
2550                         break;
2551
2552                 ret = IRQ_HANDLED;
2553
2554                 /* Consume port.  Then clear IIR or we'll miss events */
2555                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2556                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2557
2558                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2559                                   hotplug_status);
2560                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2561                                 queue_work(dev_priv->wq,
2562                                            &dev_priv->hotplug_work);
2563
2564                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2565                         I915_READ(PORT_HOTPLUG_STAT);
2566                 }
2567
2568                 I915_WRITE(IIR, iir);
2569                 new_iir = I915_READ(IIR); /* Flush posted writes */
2570
2571                 if (iir & I915_USER_INTERRUPT)
2572                         notify_ring(dev, &dev_priv->ring[RCS]);
2573                 if (iir & I915_BSD_USER_INTERRUPT)
2574                         notify_ring(dev, &dev_priv->ring[VCS]);
2575
2576                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2577                         intel_prepare_page_flip(dev, 0);
2578
2579                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2580                         intel_prepare_page_flip(dev, 1);
2581
2582                 for_each_pipe(pipe) {
2583                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2584                             drm_handle_vblank(dev, pipe)) {
2585                                 i915_pageflip_stall_check(dev, pipe);
2586                                 intel_finish_page_flip(dev, pipe);
2587                         }
2588
2589                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2590                                 blc_event = true;
2591                 }
2592
2593
2594                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2595                         intel_opregion_asle_intr(dev);
2596
2597                 /* With MSI, interrupts are only generated when iir
2598                  * transitions from zero to nonzero.  If another bit got
2599                  * set while we were handling the existing iir bits, then
2600                  * we would never get another interrupt.
2601                  *
2602                  * This is fine on non-MSI as well, as if we hit this path
2603                  * we avoid exiting the interrupt handler only to generate
2604                  * another one.
2605                  *
2606                  * Note that for MSI this could cause a stray interrupt report
2607                  * if an interrupt landed in the time between writing IIR and
2608                  * the posting read.  This should be rare enough to never
2609                  * trigger the 99% of 100,000 interrupts test for disabling
2610                  * stray interrupts.
2611                  */
2612                 iir = new_iir;
2613         }
2614
2615         i915_update_dri1_breadcrumb(dev);
2616
2617         return ret;
2618 }
2619
2620 static void i965_irq_uninstall(struct drm_device * dev)
2621 {
2622         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2623         int pipe;
2624
2625         if (!dev_priv)
2626                 return;
2627
2628         I915_WRITE(PORT_HOTPLUG_EN, 0);
2629         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2630
2631         I915_WRITE(HWSTAM, 0xffffffff);
2632         for_each_pipe(pipe)
2633                 I915_WRITE(PIPESTAT(pipe), 0);
2634         I915_WRITE(IMR, 0xffffffff);
2635         I915_WRITE(IER, 0x0);
2636
2637         for_each_pipe(pipe)
2638                 I915_WRITE(PIPESTAT(pipe),
2639                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2640         I915_WRITE(IIR, I915_READ(IIR));
2641 }
2642
2643 void intel_irq_init(struct drm_device *dev)
2644 {
2645         struct drm_i915_private *dev_priv = dev->dev_private;
2646
2647         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2648         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2649         INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2650         INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
2651
2652         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2653         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2654         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2655                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2656                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2657         }
2658
2659         if (drm_core_check_feature(dev, DRIVER_MODESET))
2660                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2661         else
2662                 dev->driver->get_vblank_timestamp = NULL;
2663         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2664
2665         if (IS_VALLEYVIEW(dev)) {
2666                 dev->driver->irq_handler = valleyview_irq_handler;
2667                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2668                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2669                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2670                 dev->driver->enable_vblank = valleyview_enable_vblank;
2671                 dev->driver->disable_vblank = valleyview_disable_vblank;
2672         } else if (IS_IVYBRIDGE(dev)) {
2673                 /* Share pre & uninstall handlers with ILK/SNB */
2674                 dev->driver->irq_handler = ivybridge_irq_handler;
2675                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2676                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2677                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2678                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2679                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2680         } else if (IS_HASWELL(dev)) {
2681                 /* Share interrupts handling with IVB */
2682                 dev->driver->irq_handler = ivybridge_irq_handler;
2683                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2684                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2685                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2686                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2687                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2688         } else if (HAS_PCH_SPLIT(dev)) {
2689                 dev->driver->irq_handler = ironlake_irq_handler;
2690                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2691                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2692                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2693                 dev->driver->enable_vblank = ironlake_enable_vblank;
2694                 dev->driver->disable_vblank = ironlake_disable_vblank;
2695         } else {
2696                 if (INTEL_INFO(dev)->gen == 2) {
2697                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2698                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2699                         dev->driver->irq_handler = i8xx_irq_handler;
2700                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2701                 } else if (INTEL_INFO(dev)->gen == 3) {
2702                         /* IIR "flip pending" means done if this bit is set */
2703                         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2704
2705                         dev->driver->irq_preinstall = i915_irq_preinstall;
2706                         dev->driver->irq_postinstall = i915_irq_postinstall;
2707                         dev->driver->irq_uninstall = i915_irq_uninstall;
2708                         dev->driver->irq_handler = i915_irq_handler;
2709                 } else {
2710                         dev->driver->irq_preinstall = i965_irq_preinstall;
2711                         dev->driver->irq_postinstall = i965_irq_postinstall;
2712                         dev->driver->irq_uninstall = i965_irq_uninstall;
2713                         dev->driver->irq_handler = i965_irq_handler;
2714                 }
2715                 dev->driver->enable_vblank = i915_enable_vblank;
2716                 dev->driver->disable_vblank = i915_disable_vblank;
2717         }
2718 }