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24 #include <linux/circ_buf.h>
29 * DOC: GuC-based command submission
32 * We use the term client to avoid confusion with contexts. A i915_guc_client is
33 * equivalent to GuC object guc_context_desc. This context descriptor is
34 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
35 * and workqueue for it. Also the process descriptor (guc_process_desc), which
36 * is mapped to client space. So the client can write Work Item then ring the
39 * To simplify the implementation, we allocate one gem object that contains all
40 * pages for doorbell, process descriptor and workqueue.
42 * The Scratch registers:
43 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
44 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
45 * triggers an interrupt on the GuC via another register write (0xC4C8).
46 * Firmware writes a success/fail code back to the action register after
47 * processes the request. The kernel driver polls waiting for this update and
49 * See intel_guc_send()
52 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
53 * mapped into process space.
56 * There are several types of work items that the host may place into a
57 * workqueue, each with its own requirements and limitations. Currently only
58 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
59 * represents in-order queue. The kernel driver packs ring tail pointer and an
60 * ELSP context descriptor dword into Work Item.
61 * See guc_wq_item_append()
66 * Tell the GuC to allocate or deallocate a specific doorbell
69 static int guc_allocate_doorbell(struct intel_guc *guc,
70 struct i915_guc_client *client)
73 INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
77 return intel_guc_send(guc, action, ARRAY_SIZE(action));
80 static int guc_release_doorbell(struct intel_guc *guc,
81 struct i915_guc_client *client)
84 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
88 return intel_guc_send(guc, action, ARRAY_SIZE(action));
92 * Initialise, update, or clear doorbell data shared with the GuC
94 * These functions modify shared data and so need access to the mapped
95 * client object which contains the page being used for the doorbell
98 static int guc_update_doorbell_id(struct intel_guc *guc,
99 struct i915_guc_client *client,
102 struct sg_table *sg = guc->ctx_pool_vma->pages;
103 void *doorbell_bitmap = guc->doorbell_bitmap;
104 struct guc_doorbell_info *doorbell;
105 struct guc_context_desc desc;
108 doorbell = client->vaddr + client->doorbell_offset;
110 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID &&
111 test_bit(client->doorbell_id, doorbell_bitmap)) {
112 /* Deactivate the old doorbell */
113 doorbell->db_status = GUC_DOORBELL_DISABLED;
114 (void)guc_release_doorbell(guc, client);
115 __clear_bit(client->doorbell_id, doorbell_bitmap);
118 /* Update the GuC's idea of the doorbell ID */
119 len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
120 sizeof(desc) * client->ctx_index);
121 if (len != sizeof(desc))
124 len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
125 sizeof(desc) * client->ctx_index);
126 if (len != sizeof(desc))
129 client->doorbell_id = new_id;
130 if (new_id == GUC_INVALID_DOORBELL_ID)
133 /* Activate the new doorbell */
134 __set_bit(new_id, doorbell_bitmap);
135 doorbell->db_status = GUC_DOORBELL_ENABLED;
136 doorbell->cookie = client->doorbell_cookie;
137 return guc_allocate_doorbell(guc, client);
140 static void guc_disable_doorbell(struct intel_guc *guc,
141 struct i915_guc_client *client)
143 (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID);
145 /* XXX: wait for any interrupts */
146 /* XXX: wait for workqueue to drain */
150 select_doorbell_register(struct intel_guc *guc, uint32_t priority)
153 * The bitmap tracks which doorbell registers are currently in use.
154 * It is split into two halves; the first half is used for normal
155 * priority contexts, the second half for high-priority ones.
156 * Note that logically higher priorities are numerically less than
157 * normal ones, so the test below means "is it high-priority?"
159 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
160 const uint16_t half = GUC_MAX_DOORBELLS / 2;
161 const uint16_t start = hi_pri ? half : 0;
162 const uint16_t end = start + half;
165 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
167 id = GUC_INVALID_DOORBELL_ID;
169 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
170 hi_pri ? "high" : "normal", id);
176 * Select, assign and relase doorbell cachelines
178 * These functions track which doorbell cachelines are in use.
179 * The data they manipulate is protected by the intel_guc_send lock.
182 static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
184 const uint32_t cacheline_size = cache_line_size();
187 /* Doorbell uses a single cache line within a page */
188 offset = offset_in_page(guc->db_cacheline);
190 /* Moving to next cache line to reduce contention */
191 guc->db_cacheline += cacheline_size;
193 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
194 offset, guc->db_cacheline, cacheline_size);
200 * Initialise the process descriptor shared with the GuC firmware.
202 static void guc_proc_desc_init(struct intel_guc *guc,
203 struct i915_guc_client *client)
205 struct guc_process_desc *desc;
207 desc = client->vaddr + client->proc_desc_offset;
209 memset(desc, 0, sizeof(*desc));
212 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
213 * space for ring3 clients (set them as in mmap_ioctl) or kernel
214 * space for kernel clients (map on demand instead? May make debug
215 * easier to have it mapped).
217 desc->wq_base_addr = 0;
218 desc->db_base_addr = 0;
220 desc->context_id = client->ctx_index;
221 desc->wq_size_bytes = client->wq_size;
222 desc->wq_status = WQ_STATUS_ACTIVE;
223 desc->priority = client->priority;
227 * Initialise/clear the context descriptor shared with the GuC firmware.
229 * This descriptor tells the GuC where (in GGTT space) to find the important
230 * data structures relating to this client (doorbell, process descriptor,
234 static void guc_ctx_desc_init(struct intel_guc *guc,
235 struct i915_guc_client *client)
237 struct drm_i915_private *dev_priv = guc_to_i915(guc);
238 struct intel_engine_cs *engine;
239 struct i915_gem_context *ctx = client->owner;
240 struct guc_context_desc desc;
245 memset(&desc, 0, sizeof(desc));
247 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
248 desc.context_id = client->ctx_index;
249 desc.priority = client->priority;
250 desc.db_id = client->doorbell_id;
252 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
253 struct intel_context *ce = &ctx->engine[engine->id];
254 uint32_t guc_engine_id = engine->guc_id;
255 struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
257 /* TODO: We have a design issue to be solved here. Only when we
258 * receive the first batch, we know which engine is used by the
259 * user. But here GuC expects the lrc and ring to be pinned. It
260 * is not an issue for default context, which is the only one
261 * for now who owns a GuC client. But for future owner of GuC
262 * client, need to make sure lrc is pinned prior to enter here.
265 break; /* XXX: continue? */
267 lrc->context_desc = lower_32_bits(ce->lrc_desc);
269 /* The state page is after PPHWSP */
271 guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
272 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
273 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
275 lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
276 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
277 lrc->ring_next_free_location = lrc->ring_begin;
278 lrc->ring_current_tail_pointer_value = 0;
280 desc.engines_used |= (1 << guc_engine_id);
283 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
284 client->engines, desc.engines_used);
285 WARN_ON(desc.engines_used == 0);
288 * The doorbell, process descriptor, and workqueue are all parts
289 * of the client object, which the GuC will reference via the GGTT
291 gfx_addr = guc_ggtt_offset(client->vma);
292 desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
293 client->doorbell_offset;
294 desc.db_trigger_cpu =
295 (uintptr_t)client->vaddr + client->doorbell_offset;
296 desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
297 desc.process_desc = gfx_addr + client->proc_desc_offset;
298 desc.wq_addr = gfx_addr + client->wq_offset;
299 desc.wq_size = client->wq_size;
302 * XXX: Take LRCs from an existing context if this is not an
303 * IsKMDCreatedContext client
305 desc.desc_private = (uintptr_t)client;
307 /* Pool context is pinned already */
308 sg = guc->ctx_pool_vma->pages;
309 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
310 sizeof(desc) * client->ctx_index);
313 static void guc_ctx_desc_fini(struct intel_guc *guc,
314 struct i915_guc_client *client)
316 struct guc_context_desc desc;
319 memset(&desc, 0, sizeof(desc));
321 sg = guc->ctx_pool_vma->pages;
322 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
323 sizeof(desc) * client->ctx_index);
327 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
328 * @request: request associated with the commands
330 * Return: 0 if space is available
331 * -EAGAIN if space is not currently available
333 * This function must be called (and must return 0) before a request
334 * is submitted to the GuC via i915_guc_submit() below. Once a result
335 * of 0 has been returned, it must be balanced by a corresponding
338 * Reservation allows the caller to determine in advance that space
339 * will be available for the next submission before committing resources
340 * to it, and helps avoid late failures with complicated recovery paths.
342 int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
344 const size_t wqi_size = sizeof(struct guc_wq_item);
345 struct i915_guc_client *client = request->i915->guc.execbuf_client;
346 struct guc_process_desc *desc = client->vaddr +
347 client->proc_desc_offset;
351 spin_lock(&client->wq_lock);
352 freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
353 freespace -= client->wq_rsvd;
354 if (likely(freespace >= wqi_size)) {
355 client->wq_rsvd += wqi_size;
358 client->no_wq_space++;
361 spin_unlock(&client->wq_lock);
366 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
368 const size_t wqi_size = sizeof(struct guc_wq_item);
369 struct i915_guc_client *client = request->i915->guc.execbuf_client;
371 GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
373 spin_lock(&client->wq_lock);
374 client->wq_rsvd -= wqi_size;
375 spin_unlock(&client->wq_lock);
378 /* Construct a Work Item and append it to the GuC's Work Queue */
379 static void guc_wq_item_append(struct i915_guc_client *client,
380 struct drm_i915_gem_request *rq)
382 /* wqi_len is in DWords, and does not include the one-word header */
383 const size_t wqi_size = sizeof(struct guc_wq_item);
384 const u32 wqi_len = wqi_size/sizeof(u32) - 1;
385 struct intel_engine_cs *engine = rq->engine;
386 struct guc_process_desc *desc;
387 struct guc_wq_item *wqi;
388 u32 freespace, tail, wq_off;
390 desc = client->vaddr + client->proc_desc_offset;
392 /* Free space is guaranteed, see i915_guc_wq_reserve() above */
393 freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
394 GEM_BUG_ON(freespace < wqi_size);
396 /* The GuC firmware wants the tail index in QWords, not bytes */
398 GEM_BUG_ON(tail & 7);
400 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
402 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
403 * should not have the case where structure wqi is across page, neither
404 * wrapped to the beginning. This simplifies the implementation below.
406 * XXX: if not the case, we need save data to a temp wqi and copy it to
407 * workqueue buffer dw by dw.
409 BUILD_BUG_ON(wqi_size != 16);
410 GEM_BUG_ON(client->wq_rsvd < wqi_size);
412 /* postincrement WQ tail for next time */
413 wq_off = client->wq_tail;
414 GEM_BUG_ON(wq_off & (wqi_size - 1));
415 client->wq_tail += wqi_size;
416 client->wq_tail &= client->wq_size - 1;
417 client->wq_rsvd -= wqi_size;
419 /* WQ starts from the page after doorbell / process_desc */
420 wqi = client->vaddr + wq_off + GUC_DB_SIZE;
422 /* Now fill in the 4-word work queue item */
423 wqi->header = WQ_TYPE_INORDER |
424 (wqi_len << WQ_LEN_SHIFT) |
425 (engine->guc_id << WQ_TARGET_SHIFT) |
428 /* The GuC wants only the low-order word of the context descriptor */
429 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
431 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
432 wqi->fence_id = rq->global_seqno;
435 static int guc_ring_doorbell(struct i915_guc_client *client)
437 struct guc_process_desc *desc;
438 union guc_doorbell_qw db_cmp, db_exc, db_ret;
439 union guc_doorbell_qw *db;
440 int attempt = 2, ret = -EAGAIN;
442 desc = client->vaddr + client->proc_desc_offset;
444 /* Update the tail so it is visible to GuC */
445 desc->tail = client->wq_tail;
448 db_cmp.db_status = GUC_DOORBELL_ENABLED;
449 db_cmp.cookie = client->doorbell_cookie;
451 /* cookie to be updated */
452 db_exc.db_status = GUC_DOORBELL_ENABLED;
453 db_exc.cookie = client->doorbell_cookie + 1;
454 if (db_exc.cookie == 0)
457 /* pointer of current doorbell cacheline */
458 db = client->vaddr + client->doorbell_offset;
461 /* lets ring the doorbell */
462 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
463 db_cmp.value_qw, db_exc.value_qw);
465 /* if the exchange was successfully executed */
466 if (db_ret.value_qw == db_cmp.value_qw) {
467 /* db was successfully rung */
468 client->doorbell_cookie = db_exc.cookie;
473 /* XXX: doorbell was lost and need to acquire it again */
474 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
477 DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
478 db_cmp.cookie, db_ret.cookie);
480 /* update the cookie to newly read cookie from GuC */
481 db_cmp.cookie = db_ret.cookie;
482 db_exc.cookie = db_ret.cookie + 1;
483 if (db_exc.cookie == 0)
491 * __i915_guc_submit() - Submit commands through GuC
492 * @rq: request associated with the commands
494 * The caller must have already called i915_guc_wq_reserve() above with
495 * a result of 0 (success), guaranteeing that there is space in the work
496 * queue for the new request, so enqueuing the item cannot fail.
498 * Bad Things Will Happen if the caller violates this protocol e.g. calls
499 * submit() when _reserve() says there's no space, or calls _submit()
500 * a different number of times from (successful) calls to _reserve().
502 * The only error here arises if the doorbell hardware isn't functioning
503 * as expected, which really shouln't happen.
505 static void __i915_guc_submit(struct drm_i915_gem_request *rq)
507 struct drm_i915_private *dev_priv = rq->i915;
508 struct intel_engine_cs *engine = rq->engine;
509 unsigned int engine_id = engine->id;
510 struct intel_guc *guc = &rq->i915->guc;
511 struct i915_guc_client *client = guc->execbuf_client;
514 spin_lock(&client->wq_lock);
515 guc_wq_item_append(client, rq);
517 /* WA to flush out the pending GMADR writes to ring buffer. */
518 if (i915_vma_is_map_and_fenceable(rq->ring->vma))
519 POSTING_READ_FW(GUC_STATUS);
521 b_ret = guc_ring_doorbell(client);
523 client->submissions[engine_id] += 1;
524 client->retcode = b_ret;
528 guc->submissions[engine_id] += 1;
529 guc->last_seqno[engine_id] = rq->global_seqno;
530 spin_unlock(&client->wq_lock);
533 static void i915_guc_submit(struct drm_i915_gem_request *rq)
535 i915_gem_request_submit(rq);
536 __i915_guc_submit(rq);
540 * Everything below here is concerned with setup & teardown, and is
541 * therefore not part of the somewhat time-critical batch-submission
542 * path of i915_guc_submit() above.
546 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
548 * @size: size of area to allocate (both virtual space and memory)
550 * This is a wrapper to create an object for use with the GuC. In order to
551 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
552 * both some backing storage and a range inside the Global GTT. We must pin
553 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
554 * range is reserved inside GuC.
556 * Return: A i915_vma if successful, otherwise an ERR_PTR.
558 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
560 struct drm_i915_private *dev_priv = guc_to_i915(guc);
561 struct drm_i915_gem_object *obj;
562 struct i915_vma *vma;
565 obj = i915_gem_object_create(dev_priv, size);
567 return ERR_CAST(obj);
569 vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
573 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
574 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
583 i915_gem_object_put(obj);
588 guc_client_free(struct drm_i915_private *dev_priv,
589 struct i915_guc_client *client)
591 struct intel_guc *guc = &dev_priv->guc;
597 * XXX: wait for any outstanding submissions before freeing memory.
598 * Be sure to drop any locks
603 * If we got as far as setting up a doorbell, make sure we
604 * shut it down before unmapping & deallocating the memory.
606 guc_disable_doorbell(guc, client);
608 i915_gem_object_unpin_map(client->vma->obj);
611 i915_vma_unpin_and_release(&client->vma);
613 if (client->ctx_index != GUC_INVALID_CTX_ID) {
614 guc_ctx_desc_fini(guc, client);
615 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
621 /* Check that a doorbell register is in the expected state */
622 static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
624 struct drm_i915_private *dev_priv = guc_to_i915(guc);
625 i915_reg_t drbreg = GEN8_DRBREGL(db_id);
626 uint32_t value = I915_READ(drbreg);
627 bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
628 bool expected = test_bit(db_id, guc->doorbell_bitmap);
630 if (enabled == expected)
633 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
634 db_id, drbreg.reg, value,
635 expected ? "active" : "inactive");
641 * Borrow the first client to set up & tear down each unused doorbell
642 * in turn, to ensure that all doorbell h/w is (re)initialised.
644 static void guc_init_doorbell_hw(struct intel_guc *guc)
646 struct i915_guc_client *client = guc->execbuf_client;
650 guc_disable_doorbell(guc, client);
652 for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
653 /* Skip if doorbell is OK */
654 if (guc_doorbell_check(guc, i))
657 err = guc_update_doorbell_id(guc, client, i);
659 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
663 db_id = select_doorbell_register(guc, client->priority);
664 WARN_ON(db_id == GUC_INVALID_DOORBELL_ID);
666 err = guc_update_doorbell_id(guc, client, db_id);
668 DRM_WARN("Failed to restore doorbell to %d, err %d\n",
671 /* Read back & verify all doorbell registers */
672 for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
673 (void)guc_doorbell_check(guc, i);
677 * guc_client_alloc() - Allocate an i915_guc_client
678 * @dev_priv: driver private data structure
679 * @engines: The set of engines to enable for this client
680 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
681 * The kernel client to replace ExecList submission is created with
682 * NORMAL priority. Priority of a client for scheduler can be HIGH,
683 * while a preemption context can use CRITICAL.
684 * @ctx: the context that owns the client (we use the default render
687 * Return: An i915_guc_client object if success, else NULL.
689 static struct i915_guc_client *
690 guc_client_alloc(struct drm_i915_private *dev_priv,
693 struct i915_gem_context *ctx)
695 struct i915_guc_client *client;
696 struct intel_guc *guc = &dev_priv->guc;
697 struct i915_vma *vma;
701 client = kzalloc(sizeof(*client), GFP_KERNEL);
707 client->engines = engines;
708 client->priority = priority;
709 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
711 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
712 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
713 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
714 client->ctx_index = GUC_INVALID_CTX_ID;
718 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
719 vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
723 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
726 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
730 client->vaddr = vaddr;
732 spin_lock_init(&client->wq_lock);
733 client->wq_offset = GUC_DB_SIZE;
734 client->wq_size = GUC_WQ_SIZE;
736 db_id = select_doorbell_register(guc, client->priority);
737 if (db_id == GUC_INVALID_DOORBELL_ID)
738 /* XXX: evict a doorbell instead? */
741 client->doorbell_offset = select_doorbell_cacheline(guc);
744 * Since the doorbell only requires a single cacheline, we can save
745 * space by putting the application process descriptor in the same
746 * page. Use the half of the page that doesn't include the doorbell.
748 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
749 client->proc_desc_offset = 0;
751 client->proc_desc_offset = (GUC_DB_SIZE / 2);
753 guc_proc_desc_init(guc, client);
754 guc_ctx_desc_init(guc, client);
756 /* For runtime client allocation we need to enable the doorbell. Not
757 * required yet for the static execbuf_client as this special kernel
758 * client is enabled from i915_guc_submission_enable().
760 * guc_update_doorbell_id(guc, client, db_id);
763 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
764 priority, client, client->engines, client->ctx_index);
765 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
766 client->doorbell_id, client->doorbell_offset);
771 guc_client_free(dev_priv, client);
777 static void guc_policies_init(struct guc_policies *policies)
779 struct guc_policy *policy;
782 policies->dpc_promote_time = 500000;
783 policies->max_num_work_items = POLICY_MAX_NUM_WI;
785 for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
786 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
787 policy = &policies->policy[p][i];
789 policy->execution_quantum = 1000000;
790 policy->preemption_time = 500000;
791 policy->fault_time = 250000;
792 policy->policy_flags = 0;
796 policies->is_valid = 1;
799 static void guc_addon_create(struct intel_guc *guc)
801 struct drm_i915_private *dev_priv = guc_to_i915(guc);
802 struct i915_vma *vma;
804 struct guc_policies *policies;
805 struct guc_mmio_reg_state *reg_state;
806 struct intel_engine_cs *engine;
807 enum intel_engine_id id;
811 /* The ads obj includes the struct itself and buffers passed to GuC */
812 size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
813 sizeof(struct guc_mmio_reg_state) +
814 GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
818 vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(size));
825 page = i915_vma_first_page(vma);
829 * The GuC requires a "Golden Context" when it reinitialises
830 * engines after a reset. Here we use the Render ring default
831 * context, which must already exist and be pinned in the GGTT,
832 * so its address won't change after we've told the GuC where
835 engine = dev_priv->engine[RCS];
836 ads->golden_context_lrca = engine->status_page.ggtt_offset;
838 for_each_engine(engine, dev_priv, id)
839 ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
841 /* GuC scheduling policies */
842 policies = (void *)ads + sizeof(struct guc_ads);
843 guc_policies_init(policies);
845 ads->scheduler_policies =
846 guc_ggtt_offset(vma) + sizeof(struct guc_ads);
849 reg_state = (void *)policies + sizeof(struct guc_policies);
851 for_each_engine(engine, dev_priv, id) {
852 reg_state->mmio_white_list[engine->guc_id].mmio_start =
853 engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
855 /* Nothing to be saved or restored for now. */
856 reg_state->mmio_white_list[engine->guc_id].count = 0;
859 ads->reg_state_addr = ads->scheduler_policies +
860 sizeof(struct guc_policies);
862 ads->reg_state_buffer = ads->reg_state_addr +
863 sizeof(struct guc_mmio_reg_state);
869 * Set up the memory resources to be shared with the GuC. At this point,
870 * we require just one object that can be mapped through the GGTT.
872 int i915_guc_submission_init(struct drm_i915_private *dev_priv)
874 const size_t ctxsize = sizeof(struct guc_context_desc);
875 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
876 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
877 struct intel_guc *guc = &dev_priv->guc;
878 struct i915_vma *vma;
880 if (!HAS_GUC_SCHED(dev_priv))
883 /* Wipe bitmap & delete client in case of reinitialisation */
884 bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS);
885 i915_guc_submission_disable(dev_priv);
887 if (!i915.enable_guc_submission)
888 return 0; /* not enabled */
890 if (guc->ctx_pool_vma)
891 return 0; /* already allocated */
893 vma = intel_guc_allocate_vma(guc, gemsize);
897 guc->ctx_pool_vma = vma;
898 ida_init(&guc->ctx_ids);
899 intel_guc_log_create(guc);
900 guc_addon_create(guc);
902 guc->execbuf_client = guc_client_alloc(dev_priv,
903 INTEL_INFO(dev_priv)->ring_mask,
904 GUC_CTX_PRIORITY_KMD_NORMAL,
905 dev_priv->kernel_context);
906 if (!guc->execbuf_client) {
907 DRM_ERROR("Failed to create GuC client for execbuf!\n");
914 i915_guc_submission_fini(dev_priv);
918 static void guc_reset_wq(struct i915_guc_client *client)
920 struct guc_process_desc *desc = client->vaddr +
921 client->proc_desc_offset;
929 int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
931 struct intel_guc *guc = &dev_priv->guc;
932 struct i915_guc_client *client = guc->execbuf_client;
933 struct intel_engine_cs *engine;
934 enum intel_engine_id id;
939 intel_guc_sample_forcewake(guc);
941 guc_reset_wq(client);
942 guc_init_doorbell_hw(guc);
944 /* Take over from manual control of ELSP (execlists) */
945 for_each_engine(engine, dev_priv, id) {
946 struct drm_i915_gem_request *rq;
948 engine->submit_request = i915_guc_submit;
949 engine->schedule = NULL;
951 /* Replay the current set of previously submitted requests */
952 list_for_each_entry(rq, &engine->timeline->requests, link) {
953 client->wq_rsvd += sizeof(struct guc_wq_item);
954 __i915_guc_submit(rq);
961 void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
963 struct intel_guc *guc = &dev_priv->guc;
965 if (!guc->execbuf_client)
968 /* Revert back to manual ELSP submission */
969 intel_execlists_enable_submission(dev_priv);
972 void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
974 struct intel_guc *guc = &dev_priv->guc;
975 struct i915_guc_client *client;
977 client = fetch_and_zero(&guc->execbuf_client);
981 guc_client_free(dev_priv, client);
983 i915_vma_unpin_and_release(&guc->ads_vma);
984 i915_vma_unpin_and_release(&guc->log.vma);
986 if (guc->ctx_pool_vma)
987 ida_destroy(&guc->ctx_ids);
988 i915_vma_unpin_and_release(&guc->ctx_pool_vma);
992 * intel_guc_suspend() - notify GuC entering suspend state
993 * @dev_priv: i915 device private
995 int intel_guc_suspend(struct drm_i915_private *dev_priv)
997 struct intel_guc *guc = &dev_priv->guc;
998 struct i915_gem_context *ctx;
1001 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
1004 gen9_disable_guc_interrupts(dev_priv);
1006 ctx = dev_priv->kernel_context;
1008 data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
1009 /* any value greater than GUC_POWER_D0 */
1010 data[1] = GUC_POWER_D1;
1011 /* first page is shared data with GuC */
1012 data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
1014 return intel_guc_send(guc, data, ARRAY_SIZE(data));
1019 * intel_guc_resume() - notify GuC resuming from suspend state
1020 * @dev_priv: i915 device private
1022 int intel_guc_resume(struct drm_i915_private *dev_priv)
1024 struct intel_guc *guc = &dev_priv->guc;
1025 struct i915_gem_context *ctx;
1028 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
1031 if (i915.guc_log_level >= 0)
1032 gen9_enable_guc_interrupts(dev_priv);
1034 ctx = dev_priv->kernel_context;
1036 data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
1037 data[1] = GUC_POWER_D0;
1038 /* first page is shared data with GuC */
1039 data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
1041 return intel_guc_send(guc, data, ARRAY_SIZE(data));