drivers/gpu/drm/i915/i915_gem_fence_reg.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include <drm/i915_drm.h>
  26 #include "i915_drv.h"
  27
  28 /**
  29  * DOC: fence register handling
  30  *
  31  * Important to avoid confusions: "fences" in the i915 driver are not execution
  32  * fences used to track command completion but hardware detiler objects which
  33  * wrap a given range of the global GTT. Each platform has only a fairly limited
  34  * set of these objects.
  35  *
  36  * Fences are used to detile GTT memory mappings. They're also connected to the
  37  * hardware frontbuffer render tracking and hence interact with frontbuffer
  38  * compression. Furthermore on older platforms fences are required for tiled
  39  * objects used by the display engine. They can also be used by the render
  40  * engine - they're required for blitter commands and are optional for render
  41  * commands. But on gen4+ both display (with the exception of fbc) and rendering
  42  * have their own tiling state bits and don't need fences.
  43  *
  44  * Also note that fences only support X and Y tiling and hence can't be used for
  45  * the fancier new tiling formats like W, Ys and Yf.
  46  *
  47  * Finally note that because fences are such a restricted resource they're
  48  * dynamically associated with objects. Furthermore fence state is committed to
  49  * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
  50  * explicitly call i915_gem_object_get_fence() to synchronize fencing status
  51  * for cpu access. Also note that some code wants an unfenced view, for those
  52  * cases the fence can be removed forcefully with i915_gem_object_put_fence().
  53  *
  54  * Internally these functions will synchronize with userspace access by removing
  55  * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
  56  */
  57
  58 #define pipelined 0
  59
  60 static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
  61                                  struct i915_vma *vma)
  62 {
  63         i915_reg_t fence_reg_lo, fence_reg_hi;
  64         int fence_pitch_shift;
  65         u64 val;
  66
  67         if (INTEL_INFO(fence->i915)->gen >= 6) {
  68                 fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
  69                 fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
  70                 fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
  71
  72         } else {
  73                 fence_reg_lo = FENCE_REG_965_LO(fence->id);
  74                 fence_reg_hi = FENCE_REG_965_HI(fence->id);
  75                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
  76         }
  77
  78         val = 0;
  79         if (vma) {
  80                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
  81
  82                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
  83                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, I965_FENCE_PAGE));
  84                 GEM_BUG_ON(!IS_ALIGNED(vma->fence_size, I965_FENCE_PAGE));
  85                 GEM_BUG_ON(!IS_ALIGNED(stride, 128));
  86
  87                 val = (vma->node.start + vma->fence_size - I965_FENCE_PAGE) << 32;
  88                 val |= vma->node.start;
  89                 val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
  90                 if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
  91                         val |= BIT(I965_FENCE_TILING_Y_SHIFT);
  92                 val |= I965_FENCE_REG_VALID;
  93         }
  94
  95         if (!pipelined) {
  96                 struct drm_i915_private *dev_priv = fence->i915;
  97
  98                 /* To w/a incoherency with non-atomic 64-bit register updates,
  99                  * we split the 64-bit update into two 32-bit writes. In order
 100                  * for a partial fence not to be evaluated between writes, we
 101                  * precede the update with write to turn off the fence register,
 102                  * and only enable the fence as the last step.
 103                  *
 104                  * For extra levels of paranoia, we make sure each step lands
 105                  * before applying the next step.
 106                  */
 107                 I915_WRITE(fence_reg_lo, 0);
 108                 POSTING_READ(fence_reg_lo);
 109
 110                 I915_WRITE(fence_reg_hi, upper_32_bits(val));
 111                 I915_WRITE(fence_reg_lo, lower_32_bits(val));
 112                 POSTING_READ(fence_reg_lo);
 113         }
 114 }
 115
 116 static void i915_write_fence_reg(struct drm_i915_fence_reg *fence,
 117                                  struct i915_vma *vma)
 118 {
 119         u32 val;
 120
 121         val = 0;
 122         if (vma) {
 123                 unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
 124                 bool is_y_tiled = tiling == I915_TILING_Y;
 125                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
 126
 127                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 128                 GEM_BUG_ON(vma->node.start & ~I915_FENCE_START_MASK);
 129                 GEM_BUG_ON(!is_power_of_2(vma->fence_size));
 130                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
 131
 132                 if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence->i915))
 133                         stride /= 128;
 134                 else
 135                         stride /= 512;
 136                 GEM_BUG_ON(!is_power_of_2(stride));
 137
 138                 val = vma->node.start;
 139                 if (is_y_tiled)
 140                         val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 141                 val |= I915_FENCE_SIZE_BITS(vma->fence_size);
 142                 val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
 143
 144                 val |= I830_FENCE_REG_VALID;
 145         }
 146
 147         if (!pipelined) {
 148                 struct drm_i915_private *dev_priv = fence->i915;
 149                 i915_reg_t reg = FENCE_REG(fence->id);
 150
 151                 I915_WRITE(reg, val);
 152                 POSTING_READ(reg);
 153         }
 154 }
 155
 156 static void i830_write_fence_reg(struct drm_i915_fence_reg *fence,
 157                                  struct i915_vma *vma)
 158 {
 159         u32 val;
 160
 161         val = 0;
 162         if (vma) {
 163                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
 164
 165                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 166                 GEM_BUG_ON(vma->node.start & ~I830_FENCE_START_MASK);
 167                 GEM_BUG_ON(!is_power_of_2(vma->fence_size));
 168                 GEM_BUG_ON(!is_power_of_2(stride / 128));
 169                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
 170
 171                 val = vma->node.start;
 172                 if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
 173                         val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 174                 val |= I830_FENCE_SIZE_BITS(vma->fence_size);
 175                 val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
 176                 val |= I830_FENCE_REG_VALID;
 177         }
 178
 179         if (!pipelined) {
 180                 struct drm_i915_private *dev_priv = fence->i915;
 181                 i915_reg_t reg = FENCE_REG(fence->id);
 182
 183                 I915_WRITE(reg, val);
 184                 POSTING_READ(reg);
 185         }
 186 }
 187
 188 static void fence_write(struct drm_i915_fence_reg *fence,
 189                         struct i915_vma *vma)
 190 {
 191         /* Previous access through the fence register is marshalled by
 192          * the mb() inside the fault handlers (i915_gem_release_mmaps)
 193          * and explicitly managed for internal users.
 194          */
 195
 196         if (IS_GEN2(fence->i915))
 197                 i830_write_fence_reg(fence, vma);
 198         else if (IS_GEN3(fence->i915))
 199                 i915_write_fence_reg(fence, vma);
 200         else
 201                 i965_write_fence_reg(fence, vma);
 202
 203         /* Access through the fenced region afterwards is
 204          * ordered by the posting reads whilst writing the registers.
 205          */
 206
 207         fence->dirty = false;
 208 }
 209
 210 static int fence_update(struct drm_i915_fence_reg *fence,
 211                         struct i915_vma *vma)
 212 {
 213         int ret;
 214
 215         if (vma) {
 216                 if (!i915_vma_is_map_and_fenceable(vma))
 217                         return -EINVAL;
 218
 219                 if (WARN(!i915_gem_object_get_stride(vma->obj) ||
 220                          !i915_gem_object_get_tiling(vma->obj),
 221                          "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
 222                          i915_gem_object_get_stride(vma->obj),
 223                          i915_gem_object_get_tiling(vma->obj)))
 224                         return -EINVAL;
 225
 226                 ret = i915_gem_active_retire(&vma->last_fence,
 227                                              &vma->obj->base.dev->struct_mutex);
 228                 if (ret)
 229                         return ret;
 230         }
 231
 232         if (fence->vma) {
 233                 ret = i915_gem_active_retire(&fence->vma->last_fence,
 234                                       &fence->vma->obj->base.dev->struct_mutex);
 235                 if (ret)
 236                         return ret;
 237         }
 238
 239         if (fence->vma && fence->vma != vma) {
 240                 /* Ensure that all userspace CPU access is completed before
 241                  * stealing the fence.
 242                  */
 243                 i915_gem_release_mmap(fence->vma->obj);
 244
 245                 fence->vma->fence = NULL;
 246                 fence->vma = NULL;
 247
 248                 list_move(&fence->link, &fence->i915->mm.fence_list);
 249         }
 250
 251         fence_write(fence, vma);
 252
 253         if (vma) {
 254                 if (fence->vma != vma) {
 255                         vma->fence = fence;
 256                         fence->vma = vma;
 257                 }
 258
 259                 list_move_tail(&fence->link, &fence->i915->mm.fence_list);
 260         }
 261
 262         return 0;
 263 }
 264
 265 /**
 266  * i915_vma_put_fence - force-remove fence for a VMA
 267  * @vma: vma to map linearly (not through a fence reg)
 268  *
 269  * This function force-removes any fence from the given object, which is useful
 270  * if the kernel wants to do untiled GTT access.
 271  *
 272  * Returns:
 273  *
 274  * 0 on success, negative error code on failure.
 275  */
 276 int
 277 i915_vma_put_fence(struct i915_vma *vma)
 278 {
 279         struct drm_i915_fence_reg *fence = vma->fence;
 280
 281         assert_rpm_wakelock_held(vma->vm->i915);
 282
 283         if (!fence)
 284                 return 0;
 285
 286         if (fence->pin_count)
 287                 return -EBUSY;
 288
 289         return fence_update(fence, NULL);
 290 }
 291
 292 static struct drm_i915_fence_reg *fence_find(struct drm_i915_private *dev_priv)
 293 {
 294         struct drm_i915_fence_reg *fence;
 295
 296         list_for_each_entry(fence, &dev_priv->mm.fence_list, link) {
 297                 if (fence->pin_count)
 298                         continue;
 299
 300                 return fence;
 301         }
 302
 303         /* Wait for completion of pending flips which consume fences */
 304         if (intel_has_pending_fb_unpin(dev_priv))
 305                 return ERR_PTR(-EAGAIN);
 306
 307         return ERR_PTR(-EDEADLK);
 308 }
 309
 310 /**
 311  * i915_vma_get_fence - set up fencing for a vma
 312  * @vma: vma to map through a fence reg
 313  *
 314  * When mapping objects through the GTT, userspace wants to be able to write
 315  * to them without having to worry about swizzling if the object is tiled.
 316  * This function walks the fence regs looking for a free one for @obj,
 317  * stealing one if it can't find any.
 318  *
 319  * It then sets up the reg based on the object's properties: address, pitch
 320  * and tiling format.
 321  *
 322  * For an untiled surface, this removes any existing fence.
 323  *
 324  * Returns:
 325  *
 326  * 0 on success, negative error code on failure.
 327  */
 328 int
 329 i915_vma_get_fence(struct i915_vma *vma)
 330 {
 331         struct drm_i915_fence_reg *fence;
 332         struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
 333
 334         /* Note that we revoke fences on runtime suspend. Therefore the user
 335          * must keep the device awake whilst using the fence.
 336          */
 337         assert_rpm_wakelock_held(vma->vm->i915);
 338
 339         /* Just update our place in the LRU if our fence is getting reused. */
 340         if (vma->fence) {
 341                 fence = vma->fence;
 342                 if (!fence->dirty) {
 343                         list_move_tail(&fence->link,
 344                                        &fence->i915->mm.fence_list);
 345                         return 0;
 346                 }
 347         } else if (set) {
 348                 fence = fence_find(vma->vm->i915);
 349                 if (IS_ERR(fence))
 350                         return PTR_ERR(fence);
 351         } else
 352                 return 0;
 353
 354         return fence_update(fence, set);
 355 }
 356
 357 /**
 358  * i915_gem_revoke_fences - revoke fence state
 359  * @dev_priv: i915 device private
 360  *
 361  * Removes all GTT mmappings via the fence registers. This forces any user
 362  * of the fence to reacquire that fence before continuing with their access.
 363  * One use is during GPU reset where the fence register is lost and we need to
 364  * revoke concurrent userspace access via GTT mmaps until the hardware has been
 365  * reset and the fence registers have been restored.
 366  */
 367 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv)
 368 {
 369         int i;
 370
 371         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 372
 373         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 374                 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
 375
 376                 if (fence->vma)
 377                         i915_gem_release_mmap(fence->vma->obj);
 378         }
 379 }
 380
 381 /**
 382  * i915_gem_restore_fences - restore fence state
 383  * @dev_priv: i915 device private
 384  *
 385  * Restore the hw fence state to match the software tracking again, to be called
 386  * after a gpu reset and on resume. Note that on runtime suspend we only cancel
 387  * the fences, to be reacquired by the user later.
 388  */
 389 void i915_gem_restore_fences(struct drm_i915_private *dev_priv)
 390 {
 391         int i;
 392
 393         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 394                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
 395                 struct i915_vma *vma = reg->vma;
 396
 397                 /*
 398                  * Commit delayed tiling changes if we have an object still
 399                  * attached to the fence, otherwise just clear the fence.
 400                  */
 401                 if (vma && !i915_gem_object_is_tiled(vma->obj)) {
 402                         GEM_BUG_ON(!reg->dirty);
 403                         GEM_BUG_ON(!list_empty(&vma->obj->userfault_link));
 404
 405                         list_move(&reg->link, &dev_priv->mm.fence_list);
 406                         vma->fence = NULL;
 407                         vma = NULL;
 408                 }
 409
 410                 fence_write(reg, vma);
 411                 reg->vma = vma;
 412         }
 413 }
 414
 415 /**
 416  * DOC: tiling swizzling details
 417  *
 418  * The idea behind tiling is to increase cache hit rates by rearranging
 419  * pixel data so that a group of pixel accesses are in the same cacheline.
 420  * Performance improvement from doing this on the back/depth buffer are on
 421  * the order of 30%.
 422  *
 423  * Intel architectures make this somewhat more complicated, though, by
 424  * adjustments made to addressing of data when the memory is in interleaved
 425  * mode (matched pairs of DIMMS) to improve memory bandwidth.
 426  * For interleaved memory, the CPU sends every sequential 64 bytes
 427  * to an alternate memory channel so it can get the bandwidth from both.
 428  *
 429  * The GPU also rearranges its accesses for increased bandwidth to interleaved
 430  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 431  * it does it a little differently, since one walks addresses not just in the
 432  * X direction but also Y.  So, along with alternating channels when bit
 433  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 434  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 435  * are common to both the 915 and 965-class hardware.
 436  *
 437  * The CPU also sometimes XORs in higher bits as well, to improve
 438  * bandwidth doing strided access like we do so frequently in graphics.  This
 439  * is called "Channel XOR Randomization" in the MCH documentation.  The result
 440  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 441  * decode.
 442  *
 443  * All of this bit 6 XORing has an effect on our memory management,
 444  * as we need to make sure that the 3d driver can correctly address object
 445  * contents.
 446  *
 447  * If we don't have interleaved memory, all tiling is safe and no swizzling is
 448  * required.
 449  *
 450  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 451  * 17 is not just a page offset, so as we page an object out and back in,
 452  * individual pages in it will have different bit 17 addresses, resulting in
 453  * each 64 bytes being swapped with its neighbor!
 454  *
 455  * Otherwise, if interleaved, we have to tell the 3d driver what the address
 456  * swizzling it needs to do is, since it's writing with the CPU to the pages
 457  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 458  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 459  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 460  * to match what the GPU expects.
 461  */
 462
 463 /**
 464  * i915_gem_detect_bit_6_swizzle - detect bit 6 swizzling pattern
 465  * @dev_priv: i915 device private
 466  *
 467  * Detects bit 6 swizzling of address lookup between IGD access and CPU
 468  * access through main memory.
 469  */
 470 void
 471 i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
 472 {
 473         uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 474         uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 475
 476         if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
 477                 /*
 478                  * On BDW+, swizzling is not used. We leave the CPU memory
 479                  * controller in charge of optimizing memory accesses without
 480                  * the extra address manipulation GPU side.
 481                  *
 482                  * VLV and CHV don't have GPU swizzling.
 483                  */
 484                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 485                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 486         } else if (INTEL_GEN(dev_priv) >= 6) {
 487                 if (dev_priv->preserve_bios_swizzle) {
 488                         if (I915_READ(DISP_ARB_CTL) &
 489                             DISP_TILE_SURFACE_SWIZZLING) {
 490                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 491                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 492                         } else {
 493                                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 494                                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 495                         }
 496                 } else {
 497                         uint32_t dimm_c0, dimm_c1;
 498                         dimm_c0 = I915_READ(MAD_DIMM_C0);
 499                         dimm_c1 = I915_READ(MAD_DIMM_C1);
 500                         dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 501                         dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 502                         /* Enable swizzling when the channels are populated
 503                          * with identically sized dimms. We don't need to check
 504                          * the 3rd channel because no cpu with gpu attached
 505                          * ships in that configuration. Also, swizzling only
 506                          * makes sense for 2 channels anyway. */
 507                         if (dimm_c0 == dimm_c1) {
 508                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 509                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 510                         } else {
 511                                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 512                                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 513                         }
 514                 }
 515         } else if (IS_GEN5(dev_priv)) {
 516                 /* On Ironlake whatever DRAM config, GPU always do
 517                  * same swizzling setup.
 518                  */
 519                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 520                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 521         } else if (IS_GEN2(dev_priv)) {
 522                 /* As far as we know, the 865 doesn't have these bit 6
 523                  * swizzling issues.
 524                  */
 525                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 526                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 527         } else if (IS_MOBILE(dev_priv) ||
 528                    IS_I915G(dev_priv) || IS_I945G(dev_priv)) {
 529                 uint32_t dcc;
 530
 531                 /* On 9xx chipsets, channel interleave by the CPU is
 532                  * determined by DCC.  For single-channel, neither the CPU
 533                  * nor the GPU do swizzling.  For dual channel interleaved,
 534                  * the GPU's interleave is bit 9 and 10 for X tiled, and bit
 535                  * 9 for Y tiled.  The CPU's interleave is independent, and
 536                  * can be based on either bit 11 (haven't seen this yet) or
 537                  * bit 17 (common).
 538                  */
 539                 dcc = I915_READ(DCC);
 540                 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
 541                 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
 542                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
 543                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 544                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 545                         break;
 546                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
 547                         if (dcc & DCC_CHANNEL_XOR_DISABLE) {
 548                                 /* This is the base swizzling by the GPU for
 549                                  * tiled buffers.
 550                                  */
 551                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 552                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 553                         } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
 554                                 /* Bit 11 swizzling by the CPU in addition. */
 555                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
 556                                 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
 557                         } else {
 558                                 /* Bit 17 swizzling by the CPU in addition. */
 559                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 560                                 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 561                         }
 562                         break;
 563                 }
 564
 565                 /* check for L-shaped memory aka modified enhanced addressing */
 566                 if (IS_GEN4(dev_priv) &&
 567                     !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
 568                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 569                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 570                 }
 571
 572                 if (dcc == 0xffffffff) {
 573                         DRM_ERROR("Couldn't read from MCHBAR.  "
 574                                   "Disabling tiling.\n");
 575                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 576                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 577                 }
 578         } else {
 579                 /* The 965, G33, and newer, have a very flexible memory
 580                  * configuration.  It will enable dual-channel mode
 581                  * (interleaving) on as much memory as it can, and the GPU
 582                  * will additionally sometimes enable different bit 6
 583                  * swizzling for tiled objects from the CPU.
 584                  *
 585                  * Here's what I found on the G965:
 586                  *    slot fill         memory size  swizzling
 587                  * 0A   0B   1A   1B    1-ch   2-ch
 588                  * 512  0    0    0     512    0     O
 589                  * 512  0    512  0     16     1008  X
 590                  * 512  0    0    512   16     1008  X
 591                  * 0    512  0    512   16     1008  X
 592                  * 1024 1024 1024 0     2048   1024  O
 593                  *
 594                  * We could probably detect this based on either the DRB
 595                  * matching, which was the case for the swizzling required in
 596                  * the table above, or from the 1-ch value being less than
 597                  * the minimum size of a rank.
 598                  *
 599                  * Reports indicate that the swizzling actually
 600                  * varies depending upon page placement inside the
 601                  * channels, i.e. we see swizzled pages where the
 602                  * banks of memory are paired and unswizzled on the
 603                  * uneven portion, so leave that as unknown.
 604                  */
 605                 if (I915_READ16(C0DRB3) == I915_READ16(C1DRB3)) {
 606                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 607                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 608                 }
 609         }
 610
 611         if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
 612             swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
 613                 /* Userspace likes to explode if it sees unknown swizzling,
 614                  * so lie. We will finish the lie when reporting through
 615                  * the get-tiling-ioctl by reporting the physical swizzle
 616                  * mode as unknown instead.
 617                  *
 618                  * As we don't strictly know what the swizzling is, it may be
 619                  * bit17 dependent, and so we need to also prevent the pages
 620                  * from being moved.
 621                  */
 622                 dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
 623                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 624                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 625         }
 626
 627         dev_priv->mm.bit_6_swizzle_x = swizzle_x;
 628         dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 629 }
 630
 631 /*
 632  * Swap every 64 bytes of this page around, to account for it having a new
 633  * bit 17 of its physical address and therefore being interpreted differently
 634  * by the GPU.
 635  */
 636 static void
 637 i915_gem_swizzle_page(struct page *page)
 638 {
 639         char temp[64];
 640         char *vaddr;
 641         int i;
 642
 643         vaddr = kmap(page);
 644
 645         for (i = 0; i < PAGE_SIZE; i += 128) {
 646                 memcpy(temp, &vaddr[i], 64);
 647                 memcpy(&vaddr[i], &vaddr[i + 64], 64);
 648                 memcpy(&vaddr[i + 64], temp, 64);
 649         }
 650
 651         kunmap(page);
 652 }
 653
 654 /**
 655  * i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling
 656  * @obj: i915 GEM buffer object
 657  * @pages: the scattergather list of physical pages
 658  *
 659  * This function fixes up the swizzling in case any page frame number for this
 660  * object has changed in bit 17 since that state has been saved with
 661  * i915_gem_object_save_bit_17_swizzle().
 662  *
 663  * This is called when pinning backing storage again, since the kernel is free
 664  * to move unpinned backing storage around (either by directly moving pages or
 665  * by swapping them out and back in again).
 666  */
 667 void
 668 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
 669                                   struct sg_table *pages)
 670 {
 671         struct sgt_iter sgt_iter;
 672         struct page *page;
 673         int i;
 674
 675         if (obj->bit_17 == NULL)
 676                 return;
 677
 678         i = 0;
 679         for_each_sgt_page(page, sgt_iter, pages) {
 680                 char new_bit_17 = page_to_phys(page) >> 17;
 681                 if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {
 682                         i915_gem_swizzle_page(page);
 683                         set_page_dirty(page);
 684                 }
 685                 i++;
 686         }
 687 }
 688
 689 /**
 690  * i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling
 691  * @obj: i915 GEM buffer object
 692  * @pages: the scattergather list of physical pages
 693  *
 694  * This function saves the bit 17 of each page frame number so that swizzling
 695  * can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must
 696  * be called before the backing storage can be unpinned.
 697  */
 698 void
 699 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 700                                     struct sg_table *pages)
 701 {
 702         const unsigned int page_count = obj->base.size >> PAGE_SHIFT;
 703         struct sgt_iter sgt_iter;
 704         struct page *page;
 705         int i;
 706
 707         if (obj->bit_17 == NULL) {
 708                 obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
 709                                       sizeof(long), GFP_KERNEL);
 710                 if (obj->bit_17 == NULL) {
 711                         DRM_ERROR("Failed to allocate memory for bit 17 "
 712                                   "record\n");
 713                         return;
 714                 }
 715         }
 716
 717         i = 0;
 718
 719         for_each_sgt_page(page, sgt_iter, pages) {
 720                 if (page_to_phys(page) & (1 << 17))
 721                         __set_bit(i, obj->bit_17);
 722                 else
 723                         __clear_bit(i, obj->bit_17);
 724                 i++;
 725         }
 726 }