2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/sync_file.h>
32 #include <linux/uaccess.h>
35 #include <drm/drm_syncobj.h>
36 #include <drm/i915_drm.h>
39 #include "i915_gem_clflush.h"
40 #include "i915_trace.h"
41 #include "intel_drv.h"
42 #include "intel_frontbuffer.h"
48 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
51 #define __EXEC_OBJECT_HAS_REF BIT(31)
52 #define __EXEC_OBJECT_HAS_PIN BIT(30)
53 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
54 #define __EXEC_OBJECT_NEEDS_MAP BIT(28)
55 #define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
56 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */
57 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
59 #define __EXEC_HAS_RELOC BIT(31)
60 #define __EXEC_VALIDATED BIT(30)
61 #define __EXEC_INTERNAL_FLAGS (~0u << 30)
62 #define UPDATE PIN_OFFSET_FIXED
64 #define BATCH_OFFSET_BIAS (256*1024)
66 #define __I915_EXEC_ILLEGAL_FLAGS \
67 (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK)
70 * DOC: User command execution
72 * Userspace submits commands to be executed on the GPU as an instruction
73 * stream within a GEM object we call a batchbuffer. This instructions may
74 * refer to other GEM objects containing auxiliary state such as kernels,
75 * samplers, render targets and even secondary batchbuffers. Userspace does
76 * not know where in the GPU memory these objects reside and so before the
77 * batchbuffer is passed to the GPU for execution, those addresses in the
78 * batchbuffer and auxiliary objects are updated. This is known as relocation,
79 * or patching. To try and avoid having to relocate each object on the next
80 * execution, userspace is told the location of those objects in this pass,
81 * but this remains just a hint as the kernel may choose a new location for
82 * any object in the future.
84 * At the level of talking to the hardware, submitting a batchbuffer for the
85 * GPU to execute is to add content to a buffer from which the HW
86 * command streamer is reading.
88 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
89 * Execlists, this command is not placed on the same buffer as the
92 * 2. Add a command to invalidate caches to the buffer.
94 * 3. Add a batchbuffer start command to the buffer; the start command is
95 * essentially a token together with the GPU address of the batchbuffer
98 * 4. Add a pipeline flush to the buffer.
100 * 5. Add a memory write command to the buffer to record when the GPU
101 * is done executing the batchbuffer. The memory write writes the
102 * global sequence number of the request, ``i915_request::global_seqno``;
103 * the i915 driver uses the current value in the register to determine
104 * if the GPU has completed the batchbuffer.
106 * 6. Add a user interrupt command to the buffer. This command instructs
107 * the GPU to issue an interrupt when the command, pipeline flush and
108 * memory write are completed.
110 * 7. Inform the hardware of the additional commands added to the buffer
111 * (by updating the tail pointer).
113 * Processing an execbuf ioctl is conceptually split up into a few phases.
115 * 1. Validation - Ensure all the pointers, handles and flags are valid.
116 * 2. Reservation - Assign GPU address space for every object
117 * 3. Relocation - Update any addresses to point to the final locations
118 * 4. Serialisation - Order the request with respect to its dependencies
119 * 5. Construction - Construct a request to execute the batchbuffer
120 * 6. Submission (at some point in the future execution)
122 * Reserving resources for the execbuf is the most complicated phase. We
123 * neither want to have to migrate the object in the address space, nor do
124 * we want to have to update any relocations pointing to this object. Ideally,
125 * we want to leave the object where it is and for all the existing relocations
126 * to match. If the object is given a new address, or if userspace thinks the
127 * object is elsewhere, we have to parse all the relocation entries and update
128 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
129 * all the target addresses in all of its objects match the value in the
130 * relocation entries and that they all match the presumed offsets given by the
131 * list of execbuffer objects. Using this knowledge, we know that if we haven't
132 * moved any buffers, all the relocation entries are valid and we can skip
133 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
134 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
136 * The addresses written in the objects must match the corresponding
137 * reloc.presumed_offset which in turn must match the corresponding
140 * Any render targets written to in the batch must be flagged with
143 * To avoid stalling, execobject.offset should match the current
144 * address of that object within the active context.
146 * The reservation is done is multiple phases. First we try and keep any
147 * object already bound in its current location - so as long as meets the
148 * constraints imposed by the new execbuffer. Any object left unbound after the
149 * first pass is then fitted into any available idle space. If an object does
150 * not fit, all objects are removed from the reservation and the process rerun
151 * after sorting the objects into a priority order (more difficult to fit
152 * objects are tried first). Failing that, the entire VM is cleared and we try
153 * to fit the execbuf once last time before concluding that it simply will not
156 * A small complication to all of this is that we allow userspace not only to
157 * specify an alignment and a size for the object in the address space, but
158 * we also allow userspace to specify the exact offset. This objects are
159 * simpler to place (the location is known a priori) all we have to do is make
160 * sure the space is available.
162 * Once all the objects are in place, patching up the buried pointers to point
163 * to the final locations is a fairly simple job of walking over the relocation
164 * entry arrays, looking up the right address and rewriting the value into
165 * the object. Simple! ... The relocation entries are stored in user memory
166 * and so to access them we have to copy them into a local buffer. That copy
167 * has to avoid taking any pagefaults as they may lead back to a GEM object
168 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
169 * the relocation into multiple passes. First we try to do everything within an
170 * atomic context (avoid the pagefaults) which requires that we never wait. If
171 * we detect that we may wait, or if we need to fault, then we have to fallback
172 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
173 * bells yet?) Dropping the mutex means that we lose all the state we have
174 * built up so far for the execbuf and we must reset any global data. However,
175 * we do leave the objects pinned in their final locations - which is a
176 * potential issue for concurrent execbufs. Once we have left the mutex, we can
177 * allocate and copy all the relocation entries into a large array at our
178 * leisure, reacquire the mutex, reclaim all the objects and other state and
179 * then proceed to update any incorrect addresses with the objects.
181 * As we process the relocation entries, we maintain a record of whether the
182 * object is being written to. Using NORELOC, we expect userspace to provide
183 * this information instead. We also check whether we can skip the relocation
184 * by comparing the expected value inside the relocation entry with the target's
185 * final address. If they differ, we have to map the current object and rewrite
186 * the 4 or 8 byte pointer within.
188 * Serialising an execbuf is quite simple according to the rules of the GEM
189 * ABI. Execution within each context is ordered by the order of submission.
190 * Writes to any GEM object are in order of submission and are exclusive. Reads
191 * from a GEM object are unordered with respect to other reads, but ordered by
192 * writes. A write submitted after a read cannot occur before the read, and
193 * similarly any read submitted after a write cannot occur before the write.
194 * Writes are ordered between engines such that only one write occurs at any
195 * time (completing any reads beforehand) - using semaphores where available
196 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
197 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
198 * reads before starting, and any read (either using set-domain or pread) must
199 * flush all GPU writes before starting. (Note we only employ a barrier before,
200 * we currently rely on userspace not concurrently starting a new execution
201 * whilst reading or writing to an object. This may be an advantage or not
202 * depending on how much you trust userspace not to shoot themselves in the
203 * foot.) Serialisation may just result in the request being inserted into
204 * a DAG awaiting its turn, but most simple is to wait on the CPU until
205 * all dependencies are resolved.
207 * After all of that, is just a matter of closing the request and handing it to
208 * the hardware (well, leaving it in a queue to be executed). However, we also
209 * offer the ability for batchbuffers to be run with elevated privileges so
210 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
211 * Before any batch is given extra privileges we first must check that it
212 * contains no nefarious instructions, we check that each instruction is from
213 * our whitelist and all registers are also from an allowed list. We first
214 * copy the user's batchbuffer to a shadow (so that the user doesn't have
215 * access to it, either by the CPU or GPU as we scan it) and then parse each
216 * instruction. If everything is ok, we set a flag telling the hardware to run
217 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
220 struct i915_execbuffer {
221 struct drm_i915_private *i915; /** i915 backpointer */
222 struct drm_file *file; /** per-file lookup tables and limits */
223 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
224 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
225 struct i915_vma **vma;
228 struct intel_engine_cs *engine; /** engine to queue the request to */
229 struct i915_gem_context *ctx; /** context for building the request */
230 struct i915_address_space *vm; /** GTT and vma for the request */
232 struct i915_request *request; /** our request to build */
233 struct i915_vma *batch; /** identity of the batch obj/vma */
235 /** actual size of execobj[] as we may extend it for the cmdparser */
236 unsigned int buffer_count;
238 /** list of vma not yet bound during reservation phase */
239 struct list_head unbound;
241 /** list of vma that have execobj.relocation_count */
242 struct list_head relocs;
245 * Track the most recently used object for relocations, as we
246 * frequently have to perform multiple relocations within the same
250 struct drm_mm_node node; /** temporary GTT binding */
251 unsigned long vaddr; /** Current kmap address */
252 unsigned long page; /** Currently mapped page index */
253 unsigned int gen; /** Cached value of INTEL_GEN */
254 bool use_64bit_reloc : 1;
257 bool needs_unfenced : 1;
259 struct i915_request *rq;
261 unsigned int rq_size;
264 u64 invalid_flags; /** Set of execobj.flags that are invalid */
265 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
267 u32 batch_start_offset; /** Location within object of batch */
268 u32 batch_len; /** Length of batch within object */
269 u32 batch_flags; /** Flags composed for emit_bb_start() */
272 * Indicate either the size of the hastable used to resolve
273 * relocation handles, or if negative that we are using a direct
274 * index into the execobj[].
277 struct hlist_head *buckets; /** ht for relocation handles */
280 #define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
283 * Used to convert any address to canonical form.
284 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
285 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
286 * addresses to be in a canonical form:
287 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
288 * canonical form [63:48] == [47]."
290 #define GEN8_HIGH_ADDRESS_BIT 47
291 static inline u64 gen8_canonical_addr(u64 address)
293 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
296 static inline u64 gen8_noncanonical_addr(u64 address)
298 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
301 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
303 return intel_engine_needs_cmd_parser(eb->engine) && eb->batch_len;
306 static int eb_create(struct i915_execbuffer *eb)
308 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
309 unsigned int size = 1 + ilog2(eb->buffer_count);
312 * Without a 1:1 association between relocation handles and
313 * the execobject[] index, we instead create a hashtable.
314 * We size it dynamically based on available memory, starting
315 * first with 1:1 assocative hash and scaling back until
316 * the allocation succeeds.
318 * Later on we use a positive lut_size to indicate we are
319 * using this hashtable, and a negative value to indicate a
325 /* While we can still reduce the allocation size, don't
326 * raise a warning and allow the allocation to fail.
327 * On the last pass though, we want to try as hard
328 * as possible to perform the allocation and warn
333 flags |= __GFP_NORETRY | __GFP_NOWARN;
335 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
346 eb->lut_size = -eb->buffer_count;
353 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
354 const struct i915_vma *vma,
357 if (vma->node.size < entry->pad_to_size)
360 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
363 if (flags & EXEC_OBJECT_PINNED &&
364 vma->node.start != entry->offset)
367 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
368 vma->node.start < BATCH_OFFSET_BIAS)
371 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
372 (vma->node.start + vma->node.size - 1) >> 32)
375 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
376 !i915_vma_is_map_and_fenceable(vma))
383 eb_pin_vma(struct i915_execbuffer *eb,
384 const struct drm_i915_gem_exec_object2 *entry,
385 struct i915_vma *vma)
387 unsigned int exec_flags = *vma->exec_flags;
391 pin_flags = vma->node.start;
393 pin_flags = entry->offset & PIN_OFFSET_MASK;
395 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
396 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT))
397 pin_flags |= PIN_GLOBAL;
399 if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags)))
402 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
403 if (unlikely(i915_vma_pin_fence(vma))) {
409 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
412 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
413 return !eb_vma_misplaced(entry, vma, exec_flags);
416 static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
418 GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
420 if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
421 __i915_vma_unpin_fence(vma);
423 __i915_vma_unpin(vma);
427 eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags)
429 if (!(*flags & __EXEC_OBJECT_HAS_PIN))
432 __eb_unreserve_vma(vma, *flags);
433 *flags &= ~__EXEC_OBJECT_RESERVED;
437 eb_validate_vma(struct i915_execbuffer *eb,
438 struct drm_i915_gem_exec_object2 *entry,
439 struct i915_vma *vma)
441 if (unlikely(entry->flags & eb->invalid_flags))
444 if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
448 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
449 * any non-page-aligned or non-canonical addresses.
451 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
452 entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
455 /* pad_to_size was once a reserved field, so sanitize it */
456 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
457 if (unlikely(offset_in_page(entry->pad_to_size)))
460 entry->pad_to_size = 0;
463 if (unlikely(vma->exec_flags)) {
464 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
465 entry->handle, (int)(entry - eb->exec));
470 * From drm_mm perspective address space is continuous,
471 * so from this point we're always using non-canonical
474 entry->offset = gen8_noncanonical_addr(entry->offset);
476 if (!eb->reloc_cache.has_fence) {
477 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
479 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
480 eb->reloc_cache.needs_unfenced) &&
481 i915_gem_object_is_tiled(vma->obj))
482 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
485 if (!(entry->flags & EXEC_OBJECT_PINNED))
486 entry->flags |= eb->context_flags;
492 eb_add_vma(struct i915_execbuffer *eb,
493 unsigned int i, unsigned batch_idx,
494 struct i915_vma *vma)
496 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
499 GEM_BUG_ON(i915_vma_is_closed(vma));
501 if (!(eb->args->flags & __EXEC_VALIDATED)) {
502 err = eb_validate_vma(eb, entry, vma);
507 if (eb->lut_size > 0) {
508 vma->exec_handle = entry->handle;
509 hlist_add_head(&vma->exec_node,
510 &eb->buckets[hash_32(entry->handle,
514 if (entry->relocation_count)
515 list_add_tail(&vma->reloc_link, &eb->relocs);
518 * Stash a pointer from the vma to execobj, so we can query its flags,
519 * size, alignment etc as provided by the user. Also we stash a pointer
520 * to the vma inside the execobj so that we can use a direct lookup
521 * to find the right target VMA when doing relocations.
524 eb->flags[i] = entry->flags;
525 vma->exec_flags = &eb->flags[i];
528 * SNA is doing fancy tricks with compressing batch buffers, which leads
529 * to negative relocation deltas. Usually that works out ok since the
530 * relocate address is still positive, except when the batch is placed
531 * very low in the GTT. Ensure this doesn't happen.
533 * Note that actual hangs have only been observed on gen7, but for
534 * paranoia do it everywhere.
536 if (i == batch_idx) {
537 if (!(eb->flags[i] & EXEC_OBJECT_PINNED))
538 eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
539 if (eb->reloc_cache.has_fence)
540 eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
546 if (eb_pin_vma(eb, entry, vma)) {
547 if (entry->offset != vma->node.start) {
548 entry->offset = vma->node.start | UPDATE;
549 eb->args->flags |= __EXEC_HAS_RELOC;
552 eb_unreserve_vma(vma, vma->exec_flags);
554 list_add_tail(&vma->exec_link, &eb->unbound);
555 if (drm_mm_node_allocated(&vma->node))
556 err = i915_vma_unbind(vma);
558 vma->exec_flags = NULL;
563 static inline int use_cpu_reloc(const struct reloc_cache *cache,
564 const struct drm_i915_gem_object *obj)
566 if (!i915_gem_object_has_struct_page(obj))
569 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
572 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
575 return (cache->has_llc ||
577 obj->cache_level != I915_CACHE_NONE);
580 static int eb_reserve_vma(const struct i915_execbuffer *eb,
581 struct i915_vma *vma)
583 struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
584 unsigned int exec_flags = *vma->exec_flags;
588 pin_flags = PIN_USER | PIN_NONBLOCK;
589 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
590 pin_flags |= PIN_GLOBAL;
593 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
594 * limit address to the first 4GBs for unflagged objects.
596 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
597 pin_flags |= PIN_ZONE_4G;
599 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
600 pin_flags |= PIN_MAPPABLE;
602 if (exec_flags & EXEC_OBJECT_PINNED) {
603 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
604 pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */
605 } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) {
606 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
609 err = i915_vma_pin(vma,
610 entry->pad_to_size, entry->alignment,
615 if (entry->offset != vma->node.start) {
616 entry->offset = vma->node.start | UPDATE;
617 eb->args->flags |= __EXEC_HAS_RELOC;
620 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
621 err = i915_vma_pin_fence(vma);
628 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
631 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
632 GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags));
637 static int eb_reserve(struct i915_execbuffer *eb)
639 const unsigned int count = eb->buffer_count;
640 struct list_head last;
641 struct i915_vma *vma;
642 unsigned int i, pass;
646 * Attempt to pin all of the buffers into the GTT.
647 * This is done in 3 phases:
649 * 1a. Unbind all objects that do not match the GTT constraints for
650 * the execbuffer (fenceable, mappable, alignment etc).
651 * 1b. Increment pin count for already bound objects.
652 * 2. Bind new objects.
653 * 3. Decrement pin count.
655 * This avoid unnecessary unbinding of later objects in order to make
656 * room for the earlier objects *unless* we need to defragment.
662 list_for_each_entry(vma, &eb->unbound, exec_link) {
663 err = eb_reserve_vma(eb, vma);
670 /* Resort *all* the objects into priority order */
671 INIT_LIST_HEAD(&eb->unbound);
672 INIT_LIST_HEAD(&last);
673 for (i = 0; i < count; i++) {
674 unsigned int flags = eb->flags[i];
675 struct i915_vma *vma = eb->vma[i];
677 if (flags & EXEC_OBJECT_PINNED &&
678 flags & __EXEC_OBJECT_HAS_PIN)
681 eb_unreserve_vma(vma, &eb->flags[i]);
683 if (flags & EXEC_OBJECT_PINNED)
684 list_add(&vma->exec_link, &eb->unbound);
685 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
686 list_add_tail(&vma->exec_link, &eb->unbound);
688 list_add_tail(&vma->exec_link, &last);
690 list_splice_tail(&last, &eb->unbound);
697 /* Too fragmented, unbind everything and retry */
698 err = i915_gem_evict_vm(eb->vm);
709 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
711 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
714 return eb->buffer_count - 1;
717 static int eb_select_context(struct i915_execbuffer *eb)
719 struct i915_gem_context *ctx;
721 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
726 eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base;
728 eb->context_flags = 0;
729 if (ctx->flags & CONTEXT_NO_ZEROMAP)
730 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
735 static int eb_lookup_vmas(struct i915_execbuffer *eb)
737 struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
738 struct drm_i915_gem_object *obj;
739 unsigned int i, batch;
742 if (unlikely(i915_gem_context_is_closed(eb->ctx)))
745 if (unlikely(i915_gem_context_is_banned(eb->ctx)))
748 INIT_LIST_HEAD(&eb->relocs);
749 INIT_LIST_HEAD(&eb->unbound);
751 batch = eb_batch_index(eb);
753 for (i = 0; i < eb->buffer_count; i++) {
754 u32 handle = eb->exec[i].handle;
755 struct i915_lut_handle *lut;
756 struct i915_vma *vma;
758 vma = radix_tree_lookup(handles_vma, handle);
762 obj = i915_gem_object_lookup(eb->file, handle);
763 if (unlikely(!obj)) {
768 vma = i915_vma_instance(obj, eb->vm, NULL);
769 if (unlikely(IS_ERR(vma))) {
774 lut = kmem_cache_alloc(eb->i915->luts, GFP_KERNEL);
775 if (unlikely(!lut)) {
780 err = radix_tree_insert(handles_vma, handle, vma);
782 kmem_cache_free(eb->i915->luts, lut);
786 /* transfer ref to ctx */
787 if (!vma->open_count++)
788 i915_vma_reopen(vma);
789 list_add(&lut->obj_link, &obj->lut_list);
790 list_add(&lut->ctx_link, &eb->ctx->handles_list);
792 lut->handle = handle;
795 err = eb_add_vma(eb, i, batch, vma);
799 GEM_BUG_ON(vma != eb->vma[i]);
800 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
801 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
802 eb_vma_misplaced(&eb->exec[i], vma, eb->flags[i]));
805 eb->args->flags |= __EXEC_VALIDATED;
806 return eb_reserve(eb);
809 i915_gem_object_put(obj);
815 static struct i915_vma *
816 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
818 if (eb->lut_size < 0) {
819 if (handle >= -eb->lut_size)
821 return eb->vma[handle];
823 struct hlist_head *head;
824 struct i915_vma *vma;
826 head = &eb->buckets[hash_32(handle, eb->lut_size)];
827 hlist_for_each_entry(vma, head, exec_node) {
828 if (vma->exec_handle == handle)
835 static void eb_release_vmas(const struct i915_execbuffer *eb)
837 const unsigned int count = eb->buffer_count;
840 for (i = 0; i < count; i++) {
841 struct i915_vma *vma = eb->vma[i];
842 unsigned int flags = eb->flags[i];
847 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
848 vma->exec_flags = NULL;
851 if (flags & __EXEC_OBJECT_HAS_PIN)
852 __eb_unreserve_vma(vma, flags);
854 if (flags & __EXEC_OBJECT_HAS_REF)
859 static void eb_reset_vmas(const struct i915_execbuffer *eb)
862 if (eb->lut_size > 0)
863 memset(eb->buckets, 0,
864 sizeof(struct hlist_head) << eb->lut_size);
867 static void eb_destroy(const struct i915_execbuffer *eb)
869 GEM_BUG_ON(eb->reloc_cache.rq);
871 if (eb->lut_size > 0)
876 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
877 const struct i915_vma *target)
879 return gen8_canonical_addr((int)reloc->delta + target->node.start);
882 static void reloc_cache_init(struct reloc_cache *cache,
883 struct drm_i915_private *i915)
887 /* Must be a variable in the struct to allow GCC to unroll. */
888 cache->gen = INTEL_GEN(i915);
889 cache->has_llc = HAS_LLC(i915);
890 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
891 cache->has_fence = cache->gen < 4;
892 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
893 cache->node.allocated = false;
898 static inline void *unmask_page(unsigned long p)
900 return (void *)(uintptr_t)(p & PAGE_MASK);
903 static inline unsigned int unmask_flags(unsigned long p)
905 return p & ~PAGE_MASK;
908 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
910 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
912 struct drm_i915_private *i915 =
913 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
917 static void reloc_gpu_flush(struct reloc_cache *cache)
919 GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32));
920 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
921 i915_gem_object_unpin_map(cache->rq->batch->obj);
922 i915_gem_chipset_flush(cache->rq->i915);
924 __i915_request_add(cache->rq, true);
928 static void reloc_cache_reset(struct reloc_cache *cache)
933 reloc_gpu_flush(cache);
938 vaddr = unmask_page(cache->vaddr);
939 if (cache->vaddr & KMAP) {
940 if (cache->vaddr & CLFLUSH_AFTER)
943 kunmap_atomic(vaddr);
944 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
947 io_mapping_unmap_atomic((void __iomem *)vaddr);
948 if (cache->node.allocated) {
949 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
951 ggtt->base.clear_range(&ggtt->base,
954 drm_mm_remove_node(&cache->node);
956 i915_vma_unpin((struct i915_vma *)cache->node.mm);
964 static void *reloc_kmap(struct drm_i915_gem_object *obj,
965 struct reloc_cache *cache,
971 kunmap_atomic(unmask_page(cache->vaddr));
973 unsigned int flushes;
976 err = i915_gem_obj_prepare_shmem_write(obj, &flushes);
980 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
981 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
983 cache->vaddr = flushes | KMAP;
984 cache->node.mm = (void *)obj;
989 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
990 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
996 static void *reloc_iomap(struct drm_i915_gem_object *obj,
997 struct reloc_cache *cache,
1000 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1001 unsigned long offset;
1005 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1007 struct i915_vma *vma;
1010 if (use_cpu_reloc(cache, obj))
1013 err = i915_gem_object_set_to_gtt_domain(obj, true);
1015 return ERR_PTR(err);
1017 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1022 memset(&cache->node, 0, sizeof(cache->node));
1023 err = drm_mm_insert_node_in_range
1024 (&ggtt->base.mm, &cache->node,
1025 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1026 0, ggtt->mappable_end,
1028 if (err) /* no inactive aperture space, use cpu reloc */
1031 err = i915_vma_put_fence(vma);
1033 i915_vma_unpin(vma);
1034 return ERR_PTR(err);
1037 cache->node.start = vma->node.start;
1038 cache->node.mm = (void *)vma;
1042 offset = cache->node.start;
1043 if (cache->node.allocated) {
1045 ggtt->base.insert_page(&ggtt->base,
1046 i915_gem_object_get_dma_address(obj, page),
1047 offset, I915_CACHE_NONE, 0);
1049 offset += page << PAGE_SHIFT;
1052 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1055 cache->vaddr = (unsigned long)vaddr;
1060 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1061 struct reloc_cache *cache,
1066 if (cache->page == page) {
1067 vaddr = unmask_page(cache->vaddr);
1070 if ((cache->vaddr & KMAP) == 0)
1071 vaddr = reloc_iomap(obj, cache, page);
1073 vaddr = reloc_kmap(obj, cache, page);
1079 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1081 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1082 if (flushes & CLFLUSH_BEFORE) {
1090 * Writes to the same cacheline are serialised by the CPU
1091 * (including clflush). On the write path, we only require
1092 * that it hits memory in an orderly fashion and place
1093 * mb barriers at the start and end of the relocation phase
1094 * to ensure ordering of clflush wrt to the system.
1096 if (flushes & CLFLUSH_AFTER)
1102 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1103 struct i915_vma *vma,
1106 struct reloc_cache *cache = &eb->reloc_cache;
1107 struct drm_i915_gem_object *obj;
1108 struct i915_request *rq;
1109 struct i915_vma *batch;
1113 GEM_BUG_ON(vma->obj->write_domain & I915_GEM_DOMAIN_CPU);
1115 obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
1117 return PTR_ERR(obj);
1119 cmd = i915_gem_object_pin_map(obj,
1123 i915_gem_object_unpin_pages(obj);
1125 return PTR_ERR(cmd);
1127 err = i915_gem_object_set_to_wc_domain(obj, false);
1131 batch = i915_vma_instance(obj, vma->vm, NULL);
1132 if (IS_ERR(batch)) {
1133 err = PTR_ERR(batch);
1137 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1141 rq = i915_request_alloc(eb->engine, eb->ctx);
1147 err = i915_request_await_object(rq, vma->obj, true);
1151 err = eb->engine->emit_bb_start(rq,
1152 batch->node.start, PAGE_SIZE,
1153 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1157 GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch->resv, true));
1158 i915_vma_move_to_active(batch, rq, 0);
1159 reservation_object_lock(batch->resv, NULL);
1160 reservation_object_add_excl_fence(batch->resv, &rq->fence);
1161 reservation_object_unlock(batch->resv);
1162 i915_vma_unpin(batch);
1164 i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1165 reservation_object_lock(vma->resv, NULL);
1166 reservation_object_add_excl_fence(vma->resv, &rq->fence);
1167 reservation_object_unlock(vma->resv);
1172 cache->rq_cmd = cmd;
1175 /* Return with batch mapping (cmd) still pinned */
1179 i915_request_add(rq);
1181 i915_vma_unpin(batch);
1183 i915_gem_object_unpin_map(obj);
1187 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1188 struct i915_vma *vma,
1191 struct reloc_cache *cache = &eb->reloc_cache;
1194 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1195 reloc_gpu_flush(cache);
1197 if (unlikely(!cache->rq)) {
1200 /* If we need to copy for the cmdparser, we will stall anyway */
1201 if (eb_use_cmdparser(eb))
1202 return ERR_PTR(-EWOULDBLOCK);
1204 if (!intel_engine_can_store_dword(eb->engine))
1205 return ERR_PTR(-ENODEV);
1207 err = __reloc_gpu_alloc(eb, vma, len);
1209 return ERR_PTR(err);
1212 cmd = cache->rq_cmd + cache->rq_size;
1213 cache->rq_size += len;
1219 relocate_entry(struct i915_vma *vma,
1220 const struct drm_i915_gem_relocation_entry *reloc,
1221 struct i915_execbuffer *eb,
1222 const struct i915_vma *target)
1224 u64 offset = reloc->offset;
1225 u64 target_offset = relocation_target(reloc, target);
1226 bool wide = eb->reloc_cache.use_64bit_reloc;
1229 if (!eb->reloc_cache.vaddr &&
1230 (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
1231 !reservation_object_test_signaled_rcu(vma->resv, true))) {
1232 const unsigned int gen = eb->reloc_cache.gen;
1238 len = offset & 7 ? 8 : 5;
1244 batch = reloc_gpu(eb, vma, len);
1248 addr = gen8_canonical_addr(vma->node.start + offset);
1251 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1252 *batch++ = lower_32_bits(addr);
1253 *batch++ = upper_32_bits(addr);
1254 *batch++ = lower_32_bits(target_offset);
1256 addr = gen8_canonical_addr(addr + 4);
1258 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1259 *batch++ = lower_32_bits(addr);
1260 *batch++ = upper_32_bits(addr);
1261 *batch++ = upper_32_bits(target_offset);
1263 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1264 *batch++ = lower_32_bits(addr);
1265 *batch++ = upper_32_bits(addr);
1266 *batch++ = lower_32_bits(target_offset);
1267 *batch++ = upper_32_bits(target_offset);
1269 } else if (gen >= 6) {
1270 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1273 *batch++ = target_offset;
1274 } else if (gen >= 4) {
1275 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1278 *batch++ = target_offset;
1280 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1282 *batch++ = target_offset;
1289 vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT);
1291 return PTR_ERR(vaddr);
1293 clflush_write32(vaddr + offset_in_page(offset),
1294 lower_32_bits(target_offset),
1295 eb->reloc_cache.vaddr);
1298 offset += sizeof(u32);
1299 target_offset >>= 32;
1305 return target->node.start | UPDATE;
1309 eb_relocate_entry(struct i915_execbuffer *eb,
1310 struct i915_vma *vma,
1311 const struct drm_i915_gem_relocation_entry *reloc)
1313 struct i915_vma *target;
1316 /* we've already hold a reference to all valid objects */
1317 target = eb_get_vma(eb, reloc->target_handle);
1318 if (unlikely(!target))
1321 /* Validate that the target is in a valid r/w GPU domain */
1322 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1323 DRM_DEBUG("reloc with multiple write domains: "
1324 "target %d offset %d "
1325 "read %08x write %08x",
1326 reloc->target_handle,
1327 (int) reloc->offset,
1328 reloc->read_domains,
1329 reloc->write_domain);
1332 if (unlikely((reloc->write_domain | reloc->read_domains)
1333 & ~I915_GEM_GPU_DOMAINS)) {
1334 DRM_DEBUG("reloc with read/write non-GPU domains: "
1335 "target %d offset %d "
1336 "read %08x write %08x",
1337 reloc->target_handle,
1338 (int) reloc->offset,
1339 reloc->read_domains,
1340 reloc->write_domain);
1344 if (reloc->write_domain) {
1345 *target->exec_flags |= EXEC_OBJECT_WRITE;
1348 * Sandybridge PPGTT errata: We need a global gtt mapping
1349 * for MI and pipe_control writes because the gpu doesn't
1350 * properly redirect them through the ppgtt for non_secure
1353 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1354 IS_GEN6(eb->i915)) {
1355 err = i915_vma_bind(target, target->obj->cache_level,
1358 "Unexpected failure to bind target VMA!"))
1364 * If the relocation already has the right value in it, no
1365 * more work needs to be done.
1367 if (!DBG_FORCE_RELOC &&
1368 gen8_canonical_addr(target->node.start) == reloc->presumed_offset)
1371 /* Check that the relocation address is valid... */
1372 if (unlikely(reloc->offset >
1373 vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1374 DRM_DEBUG("Relocation beyond object bounds: "
1375 "target %d offset %d size %d.\n",
1376 reloc->target_handle,
1381 if (unlikely(reloc->offset & 3)) {
1382 DRM_DEBUG("Relocation not 4-byte aligned: "
1383 "target %d offset %d.\n",
1384 reloc->target_handle,
1385 (int)reloc->offset);
1390 * If we write into the object, we need to force the synchronisation
1391 * barrier, either with an asynchronous clflush or if we executed the
1392 * patching using the GPU (though that should be serialised by the
1393 * timeline). To be completely sure, and since we are required to
1394 * do relocations we are already stalling, disable the user's opt
1395 * out of our synchronisation.
1397 *vma->exec_flags &= ~EXEC_OBJECT_ASYNC;
1399 /* and update the user's relocation entry */
1400 return relocate_entry(vma, reloc, eb, target);
1403 static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
1405 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1406 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1407 struct drm_i915_gem_relocation_entry __user *urelocs;
1408 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1409 unsigned int remain;
1411 urelocs = u64_to_user_ptr(entry->relocs_ptr);
1412 remain = entry->relocation_count;
1413 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1417 * We must check that the entire relocation array is safe
1418 * to read. However, if the array is not writable the user loses
1419 * the updated relocation values.
1421 if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs))))
1425 struct drm_i915_gem_relocation_entry *r = stack;
1426 unsigned int count =
1427 min_t(unsigned int, remain, ARRAY_SIZE(stack));
1428 unsigned int copied;
1431 * This is the fast path and we cannot handle a pagefault
1432 * whilst holding the struct mutex lest the user pass in the
1433 * relocations contained within a mmaped bo. For in such a case
1434 * we, the page fault handler would call i915_gem_fault() and
1435 * we would try to acquire the struct mutex again. Obviously
1436 * this is bad and so lockdep complains vehemently.
1438 pagefault_disable();
1439 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1441 if (unlikely(copied)) {
1448 u64 offset = eb_relocate_entry(eb, vma, r);
1450 if (likely(offset == 0)) {
1451 } else if ((s64)offset < 0) {
1452 remain = (int)offset;
1456 * Note that reporting an error now
1457 * leaves everything in an inconsistent
1458 * state as we have *already* changed
1459 * the relocation value inside the
1460 * object. As we have not changed the
1461 * reloc.presumed_offset or will not
1462 * change the execobject.offset, on the
1463 * call we may not rewrite the value
1464 * inside the object, leaving it
1465 * dangling and causing a GPU hang. Unless
1466 * userspace dynamically rebuilds the
1467 * relocations on each execbuf rather than
1468 * presume a static tree.
1470 * We did previously check if the relocations
1471 * were writable (access_ok), an error now
1472 * would be a strange race with mprotect,
1473 * having already demonstrated that we
1474 * can read from this userspace address.
1476 offset = gen8_canonical_addr(offset & ~UPDATE);
1478 &urelocs[r-stack].presumed_offset);
1480 } while (r++, --count);
1481 urelocs += ARRAY_SIZE(stack);
1484 reloc_cache_reset(&eb->reloc_cache);
1489 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma)
1491 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1492 struct drm_i915_gem_relocation_entry *relocs =
1493 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1497 for (i = 0; i < entry->relocation_count; i++) {
1498 u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);
1500 if ((s64)offset < 0) {
1507 reloc_cache_reset(&eb->reloc_cache);
1511 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1513 const char __user *addr, *end;
1515 char __maybe_unused c;
1517 size = entry->relocation_count;
1521 if (size > N_RELOC(ULONG_MAX))
1524 addr = u64_to_user_ptr(entry->relocs_ptr);
1525 size *= sizeof(struct drm_i915_gem_relocation_entry);
1526 if (!access_ok(VERIFY_READ, addr, size))
1530 for (; addr < end; addr += PAGE_SIZE) {
1531 int err = __get_user(c, addr);
1535 return __get_user(c, end - 1);
1538 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1540 const unsigned int count = eb->buffer_count;
1544 for (i = 0; i < count; i++) {
1545 const unsigned int nreloc = eb->exec[i].relocation_count;
1546 struct drm_i915_gem_relocation_entry __user *urelocs;
1547 struct drm_i915_gem_relocation_entry *relocs;
1549 unsigned long copied;
1554 err = check_relocations(&eb->exec[i]);
1558 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1559 size = nreloc * sizeof(*relocs);
1561 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1568 /* copy_from_user is limited to < 4GiB */
1572 min_t(u64, BIT_ULL(31), size - copied);
1574 if (__copy_from_user((char *)relocs + copied,
1575 (char __user *)urelocs + copied,
1583 } while (copied < size);
1586 * As we do not update the known relocation offsets after
1587 * relocating (due to the complexities in lock handling),
1588 * we need to mark them as invalid now so that we force the
1589 * relocation processing next time. Just in case the target
1590 * object is evicted and then rebound into its old
1591 * presumed_offset before the next execbuffer - if that
1592 * happened we would make the mistake of assuming that the
1593 * relocations were valid.
1595 user_access_begin();
1596 for (copied = 0; copied < nreloc; copied++)
1598 &urelocs[copied].presumed_offset,
1603 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1610 struct drm_i915_gem_relocation_entry *relocs =
1611 u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1612 if (eb->exec[i].relocation_count)
1618 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1620 const unsigned int count = eb->buffer_count;
1623 if (unlikely(i915_modparams.prefault_disable))
1626 for (i = 0; i < count; i++) {
1629 err = check_relocations(&eb->exec[i]);
1637 static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
1639 struct drm_device *dev = &eb->i915->drm;
1640 bool have_copy = false;
1641 struct i915_vma *vma;
1645 if (signal_pending(current)) {
1650 /* We may process another execbuffer during the unlock... */
1652 mutex_unlock(&dev->struct_mutex);
1655 * We take 3 passes through the slowpatch.
1657 * 1 - we try to just prefault all the user relocation entries and
1658 * then attempt to reuse the atomic pagefault disabled fast path again.
1660 * 2 - we copy the user entries to a local buffer here outside of the
1661 * local and allow ourselves to wait upon any rendering before
1664 * 3 - we already have a local copy of the relocation entries, but
1665 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1668 err = eb_prefault_relocations(eb);
1669 } else if (!have_copy) {
1670 err = eb_copy_relocations(eb);
1671 have_copy = err == 0;
1677 mutex_lock(&dev->struct_mutex);
1681 /* A frequent cause for EAGAIN are currently unavailable client pages */
1682 flush_workqueue(eb->i915->mm.userptr_wq);
1684 err = i915_mutex_lock_interruptible(dev);
1686 mutex_lock(&dev->struct_mutex);
1690 /* reacquire the objects */
1691 err = eb_lookup_vmas(eb);
1695 GEM_BUG_ON(!eb->batch);
1697 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1699 pagefault_disable();
1700 err = eb_relocate_vma(eb, vma);
1705 err = eb_relocate_vma_slow(eb, vma);
1712 * Leave the user relocations as are, this is the painfully slow path,
1713 * and we want to avoid the complication of dropping the lock whilst
1714 * having buffers reserved in the aperture and so causing spurious
1715 * ENOSPC for random operations.
1724 const unsigned int count = eb->buffer_count;
1727 for (i = 0; i < count; i++) {
1728 const struct drm_i915_gem_exec_object2 *entry =
1730 struct drm_i915_gem_relocation_entry *relocs;
1732 if (!entry->relocation_count)
1735 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1743 static int eb_relocate(struct i915_execbuffer *eb)
1745 if (eb_lookup_vmas(eb))
1748 /* The objects are in their final locations, apply the relocations. */
1749 if (eb->args->flags & __EXEC_HAS_RELOC) {
1750 struct i915_vma *vma;
1752 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1753 if (eb_relocate_vma(eb, vma))
1761 return eb_relocate_slow(eb);
1764 static void eb_export_fence(struct i915_vma *vma,
1765 struct i915_request *rq,
1768 struct reservation_object *resv = vma->resv;
1771 * Ignore errors from failing to allocate the new fence, we can't
1772 * handle an error right now. Worst case should be missed
1773 * synchronisation leading to rendering corruption.
1775 reservation_object_lock(resv, NULL);
1776 if (flags & EXEC_OBJECT_WRITE)
1777 reservation_object_add_excl_fence(resv, &rq->fence);
1778 else if (reservation_object_reserve_shared(resv) == 0)
1779 reservation_object_add_shared_fence(resv, &rq->fence);
1780 reservation_object_unlock(resv);
1783 static int eb_move_to_gpu(struct i915_execbuffer *eb)
1785 const unsigned int count = eb->buffer_count;
1789 for (i = 0; i < count; i++) {
1790 unsigned int flags = eb->flags[i];
1791 struct i915_vma *vma = eb->vma[i];
1792 struct drm_i915_gem_object *obj = vma->obj;
1794 if (flags & EXEC_OBJECT_CAPTURE) {
1795 struct i915_capture_list *capture;
1797 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1798 if (unlikely(!capture))
1801 capture->next = eb->request->capture_list;
1802 capture->vma = eb->vma[i];
1803 eb->request->capture_list = capture;
1807 * If the GPU is not _reading_ through the CPU cache, we need
1808 * to make sure that any writes (both previous GPU writes from
1809 * before a change in snooping levels and normal CPU writes)
1810 * caught in that cache are flushed to main memory.
1813 * obj->cache_dirty &&
1814 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
1815 * but gcc's optimiser doesn't handle that as well and emits
1816 * two jumps instead of one. Maybe one day...
1818 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
1819 if (i915_gem_clflush_object(obj, 0))
1820 flags &= ~EXEC_OBJECT_ASYNC;
1823 if (flags & EXEC_OBJECT_ASYNC)
1826 err = i915_request_await_object
1827 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
1832 for (i = 0; i < count; i++) {
1833 unsigned int flags = eb->flags[i];
1834 struct i915_vma *vma = eb->vma[i];
1836 i915_vma_move_to_active(vma, eb->request, flags);
1837 eb_export_fence(vma, eb->request, flags);
1839 __eb_unreserve_vma(vma, flags);
1840 vma->exec_flags = NULL;
1842 if (unlikely(flags & __EXEC_OBJECT_HAS_REF))
1847 /* Unconditionally flush any chipset caches (for streaming writes). */
1848 i915_gem_chipset_flush(eb->i915);
1853 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1855 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1858 /* Kernel clipping was a DRI1 misfeature */
1859 if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
1860 if (exec->num_cliprects || exec->cliprects_ptr)
1864 if (exec->DR4 == 0xffffffff) {
1865 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1868 if (exec->DR1 || exec->DR4)
1871 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1877 void i915_vma_move_to_active(struct i915_vma *vma,
1878 struct i915_request *rq,
1881 struct drm_i915_gem_object *obj = vma->obj;
1882 const unsigned int idx = rq->engine->id;
1884 lockdep_assert_held(&rq->i915->drm.struct_mutex);
1885 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1888 * Add a reference if we're newly entering the active list.
1889 * The order in which we add operations to the retirement queue is
1890 * vital here: mark_active adds to the start of the callback list,
1891 * such that subsequent callbacks are called first. Therefore we
1892 * add the active reference first and queue for it to be dropped
1895 if (!i915_vma_is_active(vma))
1896 obj->active_count++;
1897 i915_vma_set_active(vma, idx);
1898 i915_gem_active_set(&vma->last_read[idx], rq);
1899 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1901 obj->write_domain = 0;
1902 if (flags & EXEC_OBJECT_WRITE) {
1903 obj->write_domain = I915_GEM_DOMAIN_RENDER;
1905 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1906 i915_gem_active_set(&obj->frontbuffer_write, rq);
1908 obj->read_domains = 0;
1910 obj->read_domains |= I915_GEM_GPU_DOMAINS;
1912 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1913 i915_gem_active_set(&vma->last_fence, rq);
1916 static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
1921 if (!IS_GEN7(rq->i915) || rq->engine->id != RCS) {
1922 DRM_DEBUG("sol reset is gen7/rcs only\n");
1926 cs = intel_ring_begin(rq, 4 * 2 + 2);
1930 *cs++ = MI_LOAD_REGISTER_IMM(4);
1931 for (i = 0; i < 4; i++) {
1932 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
1936 intel_ring_advance(rq, cs);
1941 static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master)
1943 struct drm_i915_gem_object *shadow_batch_obj;
1944 struct i915_vma *vma;
1947 shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool,
1948 PAGE_ALIGN(eb->batch_len));
1949 if (IS_ERR(shadow_batch_obj))
1950 return ERR_CAST(shadow_batch_obj);
1952 err = intel_engine_cmd_parser(eb->engine,
1955 eb->batch_start_offset,
1959 if (err == -EACCES) /* unhandled chained batch */
1966 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1970 eb->vma[eb->buffer_count] = i915_vma_get(vma);
1971 eb->flags[eb->buffer_count] =
1972 __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF;
1973 vma->exec_flags = &eb->flags[eb->buffer_count];
1977 i915_gem_object_unpin_pages(shadow_batch_obj);
1982 add_to_client(struct i915_request *rq, struct drm_file *file)
1984 rq->file_priv = file->driver_priv;
1985 list_add_tail(&rq->client_link, &rq->file_priv->mm.request_list);
1988 static int eb_submit(struct i915_execbuffer *eb)
1992 err = eb_move_to_gpu(eb);
1996 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
1997 err = i915_reset_gen7_sol_offsets(eb->request);
2002 err = eb->engine->emit_bb_start(eb->request,
2003 eb->batch->node.start +
2004 eb->batch_start_offset,
2014 * Find one BSD ring to dispatch the corresponding BSD command.
2015 * The engine index is returned.
2018 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2019 struct drm_file *file)
2021 struct drm_i915_file_private *file_priv = file->driver_priv;
2023 /* Check whether the file_priv has already selected one ring. */
2024 if ((int)file_priv->bsd_engine < 0)
2025 file_priv->bsd_engine = atomic_fetch_xor(1,
2026 &dev_priv->mm.bsd_engine_dispatch_index);
2028 return file_priv->bsd_engine;
2031 #define I915_USER_RINGS (4)
2033 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
2034 [I915_EXEC_DEFAULT] = RCS,
2035 [I915_EXEC_RENDER] = RCS,
2036 [I915_EXEC_BLT] = BCS,
2037 [I915_EXEC_BSD] = VCS,
2038 [I915_EXEC_VEBOX] = VECS
2041 static struct intel_engine_cs *
2042 eb_select_engine(struct drm_i915_private *dev_priv,
2043 struct drm_file *file,
2044 struct drm_i915_gem_execbuffer2 *args)
2046 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2047 struct intel_engine_cs *engine;
2049 if (user_ring_id > I915_USER_RINGS) {
2050 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
2054 if ((user_ring_id != I915_EXEC_BSD) &&
2055 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
2056 DRM_DEBUG("execbuf with non bsd ring but with invalid "
2057 "bsd dispatch flags: %d\n", (int)(args->flags));
2061 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
2062 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2064 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2065 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
2066 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2067 bsd_idx <= I915_EXEC_BSD_RING2) {
2068 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2071 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
2076 engine = dev_priv->engine[_VCS(bsd_idx)];
2078 engine = dev_priv->engine[user_ring_map[user_ring_id]];
2082 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
2090 __free_fence_array(struct drm_syncobj **fences, unsigned int n)
2093 drm_syncobj_put(ptr_mask_bits(fences[n], 2));
2097 static struct drm_syncobj **
2098 get_fence_array(struct drm_i915_gem_execbuffer2 *args,
2099 struct drm_file *file)
2101 const unsigned long nfences = args->num_cliprects;
2102 struct drm_i915_gem_exec_fence __user *user;
2103 struct drm_syncobj **fences;
2107 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2110 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2111 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2112 if (nfences > min_t(unsigned long,
2113 ULONG_MAX / sizeof(*user),
2114 SIZE_MAX / sizeof(*fences)))
2115 return ERR_PTR(-EINVAL);
2117 user = u64_to_user_ptr(args->cliprects_ptr);
2118 if (!access_ok(VERIFY_READ, user, nfences * sizeof(*user)))
2119 return ERR_PTR(-EFAULT);
2121 fences = kvmalloc_array(nfences, sizeof(*fences),
2122 __GFP_NOWARN | GFP_KERNEL);
2124 return ERR_PTR(-ENOMEM);
2126 for (n = 0; n < nfences; n++) {
2127 struct drm_i915_gem_exec_fence fence;
2128 struct drm_syncobj *syncobj;
2130 if (__copy_from_user(&fence, user++, sizeof(fence))) {
2135 if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
2140 syncobj = drm_syncobj_find(file, fence.handle);
2142 DRM_DEBUG("Invalid syncobj handle provided\n");
2147 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2148 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2150 fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
2156 __free_fence_array(fences, n);
2157 return ERR_PTR(err);
2161 put_fence_array(struct drm_i915_gem_execbuffer2 *args,
2162 struct drm_syncobj **fences)
2165 __free_fence_array(fences, args->num_cliprects);
2169 await_fence_array(struct i915_execbuffer *eb,
2170 struct drm_syncobj **fences)
2172 const unsigned int nfences = eb->args->num_cliprects;
2176 for (n = 0; n < nfences; n++) {
2177 struct drm_syncobj *syncobj;
2178 struct dma_fence *fence;
2181 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2182 if (!(flags & I915_EXEC_FENCE_WAIT))
2185 fence = drm_syncobj_fence_get(syncobj);
2189 err = i915_request_await_dma_fence(eb->request, fence);
2190 dma_fence_put(fence);
2199 signal_fence_array(struct i915_execbuffer *eb,
2200 struct drm_syncobj **fences)
2202 const unsigned int nfences = eb->args->num_cliprects;
2203 struct dma_fence * const fence = &eb->request->fence;
2206 for (n = 0; n < nfences; n++) {
2207 struct drm_syncobj *syncobj;
2210 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2211 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2214 drm_syncobj_replace_fence(syncobj, fence);
2219 i915_gem_do_execbuffer(struct drm_device *dev,
2220 struct drm_file *file,
2221 struct drm_i915_gem_execbuffer2 *args,
2222 struct drm_i915_gem_exec_object2 *exec,
2223 struct drm_syncobj **fences)
2225 struct i915_execbuffer eb;
2226 struct dma_fence *in_fence = NULL;
2227 struct sync_file *out_fence = NULL;
2228 int out_fence_fd = -1;
2231 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
2232 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
2233 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
2235 eb.i915 = to_i915(dev);
2238 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
2239 args->flags |= __EXEC_HAS_RELOC;
2242 eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1);
2244 eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
2246 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2247 if (USES_FULL_PPGTT(eb.i915))
2248 eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
2249 reloc_cache_init(&eb.reloc_cache, eb.i915);
2251 eb.buffer_count = args->buffer_count;
2252 eb.batch_start_offset = args->batch_start_offset;
2253 eb.batch_len = args->batch_len;
2256 if (args->flags & I915_EXEC_SECURE) {
2257 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
2260 eb.batch_flags |= I915_DISPATCH_SECURE;
2262 if (args->flags & I915_EXEC_IS_PINNED)
2263 eb.batch_flags |= I915_DISPATCH_PINNED;
2265 eb.engine = eb_select_engine(eb.i915, file, args);
2269 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
2270 if (!HAS_RESOURCE_STREAMER(eb.i915)) {
2271 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
2274 if (eb.engine->id != RCS) {
2275 DRM_DEBUG("RS is not available on %s\n",
2280 eb.batch_flags |= I915_DISPATCH_RS;
2283 if (args->flags & I915_EXEC_FENCE_IN) {
2284 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2289 if (args->flags & I915_EXEC_FENCE_OUT) {
2290 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
2291 if (out_fence_fd < 0) {
2297 err = eb_create(&eb);
2301 GEM_BUG_ON(!eb.lut_size);
2303 err = eb_select_context(&eb);
2308 * Take a local wakeref for preparing to dispatch the execbuf as
2309 * we expect to access the hardware fairly frequently in the
2310 * process. Upon first dispatch, we acquire another prolonged
2311 * wakeref that we hold until the GPU has been idle for at least
2314 intel_runtime_pm_get(eb.i915);
2316 err = i915_mutex_lock_interruptible(dev);
2320 err = eb_relocate(&eb);
2323 * If the user expects the execobject.offset and
2324 * reloc.presumed_offset to be an exact match,
2325 * as for using NO_RELOC, then we cannot update
2326 * the execobject.offset until we have completed
2329 args->flags &= ~__EXEC_HAS_RELOC;
2333 if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) {
2334 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
2338 if (eb.batch_start_offset > eb.batch->size ||
2339 eb.batch_len > eb.batch->size - eb.batch_start_offset) {
2340 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
2345 if (eb_use_cmdparser(&eb)) {
2346 struct i915_vma *vma;
2348 vma = eb_parse(&eb, drm_is_current_master(file));
2356 * Batch parsed and accepted:
2358 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
2359 * bit from MI_BATCH_BUFFER_START commands issued in
2360 * the dispatch_execbuffer implementations. We
2361 * specifically don't want that set on batches the
2362 * command parser has accepted.
2364 eb.batch_flags |= I915_DISPATCH_SECURE;
2365 eb.batch_start_offset = 0;
2370 if (eb.batch_len == 0)
2371 eb.batch_len = eb.batch->size - eb.batch_start_offset;
2374 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2375 * batch" bit. Hence we need to pin secure batches into the global gtt.
2376 * hsw should have this fixed, but bdw mucks it up again. */
2377 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2378 struct i915_vma *vma;
2381 * So on first glance it looks freaky that we pin the batch here
2382 * outside of the reservation loop. But:
2383 * - The batch is already pinned into the relevant ppgtt, so we
2384 * already have the backing storage fully allocated.
2385 * - No other BO uses the global gtt (well contexts, but meh),
2386 * so we don't really have issues with multiple objects not
2387 * fitting due to fragmentation.
2388 * So this is actually safe.
2390 vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0);
2399 /* All GPU relocation batches must be submitted prior to the user rq */
2400 GEM_BUG_ON(eb.reloc_cache.rq);
2402 /* Allocate a request for this batch buffer nice and early. */
2403 eb.request = i915_request_alloc(eb.engine, eb.ctx);
2404 if (IS_ERR(eb.request)) {
2405 err = PTR_ERR(eb.request);
2406 goto err_batch_unpin;
2410 err = i915_request_await_dma_fence(eb.request, in_fence);
2416 err = await_fence_array(&eb, fences);
2421 if (out_fence_fd != -1) {
2422 out_fence = sync_file_create(&eb.request->fence);
2430 * Whilst this request exists, batch_obj will be on the
2431 * active_list, and so will hold the active reference. Only when this
2432 * request is retired will the the batch_obj be moved onto the
2433 * inactive_list and lose its active reference. Hence we do not need
2434 * to explicitly hold another reference here.
2436 eb.request->batch = eb.batch;
2438 trace_i915_request_queue(eb.request, eb.batch_flags);
2439 err = eb_submit(&eb);
2441 __i915_request_add(eb.request, err == 0);
2442 add_to_client(eb.request, file);
2445 signal_fence_array(&eb, fences);
2449 fd_install(out_fence_fd, out_fence->file);
2450 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
2451 args->rsvd2 |= (u64)out_fence_fd << 32;
2454 fput(out_fence->file);
2459 if (eb.batch_flags & I915_DISPATCH_SECURE)
2460 i915_vma_unpin(eb.batch);
2463 eb_release_vmas(&eb);
2464 mutex_unlock(&dev->struct_mutex);
2466 intel_runtime_pm_put(eb.i915);
2467 i915_gem_context_put(eb.ctx);
2471 if (out_fence_fd != -1)
2472 put_unused_fd(out_fence_fd);
2474 dma_fence_put(in_fence);
2478 static size_t eb_element_size(void)
2480 return (sizeof(struct drm_i915_gem_exec_object2) +
2481 sizeof(struct i915_vma *) +
2482 sizeof(unsigned int));
2485 static bool check_buffer_count(size_t count)
2487 const size_t sz = eb_element_size();
2490 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
2491 * array size (see eb_create()). Otherwise, we can accept an array as
2492 * large as can be addressed (though use large arrays at your peril)!
2495 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
2499 * Legacy execbuffer just creates an exec2 list from the original exec object
2500 * list array and passes it to the real function.
2503 i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2504 struct drm_file *file)
2506 struct drm_i915_gem_execbuffer *args = data;
2507 struct drm_i915_gem_execbuffer2 exec2;
2508 struct drm_i915_gem_exec_object *exec_list = NULL;
2509 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2510 const size_t count = args->buffer_count;
2514 if (!check_buffer_count(count)) {
2515 DRM_DEBUG("execbuf2 with %zd buffers\n", count);
2519 exec2.buffers_ptr = args->buffers_ptr;
2520 exec2.buffer_count = args->buffer_count;
2521 exec2.batch_start_offset = args->batch_start_offset;
2522 exec2.batch_len = args->batch_len;
2523 exec2.DR1 = args->DR1;
2524 exec2.DR4 = args->DR4;
2525 exec2.num_cliprects = args->num_cliprects;
2526 exec2.cliprects_ptr = args->cliprects_ptr;
2527 exec2.flags = I915_EXEC_RENDER;
2528 i915_execbuffer2_set_context_id(exec2, 0);
2530 if (!i915_gem_check_execbuffer(&exec2))
2533 /* Copy in the exec list from userland */
2534 exec_list = kvmalloc_array(count, sizeof(*exec_list),
2535 __GFP_NOWARN | GFP_KERNEL);
2536 exec2_list = kvmalloc_array(count + 1, eb_element_size(),
2537 __GFP_NOWARN | GFP_KERNEL);
2538 if (exec_list == NULL || exec2_list == NULL) {
2539 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2540 args->buffer_count);
2545 err = copy_from_user(exec_list,
2546 u64_to_user_ptr(args->buffers_ptr),
2547 sizeof(*exec_list) * count);
2549 DRM_DEBUG("copy %d exec entries failed %d\n",
2550 args->buffer_count, err);
2556 for (i = 0; i < args->buffer_count; i++) {
2557 exec2_list[i].handle = exec_list[i].handle;
2558 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2559 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2560 exec2_list[i].alignment = exec_list[i].alignment;
2561 exec2_list[i].offset = exec_list[i].offset;
2562 if (INTEL_GEN(to_i915(dev)) < 4)
2563 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2565 exec2_list[i].flags = 0;
2568 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
2569 if (exec2.flags & __EXEC_HAS_RELOC) {
2570 struct drm_i915_gem_exec_object __user *user_exec_list =
2571 u64_to_user_ptr(args->buffers_ptr);
2573 /* Copy the new buffer offsets back to the user's exec list. */
2574 for (i = 0; i < args->buffer_count; i++) {
2575 if (!(exec2_list[i].offset & UPDATE))
2578 exec2_list[i].offset =
2579 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2580 exec2_list[i].offset &= PIN_OFFSET_MASK;
2581 if (__copy_to_user(&user_exec_list[i].offset,
2582 &exec2_list[i].offset,
2583 sizeof(user_exec_list[i].offset)))
2594 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2595 struct drm_file *file)
2597 struct drm_i915_gem_execbuffer2 *args = data;
2598 struct drm_i915_gem_exec_object2 *exec2_list;
2599 struct drm_syncobj **fences = NULL;
2600 const size_t count = args->buffer_count;
2603 if (!check_buffer_count(count)) {
2604 DRM_DEBUG("execbuf2 with %zd buffers\n", count);
2608 if (!i915_gem_check_execbuffer(args))
2611 /* Allocate an extra slot for use by the command parser */
2612 exec2_list = kvmalloc_array(count + 1, eb_element_size(),
2613 __GFP_NOWARN | GFP_KERNEL);
2614 if (exec2_list == NULL) {
2615 DRM_DEBUG("Failed to allocate exec list for %zd buffers\n",
2619 if (copy_from_user(exec2_list,
2620 u64_to_user_ptr(args->buffers_ptr),
2621 sizeof(*exec2_list) * count)) {
2622 DRM_DEBUG("copy %zd exec entries failed\n", count);
2627 if (args->flags & I915_EXEC_FENCE_ARRAY) {
2628 fences = get_fence_array(args, file);
2629 if (IS_ERR(fences)) {
2631 return PTR_ERR(fences);
2635 err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
2638 * Now that we have begun execution of the batchbuffer, we ignore
2639 * any new error after this point. Also given that we have already
2640 * updated the associated relocations, we try to write out the current
2641 * object locations irrespective of any error.
2643 if (args->flags & __EXEC_HAS_RELOC) {
2644 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2645 u64_to_user_ptr(args->buffers_ptr);
2648 /* Copy the new buffer offsets back to the user's exec list. */
2649 user_access_begin();
2650 for (i = 0; i < args->buffer_count; i++) {
2651 if (!(exec2_list[i].offset & UPDATE))
2654 exec2_list[i].offset =
2655 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2656 unsafe_put_user(exec2_list[i].offset,
2657 &user_exec_list[i].offset,
2664 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
2665 put_fence_array(args, fences);