2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include "intel_workarounds.h"
39 #include "i915_gemfs.h"
40 #include <linux/dma-fence-array.h>
41 #include <linux/kthread.h>
42 #include <linux/reservation.h>
43 #include <linux/shmem_fs.h>
44 #include <linux/slab.h>
45 #include <linux/stop_machine.h>
46 #include <linux/swap.h>
47 #include <linux/pci.h>
48 #include <linux/dma-buf.h>
50 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
52 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
57 if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
60 return obj->pin_global; /* currently in use by HW, keep flushed */
64 insert_mappable_node(struct i915_ggtt *ggtt,
65 struct drm_mm_node *node, u32 size)
67 memset(node, 0, sizeof(*node));
68 return drm_mm_insert_node_in_range(&ggtt->vm.mm, node,
69 size, 0, I915_COLOR_UNEVICTABLE,
70 0, ggtt->mappable_end,
75 remove_mappable_node(struct drm_mm_node *node)
77 drm_mm_remove_node(node);
80 /* some bookkeeping */
81 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
84 spin_lock(&dev_priv->mm.object_stat_lock);
85 dev_priv->mm.object_count++;
86 dev_priv->mm.object_memory += size;
87 spin_unlock(&dev_priv->mm.object_stat_lock);
90 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
93 spin_lock(&dev_priv->mm.object_stat_lock);
94 dev_priv->mm.object_count--;
95 dev_priv->mm.object_memory -= size;
96 spin_unlock(&dev_priv->mm.object_stat_lock);
100 i915_gem_wait_for_error(struct i915_gpu_error *error)
107 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
108 * userspace. If it takes that long something really bad is going on and
109 * we should simply try to bail out and fail as gracefully as possible.
111 ret = wait_event_interruptible_timeout(error->reset_queue,
112 !i915_reset_backoff(error),
115 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
117 } else if (ret < 0) {
124 int i915_mutex_lock_interruptible(struct drm_device *dev)
126 struct drm_i915_private *dev_priv = to_i915(dev);
129 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
133 ret = mutex_lock_interruptible(&dev->struct_mutex);
140 static u32 __i915_gem_park(struct drm_i915_private *i915)
144 lockdep_assert_held(&i915->drm.struct_mutex);
145 GEM_BUG_ON(i915->gt.active_requests);
146 GEM_BUG_ON(!list_empty(&i915->gt.active_rings));
149 return I915_EPOCH_INVALID;
151 GEM_BUG_ON(i915->gt.epoch == I915_EPOCH_INVALID);
154 * Be paranoid and flush a concurrent interrupt to make sure
155 * we don't reactivate any irq tasklets after parking.
157 * FIXME: Note that even though we have waited for execlists to be idle,
158 * there may still be an in-flight interrupt even though the CSB
159 * is now empty. synchronize_irq() makes sure that a residual interrupt
160 * is completed before we continue, but it doesn't prevent the HW from
161 * raising a spurious interrupt later. To complete the shield we should
162 * coordinate disabling the CS irq with flushing the interrupts.
164 synchronize_irq(i915->drm.irq);
166 intel_engines_park(i915);
167 i915_timelines_park(i915);
169 i915_pmu_gt_parked(i915);
170 i915_vma_parked(i915);
172 i915->gt.awake = false;
174 if (INTEL_GEN(i915) >= 6)
177 intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
179 intel_runtime_pm_put(i915);
181 return i915->gt.epoch;
184 void i915_gem_park(struct drm_i915_private *i915)
188 lockdep_assert_held(&i915->drm.struct_mutex);
189 GEM_BUG_ON(i915->gt.active_requests);
194 /* Defer the actual call to __i915_gem_park() to prevent ping-pongs */
195 mod_delayed_work(i915->wq, &i915->gt.idle_work, msecs_to_jiffies(100));
198 void i915_gem_unpark(struct drm_i915_private *i915)
202 lockdep_assert_held(&i915->drm.struct_mutex);
203 GEM_BUG_ON(!i915->gt.active_requests);
208 intel_runtime_pm_get_noresume(i915);
211 * It seems that the DMC likes to transition between the DC states a lot
212 * when there are no connected displays (no active power domains) during
213 * command submission.
215 * This activity has negative impact on the performance of the chip with
216 * huge latencies observed in the interrupt handler and elsewhere.
218 * Work around it by grabbing a GT IRQ power domain whilst there is any
219 * GT activity, preventing any DC state transitions.
221 intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
223 i915->gt.awake = true;
224 if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
227 intel_enable_gt_powersave(i915);
228 i915_update_gfx_val(i915);
229 if (INTEL_GEN(i915) >= 6)
231 i915_pmu_gt_unparked(i915);
233 intel_engines_unpark(i915);
235 i915_queue_hangcheck(i915);
237 queue_delayed_work(i915->wq,
238 &i915->gt.retire_work,
239 round_jiffies_up_relative(HZ));
243 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
246 struct drm_i915_private *dev_priv = to_i915(dev);
247 struct i915_ggtt *ggtt = &dev_priv->ggtt;
248 struct drm_i915_gem_get_aperture *args = data;
249 struct i915_vma *vma;
252 pinned = ggtt->vm.reserved;
253 mutex_lock(&dev->struct_mutex);
254 list_for_each_entry(vma, &ggtt->vm.active_list, vm_link)
255 if (i915_vma_is_pinned(vma))
256 pinned += vma->node.size;
257 list_for_each_entry(vma, &ggtt->vm.inactive_list, vm_link)
258 if (i915_vma_is_pinned(vma))
259 pinned += vma->node.size;
260 mutex_unlock(&dev->struct_mutex);
262 args->aper_size = ggtt->vm.total;
263 args->aper_available_size = args->aper_size - pinned;
268 static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
270 struct address_space *mapping = obj->base.filp->f_mapping;
271 drm_dma_handle_t *phys;
273 struct scatterlist *sg;
278 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
281 /* Always aligning to the object size, allows a single allocation
282 * to handle all possible callers, and given typical object sizes,
283 * the alignment of the buddy allocation will naturally match.
285 phys = drm_pci_alloc(obj->base.dev,
286 roundup_pow_of_two(obj->base.size),
287 roundup_pow_of_two(obj->base.size));
292 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
296 page = shmem_read_mapping_page(mapping, i);
302 src = kmap_atomic(page);
303 memcpy(vaddr, src, PAGE_SIZE);
304 drm_clflush_virt_range(vaddr, PAGE_SIZE);
311 i915_gem_chipset_flush(to_i915(obj->base.dev));
313 st = kmalloc(sizeof(*st), GFP_KERNEL);
319 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
327 sg->length = obj->base.size;
329 sg_dma_address(sg) = phys->busaddr;
330 sg_dma_len(sg) = obj->base.size;
332 obj->phys_handle = phys;
334 __i915_gem_object_set_pages(obj, st, sg->length);
339 drm_pci_free(obj->base.dev, phys);
344 static void __start_cpu_write(struct drm_i915_gem_object *obj)
346 obj->read_domains = I915_GEM_DOMAIN_CPU;
347 obj->write_domain = I915_GEM_DOMAIN_CPU;
348 if (cpu_write_needs_clflush(obj))
349 obj->cache_dirty = true;
353 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
354 struct sg_table *pages,
357 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
359 if (obj->mm.madv == I915_MADV_DONTNEED)
360 obj->mm.dirty = false;
363 (obj->read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
364 !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
365 drm_clflush_sg(pages);
367 __start_cpu_write(obj);
371 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
372 struct sg_table *pages)
374 __i915_gem_object_release_shmem(obj, pages, false);
377 struct address_space *mapping = obj->base.filp->f_mapping;
378 char *vaddr = obj->phys_handle->vaddr;
381 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
385 page = shmem_read_mapping_page(mapping, i);
389 dst = kmap_atomic(page);
390 drm_clflush_virt_range(vaddr, PAGE_SIZE);
391 memcpy(dst, vaddr, PAGE_SIZE);
394 set_page_dirty(page);
395 if (obj->mm.madv == I915_MADV_WILLNEED)
396 mark_page_accessed(page);
400 obj->mm.dirty = false;
403 sg_free_table(pages);
406 drm_pci_free(obj->base.dev, obj->phys_handle);
410 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
412 i915_gem_object_unpin_pages(obj);
415 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
416 .get_pages = i915_gem_object_get_pages_phys,
417 .put_pages = i915_gem_object_put_pages_phys,
418 .release = i915_gem_object_release_phys,
421 static const struct drm_i915_gem_object_ops i915_gem_object_ops;
423 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
425 struct i915_vma *vma;
426 LIST_HEAD(still_in_list);
429 lockdep_assert_held(&obj->base.dev->struct_mutex);
431 /* Closed vma are removed from the obj->vma_list - but they may
432 * still have an active binding on the object. To remove those we
433 * must wait for all rendering to complete to the object (as unbinding
434 * must anyway), and retire the requests.
436 ret = i915_gem_object_set_to_cpu_domain(obj, false);
440 while ((vma = list_first_entry_or_null(&obj->vma_list,
443 list_move_tail(&vma->obj_link, &still_in_list);
444 ret = i915_vma_unbind(vma);
448 list_splice(&still_in_list, &obj->vma_list);
454 i915_gem_object_wait_fence(struct dma_fence *fence,
457 struct intel_rps_client *rps_client)
459 struct i915_request *rq;
461 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
463 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
466 if (!dma_fence_is_i915(fence))
467 return dma_fence_wait_timeout(fence,
468 flags & I915_WAIT_INTERRUPTIBLE,
471 rq = to_request(fence);
472 if (i915_request_completed(rq))
476 * This client is about to stall waiting for the GPU. In many cases
477 * this is undesirable and limits the throughput of the system, as
478 * many clients cannot continue processing user input/output whilst
479 * blocked. RPS autotuning may take tens of milliseconds to respond
480 * to the GPU load and thus incurs additional latency for the client.
481 * We can circumvent that by promoting the GPU frequency to maximum
482 * before we wait. This makes the GPU throttle up much more quickly
483 * (good for benchmarks and user experience, e.g. window animations),
484 * but at a cost of spending more power processing the workload
485 * (bad for battery). Not all clients even want their results
486 * immediately and for them we should just let the GPU select its own
487 * frequency to maximise efficiency. To prevent a single client from
488 * forcing the clocks too high for the whole system, we only allow
489 * each client to waitboost once in a busy period.
491 if (rps_client && !i915_request_started(rq)) {
492 if (INTEL_GEN(rq->i915) >= 6)
493 gen6_rps_boost(rq, rps_client);
496 timeout = i915_request_wait(rq, flags, timeout);
499 if (flags & I915_WAIT_LOCKED && i915_request_completed(rq))
500 i915_request_retire_upto(rq);
506 i915_gem_object_wait_reservation(struct reservation_object *resv,
509 struct intel_rps_client *rps_client)
511 unsigned int seq = __read_seqcount_begin(&resv->seq);
512 struct dma_fence *excl;
513 bool prune_fences = false;
515 if (flags & I915_WAIT_ALL) {
516 struct dma_fence **shared;
517 unsigned int count, i;
520 ret = reservation_object_get_fences_rcu(resv,
521 &excl, &count, &shared);
525 for (i = 0; i < count; i++) {
526 timeout = i915_gem_object_wait_fence(shared[i],
532 dma_fence_put(shared[i]);
535 for (; i < count; i++)
536 dma_fence_put(shared[i]);
540 * If both shared fences and an exclusive fence exist,
541 * then by construction the shared fences must be later
542 * than the exclusive fence. If we successfully wait for
543 * all the shared fences, we know that the exclusive fence
544 * must all be signaled. If all the shared fences are
545 * signaled, we can prune the array and recover the
546 * floating references on the fences/requests.
548 prune_fences = count && timeout >= 0;
550 excl = reservation_object_get_excl_rcu(resv);
553 if (excl && timeout >= 0)
554 timeout = i915_gem_object_wait_fence(excl, flags, timeout,
560 * Opportunistically prune the fences iff we know they have *all* been
561 * signaled and that the reservation object has not been changed (i.e.
562 * no new fences have been added).
564 if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
565 if (reservation_object_trylock(resv)) {
566 if (!__read_seqcount_retry(&resv->seq, seq))
567 reservation_object_add_excl_fence(resv, NULL);
568 reservation_object_unlock(resv);
575 static void __fence_set_priority(struct dma_fence *fence,
576 const struct i915_sched_attr *attr)
578 struct i915_request *rq;
579 struct intel_engine_cs *engine;
581 if (dma_fence_is_signaled(fence) || !dma_fence_is_i915(fence))
584 rq = to_request(fence);
588 rcu_read_lock(); /* RCU serialisation for set-wedged protection */
589 if (engine->schedule)
590 engine->schedule(rq, attr);
592 local_bh_enable(); /* kick the tasklets if queues were reprioritised */
595 static void fence_set_priority(struct dma_fence *fence,
596 const struct i915_sched_attr *attr)
598 /* Recurse once into a fence-array */
599 if (dma_fence_is_array(fence)) {
600 struct dma_fence_array *array = to_dma_fence_array(fence);
603 for (i = 0; i < array->num_fences; i++)
604 __fence_set_priority(array->fences[i], attr);
606 __fence_set_priority(fence, attr);
611 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
613 const struct i915_sched_attr *attr)
615 struct dma_fence *excl;
617 if (flags & I915_WAIT_ALL) {
618 struct dma_fence **shared;
619 unsigned int count, i;
622 ret = reservation_object_get_fences_rcu(obj->resv,
623 &excl, &count, &shared);
627 for (i = 0; i < count; i++) {
628 fence_set_priority(shared[i], attr);
629 dma_fence_put(shared[i]);
634 excl = reservation_object_get_excl_rcu(obj->resv);
638 fence_set_priority(excl, attr);
645 * Waits for rendering to the object to be completed
646 * @obj: i915 gem object
647 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
648 * @timeout: how long to wait
649 * @rps_client: client (user process) to charge for any waitboosting
652 i915_gem_object_wait(struct drm_i915_gem_object *obj,
655 struct intel_rps_client *rps_client)
658 #if IS_ENABLED(CONFIG_LOCKDEP)
659 GEM_BUG_ON(debug_locks &&
660 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
661 !!(flags & I915_WAIT_LOCKED));
663 GEM_BUG_ON(timeout < 0);
665 timeout = i915_gem_object_wait_reservation(obj->resv,
668 return timeout < 0 ? timeout : 0;
671 static struct intel_rps_client *to_rps_client(struct drm_file *file)
673 struct drm_i915_file_private *fpriv = file->driver_priv;
675 return &fpriv->rps_client;
679 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
680 struct drm_i915_gem_pwrite *args,
681 struct drm_file *file)
683 void *vaddr = obj->phys_handle->vaddr + args->offset;
684 char __user *user_data = u64_to_user_ptr(args->data_ptr);
686 /* We manually control the domain here and pretend that it
687 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
689 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
690 if (copy_from_user(vaddr, user_data, args->size))
693 drm_clflush_virt_range(vaddr, args->size);
694 i915_gem_chipset_flush(to_i915(obj->base.dev));
696 intel_fb_obj_flush(obj, ORIGIN_CPU);
700 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
702 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
705 void i915_gem_object_free(struct drm_i915_gem_object *obj)
707 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
708 kmem_cache_free(dev_priv->objects, obj);
712 i915_gem_create(struct drm_file *file,
713 struct drm_i915_private *dev_priv,
717 struct drm_i915_gem_object *obj;
721 size = roundup(size, PAGE_SIZE);
725 /* Allocate the new object */
726 obj = i915_gem_object_create(dev_priv, size);
730 ret = drm_gem_handle_create(file, &obj->base, &handle);
731 /* drop reference from allocate - handle holds it now */
732 i915_gem_object_put(obj);
741 i915_gem_dumb_create(struct drm_file *file,
742 struct drm_device *dev,
743 struct drm_mode_create_dumb *args)
745 /* have to work out size/pitch and return them */
746 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
747 args->size = args->pitch * args->height;
748 return i915_gem_create(file, to_i915(dev),
749 args->size, &args->handle);
752 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
754 return !(obj->cache_level == I915_CACHE_NONE ||
755 obj->cache_level == I915_CACHE_WT);
759 * Creates a new mm object and returns a handle to it.
760 * @dev: drm device pointer
761 * @data: ioctl data blob
762 * @file: drm file pointer
765 i915_gem_create_ioctl(struct drm_device *dev, void *data,
766 struct drm_file *file)
768 struct drm_i915_private *dev_priv = to_i915(dev);
769 struct drm_i915_gem_create *args = data;
771 i915_gem_flush_free_objects(dev_priv);
773 return i915_gem_create(file, dev_priv,
774 args->size, &args->handle);
777 static inline enum fb_op_origin
778 fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)
780 return (domain == I915_GEM_DOMAIN_GTT ?
781 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
784 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
787 * No actual flushing is required for the GTT write domain for reads
788 * from the GTT domain. Writes to it "immediately" go to main memory
789 * as far as we know, so there's no chipset flush. It also doesn't
790 * land in the GPU render cache.
792 * However, we do have to enforce the order so that all writes through
793 * the GTT land before any writes to the device, such as updates to
796 * We also have to wait a bit for the writes to land from the GTT.
797 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
798 * timing. This issue has only been observed when switching quickly
799 * between GTT writes and CPU reads from inside the kernel on recent hw,
800 * and it appears to only affect discrete GTT blocks (i.e. on LLC
801 * system agents we cannot reproduce this behaviour, until Cannonlake
807 if (INTEL_INFO(dev_priv)->has_coherent_ggtt)
810 i915_gem_chipset_flush(dev_priv);
812 intel_runtime_pm_get(dev_priv);
813 spin_lock_irq(&dev_priv->uncore.lock);
815 POSTING_READ_FW(RING_HEAD(RENDER_RING_BASE));
817 spin_unlock_irq(&dev_priv->uncore.lock);
818 intel_runtime_pm_put(dev_priv);
822 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
824 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
825 struct i915_vma *vma;
827 if (!(obj->write_domain & flush_domains))
830 switch (obj->write_domain) {
831 case I915_GEM_DOMAIN_GTT:
832 i915_gem_flush_ggtt_writes(dev_priv);
834 intel_fb_obj_flush(obj,
835 fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
837 for_each_ggtt_vma(vma, obj) {
841 i915_vma_unset_ggtt_write(vma);
845 case I915_GEM_DOMAIN_WC:
849 case I915_GEM_DOMAIN_CPU:
850 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
853 case I915_GEM_DOMAIN_RENDER:
854 if (gpu_write_needs_clflush(obj))
855 obj->cache_dirty = true;
859 obj->write_domain = 0;
863 __copy_to_user_swizzled(char __user *cpu_vaddr,
864 const char *gpu_vaddr, int gpu_offset,
867 int ret, cpu_offset = 0;
870 int cacheline_end = ALIGN(gpu_offset + 1, 64);
871 int this_length = min(cacheline_end - gpu_offset, length);
872 int swizzled_gpu_offset = gpu_offset ^ 64;
874 ret = __copy_to_user(cpu_vaddr + cpu_offset,
875 gpu_vaddr + swizzled_gpu_offset,
880 cpu_offset += this_length;
881 gpu_offset += this_length;
882 length -= this_length;
889 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
890 const char __user *cpu_vaddr,
893 int ret, cpu_offset = 0;
896 int cacheline_end = ALIGN(gpu_offset + 1, 64);
897 int this_length = min(cacheline_end - gpu_offset, length);
898 int swizzled_gpu_offset = gpu_offset ^ 64;
900 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
901 cpu_vaddr + cpu_offset,
906 cpu_offset += this_length;
907 gpu_offset += this_length;
908 length -= this_length;
915 * Pins the specified object's pages and synchronizes the object with
916 * GPU accesses. Sets needs_clflush to non-zero if the caller should
917 * flush the object from the CPU cache.
919 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
920 unsigned int *needs_clflush)
924 lockdep_assert_held(&obj->base.dev->struct_mutex);
927 if (!i915_gem_object_has_struct_page(obj))
930 ret = i915_gem_object_wait(obj,
931 I915_WAIT_INTERRUPTIBLE |
933 MAX_SCHEDULE_TIMEOUT,
938 ret = i915_gem_object_pin_pages(obj);
942 if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
943 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
944 ret = i915_gem_object_set_to_cpu_domain(obj, false);
951 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
953 /* If we're not in the cpu read domain, set ourself into the gtt
954 * read domain and manually flush cachelines (if required). This
955 * optimizes for the case when the gpu will dirty the data
956 * anyway again before the next pread happens.
958 if (!obj->cache_dirty &&
959 !(obj->read_domains & I915_GEM_DOMAIN_CPU))
960 *needs_clflush = CLFLUSH_BEFORE;
963 /* return with the pages pinned */
967 i915_gem_object_unpin_pages(obj);
971 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
972 unsigned int *needs_clflush)
976 lockdep_assert_held(&obj->base.dev->struct_mutex);
979 if (!i915_gem_object_has_struct_page(obj))
982 ret = i915_gem_object_wait(obj,
983 I915_WAIT_INTERRUPTIBLE |
986 MAX_SCHEDULE_TIMEOUT,
991 ret = i915_gem_object_pin_pages(obj);
995 if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
996 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
997 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1004 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
1006 /* If we're not in the cpu write domain, set ourself into the
1007 * gtt write domain and manually flush cachelines (as required).
1008 * This optimizes for the case when the gpu will use the data
1009 * right away and we therefore have to clflush anyway.
1011 if (!obj->cache_dirty) {
1012 *needs_clflush |= CLFLUSH_AFTER;
1015 * Same trick applies to invalidate partially written
1016 * cachelines read before writing.
1018 if (!(obj->read_domains & I915_GEM_DOMAIN_CPU))
1019 *needs_clflush |= CLFLUSH_BEFORE;
1023 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1024 obj->mm.dirty = true;
1025 /* return with the pages pinned */
1029 i915_gem_object_unpin_pages(obj);
1034 shmem_clflush_swizzled_range(char *addr, unsigned long length,
1037 if (unlikely(swizzled)) {
1038 unsigned long start = (unsigned long) addr;
1039 unsigned long end = (unsigned long) addr + length;
1041 /* For swizzling simply ensure that we always flush both
1042 * channels. Lame, but simple and it works. Swizzled
1043 * pwrite/pread is far from a hotpath - current userspace
1044 * doesn't use it at all. */
1045 start = round_down(start, 128);
1046 end = round_up(end, 128);
1048 drm_clflush_virt_range((void *)start, end - start);
1050 drm_clflush_virt_range(addr, length);
1055 /* Only difference to the fast-path function is that this can handle bit17
1056 * and uses non-atomic copy and kmap functions. */
1058 shmem_pread_slow(struct page *page, int offset, int length,
1059 char __user *user_data,
1060 bool page_do_bit17_swizzling, bool needs_clflush)
1067 shmem_clflush_swizzled_range(vaddr + offset, length,
1068 page_do_bit17_swizzling);
1070 if (page_do_bit17_swizzling)
1071 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
1073 ret = __copy_to_user(user_data, vaddr + offset, length);
1076 return ret ? - EFAULT : 0;
1080 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
1081 bool page_do_bit17_swizzling, bool needs_clflush)
1086 if (!page_do_bit17_swizzling) {
1087 char *vaddr = kmap_atomic(page);
1090 drm_clflush_virt_range(vaddr + offset, length);
1091 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1092 kunmap_atomic(vaddr);
1097 return shmem_pread_slow(page, offset, length, user_data,
1098 page_do_bit17_swizzling, needs_clflush);
1102 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
1103 struct drm_i915_gem_pread *args)
1105 char __user *user_data;
1107 unsigned int obj_do_bit17_swizzling;
1108 unsigned int needs_clflush;
1109 unsigned int idx, offset;
1112 obj_do_bit17_swizzling = 0;
1113 if (i915_gem_object_needs_bit17_swizzle(obj))
1114 obj_do_bit17_swizzling = BIT(17);
1116 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
1120 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
1121 mutex_unlock(&obj->base.dev->struct_mutex);
1125 remain = args->size;
1126 user_data = u64_to_user_ptr(args->data_ptr);
1127 offset = offset_in_page(args->offset);
1128 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1129 struct page *page = i915_gem_object_get_page(obj, idx);
1133 if (offset + length > PAGE_SIZE)
1134 length = PAGE_SIZE - offset;
1136 ret = shmem_pread(page, offset, length, user_data,
1137 page_to_phys(page) & obj_do_bit17_swizzling,
1143 user_data += length;
1147 i915_gem_obj_finish_shmem_access(obj);
1152 gtt_user_read(struct io_mapping *mapping,
1153 loff_t base, int offset,
1154 char __user *user_data, int length)
1156 void __iomem *vaddr;
1157 unsigned long unwritten;
1159 /* We can use the cpu mem copy function because this is X86. */
1160 vaddr = io_mapping_map_atomic_wc(mapping, base);
1161 unwritten = __copy_to_user_inatomic(user_data,
1162 (void __force *)vaddr + offset,
1164 io_mapping_unmap_atomic(vaddr);
1166 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
1167 unwritten = copy_to_user(user_data,
1168 (void __force *)vaddr + offset,
1170 io_mapping_unmap(vaddr);
1176 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1177 const struct drm_i915_gem_pread *args)
1179 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1180 struct i915_ggtt *ggtt = &i915->ggtt;
1181 struct drm_mm_node node;
1182 struct i915_vma *vma;
1183 void __user *user_data;
1187 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1191 intel_runtime_pm_get(i915);
1192 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1197 node.start = i915_ggtt_offset(vma);
1198 node.allocated = false;
1199 ret = i915_vma_put_fence(vma);
1201 i915_vma_unpin(vma);
1206 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1209 GEM_BUG_ON(!node.allocated);
1212 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1216 mutex_unlock(&i915->drm.struct_mutex);
1218 user_data = u64_to_user_ptr(args->data_ptr);
1219 remain = args->size;
1220 offset = args->offset;
1222 while (remain > 0) {
1223 /* Operation in this page
1225 * page_base = page offset within aperture
1226 * page_offset = offset within page
1227 * page_length = bytes to copy for this page
1229 u32 page_base = node.start;
1230 unsigned page_offset = offset_in_page(offset);
1231 unsigned page_length = PAGE_SIZE - page_offset;
1232 page_length = remain < page_length ? remain : page_length;
1233 if (node.allocated) {
1235 ggtt->vm.insert_page(&ggtt->vm,
1236 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1237 node.start, I915_CACHE_NONE, 0);
1240 page_base += offset & PAGE_MASK;
1243 if (gtt_user_read(&ggtt->iomap, page_base, page_offset,
1244 user_data, page_length)) {
1249 remain -= page_length;
1250 user_data += page_length;
1251 offset += page_length;
1254 mutex_lock(&i915->drm.struct_mutex);
1256 if (node.allocated) {
1258 ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
1259 remove_mappable_node(&node);
1261 i915_vma_unpin(vma);
1264 intel_runtime_pm_put(i915);
1265 mutex_unlock(&i915->drm.struct_mutex);
1271 * Reads data from the object referenced by handle.
1272 * @dev: drm device pointer
1273 * @data: ioctl data blob
1274 * @file: drm file pointer
1276 * On error, the contents of *data are undefined.
1279 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1280 struct drm_file *file)
1282 struct drm_i915_gem_pread *args = data;
1283 struct drm_i915_gem_object *obj;
1286 if (args->size == 0)
1289 if (!access_ok(VERIFY_WRITE,
1290 u64_to_user_ptr(args->data_ptr),
1294 obj = i915_gem_object_lookup(file, args->handle);
1298 /* Bounds check source. */
1299 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1304 trace_i915_gem_object_pread(obj, args->offset, args->size);
1306 ret = i915_gem_object_wait(obj,
1307 I915_WAIT_INTERRUPTIBLE,
1308 MAX_SCHEDULE_TIMEOUT,
1309 to_rps_client(file));
1313 ret = i915_gem_object_pin_pages(obj);
1317 ret = i915_gem_shmem_pread(obj, args);
1318 if (ret == -EFAULT || ret == -ENODEV)
1319 ret = i915_gem_gtt_pread(obj, args);
1321 i915_gem_object_unpin_pages(obj);
1323 i915_gem_object_put(obj);
1327 /* This is the fast write path which cannot handle
1328 * page faults in the source data
1332 ggtt_write(struct io_mapping *mapping,
1333 loff_t base, int offset,
1334 char __user *user_data, int length)
1336 void __iomem *vaddr;
1337 unsigned long unwritten;
1339 /* We can use the cpu mem copy function because this is X86. */
1340 vaddr = io_mapping_map_atomic_wc(mapping, base);
1341 unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
1343 io_mapping_unmap_atomic(vaddr);
1345 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
1346 unwritten = copy_from_user((void __force *)vaddr + offset,
1348 io_mapping_unmap(vaddr);
1355 * This is the fast pwrite path, where we copy the data directly from the
1356 * user into the GTT, uncached.
1357 * @obj: i915 GEM object
1358 * @args: pwrite arguments structure
1361 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1362 const struct drm_i915_gem_pwrite *args)
1364 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1365 struct i915_ggtt *ggtt = &i915->ggtt;
1366 struct drm_mm_node node;
1367 struct i915_vma *vma;
1369 void __user *user_data;
1372 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1376 if (i915_gem_object_has_struct_page(obj)) {
1378 * Avoid waking the device up if we can fallback, as
1379 * waking/resuming is very slow (worst-case 10-100 ms
1380 * depending on PCI sleeps and our own resume time).
1381 * This easily dwarfs any performance advantage from
1382 * using the cache bypass of indirect GGTT access.
1384 if (!intel_runtime_pm_get_if_in_use(i915)) {
1389 /* No backing pages, no fallback, we must force GGTT access */
1390 intel_runtime_pm_get(i915);
1393 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1398 node.start = i915_ggtt_offset(vma);
1399 node.allocated = false;
1400 ret = i915_vma_put_fence(vma);
1402 i915_vma_unpin(vma);
1407 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1410 GEM_BUG_ON(!node.allocated);
1413 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1417 mutex_unlock(&i915->drm.struct_mutex);
1419 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1421 user_data = u64_to_user_ptr(args->data_ptr);
1422 offset = args->offset;
1423 remain = args->size;
1425 /* Operation in this page
1427 * page_base = page offset within aperture
1428 * page_offset = offset within page
1429 * page_length = bytes to copy for this page
1431 u32 page_base = node.start;
1432 unsigned int page_offset = offset_in_page(offset);
1433 unsigned int page_length = PAGE_SIZE - page_offset;
1434 page_length = remain < page_length ? remain : page_length;
1435 if (node.allocated) {
1436 wmb(); /* flush the write before we modify the GGTT */
1437 ggtt->vm.insert_page(&ggtt->vm,
1438 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1439 node.start, I915_CACHE_NONE, 0);
1440 wmb(); /* flush modifications to the GGTT (insert_page) */
1442 page_base += offset & PAGE_MASK;
1444 /* If we get a fault while copying data, then (presumably) our
1445 * source page isn't available. Return the error and we'll
1446 * retry in the slow path.
1447 * If the object is non-shmem backed, we retry again with the
1448 * path that handles page fault.
1450 if (ggtt_write(&ggtt->iomap, page_base, page_offset,
1451 user_data, page_length)) {
1456 remain -= page_length;
1457 user_data += page_length;
1458 offset += page_length;
1460 intel_fb_obj_flush(obj, ORIGIN_CPU);
1462 mutex_lock(&i915->drm.struct_mutex);
1464 if (node.allocated) {
1466 ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
1467 remove_mappable_node(&node);
1469 i915_vma_unpin(vma);
1472 intel_runtime_pm_put(i915);
1474 mutex_unlock(&i915->drm.struct_mutex);
1479 shmem_pwrite_slow(struct page *page, int offset, int length,
1480 char __user *user_data,
1481 bool page_do_bit17_swizzling,
1482 bool needs_clflush_before,
1483 bool needs_clflush_after)
1489 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1490 shmem_clflush_swizzled_range(vaddr + offset, length,
1491 page_do_bit17_swizzling);
1492 if (page_do_bit17_swizzling)
1493 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1496 ret = __copy_from_user(vaddr + offset, user_data, length);
1497 if (needs_clflush_after)
1498 shmem_clflush_swizzled_range(vaddr + offset, length,
1499 page_do_bit17_swizzling);
1502 return ret ? -EFAULT : 0;
1505 /* Per-page copy function for the shmem pwrite fastpath.
1506 * Flushes invalid cachelines before writing to the target if
1507 * needs_clflush_before is set and flushes out any written cachelines after
1508 * writing if needs_clflush is set.
1511 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1512 bool page_do_bit17_swizzling,
1513 bool needs_clflush_before,
1514 bool needs_clflush_after)
1519 if (!page_do_bit17_swizzling) {
1520 char *vaddr = kmap_atomic(page);
1522 if (needs_clflush_before)
1523 drm_clflush_virt_range(vaddr + offset, len);
1524 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1525 if (needs_clflush_after)
1526 drm_clflush_virt_range(vaddr + offset, len);
1528 kunmap_atomic(vaddr);
1533 return shmem_pwrite_slow(page, offset, len, user_data,
1534 page_do_bit17_swizzling,
1535 needs_clflush_before,
1536 needs_clflush_after);
1540 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1541 const struct drm_i915_gem_pwrite *args)
1543 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1544 void __user *user_data;
1546 unsigned int obj_do_bit17_swizzling;
1547 unsigned int partial_cacheline_write;
1548 unsigned int needs_clflush;
1549 unsigned int offset, idx;
1552 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1556 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1557 mutex_unlock(&i915->drm.struct_mutex);
1561 obj_do_bit17_swizzling = 0;
1562 if (i915_gem_object_needs_bit17_swizzle(obj))
1563 obj_do_bit17_swizzling = BIT(17);
1565 /* If we don't overwrite a cacheline completely we need to be
1566 * careful to have up-to-date data by first clflushing. Don't
1567 * overcomplicate things and flush the entire patch.
1569 partial_cacheline_write = 0;
1570 if (needs_clflush & CLFLUSH_BEFORE)
1571 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1573 user_data = u64_to_user_ptr(args->data_ptr);
1574 remain = args->size;
1575 offset = offset_in_page(args->offset);
1576 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1577 struct page *page = i915_gem_object_get_page(obj, idx);
1581 if (offset + length > PAGE_SIZE)
1582 length = PAGE_SIZE - offset;
1584 ret = shmem_pwrite(page, offset, length, user_data,
1585 page_to_phys(page) & obj_do_bit17_swizzling,
1586 (offset | length) & partial_cacheline_write,
1587 needs_clflush & CLFLUSH_AFTER);
1592 user_data += length;
1596 intel_fb_obj_flush(obj, ORIGIN_CPU);
1597 i915_gem_obj_finish_shmem_access(obj);
1602 * Writes data to the object referenced by handle.
1604 * @data: ioctl data blob
1607 * On error, the contents of the buffer that were to be modified are undefined.
1610 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1611 struct drm_file *file)
1613 struct drm_i915_gem_pwrite *args = data;
1614 struct drm_i915_gem_object *obj;
1617 if (args->size == 0)
1620 if (!access_ok(VERIFY_READ,
1621 u64_to_user_ptr(args->data_ptr),
1625 obj = i915_gem_object_lookup(file, args->handle);
1629 /* Bounds check destination. */
1630 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1635 /* Writes not allowed into this read-only object */
1636 if (i915_gem_object_is_readonly(obj)) {
1641 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1644 if (obj->ops->pwrite)
1645 ret = obj->ops->pwrite(obj, args);
1649 ret = i915_gem_object_wait(obj,
1650 I915_WAIT_INTERRUPTIBLE |
1652 MAX_SCHEDULE_TIMEOUT,
1653 to_rps_client(file));
1657 ret = i915_gem_object_pin_pages(obj);
1662 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1663 * it would end up going through the fenced access, and we'll get
1664 * different detiling behavior between reading and writing.
1665 * pread/pwrite currently are reading and writing from the CPU
1666 * perspective, requiring manual detiling by the client.
1668 if (!i915_gem_object_has_struct_page(obj) ||
1669 cpu_write_needs_clflush(obj))
1670 /* Note that the gtt paths might fail with non-page-backed user
1671 * pointers (e.g. gtt mappings when moving data between
1672 * textures). Fallback to the shmem path in that case.
1674 ret = i915_gem_gtt_pwrite_fast(obj, args);
1676 if (ret == -EFAULT || ret == -ENOSPC) {
1677 if (obj->phys_handle)
1678 ret = i915_gem_phys_pwrite(obj, args, file);
1680 ret = i915_gem_shmem_pwrite(obj, args);
1683 i915_gem_object_unpin_pages(obj);
1685 i915_gem_object_put(obj);
1689 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1691 struct drm_i915_private *i915;
1692 struct list_head *list;
1693 struct i915_vma *vma;
1695 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
1697 for_each_ggtt_vma(vma, obj) {
1698 if (i915_vma_is_active(vma))
1701 if (!drm_mm_node_allocated(&vma->node))
1704 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1707 i915 = to_i915(obj->base.dev);
1708 spin_lock(&i915->mm.obj_lock);
1709 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1710 list_move_tail(&obj->mm.link, list);
1711 spin_unlock(&i915->mm.obj_lock);
1715 * Called when user space prepares to use an object with the CPU, either
1716 * through the mmap ioctl's mapping or a GTT mapping.
1718 * @data: ioctl data blob
1722 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1723 struct drm_file *file)
1725 struct drm_i915_gem_set_domain *args = data;
1726 struct drm_i915_gem_object *obj;
1727 uint32_t read_domains = args->read_domains;
1728 uint32_t write_domain = args->write_domain;
1731 /* Only handle setting domains to types used by the CPU. */
1732 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1735 /* Having something in the write domain implies it's in the read
1736 * domain, and only that read domain. Enforce that in the request.
1738 if (write_domain != 0 && read_domains != write_domain)
1741 obj = i915_gem_object_lookup(file, args->handle);
1745 /* Try to flush the object off the GPU without holding the lock.
1746 * We will repeat the flush holding the lock in the normal manner
1747 * to catch cases where we are gazumped.
1749 err = i915_gem_object_wait(obj,
1750 I915_WAIT_INTERRUPTIBLE |
1751 (write_domain ? I915_WAIT_ALL : 0),
1752 MAX_SCHEDULE_TIMEOUT,
1753 to_rps_client(file));
1758 * Proxy objects do not control access to the backing storage, ergo
1759 * they cannot be used as a means to manipulate the cache domain
1760 * tracking for that backing storage. The proxy object is always
1761 * considered to be outside of any cache domain.
1763 if (i915_gem_object_is_proxy(obj)) {
1769 * Flush and acquire obj->pages so that we are coherent through
1770 * direct access in memory with previous cached writes through
1771 * shmemfs and that our cache domain tracking remains valid.
1772 * For example, if the obj->filp was moved to swap without us
1773 * being notified and releasing the pages, we would mistakenly
1774 * continue to assume that the obj remained out of the CPU cached
1777 err = i915_gem_object_pin_pages(obj);
1781 err = i915_mutex_lock_interruptible(dev);
1785 if (read_domains & I915_GEM_DOMAIN_WC)
1786 err = i915_gem_object_set_to_wc_domain(obj, write_domain);
1787 else if (read_domains & I915_GEM_DOMAIN_GTT)
1788 err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
1790 err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
1792 /* And bump the LRU for this access */
1793 i915_gem_object_bump_inactive_ggtt(obj);
1795 mutex_unlock(&dev->struct_mutex);
1797 if (write_domain != 0)
1798 intel_fb_obj_invalidate(obj,
1799 fb_write_origin(obj, write_domain));
1802 i915_gem_object_unpin_pages(obj);
1804 i915_gem_object_put(obj);
1809 * Called when user space has done writes to this buffer
1811 * @data: ioctl data blob
1815 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *file)
1818 struct drm_i915_gem_sw_finish *args = data;
1819 struct drm_i915_gem_object *obj;
1821 obj = i915_gem_object_lookup(file, args->handle);
1826 * Proxy objects are barred from CPU access, so there is no
1827 * need to ban sw_finish as it is a nop.
1830 /* Pinned buffers may be scanout, so flush the cache */
1831 i915_gem_object_flush_if_display(obj);
1832 i915_gem_object_put(obj);
1838 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1841 * @data: ioctl data blob
1844 * While the mapping holds a reference on the contents of the object, it doesn't
1845 * imply a ref on the object itself.
1849 * DRM driver writers who look a this function as an example for how to do GEM
1850 * mmap support, please don't implement mmap support like here. The modern way
1851 * to implement DRM mmap support is with an mmap offset ioctl (like
1852 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1853 * That way debug tooling like valgrind will understand what's going on, hiding
1854 * the mmap call in a driver private ioctl will break that. The i915 driver only
1855 * does cpu mmaps this way because we didn't know better.
1858 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1859 struct drm_file *file)
1861 struct drm_i915_gem_mmap *args = data;
1862 struct drm_i915_gem_object *obj;
1865 if (args->flags & ~(I915_MMAP_WC))
1868 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1871 obj = i915_gem_object_lookup(file, args->handle);
1875 /* prime objects have no backing filp to GEM mmap
1878 if (!obj->base.filp) {
1879 i915_gem_object_put(obj);
1883 addr = vm_mmap(obj->base.filp, 0, args->size,
1884 PROT_READ | PROT_WRITE, MAP_SHARED,
1886 if (args->flags & I915_MMAP_WC) {
1887 struct mm_struct *mm = current->mm;
1888 struct vm_area_struct *vma;
1890 if (down_write_killable(&mm->mmap_sem)) {
1891 i915_gem_object_put(obj);
1894 vma = find_vma(mm, addr);
1897 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1900 up_write(&mm->mmap_sem);
1902 /* This may race, but that's ok, it only gets set */
1903 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1905 i915_gem_object_put(obj);
1906 if (IS_ERR((void *)addr))
1909 args->addr_ptr = (uint64_t) addr;
1914 static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj)
1916 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1920 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1922 * A history of the GTT mmap interface:
1924 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1925 * aligned and suitable for fencing, and still fit into the available
1926 * mappable space left by the pinned display objects. A classic problem
1927 * we called the page-fault-of-doom where we would ping-pong between
1928 * two objects that could not fit inside the GTT and so the memcpy
1929 * would page one object in at the expense of the other between every
1932 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1933 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1934 * object is too large for the available space (or simply too large
1935 * for the mappable aperture!), a view is created instead and faulted
1936 * into userspace. (This view is aligned and sized appropriately for
1939 * 2 - Recognise WC as a separate cache domain so that we can flush the
1940 * delayed writes via GTT before performing direct access via WC.
1944 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1945 * hangs on some architectures, corruption on others. An attempt to service
1946 * a GTT page fault from a snoopable object will generate a SIGBUS.
1948 * * the object must be able to fit into RAM (physical memory, though no
1949 * limited to the mappable aperture).
1954 * * a new GTT page fault will synchronize rendering from the GPU and flush
1955 * all data to system memory. Subsequent access will not be synchronized.
1957 * * all mappings are revoked on runtime device suspend.
1959 * * there are only 8, 16 or 32 fence registers to share between all users
1960 * (older machines require fence register for display and blitter access
1961 * as well). Contention of the fence registers will cause the previous users
1962 * to be unmapped and any new access will generate new page faults.
1964 * * running out of memory while servicing a fault may generate a SIGBUS,
1965 * rather than the expected SIGSEGV.
1967 int i915_gem_mmap_gtt_version(void)
1972 static inline struct i915_ggtt_view
1973 compute_partial_view(const struct drm_i915_gem_object *obj,
1974 pgoff_t page_offset,
1977 struct i915_ggtt_view view;
1979 if (i915_gem_object_is_tiled(obj))
1980 chunk = roundup(chunk, tile_row_pages(obj));
1982 view.type = I915_GGTT_VIEW_PARTIAL;
1983 view.partial.offset = rounddown(page_offset, chunk);
1985 min_t(unsigned int, chunk,
1986 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1988 /* If the partial covers the entire object, just create a normal VMA. */
1989 if (chunk >= obj->base.size >> PAGE_SHIFT)
1990 view.type = I915_GGTT_VIEW_NORMAL;
1996 * i915_gem_fault - fault a page into the GTT
1999 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
2000 * from userspace. The fault handler takes care of binding the object to
2001 * the GTT (if needed), allocating and programming a fence register (again,
2002 * only if needed based on whether the old reg is still valid or the object
2003 * is tiled) and inserting a new PTE into the faulting process.
2005 * Note that the faulting process may involve evicting existing objects
2006 * from the GTT and/or fence registers to make room. So performance may
2007 * suffer if the GTT working set is large or there are few fence registers
2010 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
2011 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
2013 vm_fault_t i915_gem_fault(struct vm_fault *vmf)
2015 #define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
2016 struct vm_area_struct *area = vmf->vma;
2017 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
2018 struct drm_device *dev = obj->base.dev;
2019 struct drm_i915_private *dev_priv = to_i915(dev);
2020 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2021 bool write = area->vm_flags & VM_WRITE;
2022 struct i915_vma *vma;
2023 pgoff_t page_offset;
2026 /* Sanity check that we allow writing into this object */
2027 if (i915_gem_object_is_readonly(obj) && write)
2028 return VM_FAULT_SIGBUS;
2030 /* We don't use vmf->pgoff since that has the fake offset */
2031 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
2033 trace_i915_gem_object_fault(obj, page_offset, true, write);
2035 /* Try to flush the object off the GPU first without holding the lock.
2036 * Upon acquiring the lock, we will perform our sanity checks and then
2037 * repeat the flush holding the lock in the normal manner to catch cases
2038 * where we are gazumped.
2040 ret = i915_gem_object_wait(obj,
2041 I915_WAIT_INTERRUPTIBLE,
2042 MAX_SCHEDULE_TIMEOUT,
2047 ret = i915_gem_object_pin_pages(obj);
2051 intel_runtime_pm_get(dev_priv);
2053 ret = i915_mutex_lock_interruptible(dev);
2057 /* Access to snoopable pages through the GTT is incoherent. */
2058 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
2064 /* Now pin it into the GTT as needed */
2065 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
2070 /* Use a partial view if it is bigger than available space */
2071 struct i915_ggtt_view view =
2072 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
2075 flags = PIN_MAPPABLE;
2076 if (view.type == I915_GGTT_VIEW_NORMAL)
2077 flags |= PIN_NONBLOCK; /* avoid warnings for pinned */
2080 * Userspace is now writing through an untracked VMA, abandon
2081 * all hope that the hardware is able to track future writes.
2083 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
2085 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags);
2086 if (IS_ERR(vma) && !view.type) {
2087 flags = PIN_MAPPABLE;
2088 view.type = I915_GGTT_VIEW_PARTIAL;
2089 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags);
2097 ret = i915_gem_object_set_to_gtt_domain(obj, write);
2101 ret = i915_vma_pin_fence(vma);
2105 /* Finally, remap it using the new GTT offset */
2106 ret = remap_io_mapping(area,
2107 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
2108 (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
2109 min_t(u64, vma->size, area->vm_end - area->vm_start),
2114 /* Mark as being mmapped into userspace for later revocation */
2115 assert_rpm_wakelock_held(dev_priv);
2116 if (!i915_vma_set_userfault(vma) && !obj->userfault_count++)
2117 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
2118 GEM_BUG_ON(!obj->userfault_count);
2120 i915_vma_set_ggtt_write(vma);
2123 i915_vma_unpin_fence(vma);
2125 __i915_vma_unpin(vma);
2127 mutex_unlock(&dev->struct_mutex);
2129 intel_runtime_pm_put(dev_priv);
2130 i915_gem_object_unpin_pages(obj);
2135 * We eat errors when the gpu is terminally wedged to avoid
2136 * userspace unduly crashing (gl has no provisions for mmaps to
2137 * fail). But any other -EIO isn't ours (e.g. swap in failure)
2138 * and so needs to be reported.
2140 if (!i915_terminally_wedged(&dev_priv->gpu_error))
2141 return VM_FAULT_SIGBUS;
2142 /* else: fall through */
2145 * EAGAIN means the gpu is hung and we'll wait for the error
2146 * handler to reset everything when re-faulting in
2147 * i915_mutex_lock_interruptible.
2154 * EBUSY is ok: this just means that another thread
2155 * already did the job.
2157 return VM_FAULT_NOPAGE;
2159 return VM_FAULT_OOM;
2162 return VM_FAULT_SIGBUS;
2164 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2165 return VM_FAULT_SIGBUS;
2169 static void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)
2171 struct i915_vma *vma;
2173 GEM_BUG_ON(!obj->userfault_count);
2175 obj->userfault_count = 0;
2176 list_del(&obj->userfault_link);
2177 drm_vma_node_unmap(&obj->base.vma_node,
2178 obj->base.dev->anon_inode->i_mapping);
2180 for_each_ggtt_vma(vma, obj)
2181 i915_vma_unset_userfault(vma);
2185 * i915_gem_release_mmap - remove physical page mappings
2186 * @obj: obj in question
2188 * Preserve the reservation of the mmapping with the DRM core code, but
2189 * relinquish ownership of the pages back to the system.
2191 * It is vital that we remove the page mapping if we have mapped a tiled
2192 * object through the GTT and then lose the fence register due to
2193 * resource pressure. Similarly if the object has been moved out of the
2194 * aperture, than pages mapped into userspace must be revoked. Removing the
2195 * mapping will then trigger a page fault on the next user access, allowing
2196 * fixup by i915_gem_fault().
2199 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2201 struct drm_i915_private *i915 = to_i915(obj->base.dev);
2203 /* Serialisation between user GTT access and our code depends upon
2204 * revoking the CPU's PTE whilst the mutex is held. The next user
2205 * pagefault then has to wait until we release the mutex.
2207 * Note that RPM complicates somewhat by adding an additional
2208 * requirement that operations to the GGTT be made holding the RPM
2211 lockdep_assert_held(&i915->drm.struct_mutex);
2212 intel_runtime_pm_get(i915);
2214 if (!obj->userfault_count)
2217 __i915_gem_object_release_mmap(obj);
2219 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2220 * memory transactions from userspace before we return. The TLB
2221 * flushing implied above by changing the PTE above *should* be
2222 * sufficient, an extra barrier here just provides us with a bit
2223 * of paranoid documentation about our requirement to serialise
2224 * memory writes before touching registers / GSM.
2229 intel_runtime_pm_put(i915);
2232 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
2234 struct drm_i915_gem_object *obj, *on;
2238 * Only called during RPM suspend. All users of the userfault_list
2239 * must be holding an RPM wakeref to ensure that this can not
2240 * run concurrently with themselves (and use the struct_mutex for
2241 * protection between themselves).
2244 list_for_each_entry_safe(obj, on,
2245 &dev_priv->mm.userfault_list, userfault_link)
2246 __i915_gem_object_release_mmap(obj);
2248 /* The fence will be lost when the device powers down. If any were
2249 * in use by hardware (i.e. they are pinned), we should not be powering
2250 * down! All other fences will be reacquired by the user upon waking.
2252 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2253 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2255 /* Ideally we want to assert that the fence register is not
2256 * live at this point (i.e. that no piece of code will be
2257 * trying to write through fence + GTT, as that both violates
2258 * our tracking of activity and associated locking/barriers,
2259 * but also is illegal given that the hw is powered down).
2261 * Previously we used reg->pin_count as a "liveness" indicator.
2262 * That is not sufficient, and we need a more fine-grained
2263 * tool if we want to have a sanity check here.
2269 GEM_BUG_ON(i915_vma_has_userfault(reg->vma));
2274 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2276 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2279 err = drm_gem_create_mmap_offset(&obj->base);
2283 /* Attempt to reap some mmap space from dead objects */
2285 err = i915_gem_wait_for_idle(dev_priv,
2286 I915_WAIT_INTERRUPTIBLE,
2287 MAX_SCHEDULE_TIMEOUT);
2291 i915_gem_drain_freed_objects(dev_priv);
2292 err = drm_gem_create_mmap_offset(&obj->base);
2296 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2301 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2303 drm_gem_free_mmap_offset(&obj->base);
2307 i915_gem_mmap_gtt(struct drm_file *file,
2308 struct drm_device *dev,
2312 struct drm_i915_gem_object *obj;
2315 obj = i915_gem_object_lookup(file, handle);
2319 ret = i915_gem_object_create_mmap_offset(obj);
2321 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2323 i915_gem_object_put(obj);
2328 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2330 * @data: GTT mapping ioctl data
2331 * @file: GEM object info
2333 * Simply returns the fake offset to userspace so it can mmap it.
2334 * The mmap call will end up in drm_gem_mmap(), which will set things
2335 * up so we can get faults in the handler above.
2337 * The fault handler will take care of binding the object into the GTT
2338 * (since it may have been evicted to make room for something), allocating
2339 * a fence register, and mapping the appropriate aperture address into
2343 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2344 struct drm_file *file)
2346 struct drm_i915_gem_mmap_gtt *args = data;
2348 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2351 /* Immediately discard the backing storage */
2353 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2355 i915_gem_object_free_mmap_offset(obj);
2357 if (obj->base.filp == NULL)
2360 /* Our goal here is to return as much of the memory as
2361 * is possible back to the system as we are called from OOM.
2362 * To do this we must instruct the shmfs to drop all of its
2363 * backing pages, *now*.
2365 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2366 obj->mm.madv = __I915_MADV_PURGED;
2367 obj->mm.pages = ERR_PTR(-EFAULT);
2370 /* Try to discard unwanted pages */
2371 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2373 struct address_space *mapping;
2375 lockdep_assert_held(&obj->mm.lock);
2376 GEM_BUG_ON(i915_gem_object_has_pages(obj));
2378 switch (obj->mm.madv) {
2379 case I915_MADV_DONTNEED:
2380 i915_gem_object_truncate(obj);
2381 case __I915_MADV_PURGED:
2385 if (obj->base.filp == NULL)
2388 mapping = obj->base.filp->f_mapping,
2389 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2393 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2394 struct sg_table *pages)
2396 struct sgt_iter sgt_iter;
2399 __i915_gem_object_release_shmem(obj, pages, true);
2401 i915_gem_gtt_finish_pages(obj, pages);
2403 if (i915_gem_object_needs_bit17_swizzle(obj))
2404 i915_gem_object_save_bit_17_swizzle(obj, pages);
2406 for_each_sgt_page(page, sgt_iter, pages) {
2408 set_page_dirty(page);
2410 if (obj->mm.madv == I915_MADV_WILLNEED)
2411 mark_page_accessed(page);
2415 obj->mm.dirty = false;
2417 sg_free_table(pages);
2421 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2423 struct radix_tree_iter iter;
2427 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2428 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2432 static struct sg_table *
2433 __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
2435 struct drm_i915_private *i915 = to_i915(obj->base.dev);
2436 struct sg_table *pages;
2438 pages = fetch_and_zero(&obj->mm.pages);
2442 spin_lock(&i915->mm.obj_lock);
2443 list_del(&obj->mm.link);
2444 spin_unlock(&i915->mm.obj_lock);
2446 if (obj->mm.mapping) {
2449 ptr = page_mask_bits(obj->mm.mapping);
2450 if (is_vmalloc_addr(ptr))
2453 kunmap(kmap_to_page(ptr));
2455 obj->mm.mapping = NULL;
2458 __i915_gem_object_reset_page_iter(obj);
2459 obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;
2464 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2465 enum i915_mm_subclass subclass)
2467 struct sg_table *pages;
2469 if (i915_gem_object_has_pinned_pages(obj))
2472 GEM_BUG_ON(obj->bind_count);
2473 if (!i915_gem_object_has_pages(obj))
2476 /* May be called by shrinker from within get_pages() (on another bo) */
2477 mutex_lock_nested(&obj->mm.lock, subclass);
2478 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2482 * ->put_pages might need to allocate memory for the bit17 swizzle
2483 * array, hence protect them from being reaped by removing them from gtt
2486 pages = __i915_gem_object_unset_pages(obj);
2488 obj->ops->put_pages(obj, pages);
2491 mutex_unlock(&obj->mm.lock);
2494 static bool i915_sg_trim(struct sg_table *orig_st)
2496 struct sg_table new_st;
2497 struct scatterlist *sg, *new_sg;
2500 if (orig_st->nents == orig_st->orig_nents)
2503 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2506 new_sg = new_st.sgl;
2507 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2508 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2509 /* called before being DMA mapped, no need to copy sg->dma_* */
2510 new_sg = sg_next(new_sg);
2512 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2514 sg_free_table(orig_st);
2520 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2522 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2523 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2525 struct address_space *mapping;
2526 struct sg_table *st;
2527 struct scatterlist *sg;
2528 struct sgt_iter sgt_iter;
2530 unsigned long last_pfn = 0; /* suppress gcc warning */
2531 unsigned int max_segment = i915_sg_segment_size();
2532 unsigned int sg_page_sizes;
2537 * Assert that the object is not currently in any GPU domain. As it
2538 * wasn't in the GTT, there shouldn't be any way it could have been in
2541 GEM_BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2542 GEM_BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2545 * If there's no chance of allocating enough pages for the whole
2546 * object, bail early.
2548 if (page_count > totalram_pages)
2551 st = kmalloc(sizeof(*st), GFP_KERNEL);
2556 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2562 * Get the list of pages out of our struct file. They'll be pinned
2563 * at this point until we release them.
2565 * Fail silently without starting the shrinker
2567 mapping = obj->base.filp->f_mapping;
2568 noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM);
2569 noreclaim |= __GFP_NORETRY | __GFP_NOWARN;
2574 for (i = 0; i < page_count; i++) {
2575 const unsigned int shrink[] = {
2576 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE,
2579 gfp_t gfp = noreclaim;
2582 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2583 if (likely(!IS_ERR(page)))
2587 ret = PTR_ERR(page);
2591 i915_gem_shrink(dev_priv, 2 * page_count, NULL, *s++);
2595 * We've tried hard to allocate the memory by reaping
2596 * our own buffer, now let the real VM do its job and
2597 * go down in flames if truly OOM.
2599 * However, since graphics tend to be disposable,
2600 * defer the oom here by reporting the ENOMEM back
2604 /* reclaim and warn, but no oom */
2605 gfp = mapping_gfp_mask(mapping);
2608 * Our bo are always dirty and so we require
2609 * kswapd to reclaim our pages (direct reclaim
2610 * does not effectively begin pageout of our
2611 * buffers on its own). However, direct reclaim
2612 * only waits for kswapd when under allocation
2613 * congestion. So as a result __GFP_RECLAIM is
2614 * unreliable and fails to actually reclaim our
2615 * dirty pages -- unless you try over and over
2616 * again with !__GFP_NORETRY. However, we still
2617 * want to fail this allocation rather than
2618 * trigger the out-of-memory killer and for
2619 * this we want __GFP_RETRY_MAYFAIL.
2621 gfp |= __GFP_RETRY_MAYFAIL;
2626 sg->length >= max_segment ||
2627 page_to_pfn(page) != last_pfn + 1) {
2629 sg_page_sizes |= sg->length;
2633 sg_set_page(sg, page, PAGE_SIZE, 0);
2635 sg->length += PAGE_SIZE;
2637 last_pfn = page_to_pfn(page);
2639 /* Check that the i965g/gm workaround works. */
2640 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2642 if (sg) { /* loop terminated early; short sg table */
2643 sg_page_sizes |= sg->length;
2647 /* Trim unused sg entries to avoid wasting memory. */
2650 ret = i915_gem_gtt_prepare_pages(obj, st);
2653 * DMA remapping failed? One possible cause is that
2654 * it could not reserve enough large entries, asking
2655 * for PAGE_SIZE chunks instead may be helpful.
2657 if (max_segment > PAGE_SIZE) {
2658 for_each_sgt_page(page, sgt_iter, st)
2662 max_segment = PAGE_SIZE;
2665 dev_warn(&dev_priv->drm.pdev->dev,
2666 "Failed to DMA remap %lu pages\n",
2672 if (i915_gem_object_needs_bit17_swizzle(obj))
2673 i915_gem_object_do_bit_17_swizzle(obj, st);
2675 __i915_gem_object_set_pages(obj, st, sg_page_sizes);
2682 for_each_sgt_page(page, sgt_iter, st)
2688 * shmemfs first checks if there is enough memory to allocate the page
2689 * and reports ENOSPC should there be insufficient, along with the usual
2690 * ENOMEM for a genuine allocation failure.
2692 * We use ENOSPC in our driver to mean that we have run out of aperture
2693 * space and so want to translate the error from shmemfs back to our
2694 * usual understanding of ENOMEM.
2702 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2703 struct sg_table *pages,
2704 unsigned int sg_page_sizes)
2706 struct drm_i915_private *i915 = to_i915(obj->base.dev);
2707 unsigned long supported = INTEL_INFO(i915)->page_sizes;
2710 lockdep_assert_held(&obj->mm.lock);
2712 obj->mm.get_page.sg_pos = pages->sgl;
2713 obj->mm.get_page.sg_idx = 0;
2715 obj->mm.pages = pages;
2717 if (i915_gem_object_is_tiled(obj) &&
2718 i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2719 GEM_BUG_ON(obj->mm.quirked);
2720 __i915_gem_object_pin_pages(obj);
2721 obj->mm.quirked = true;
2724 GEM_BUG_ON(!sg_page_sizes);
2725 obj->mm.page_sizes.phys = sg_page_sizes;
2728 * Calculate the supported page-sizes which fit into the given
2729 * sg_page_sizes. This will give us the page-sizes which we may be able
2730 * to use opportunistically when later inserting into the GTT. For
2731 * example if phys=2G, then in theory we should be able to use 1G, 2M,
2732 * 64K or 4K pages, although in practice this will depend on a number of
2735 obj->mm.page_sizes.sg = 0;
2736 for_each_set_bit(i, &supported, ilog2(I915_GTT_MAX_PAGE_SIZE) + 1) {
2737 if (obj->mm.page_sizes.phys & ~0u << i)
2738 obj->mm.page_sizes.sg |= BIT(i);
2740 GEM_BUG_ON(!HAS_PAGE_SIZES(i915, obj->mm.page_sizes.sg));
2742 spin_lock(&i915->mm.obj_lock);
2743 list_add(&obj->mm.link, &i915->mm.unbound_list);
2744 spin_unlock(&i915->mm.obj_lock);
2747 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2751 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2752 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2756 err = obj->ops->get_pages(obj);
2757 GEM_BUG_ON(!err && !i915_gem_object_has_pages(obj));
2762 /* Ensure that the associated pages are gathered from the backing storage
2763 * and pinned into our object. i915_gem_object_pin_pages() may be called
2764 * multiple times before they are released by a single call to
2765 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2766 * either as a result of memory pressure (reaping pages under the shrinker)
2767 * or as the object is itself released.
2769 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2773 err = mutex_lock_interruptible(&obj->mm.lock);
2777 if (unlikely(!i915_gem_object_has_pages(obj))) {
2778 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2780 err = ____i915_gem_object_get_pages(obj);
2784 smp_mb__before_atomic();
2786 atomic_inc(&obj->mm.pages_pin_count);
2789 mutex_unlock(&obj->mm.lock);
2793 /* The 'mapping' part of i915_gem_object_pin_map() below */
2794 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2795 enum i915_map_type type)
2797 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2798 struct sg_table *sgt = obj->mm.pages;
2799 struct sgt_iter sgt_iter;
2801 struct page *stack_pages[32];
2802 struct page **pages = stack_pages;
2803 unsigned long i = 0;
2807 /* A single page can always be kmapped */
2808 if (n_pages == 1 && type == I915_MAP_WB)
2809 return kmap(sg_page(sgt->sgl));
2811 if (n_pages > ARRAY_SIZE(stack_pages)) {
2812 /* Too big for stack -- allocate temporary array instead */
2813 pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_KERNEL);
2818 for_each_sgt_page(page, sgt_iter, sgt)
2821 /* Check that we have the expected number of pages */
2822 GEM_BUG_ON(i != n_pages);
2827 /* fallthrough to use PAGE_KERNEL anyway */
2829 pgprot = PAGE_KERNEL;
2832 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2835 addr = vmap(pages, n_pages, 0, pgprot);
2837 if (pages != stack_pages)
2843 /* get, pin, and map the pages of the object into kernel space */
2844 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2845 enum i915_map_type type)
2847 enum i915_map_type has_type;
2852 if (unlikely(!i915_gem_object_has_struct_page(obj)))
2853 return ERR_PTR(-ENXIO);
2855 ret = mutex_lock_interruptible(&obj->mm.lock);
2857 return ERR_PTR(ret);
2859 pinned = !(type & I915_MAP_OVERRIDE);
2860 type &= ~I915_MAP_OVERRIDE;
2862 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2863 if (unlikely(!i915_gem_object_has_pages(obj))) {
2864 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2866 ret = ____i915_gem_object_get_pages(obj);
2870 smp_mb__before_atomic();
2872 atomic_inc(&obj->mm.pages_pin_count);
2875 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2877 ptr = page_unpack_bits(obj->mm.mapping, &has_type);
2878 if (ptr && has_type != type) {
2884 if (is_vmalloc_addr(ptr))
2887 kunmap(kmap_to_page(ptr));
2889 ptr = obj->mm.mapping = NULL;
2893 ptr = i915_gem_object_map(obj, type);
2899 obj->mm.mapping = page_pack_bits(ptr, type);
2903 mutex_unlock(&obj->mm.lock);
2907 atomic_dec(&obj->mm.pages_pin_count);
2914 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
2915 const struct drm_i915_gem_pwrite *arg)
2917 struct address_space *mapping = obj->base.filp->f_mapping;
2918 char __user *user_data = u64_to_user_ptr(arg->data_ptr);
2922 /* Before we instantiate/pin the backing store for our use, we
2923 * can prepopulate the shmemfs filp efficiently using a write into
2924 * the pagecache. We avoid the penalty of instantiating all the
2925 * pages, important if the user is just writing to a few and never
2926 * uses the object on the GPU, and using a direct write into shmemfs
2927 * allows it to avoid the cost of retrieving a page (either swapin
2928 * or clearing-before-use) before it is overwritten.
2930 if (i915_gem_object_has_pages(obj))
2933 if (obj->mm.madv != I915_MADV_WILLNEED)
2936 /* Before the pages are instantiated the object is treated as being
2937 * in the CPU domain. The pages will be clflushed as required before
2938 * use, and we can freely write into the pages directly. If userspace
2939 * races pwrite with any other operation; corruption will ensue -
2940 * that is userspace's prerogative!
2944 offset = arg->offset;
2945 pg = offset_in_page(offset);
2948 unsigned int len, unwritten;
2953 len = PAGE_SIZE - pg;
2957 err = pagecache_write_begin(obj->base.filp, mapping,
2964 unwritten = copy_from_user(vaddr + pg, user_data, len);
2967 err = pagecache_write_end(obj->base.filp, mapping,
2968 offset, len, len - unwritten,
2985 static void i915_gem_client_mark_guilty(struct drm_i915_file_private *file_priv,
2986 const struct i915_gem_context *ctx)
2989 unsigned long prev_hang;
2991 if (i915_gem_context_is_banned(ctx))
2992 score = I915_CLIENT_SCORE_CONTEXT_BAN;
2996 prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
2997 if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
2998 score += I915_CLIENT_SCORE_HANG_FAST;
3001 atomic_add(score, &file_priv->ban_score);
3003 DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
3005 atomic_read(&file_priv->ban_score));
3009 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
3012 bool banned, bannable;
3014 atomic_inc(&ctx->guilty_count);
3016 bannable = i915_gem_context_is_bannable(ctx);
3017 score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score);
3018 banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
3020 /* Cool contexts don't accumulate client ban score */
3025 DRM_DEBUG_DRIVER("context %s: guilty %d, score %u, banned\n",
3026 ctx->name, atomic_read(&ctx->guilty_count),
3028 i915_gem_context_set_banned(ctx);
3031 if (!IS_ERR_OR_NULL(ctx->file_priv))
3032 i915_gem_client_mark_guilty(ctx->file_priv, ctx);
3035 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
3037 atomic_inc(&ctx->active_count);
3040 struct i915_request *
3041 i915_gem_find_active_request(struct intel_engine_cs *engine)
3043 struct i915_request *request, *active = NULL;
3044 unsigned long flags;
3047 * We are called by the error capture, reset and to dump engine
3048 * state at random points in time. In particular, note that neither is
3049 * crucially ordered with an interrupt. After a hang, the GPU is dead
3050 * and we assume that no more writes can happen (we waited long enough
3051 * for all writes that were in transaction to be flushed) - adding an
3052 * extra delay for a recent interrupt is pointless. Hence, we do
3053 * not need an engine->irq_seqno_barrier() before the seqno reads.
3054 * At all other times, we must assume the GPU is still running, but
3055 * we only care about the snapshot of this moment.
3057 spin_lock_irqsave(&engine->timeline.lock, flags);
3058 list_for_each_entry(request, &engine->timeline.requests, link) {
3059 if (__i915_request_completed(request, request->global_seqno))
3065 spin_unlock_irqrestore(&engine->timeline.lock, flags);
3071 * Ensure irq handler finishes, and not run again.
3072 * Also return the active request so that we only search for it once.
3074 struct i915_request *
3075 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
3077 struct i915_request *request;
3080 * During the reset sequence, we must prevent the engine from
3081 * entering RC6. As the context state is undefined until we restart
3082 * the engine, if it does enter RC6 during the reset, the state
3083 * written to the powercontext is undefined and so we may lose
3084 * GPU state upon resume, i.e. fail to restart after a reset.
3086 intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
3088 request = engine->reset.prepare(engine);
3089 if (request && request->fence.error == -EIO)
3090 request = ERR_PTR(-EIO); /* Previous reset failed! */
3095 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
3097 struct intel_engine_cs *engine;
3098 struct i915_request *request;
3099 enum intel_engine_id id;
3102 for_each_engine(engine, dev_priv, id) {
3103 request = i915_gem_reset_prepare_engine(engine);
3104 if (IS_ERR(request)) {
3105 err = PTR_ERR(request);
3109 engine->hangcheck.active_request = request;
3112 i915_gem_revoke_fences(dev_priv);
3113 intel_uc_sanitize(dev_priv);
3118 static void engine_skip_context(struct i915_request *request)
3120 struct intel_engine_cs *engine = request->engine;
3121 struct i915_gem_context *hung_ctx = request->gem_context;
3122 struct i915_timeline *timeline = request->timeline;
3123 unsigned long flags;
3125 GEM_BUG_ON(timeline == &engine->timeline);
3127 spin_lock_irqsave(&engine->timeline.lock, flags);
3128 spin_lock(&timeline->lock);
3130 list_for_each_entry_continue(request, &engine->timeline.requests, link)
3131 if (request->gem_context == hung_ctx)
3132 i915_request_skip(request, -EIO);
3134 list_for_each_entry(request, &timeline->requests, link)
3135 i915_request_skip(request, -EIO);
3137 spin_unlock(&timeline->lock);
3138 spin_unlock_irqrestore(&engine->timeline.lock, flags);
3141 /* Returns the request if it was guilty of the hang */
3142 static struct i915_request *
3143 i915_gem_reset_request(struct intel_engine_cs *engine,
3144 struct i915_request *request,
3147 /* The guilty request will get skipped on a hung engine.
3149 * Users of client default contexts do not rely on logical
3150 * state preserved between batches so it is safe to execute
3151 * queued requests following the hang. Non default contexts
3152 * rely on preserved state, so skipping a batch loses the
3153 * evolution of the state and it needs to be considered corrupted.
3154 * Executing more queued batches on top of corrupted state is
3155 * risky. But we take the risk by trying to advance through
3156 * the queued requests in order to make the client behaviour
3157 * more predictable around resets, by not throwing away random
3158 * amount of batches it has prepared for execution. Sophisticated
3159 * clients can use gem_reset_stats_ioctl and dma fence status
3160 * (exported via sync_file info ioctl on explicit fences) to observe
3161 * when it loses the context state and should rebuild accordingly.
3163 * The context ban, and ultimately the client ban, mechanism are safety
3164 * valves if client submission ends up resulting in nothing more than
3168 if (i915_request_completed(request)) {
3169 GEM_TRACE("%s pardoned global=%d (fence %llx:%d), current %d\n",
3170 engine->name, request->global_seqno,
3171 request->fence.context, request->fence.seqno,
3172 intel_engine_get_seqno(engine));
3177 i915_gem_context_mark_guilty(request->gem_context);
3178 i915_request_skip(request, -EIO);
3180 /* If this context is now banned, skip all pending requests. */
3181 if (i915_gem_context_is_banned(request->gem_context))
3182 engine_skip_context(request);
3185 * Since this is not the hung engine, it may have advanced
3186 * since the hang declaration. Double check by refinding
3187 * the active request at the time of the reset.
3189 request = i915_gem_find_active_request(engine);
3191 unsigned long flags;
3193 i915_gem_context_mark_innocent(request->gem_context);
3194 dma_fence_set_error(&request->fence, -EAGAIN);
3196 /* Rewind the engine to replay the incomplete rq */
3197 spin_lock_irqsave(&engine->timeline.lock, flags);
3198 request = list_prev_entry(request, link);
3199 if (&request->link == &engine->timeline.requests)
3201 spin_unlock_irqrestore(&engine->timeline.lock, flags);
3208 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3209 struct i915_request *request,
3213 * Make sure this write is visible before we re-enable the interrupt
3214 * handlers on another CPU, as tasklet_enable() resolves to just
3215 * a compiler barrier which is insufficient for our purpose here.
3217 smp_store_mb(engine->irq_posted, 0);
3220 request = i915_gem_reset_request(engine, request, stalled);
3222 /* Setup the CS to resume from the breadcrumb of the hung request */
3223 engine->reset.reset(engine, request);
3226 void i915_gem_reset(struct drm_i915_private *dev_priv,
3227 unsigned int stalled_mask)
3229 struct intel_engine_cs *engine;
3230 enum intel_engine_id id;
3232 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3234 i915_retire_requests(dev_priv);
3236 for_each_engine(engine, dev_priv, id) {
3237 struct intel_context *ce;
3239 i915_gem_reset_engine(engine,
3240 engine->hangcheck.active_request,
3241 stalled_mask & ENGINE_MASK(id));
3242 ce = fetch_and_zero(&engine->last_retired_context);
3244 intel_context_unpin(ce);
3247 * Ostensibily, we always want a context loaded for powersaving,
3248 * so if the engine is idle after the reset, send a request
3249 * to load our scratch kernel_context.
3251 * More mysteriously, if we leave the engine idle after a reset,
3252 * the next userspace batch may hang, with what appears to be
3253 * an incoherent read by the CS (presumably stale TLB). An
3254 * empty request appears sufficient to paper over the glitch.
3256 if (intel_engine_is_idle(engine)) {
3257 struct i915_request *rq;
3259 rq = i915_request_alloc(engine,
3260 dev_priv->kernel_context);
3262 i915_request_add(rq);
3266 i915_gem_restore_fences(dev_priv);
3269 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
3271 engine->reset.finish(engine);
3273 intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
3276 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
3278 struct intel_engine_cs *engine;
3279 enum intel_engine_id id;
3281 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3283 for_each_engine(engine, dev_priv, id) {
3284 engine->hangcheck.active_request = NULL;
3285 i915_gem_reset_finish_engine(engine);
3289 static void nop_submit_request(struct i915_request *request)
3291 GEM_TRACE("%s fence %llx:%d -> -EIO\n",
3292 request->engine->name,
3293 request->fence.context, request->fence.seqno);
3294 dma_fence_set_error(&request->fence, -EIO);
3296 i915_request_submit(request);
3299 static void nop_complete_submit_request(struct i915_request *request)
3301 unsigned long flags;
3303 GEM_TRACE("%s fence %llx:%d -> -EIO\n",
3304 request->engine->name,
3305 request->fence.context, request->fence.seqno);
3306 dma_fence_set_error(&request->fence, -EIO);
3308 spin_lock_irqsave(&request->engine->timeline.lock, flags);
3309 __i915_request_submit(request);
3310 intel_engine_init_global_seqno(request->engine, request->global_seqno);
3311 spin_unlock_irqrestore(&request->engine->timeline.lock, flags);
3314 void i915_gem_set_wedged(struct drm_i915_private *i915)
3316 struct intel_engine_cs *engine;
3317 enum intel_engine_id id;
3319 GEM_TRACE("start\n");
3321 if (GEM_SHOW_DEBUG()) {
3322 struct drm_printer p = drm_debug_printer(__func__);
3324 for_each_engine(engine, i915, id)
3325 intel_engine_dump(engine, &p, "%s\n", engine->name);
3328 if (test_and_set_bit(I915_WEDGED, &i915->gpu_error.flags))
3332 * First, stop submission to hw, but do not yet complete requests by
3333 * rolling the global seqno forward (since this would complete requests
3334 * for which we haven't set the fence error to EIO yet).
3336 for_each_engine(engine, i915, id) {
3337 i915_gem_reset_prepare_engine(engine);
3339 engine->submit_request = nop_submit_request;
3340 engine->schedule = NULL;
3342 i915->caps.scheduler = 0;
3344 /* Even if the GPU reset fails, it should still stop the engines */
3345 if (INTEL_GEN(i915) >= 5)
3346 intel_gpu_reset(i915, ALL_ENGINES);
3349 * Make sure no one is running the old callback before we proceed with
3350 * cancelling requests and resetting the completion tracking. Otherwise
3351 * we might submit a request to the hardware which never completes.
3355 for_each_engine(engine, i915, id) {
3356 /* Mark all executing requests as skipped */
3357 engine->cancel_requests(engine);
3360 * Only once we've force-cancelled all in-flight requests can we
3361 * start to complete all requests.
3363 engine->submit_request = nop_complete_submit_request;
3367 * Make sure no request can slip through without getting completed by
3368 * either this call here to intel_engine_init_global_seqno, or the one
3369 * in nop_complete_submit_request.
3373 for_each_engine(engine, i915, id) {
3374 unsigned long flags;
3377 * Mark all pending requests as complete so that any concurrent
3378 * (lockless) lookup doesn't try and wait upon the request as we
3381 spin_lock_irqsave(&engine->timeline.lock, flags);
3382 intel_engine_init_global_seqno(engine,
3383 intel_engine_last_submit(engine));
3384 spin_unlock_irqrestore(&engine->timeline.lock, flags);
3386 i915_gem_reset_finish_engine(engine);
3392 wake_up_all(&i915->gpu_error.reset_queue);
3395 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
3397 struct i915_timeline *tl;
3399 lockdep_assert_held(&i915->drm.struct_mutex);
3400 if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
3403 GEM_TRACE("start\n");
3406 * Before unwedging, make sure that all pending operations
3407 * are flushed and errored out - we may have requests waiting upon
3408 * third party fences. We marked all inflight requests as EIO, and
3409 * every execbuf since returned EIO, for consistency we want all
3410 * the currently pending requests to also be marked as EIO, which
3411 * is done inside our nop_submit_request - and so we must wait.
3413 * No more can be submitted until we reset the wedged bit.
3415 list_for_each_entry(tl, &i915->gt.timelines, link) {
3416 struct i915_request *rq;
3418 rq = i915_gem_active_peek(&tl->last_request,
3419 &i915->drm.struct_mutex);
3424 * We can't use our normal waiter as we want to
3425 * avoid recursively trying to handle the current
3426 * reset. The basic dma_fence_default_wait() installs
3427 * a callback for dma_fence_signal(), which is
3428 * triggered by our nop handler (indirectly, the
3429 * callback enables the signaler thread which is
3430 * woken by the nop_submit_request() advancing the seqno
3431 * and when the seqno passes the fence, the signaler
3432 * then signals the fence waking us up).
3434 if (dma_fence_default_wait(&rq->fence, true,
3435 MAX_SCHEDULE_TIMEOUT) < 0)
3438 i915_retire_requests(i915);
3439 GEM_BUG_ON(i915->gt.active_requests);
3442 * Undo nop_submit_request. We prevent all new i915 requests from
3443 * being queued (by disallowing execbuf whilst wedged) so having
3444 * waited for all active requests above, we know the system is idle
3445 * and do not have to worry about a thread being inside
3446 * engine->submit_request() as we swap over. So unlike installing
3447 * the nop_submit_request on reset, we can do this from normal
3448 * context and do not require stop_machine().
3450 intel_engines_reset_default_submission(i915);
3451 i915_gem_contexts_lost(i915);
3455 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3456 clear_bit(I915_WEDGED, &i915->gpu_error.flags);
3462 i915_gem_retire_work_handler(struct work_struct *work)
3464 struct drm_i915_private *dev_priv =
3465 container_of(work, typeof(*dev_priv), gt.retire_work.work);
3466 struct drm_device *dev = &dev_priv->drm;
3468 /* Come back later if the device is busy... */
3469 if (mutex_trylock(&dev->struct_mutex)) {
3470 i915_retire_requests(dev_priv);
3471 mutex_unlock(&dev->struct_mutex);
3475 * Keep the retire handler running until we are finally idle.
3476 * We do not need to do this test under locking as in the worst-case
3477 * we queue the retire worker once too often.
3479 if (READ_ONCE(dev_priv->gt.awake))
3480 queue_delayed_work(dev_priv->wq,
3481 &dev_priv->gt.retire_work,
3482 round_jiffies_up_relative(HZ));
3485 static void shrink_caches(struct drm_i915_private *i915)
3488 * kmem_cache_shrink() discards empty slabs and reorders partially
3489 * filled slabs to prioritise allocating from the mostly full slabs,
3490 * with the aim of reducing fragmentation.
3492 kmem_cache_shrink(i915->priorities);
3493 kmem_cache_shrink(i915->dependencies);
3494 kmem_cache_shrink(i915->requests);
3495 kmem_cache_shrink(i915->luts);
3496 kmem_cache_shrink(i915->vmas);
3497 kmem_cache_shrink(i915->objects);
3500 struct sleep_rcu_work {
3502 struct rcu_head rcu;
3503 struct work_struct work;
3505 struct drm_i915_private *i915;
3510 same_epoch(struct drm_i915_private *i915, unsigned int epoch)
3513 * There is a small chance that the epoch wrapped since we started
3514 * sleeping. If we assume that epoch is at least a u32, then it will
3515 * take at least 2^32 * 100ms for it to wrap, or about 326 years.
3517 return epoch == READ_ONCE(i915->gt.epoch);
3520 static void __sleep_work(struct work_struct *work)
3522 struct sleep_rcu_work *s = container_of(work, typeof(*s), work);
3523 struct drm_i915_private *i915 = s->i915;
3524 unsigned int epoch = s->epoch;
3527 if (same_epoch(i915, epoch))
3528 shrink_caches(i915);
3531 static void __sleep_rcu(struct rcu_head *rcu)
3533 struct sleep_rcu_work *s = container_of(rcu, typeof(*s), rcu);
3534 struct drm_i915_private *i915 = s->i915;
3536 if (same_epoch(i915, s->epoch)) {
3537 INIT_WORK(&s->work, __sleep_work);
3538 queue_work(i915->wq, &s->work);
3545 new_requests_since_last_retire(const struct drm_i915_private *i915)
3547 return (READ_ONCE(i915->gt.active_requests) ||
3548 work_pending(&i915->gt.idle_work.work));
3551 static void assert_kernel_context_is_current(struct drm_i915_private *i915)
3553 struct intel_engine_cs *engine;
3554 enum intel_engine_id id;
3556 if (i915_terminally_wedged(&i915->gpu_error))
3559 GEM_BUG_ON(i915->gt.active_requests);
3560 for_each_engine(engine, i915, id) {
3561 GEM_BUG_ON(__i915_gem_active_peek(&engine->timeline.last_request));
3562 GEM_BUG_ON(engine->last_retired_context !=
3563 to_intel_context(i915->kernel_context, engine));
3568 i915_gem_idle_work_handler(struct work_struct *work)
3570 struct drm_i915_private *dev_priv =
3571 container_of(work, typeof(*dev_priv), gt.idle_work.work);
3572 unsigned int epoch = I915_EPOCH_INVALID;
3573 bool rearm_hangcheck;
3575 if (!READ_ONCE(dev_priv->gt.awake))
3578 if (READ_ONCE(dev_priv->gt.active_requests))
3582 * Flush out the last user context, leaving only the pinned
3583 * kernel context resident. When we are idling on the kernel_context,
3584 * no more new requests (with a context switch) are emitted and we
3585 * can finally rest. A consequence is that the idle work handler is
3586 * always called at least twice before idling (and if the system is
3587 * idle that implies a round trip through the retire worker).
3589 mutex_lock(&dev_priv->drm.struct_mutex);
3590 i915_gem_switch_to_kernel_context(dev_priv);
3591 mutex_unlock(&dev_priv->drm.struct_mutex);
3593 GEM_TRACE("active_requests=%d (after switch-to-kernel-context)\n",
3594 READ_ONCE(dev_priv->gt.active_requests));
3597 * Wait for last execlists context complete, but bail out in case a
3598 * new request is submitted. As we don't trust the hardware, we
3599 * continue on if the wait times out. This is necessary to allow
3600 * the machine to suspend even if the hardware dies, and we will
3601 * try to recover in resume (after depriving the hardware of power,
3602 * it may be in a better mmod).
3604 __wait_for(if (new_requests_since_last_retire(dev_priv)) return,
3605 intel_engines_are_idle(dev_priv),
3606 I915_IDLE_ENGINES_TIMEOUT * 1000,
3610 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
3612 if (!mutex_trylock(&dev_priv->drm.struct_mutex)) {
3613 /* Currently busy, come back later */
3614 mod_delayed_work(dev_priv->wq,
3615 &dev_priv->gt.idle_work,
3616 msecs_to_jiffies(50));
3621 * New request retired after this work handler started, extend active
3622 * period until next instance of the work.
3624 if (new_requests_since_last_retire(dev_priv))
3627 epoch = __i915_gem_park(dev_priv);
3629 assert_kernel_context_is_current(dev_priv);
3631 rearm_hangcheck = false;
3633 mutex_unlock(&dev_priv->drm.struct_mutex);
3636 if (rearm_hangcheck) {
3637 GEM_BUG_ON(!dev_priv->gt.awake);
3638 i915_queue_hangcheck(dev_priv);
3642 * When we are idle, it is an opportune time to reap our caches.
3643 * However, we have many objects that utilise RCU and the ordered
3644 * i915->wq that this work is executing on. To try and flush any
3645 * pending frees now we are idle, we first wait for an RCU grace
3646 * period, and then queue a task (that will run last on the wq) to
3647 * shrink and re-optimize the caches.
3649 if (same_epoch(dev_priv, epoch)) {
3650 struct sleep_rcu_work *s = kmalloc(sizeof(*s), GFP_KERNEL);
3654 call_rcu(&s->rcu, __sleep_rcu);
3659 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3661 struct drm_i915_private *i915 = to_i915(gem->dev);
3662 struct drm_i915_gem_object *obj = to_intel_bo(gem);
3663 struct drm_i915_file_private *fpriv = file->driver_priv;
3664 struct i915_lut_handle *lut, *ln;
3666 mutex_lock(&i915->drm.struct_mutex);
3668 list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) {
3669 struct i915_gem_context *ctx = lut->ctx;
3670 struct i915_vma *vma;
3672 GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF));
3673 if (ctx->file_priv != fpriv)
3676 vma = radix_tree_delete(&ctx->handles_vma, lut->handle);
3677 GEM_BUG_ON(vma->obj != obj);
3679 /* We allow the process to have multiple handles to the same
3680 * vma, in the same fd namespace, by virtue of flink/open.
3682 GEM_BUG_ON(!vma->open_count);
3683 if (!--vma->open_count && !i915_vma_is_ggtt(vma))
3684 i915_vma_close(vma);
3686 list_del(&lut->obj_link);
3687 list_del(&lut->ctx_link);
3689 kmem_cache_free(i915->luts, lut);
3690 __i915_gem_object_release_unless_active(obj);
3693 mutex_unlock(&i915->drm.struct_mutex);
3696 static unsigned long to_wait_timeout(s64 timeout_ns)
3699 return MAX_SCHEDULE_TIMEOUT;
3701 if (timeout_ns == 0)
3704 return nsecs_to_jiffies_timeout(timeout_ns);
3708 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3709 * @dev: drm device pointer
3710 * @data: ioctl data blob
3711 * @file: drm file pointer
3713 * Returns 0 if successful, else an error is returned with the remaining time in
3714 * the timeout parameter.
3715 * -ETIME: object is still busy after timeout
3716 * -ERESTARTSYS: signal interrupted the wait
3717 * -ENONENT: object doesn't exist
3718 * Also possible, but rare:
3719 * -EAGAIN: incomplete, restart syscall
3721 * -ENODEV: Internal IRQ fail
3722 * -E?: The add request failed
3724 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3725 * non-zero timeout parameter the wait ioctl will wait for the given number of
3726 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3727 * without holding struct_mutex the object may become re-busied before this
3728 * function completes. A similar but shorter * race condition exists in the busy
3732 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3734 struct drm_i915_gem_wait *args = data;
3735 struct drm_i915_gem_object *obj;
3739 if (args->flags != 0)
3742 obj = i915_gem_object_lookup(file, args->bo_handle);
3746 start = ktime_get();
3748 ret = i915_gem_object_wait(obj,
3749 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3750 to_wait_timeout(args->timeout_ns),
3751 to_rps_client(file));
3753 if (args->timeout_ns > 0) {
3754 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3755 if (args->timeout_ns < 0)
3756 args->timeout_ns = 0;
3759 * Apparently ktime isn't accurate enough and occasionally has a
3760 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3761 * things up to make the test happy. We allow up to 1 jiffy.
3763 * This is a regression from the timespec->ktime conversion.
3765 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3766 args->timeout_ns = 0;
3768 /* Asked to wait beyond the jiffie/scheduler precision? */
3769 if (ret == -ETIME && args->timeout_ns)
3773 i915_gem_object_put(obj);
3777 static long wait_for_timeline(struct i915_timeline *tl,
3778 unsigned int flags, long timeout)
3780 struct i915_request *rq;
3782 rq = i915_gem_active_get_unlocked(&tl->last_request);
3789 * Switching to the kernel context is often used a synchronous
3790 * step prior to idling, e.g. in suspend for flushing all
3791 * current operations to memory before sleeping. These we
3792 * want to complete as quickly as possible to avoid prolonged
3793 * stalls, so allow the gpu to boost to maximum clocks.
3795 if (flags & I915_WAIT_FOR_IDLE_BOOST)
3796 gen6_rps_boost(rq, NULL);
3798 timeout = i915_request_wait(rq, flags, timeout);
3799 i915_request_put(rq);
3804 static int wait_for_engines(struct drm_i915_private *i915)
3806 if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) {
3807 dev_err(i915->drm.dev,
3808 "Failed to idle engines, declaring wedged!\n");
3810 i915_gem_set_wedged(i915);
3817 int i915_gem_wait_for_idle(struct drm_i915_private *i915,
3818 unsigned int flags, long timeout)
3820 GEM_TRACE("flags=%x (%s), timeout=%ld%s\n",
3821 flags, flags & I915_WAIT_LOCKED ? "locked" : "unlocked",
3822 timeout, timeout == MAX_SCHEDULE_TIMEOUT ? " (forever)" : "");
3824 /* If the device is asleep, we have no requests outstanding */
3825 if (!READ_ONCE(i915->gt.awake))
3828 if (flags & I915_WAIT_LOCKED) {
3829 struct i915_timeline *tl;
3832 lockdep_assert_held(&i915->drm.struct_mutex);
3834 list_for_each_entry(tl, &i915->gt.timelines, link) {
3835 timeout = wait_for_timeline(tl, flags, timeout);
3839 if (GEM_SHOW_DEBUG() && !timeout) {
3840 /* Presume that timeout was non-zero to begin with! */
3841 dev_warn(&i915->drm.pdev->dev,
3842 "Missed idle-completion interrupt!\n");
3846 err = wait_for_engines(i915);
3850 i915_retire_requests(i915);
3851 GEM_BUG_ON(i915->gt.active_requests);
3853 struct intel_engine_cs *engine;
3854 enum intel_engine_id id;
3856 for_each_engine(engine, i915, id) {
3857 struct i915_timeline *tl = &engine->timeline;
3859 timeout = wait_for_timeline(tl, flags, timeout);
3868 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
3871 * We manually flush the CPU domain so that we can override and
3872 * force the flush for the display, and perform it asyncrhonously.
3874 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3875 if (obj->cache_dirty)
3876 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
3877 obj->write_domain = 0;
3880 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
3882 if (!READ_ONCE(obj->pin_global))
3885 mutex_lock(&obj->base.dev->struct_mutex);
3886 __i915_gem_object_flush_for_display(obj);
3887 mutex_unlock(&obj->base.dev->struct_mutex);
3891 * Moves a single object to the WC read, and possibly write domain.
3892 * @obj: object to act on
3893 * @write: ask for write access or read only
3895 * This function returns when the move is complete, including waiting on
3899 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
3903 lockdep_assert_held(&obj->base.dev->struct_mutex);
3905 ret = i915_gem_object_wait(obj,
3906 I915_WAIT_INTERRUPTIBLE |
3908 (write ? I915_WAIT_ALL : 0),
3909 MAX_SCHEDULE_TIMEOUT,
3914 if (obj->write_domain == I915_GEM_DOMAIN_WC)
3917 /* Flush and acquire obj->pages so that we are coherent through
3918 * direct access in memory with previous cached writes through
3919 * shmemfs and that our cache domain tracking remains valid.
3920 * For example, if the obj->filp was moved to swap without us
3921 * being notified and releasing the pages, we would mistakenly
3922 * continue to assume that the obj remained out of the CPU cached
3925 ret = i915_gem_object_pin_pages(obj);
3929 flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
3931 /* Serialise direct access to this object with the barriers for
3932 * coherent writes from the GPU, by effectively invalidating the
3933 * WC domain upon first access.
3935 if ((obj->read_domains & I915_GEM_DOMAIN_WC) == 0)
3938 /* It should now be out of any other write domains, and we can update
3939 * the domain values for our changes.
3941 GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_WC) != 0);
3942 obj->read_domains |= I915_GEM_DOMAIN_WC;
3944 obj->read_domains = I915_GEM_DOMAIN_WC;
3945 obj->write_domain = I915_GEM_DOMAIN_WC;
3946 obj->mm.dirty = true;
3949 i915_gem_object_unpin_pages(obj);
3954 * Moves a single object to the GTT read, and possibly write domain.
3955 * @obj: object to act on
3956 * @write: ask for write access or read only
3958 * This function returns when the move is complete, including waiting on
3962 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3966 lockdep_assert_held(&obj->base.dev->struct_mutex);
3968 ret = i915_gem_object_wait(obj,
3969 I915_WAIT_INTERRUPTIBLE |
3971 (write ? I915_WAIT_ALL : 0),
3972 MAX_SCHEDULE_TIMEOUT,
3977 if (obj->write_domain == I915_GEM_DOMAIN_GTT)
3980 /* Flush and acquire obj->pages so that we are coherent through
3981 * direct access in memory with previous cached writes through
3982 * shmemfs and that our cache domain tracking remains valid.
3983 * For example, if the obj->filp was moved to swap without us
3984 * being notified and releasing the pages, we would mistakenly
3985 * continue to assume that the obj remained out of the CPU cached
3988 ret = i915_gem_object_pin_pages(obj);
3992 flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
3994 /* Serialise direct access to this object with the barriers for
3995 * coherent writes from the GPU, by effectively invalidating the
3996 * GTT domain upon first access.
3998 if ((obj->read_domains & I915_GEM_DOMAIN_GTT) == 0)
4001 /* It should now be out of any other write domains, and we can update
4002 * the domain values for our changes.
4004 GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
4005 obj->read_domains |= I915_GEM_DOMAIN_GTT;
4007 obj->read_domains = I915_GEM_DOMAIN_GTT;
4008 obj->write_domain = I915_GEM_DOMAIN_GTT;
4009 obj->mm.dirty = true;
4012 i915_gem_object_unpin_pages(obj);
4017 * Changes the cache-level of an object across all VMA.
4018 * @obj: object to act on
4019 * @cache_level: new cache level to set for the object
4021 * After this function returns, the object will be in the new cache-level
4022 * across all GTT and the contents of the backing storage will be coherent,
4023 * with respect to the new cache-level. In order to keep the backing storage
4024 * coherent for all users, we only allow a single cache level to be set
4025 * globally on the object and prevent it from being changed whilst the
4026 * hardware is reading from the object. That is if the object is currently
4027 * on the scanout it will be set to uncached (or equivalent display
4028 * cache coherency) and all non-MOCS GPU access will also be uncached so
4029 * that all direct access to the scanout remains coherent.
4031 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
4032 enum i915_cache_level cache_level)
4034 struct i915_vma *vma;
4037 lockdep_assert_held(&obj->base.dev->struct_mutex);
4039 if (obj->cache_level == cache_level)
4042 /* Inspect the list of currently bound VMA and unbind any that would
4043 * be invalid given the new cache-level. This is principally to
4044 * catch the issue of the CS prefetch crossing page boundaries and
4045 * reading an invalid PTE on older architectures.
4048 list_for_each_entry(vma, &obj->vma_list, obj_link) {
4049 if (!drm_mm_node_allocated(&vma->node))
4052 if (i915_vma_is_pinned(vma)) {
4053 DRM_DEBUG("can not change the cache level of pinned objects\n");
4057 if (!i915_vma_is_closed(vma) &&
4058 i915_gem_valid_gtt_space(vma, cache_level))
4061 ret = i915_vma_unbind(vma);
4065 /* As unbinding may affect other elements in the
4066 * obj->vma_list (due to side-effects from retiring
4067 * an active vma), play safe and restart the iterator.
4072 /* We can reuse the existing drm_mm nodes but need to change the
4073 * cache-level on the PTE. We could simply unbind them all and
4074 * rebind with the correct cache-level on next use. However since
4075 * we already have a valid slot, dma mapping, pages etc, we may as
4076 * rewrite the PTE in the belief that doing so tramples upon less
4077 * state and so involves less work.
4079 if (obj->bind_count) {
4080 /* Before we change the PTE, the GPU must not be accessing it.
4081 * If we wait upon the object, we know that all the bound
4082 * VMA are no longer active.
4084 ret = i915_gem_object_wait(obj,
4085 I915_WAIT_INTERRUPTIBLE |
4088 MAX_SCHEDULE_TIMEOUT,
4093 if (!HAS_LLC(to_i915(obj->base.dev)) &&
4094 cache_level != I915_CACHE_NONE) {
4095 /* Access to snoopable pages through the GTT is
4096 * incoherent and on some machines causes a hard
4097 * lockup. Relinquish the CPU mmaping to force
4098 * userspace to refault in the pages and we can
4099 * then double check if the GTT mapping is still
4100 * valid for that pointer access.
4102 i915_gem_release_mmap(obj);
4104 /* As we no longer need a fence for GTT access,
4105 * we can relinquish it now (and so prevent having
4106 * to steal a fence from someone else on the next
4107 * fence request). Note GPU activity would have
4108 * dropped the fence as all snoopable access is
4109 * supposed to be linear.
4111 for_each_ggtt_vma(vma, obj) {
4112 ret = i915_vma_put_fence(vma);
4117 /* We either have incoherent backing store and
4118 * so no GTT access or the architecture is fully
4119 * coherent. In such cases, existing GTT mmaps
4120 * ignore the cache bit in the PTE and we can
4121 * rewrite it without confusing the GPU or having
4122 * to force userspace to fault back in its mmaps.
4126 list_for_each_entry(vma, &obj->vma_list, obj_link) {
4127 if (!drm_mm_node_allocated(&vma->node))
4130 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
4136 list_for_each_entry(vma, &obj->vma_list, obj_link)
4137 vma->node.color = cache_level;
4138 i915_gem_object_set_cache_coherency(obj, cache_level);
4139 obj->cache_dirty = true; /* Always invalidate stale cachelines */
4144 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
4145 struct drm_file *file)
4147 struct drm_i915_gem_caching *args = data;
4148 struct drm_i915_gem_object *obj;
4152 obj = i915_gem_object_lookup_rcu(file, args->handle);
4158 switch (obj->cache_level) {
4159 case I915_CACHE_LLC:
4160 case I915_CACHE_L3_LLC:
4161 args->caching = I915_CACHING_CACHED;
4165 args->caching = I915_CACHING_DISPLAY;
4169 args->caching = I915_CACHING_NONE;
4177 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
4178 struct drm_file *file)
4180 struct drm_i915_private *i915 = to_i915(dev);
4181 struct drm_i915_gem_caching *args = data;
4182 struct drm_i915_gem_object *obj;
4183 enum i915_cache_level level;
4186 switch (args->caching) {
4187 case I915_CACHING_NONE:
4188 level = I915_CACHE_NONE;
4190 case I915_CACHING_CACHED:
4192 * Due to a HW issue on BXT A stepping, GPU stores via a
4193 * snooped mapping may leave stale data in a corresponding CPU
4194 * cacheline, whereas normally such cachelines would get
4197 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
4200 level = I915_CACHE_LLC;
4202 case I915_CACHING_DISPLAY:
4203 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
4209 obj = i915_gem_object_lookup(file, args->handle);
4214 * The caching mode of proxy object is handled by its generator, and
4215 * not allowed to be changed by userspace.
4217 if (i915_gem_object_is_proxy(obj)) {
4222 if (obj->cache_level == level)
4225 ret = i915_gem_object_wait(obj,
4226 I915_WAIT_INTERRUPTIBLE,
4227 MAX_SCHEDULE_TIMEOUT,
4228 to_rps_client(file));
4232 ret = i915_mutex_lock_interruptible(dev);
4236 ret = i915_gem_object_set_cache_level(obj, level);
4237 mutex_unlock(&dev->struct_mutex);
4240 i915_gem_object_put(obj);
4245 * Prepare buffer for display plane (scanout, cursors, etc). Can be called from
4246 * an uninterruptible phase (modesetting) and allows any flushes to be pipelined
4247 * (for pageflips). We only flush the caches while preparing the buffer for
4248 * display, the callers are responsible for frontbuffer flush.
4251 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4253 const struct i915_ggtt_view *view,
4256 struct i915_vma *vma;
4259 lockdep_assert_held(&obj->base.dev->struct_mutex);
4261 /* Mark the global pin early so that we account for the
4262 * display coherency whilst setting up the cache domains.
4266 /* The display engine is not coherent with the LLC cache on gen6. As
4267 * a result, we make sure that the pinning that is about to occur is
4268 * done with uncached PTEs. This is lowest common denominator for all
4271 * However for gen6+, we could do better by using the GFDT bit instead
4272 * of uncaching, which would allow us to flush all the LLC-cached data
4273 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4275 ret = i915_gem_object_set_cache_level(obj,
4276 HAS_WT(to_i915(obj->base.dev)) ?
4277 I915_CACHE_WT : I915_CACHE_NONE);
4280 goto err_unpin_global;
4283 /* As the user may map the buffer once pinned in the display plane
4284 * (e.g. libkms for the bootup splash), we have to ensure that we
4285 * always use map_and_fenceable for all scanout buffers. However,
4286 * it may simply be too big to fit into mappable, in which case
4287 * put it anyway and hope that userspace can cope (but always first
4288 * try to preserve the existing ABI).
4290 vma = ERR_PTR(-ENOSPC);
4291 if ((flags & PIN_MAPPABLE) == 0 &&
4292 (!view || view->type == I915_GGTT_VIEW_NORMAL))
4293 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
4298 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
4300 goto err_unpin_global;
4302 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
4304 __i915_gem_object_flush_for_display(obj);
4306 /* It should now be out of any other write domains, and we can update
4307 * the domain values for our changes.
4309 obj->read_domains |= I915_GEM_DOMAIN_GTT;
4319 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
4321 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
4323 if (WARN_ON(vma->obj->pin_global == 0))
4326 if (--vma->obj->pin_global == 0)
4327 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
4329 /* Bump the LRU to try and avoid premature eviction whilst flipping */
4330 i915_gem_object_bump_inactive_ggtt(vma->obj);
4332 i915_vma_unpin(vma);
4336 * Moves a single object to the CPU read, and possibly write domain.
4337 * @obj: object to act on
4338 * @write: requesting write or read-only access
4340 * This function returns when the move is complete, including waiting on
4344 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4348 lockdep_assert_held(&obj->base.dev->struct_mutex);
4350 ret = i915_gem_object_wait(obj,
4351 I915_WAIT_INTERRUPTIBLE |
4353 (write ? I915_WAIT_ALL : 0),
4354 MAX_SCHEDULE_TIMEOUT,
4359 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
4361 /* Flush the CPU cache if it's still invalid. */
4362 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4363 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
4364 obj->read_domains |= I915_GEM_DOMAIN_CPU;
4367 /* It should now be out of any other write domains, and we can update
4368 * the domain values for our changes.
4370 GEM_BUG_ON(obj->write_domain & ~I915_GEM_DOMAIN_CPU);
4372 /* If we're writing through the CPU, then the GPU read domains will
4373 * need to be invalidated at next use.
4376 __start_cpu_write(obj);
4381 /* Throttle our rendering by waiting until the ring has completed our requests
4382 * emitted over 20 msec ago.
4384 * Note that if we were to use the current jiffies each time around the loop,
4385 * we wouldn't escape the function with any frames outstanding if the time to
4386 * render a frame was over 20ms.
4388 * This should get us reasonable parallelism between CPU and GPU but also
4389 * relatively low latency when blocking on a particular request to finish.
4392 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4394 struct drm_i915_private *dev_priv = to_i915(dev);
4395 struct drm_i915_file_private *file_priv = file->driver_priv;
4396 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4397 struct i915_request *request, *target = NULL;
4400 /* ABI: return -EIO if already wedged */
4401 if (i915_terminally_wedged(&dev_priv->gpu_error))
4404 spin_lock(&file_priv->mm.lock);
4405 list_for_each_entry(request, &file_priv->mm.request_list, client_link) {
4406 if (time_after_eq(request->emitted_jiffies, recent_enough))
4410 list_del(&target->client_link);
4411 target->file_priv = NULL;
4417 i915_request_get(target);
4418 spin_unlock(&file_priv->mm.lock);
4423 ret = i915_request_wait(target,
4424 I915_WAIT_INTERRUPTIBLE,
4425 MAX_SCHEDULE_TIMEOUT);
4426 i915_request_put(target);
4428 return ret < 0 ? ret : 0;
4432 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4433 const struct i915_ggtt_view *view,
4438 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
4439 struct i915_address_space *vm = &dev_priv->ggtt.vm;
4440 struct i915_vma *vma;
4443 lockdep_assert_held(&obj->base.dev->struct_mutex);
4445 if (flags & PIN_MAPPABLE &&
4446 (!view || view->type == I915_GGTT_VIEW_NORMAL)) {
4447 /* If the required space is larger than the available
4448 * aperture, we will not able to find a slot for the
4449 * object and unbinding the object now will be in
4450 * vain. Worse, doing so may cause us to ping-pong
4451 * the object in and out of the Global GTT and
4452 * waste a lot of cycles under the mutex.
4454 if (obj->base.size > dev_priv->ggtt.mappable_end)
4455 return ERR_PTR(-E2BIG);
4457 /* If NONBLOCK is set the caller is optimistically
4458 * trying to cache the full object within the mappable
4459 * aperture, and *must* have a fallback in place for
4460 * situations where we cannot bind the object. We
4461 * can be a little more lax here and use the fallback
4462 * more often to avoid costly migrations of ourselves
4463 * and other objects within the aperture.
4465 * Half-the-aperture is used as a simple heuristic.
4466 * More interesting would to do search for a free
4467 * block prior to making the commitment to unbind.
4468 * That caters for the self-harm case, and with a
4469 * little more heuristics (e.g. NOFAULT, NOEVICT)
4470 * we could try to minimise harm to others.
4472 if (flags & PIN_NONBLOCK &&
4473 obj->base.size > dev_priv->ggtt.mappable_end / 2)
4474 return ERR_PTR(-ENOSPC);
4477 vma = i915_vma_instance(obj, vm, view);
4478 if (unlikely(IS_ERR(vma)))
4481 if (i915_vma_misplaced(vma, size, alignment, flags)) {
4482 if (flags & PIN_NONBLOCK) {
4483 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))
4484 return ERR_PTR(-ENOSPC);
4486 if (flags & PIN_MAPPABLE &&
4487 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
4488 return ERR_PTR(-ENOSPC);
4491 WARN(i915_vma_is_pinned(vma),
4492 "bo is already pinned in ggtt with incorrect alignment:"
4493 " offset=%08x, req.alignment=%llx,"
4494 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
4495 i915_ggtt_offset(vma), alignment,
4496 !!(flags & PIN_MAPPABLE),
4497 i915_vma_is_map_and_fenceable(vma));
4498 ret = i915_vma_unbind(vma);
4500 return ERR_PTR(ret);
4503 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
4505 return ERR_PTR(ret);
4510 static __always_inline unsigned int __busy_read_flag(unsigned int id)
4512 /* Note that we could alias engines in the execbuf API, but
4513 * that would be very unwise as it prevents userspace from
4514 * fine control over engine selection. Ahem.
4516 * This should be something like EXEC_MAX_ENGINE instead of
4519 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
4520 return 0x10000 << id;
4523 static __always_inline unsigned int __busy_write_id(unsigned int id)
4525 /* The uABI guarantees an active writer is also amongst the read
4526 * engines. This would be true if we accessed the activity tracking
4527 * under the lock, but as we perform the lookup of the object and
4528 * its activity locklessly we can not guarantee that the last_write
4529 * being active implies that we have set the same engine flag from
4530 * last_read - hence we always set both read and write busy for
4533 return id | __busy_read_flag(id);
4536 static __always_inline unsigned int
4537 __busy_set_if_active(const struct dma_fence *fence,
4538 unsigned int (*flag)(unsigned int id))
4540 struct i915_request *rq;
4542 /* We have to check the current hw status of the fence as the uABI
4543 * guarantees forward progress. We could rely on the idle worker
4544 * to eventually flush us, but to minimise latency just ask the
4547 * Note we only report on the status of native fences.
4549 if (!dma_fence_is_i915(fence))
4552 /* opencode to_request() in order to avoid const warnings */
4553 rq = container_of(fence, struct i915_request, fence);
4554 if (i915_request_completed(rq))
4557 return flag(rq->engine->uabi_id);
4560 static __always_inline unsigned int
4561 busy_check_reader(const struct dma_fence *fence)
4563 return __busy_set_if_active(fence, __busy_read_flag);
4566 static __always_inline unsigned int
4567 busy_check_writer(const struct dma_fence *fence)
4572 return __busy_set_if_active(fence, __busy_write_id);
4576 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4577 struct drm_file *file)
4579 struct drm_i915_gem_busy *args = data;
4580 struct drm_i915_gem_object *obj;
4581 struct reservation_object_list *list;
4587 obj = i915_gem_object_lookup_rcu(file, args->handle);
4591 /* A discrepancy here is that we do not report the status of
4592 * non-i915 fences, i.e. even though we may report the object as idle,
4593 * a call to set-domain may still stall waiting for foreign rendering.
4594 * This also means that wait-ioctl may report an object as busy,
4595 * where busy-ioctl considers it idle.
4597 * We trade the ability to warn of foreign fences to report on which
4598 * i915 engines are active for the object.
4600 * Alternatively, we can trade that extra information on read/write
4603 * !reservation_object_test_signaled_rcu(obj->resv, true);
4604 * to report the overall busyness. This is what the wait-ioctl does.
4608 seq = raw_read_seqcount(&obj->resv->seq);
4610 /* Translate the exclusive fence to the READ *and* WRITE engine */
4611 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
4613 /* Translate shared fences to READ set of engines */
4614 list = rcu_dereference(obj->resv->fence);
4616 unsigned int shared_count = list->shared_count, i;
4618 for (i = 0; i < shared_count; ++i) {
4619 struct dma_fence *fence =
4620 rcu_dereference(list->shared[i]);
4622 args->busy |= busy_check_reader(fence);
4626 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
4636 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4637 struct drm_file *file_priv)
4639 return i915_gem_ring_throttle(dev, file_priv);
4643 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4644 struct drm_file *file_priv)
4646 struct drm_i915_private *dev_priv = to_i915(dev);
4647 struct drm_i915_gem_madvise *args = data;
4648 struct drm_i915_gem_object *obj;
4651 switch (args->madv) {
4652 case I915_MADV_DONTNEED:
4653 case I915_MADV_WILLNEED:
4659 obj = i915_gem_object_lookup(file_priv, args->handle);
4663 err = mutex_lock_interruptible(&obj->mm.lock);
4667 if (i915_gem_object_has_pages(obj) &&
4668 i915_gem_object_is_tiled(obj) &&
4669 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4670 if (obj->mm.madv == I915_MADV_WILLNEED) {
4671 GEM_BUG_ON(!obj->mm.quirked);
4672 __i915_gem_object_unpin_pages(obj);
4673 obj->mm.quirked = false;
4675 if (args->madv == I915_MADV_WILLNEED) {
4676 GEM_BUG_ON(obj->mm.quirked);
4677 __i915_gem_object_pin_pages(obj);
4678 obj->mm.quirked = true;
4682 if (obj->mm.madv != __I915_MADV_PURGED)
4683 obj->mm.madv = args->madv;
4685 /* if the object is no longer attached, discard its backing storage */
4686 if (obj->mm.madv == I915_MADV_DONTNEED &&
4687 !i915_gem_object_has_pages(obj))
4688 i915_gem_object_truncate(obj);
4690 args->retained = obj->mm.madv != __I915_MADV_PURGED;
4691 mutex_unlock(&obj->mm.lock);
4694 i915_gem_object_put(obj);
4699 frontbuffer_retire(struct i915_gem_active *active, struct i915_request *request)
4701 struct drm_i915_gem_object *obj =
4702 container_of(active, typeof(*obj), frontbuffer_write);
4704 intel_fb_obj_flush(obj, ORIGIN_CS);
4707 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4708 const struct drm_i915_gem_object_ops *ops)
4710 mutex_init(&obj->mm.lock);
4712 INIT_LIST_HEAD(&obj->vma_list);
4713 INIT_LIST_HEAD(&obj->lut_list);
4714 INIT_LIST_HEAD(&obj->batch_pool_link);
4718 reservation_object_init(&obj->__builtin_resv);
4719 obj->resv = &obj->__builtin_resv;
4721 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4722 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
4724 obj->mm.madv = I915_MADV_WILLNEED;
4725 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4726 mutex_init(&obj->mm.get_page.lock);
4728 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4731 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4732 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4733 I915_GEM_OBJECT_IS_SHRINKABLE,
4735 .get_pages = i915_gem_object_get_pages_gtt,
4736 .put_pages = i915_gem_object_put_pages_gtt,
4738 .pwrite = i915_gem_object_pwrite_gtt,
4741 static int i915_gem_object_create_shmem(struct drm_device *dev,
4742 struct drm_gem_object *obj,
4745 struct drm_i915_private *i915 = to_i915(dev);
4746 unsigned long flags = VM_NORESERVE;
4749 drm_gem_private_object_init(dev, obj, size);
4752 filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size,
4755 filp = shmem_file_setup("i915", size, flags);
4758 return PTR_ERR(filp);
4765 struct drm_i915_gem_object *
4766 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4768 struct drm_i915_gem_object *obj;
4769 struct address_space *mapping;
4770 unsigned int cache_level;
4774 /* There is a prevalence of the assumption that we fit the object's
4775 * page count inside a 32bit _signed_ variable. Let's document this and
4776 * catch if we ever need to fix it. In the meantime, if you do spot
4777 * such a local variable, please consider fixing!
4779 if (size >> PAGE_SHIFT > INT_MAX)
4780 return ERR_PTR(-E2BIG);
4782 if (overflows_type(size, obj->base.size))
4783 return ERR_PTR(-E2BIG);
4785 obj = i915_gem_object_alloc(dev_priv);
4787 return ERR_PTR(-ENOMEM);
4789 ret = i915_gem_object_create_shmem(&dev_priv->drm, &obj->base, size);
4793 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4794 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4795 /* 965gm cannot relocate objects above 4GiB. */
4796 mask &= ~__GFP_HIGHMEM;
4797 mask |= __GFP_DMA32;
4800 mapping = obj->base.filp->f_mapping;
4801 mapping_set_gfp_mask(mapping, mask);
4802 GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
4804 i915_gem_object_init(obj, &i915_gem_object_ops);
4806 obj->write_domain = I915_GEM_DOMAIN_CPU;
4807 obj->read_domains = I915_GEM_DOMAIN_CPU;
4809 if (HAS_LLC(dev_priv))
4810 /* On some devices, we can have the GPU use the LLC (the CPU
4811 * cache) for about a 10% performance improvement
4812 * compared to uncached. Graphics requests other than
4813 * display scanout are coherent with the CPU in
4814 * accessing this cache. This means in this mode we
4815 * don't need to clflush on the CPU side, and on the
4816 * GPU side we only need to flush internal caches to
4817 * get data visible to the CPU.
4819 * However, we maintain the display planes as UC, and so
4820 * need to rebind when first used as such.
4822 cache_level = I915_CACHE_LLC;
4824 cache_level = I915_CACHE_NONE;
4826 i915_gem_object_set_cache_coherency(obj, cache_level);
4828 trace_i915_gem_object_create(obj);
4833 i915_gem_object_free(obj);
4834 return ERR_PTR(ret);
4837 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4839 /* If we are the last user of the backing storage (be it shmemfs
4840 * pages or stolen etc), we know that the pages are going to be
4841 * immediately released. In this case, we can then skip copying
4842 * back the contents from the GPU.
4845 if (obj->mm.madv != I915_MADV_WILLNEED)
4848 if (obj->base.filp == NULL)
4851 /* At first glance, this looks racy, but then again so would be
4852 * userspace racing mmap against close. However, the first external
4853 * reference to the filp can only be obtained through the
4854 * i915_gem_mmap_ioctl() which safeguards us against the user
4855 * acquiring such a reference whilst we are in the middle of
4856 * freeing the object.
4858 return atomic_long_read(&obj->base.filp->f_count) == 1;
4861 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4862 struct llist_node *freed)
4864 struct drm_i915_gem_object *obj, *on;
4866 intel_runtime_pm_get(i915);
4867 llist_for_each_entry_safe(obj, on, freed, freed) {
4868 struct i915_vma *vma, *vn;
4870 trace_i915_gem_object_destroy(obj);
4872 mutex_lock(&i915->drm.struct_mutex);
4874 GEM_BUG_ON(i915_gem_object_is_active(obj));
4875 list_for_each_entry_safe(vma, vn,
4876 &obj->vma_list, obj_link) {
4877 GEM_BUG_ON(i915_vma_is_active(vma));
4878 vma->flags &= ~I915_VMA_PIN_MASK;
4879 i915_vma_destroy(vma);
4881 GEM_BUG_ON(!list_empty(&obj->vma_list));
4882 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4884 /* This serializes freeing with the shrinker. Since the free
4885 * is delayed, first by RCU then by the workqueue, we want the
4886 * shrinker to be able to free pages of unreferenced objects,
4887 * or else we may oom whilst there are plenty of deferred
4890 if (i915_gem_object_has_pages(obj)) {
4891 spin_lock(&i915->mm.obj_lock);
4892 list_del_init(&obj->mm.link);
4893 spin_unlock(&i915->mm.obj_lock);
4896 mutex_unlock(&i915->drm.struct_mutex);
4898 GEM_BUG_ON(obj->bind_count);
4899 GEM_BUG_ON(obj->userfault_count);
4900 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4901 GEM_BUG_ON(!list_empty(&obj->lut_list));
4903 if (obj->ops->release)
4904 obj->ops->release(obj);
4906 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4907 atomic_set(&obj->mm.pages_pin_count, 0);
4908 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4909 GEM_BUG_ON(i915_gem_object_has_pages(obj));
4911 if (obj->base.import_attach)
4912 drm_prime_gem_destroy(&obj->base, NULL);
4914 reservation_object_fini(&obj->__builtin_resv);
4915 drm_gem_object_release(&obj->base);
4916 i915_gem_info_remove_obj(i915, obj->base.size);
4919 i915_gem_object_free(obj);
4921 GEM_BUG_ON(!atomic_read(&i915->mm.free_count));
4922 atomic_dec(&i915->mm.free_count);
4927 intel_runtime_pm_put(i915);
4930 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4932 struct llist_node *freed;
4934 /* Free the oldest, most stale object to keep the free_list short */
4936 if (!llist_empty(&i915->mm.free_list)) { /* quick test for hotpath */
4937 /* Only one consumer of llist_del_first() allowed */
4938 spin_lock(&i915->mm.free_lock);
4939 freed = llist_del_first(&i915->mm.free_list);
4940 spin_unlock(&i915->mm.free_lock);
4942 if (unlikely(freed)) {
4944 __i915_gem_free_objects(i915, freed);
4948 static void __i915_gem_free_work(struct work_struct *work)
4950 struct drm_i915_private *i915 =
4951 container_of(work, struct drm_i915_private, mm.free_work);
4952 struct llist_node *freed;
4955 * All file-owned VMA should have been released by this point through
4956 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4957 * However, the object may also be bound into the global GTT (e.g.
4958 * older GPUs without per-process support, or for direct access through
4959 * the GTT either for the user or for scanout). Those VMA still need to
4963 spin_lock(&i915->mm.free_lock);
4964 while ((freed = llist_del_all(&i915->mm.free_list))) {
4965 spin_unlock(&i915->mm.free_lock);
4967 __i915_gem_free_objects(i915, freed);
4971 spin_lock(&i915->mm.free_lock);
4973 spin_unlock(&i915->mm.free_lock);
4976 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4978 struct drm_i915_gem_object *obj =
4979 container_of(head, typeof(*obj), rcu);
4980 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4983 * Since we require blocking on struct_mutex to unbind the freed
4984 * object from the GPU before releasing resources back to the
4985 * system, we can not do that directly from the RCU callback (which may
4986 * be a softirq context), but must instead then defer that work onto a
4987 * kthread. We use the RCU callback rather than move the freed object
4988 * directly onto the work queue so that we can mix between using the
4989 * worker and performing frees directly from subsequent allocations for
4990 * crude but effective memory throttling.
4992 if (llist_add(&obj->freed, &i915->mm.free_list))
4993 queue_work(i915->wq, &i915->mm.free_work);
4996 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4998 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
5000 if (obj->mm.quirked)
5001 __i915_gem_object_unpin_pages(obj);
5003 if (discard_backing_storage(obj))
5004 obj->mm.madv = I915_MADV_DONTNEED;
5007 * Before we free the object, make sure any pure RCU-only
5008 * read-side critical sections are complete, e.g.
5009 * i915_gem_busy_ioctl(). For the corresponding synchronized
5010 * lookup see i915_gem_object_lookup_rcu().
5012 atomic_inc(&to_i915(obj->base.dev)->mm.free_count);
5013 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
5016 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
5018 lockdep_assert_held(&obj->base.dev->struct_mutex);
5020 if (!i915_gem_object_has_active_reference(obj) &&
5021 i915_gem_object_is_active(obj))
5022 i915_gem_object_set_active_reference(obj);
5024 i915_gem_object_put(obj);
5027 void i915_gem_sanitize(struct drm_i915_private *i915)
5033 mutex_lock(&i915->drm.struct_mutex);
5035 intel_runtime_pm_get(i915);
5036 intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
5039 * As we have just resumed the machine and woken the device up from
5040 * deep PCI sleep (presumably D3_cold), assume the HW has been reset
5041 * back to defaults, recovering from whatever wedged state we left it
5042 * in and so worth trying to use the device once more.
5044 if (i915_terminally_wedged(&i915->gpu_error))
5045 i915_gem_unset_wedged(i915);
5048 * If we inherit context state from the BIOS or earlier occupants
5049 * of the GPU, the GPU may be in an inconsistent state when we
5050 * try to take over. The only way to remove the earlier state
5051 * is by resetting. However, resetting on earlier gen is tricky as
5052 * it may impact the display and we are uncertain about the stability
5053 * of the reset, so this could be applied to even earlier gen.
5056 if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
5057 err = WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
5059 intel_engines_sanitize(i915);
5061 intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
5062 intel_runtime_pm_put(i915);
5064 i915_gem_contexts_lost(i915);
5065 mutex_unlock(&i915->drm.struct_mutex);
5068 int i915_gem_suspend(struct drm_i915_private *i915)
5074 intel_runtime_pm_get(i915);
5075 intel_suspend_gt_powersave(i915);
5077 mutex_lock(&i915->drm.struct_mutex);
5080 * We have to flush all the executing contexts to main memory so
5081 * that they can saved in the hibernation image. To ensure the last
5082 * context image is coherent, we have to switch away from it. That
5083 * leaves the i915->kernel_context still active when
5084 * we actually suspend, and its image in memory may not match the GPU
5085 * state. Fortunately, the kernel_context is disposable and we do
5086 * not rely on its state.
5088 if (!i915_terminally_wedged(&i915->gpu_error)) {
5089 ret = i915_gem_switch_to_kernel_context(i915);
5093 ret = i915_gem_wait_for_idle(i915,
5094 I915_WAIT_INTERRUPTIBLE |
5096 I915_WAIT_FOR_IDLE_BOOST,
5097 MAX_SCHEDULE_TIMEOUT);
5098 if (ret && ret != -EIO)
5101 assert_kernel_context_is_current(i915);
5103 i915_retire_requests(i915); /* ensure we flush after wedging */
5105 mutex_unlock(&i915->drm.struct_mutex);
5107 intel_uc_suspend(i915);
5109 cancel_delayed_work_sync(&i915->gpu_error.hangcheck_work);
5110 cancel_delayed_work_sync(&i915->gt.retire_work);
5113 * As the idle_work is rearming if it detects a race, play safe and
5114 * repeat the flush until it is definitely idle.
5116 drain_delayed_work(&i915->gt.idle_work);
5119 * Assert that we successfully flushed all the work and
5120 * reset the GPU back to its idle, low power state.
5122 WARN_ON(i915->gt.awake);
5123 if (WARN_ON(!intel_engines_are_idle(i915)))
5124 i915_gem_set_wedged(i915); /* no hope, discard everything */
5126 intel_runtime_pm_put(i915);
5130 mutex_unlock(&i915->drm.struct_mutex);
5131 intel_runtime_pm_put(i915);
5135 void i915_gem_suspend_late(struct drm_i915_private *i915)
5137 struct drm_i915_gem_object *obj;
5138 struct list_head *phases[] = {
5139 &i915->mm.unbound_list,
5140 &i915->mm.bound_list,
5145 * Neither the BIOS, ourselves or any other kernel
5146 * expects the system to be in execlists mode on startup,
5147 * so we need to reset the GPU back to legacy mode. And the only
5148 * known way to disable logical contexts is through a GPU reset.
5150 * So in order to leave the system in a known default configuration,
5151 * always reset the GPU upon unload and suspend. Afterwards we then
5152 * clean up the GEM state tracking, flushing off the requests and
5153 * leaving the system in a known idle state.
5155 * Note that is of the upmost importance that the GPU is idle and
5156 * all stray writes are flushed *before* we dismantle the backing
5157 * storage for the pinned objects.
5159 * However, since we are uncertain that resetting the GPU on older
5160 * machines is a good idea, we don't - just in case it leaves the
5161 * machine in an unusable condition.
5164 mutex_lock(&i915->drm.struct_mutex);
5165 for (phase = phases; *phase; phase++) {
5166 list_for_each_entry(obj, *phase, mm.link)
5167 WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
5169 mutex_unlock(&i915->drm.struct_mutex);
5171 intel_uc_sanitize(i915);
5172 i915_gem_sanitize(i915);
5175 void i915_gem_resume(struct drm_i915_private *i915)
5179 WARN_ON(i915->gt.awake);
5181 mutex_lock(&i915->drm.struct_mutex);
5182 intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
5184 i915_gem_restore_gtt_mappings(i915);
5185 i915_gem_restore_fences(i915);
5188 * As we didn't flush the kernel context before suspend, we cannot
5189 * guarantee that the context image is complete. So let's just reset
5190 * it and start again.
5192 i915->gt.resume(i915);
5194 if (i915_gem_init_hw(i915))
5197 intel_uc_resume(i915);
5199 /* Always reload a context for powersaving. */
5200 if (i915_gem_switch_to_kernel_context(i915))
5204 intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
5205 mutex_unlock(&i915->drm.struct_mutex);
5209 if (!i915_terminally_wedged(&i915->gpu_error)) {
5210 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
5211 i915_gem_set_wedged(i915);
5216 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
5218 if (INTEL_GEN(dev_priv) < 5 ||
5219 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
5222 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
5223 DISP_TILE_SURFACE_SWIZZLING);
5225 if (IS_GEN5(dev_priv))
5228 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
5229 if (IS_GEN6(dev_priv))
5230 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
5231 else if (IS_GEN7(dev_priv))
5232 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
5233 else if (IS_GEN8(dev_priv))
5234 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
5239 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
5241 I915_WRITE(RING_CTL(base), 0);
5242 I915_WRITE(RING_HEAD(base), 0);
5243 I915_WRITE(RING_TAIL(base), 0);
5244 I915_WRITE(RING_START(base), 0);
5247 static void init_unused_rings(struct drm_i915_private *dev_priv)
5249 if (IS_I830(dev_priv)) {
5250 init_unused_ring(dev_priv, PRB1_BASE);
5251 init_unused_ring(dev_priv, SRB0_BASE);
5252 init_unused_ring(dev_priv, SRB1_BASE);
5253 init_unused_ring(dev_priv, SRB2_BASE);
5254 init_unused_ring(dev_priv, SRB3_BASE);
5255 } else if (IS_GEN2(dev_priv)) {
5256 init_unused_ring(dev_priv, SRB0_BASE);
5257 init_unused_ring(dev_priv, SRB1_BASE);
5258 } else if (IS_GEN3(dev_priv)) {
5259 init_unused_ring(dev_priv, PRB1_BASE);
5260 init_unused_ring(dev_priv, PRB2_BASE);
5264 static int __i915_gem_restart_engines(void *data)
5266 struct drm_i915_private *i915 = data;
5267 struct intel_engine_cs *engine;
5268 enum intel_engine_id id;
5271 for_each_engine(engine, i915, id) {
5272 err = engine->init_hw(engine);
5274 DRM_ERROR("Failed to restart %s (%d)\n",
5283 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
5287 dev_priv->gt.last_init_time = ktime_get();
5289 /* Double layer security blanket, see i915_gem_init() */
5290 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5292 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
5293 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
5295 if (IS_HASWELL(dev_priv))
5296 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
5297 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
5299 if (HAS_PCH_NOP(dev_priv)) {
5300 if (IS_IVYBRIDGE(dev_priv)) {
5301 u32 temp = I915_READ(GEN7_MSG_CTL);
5302 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
5303 I915_WRITE(GEN7_MSG_CTL, temp);
5304 } else if (INTEL_GEN(dev_priv) >= 7) {
5305 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
5306 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
5307 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
5311 intel_gt_workarounds_apply(dev_priv);
5313 i915_gem_init_swizzling(dev_priv);
5316 * At least 830 can leave some of the unused rings
5317 * "active" (ie. head != tail) after resume which
5318 * will prevent c3 entry. Makes sure all unused rings
5321 init_unused_rings(dev_priv);
5323 BUG_ON(!dev_priv->kernel_context);
5324 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
5329 ret = i915_ppgtt_init_hw(dev_priv);
5331 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
5335 ret = intel_wopcm_init_hw(&dev_priv->wopcm);
5337 DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
5341 /* We can't enable contexts until all firmware is loaded */
5342 ret = intel_uc_init_hw(dev_priv);
5344 DRM_ERROR("Enabling uc failed (%d)\n", ret);
5348 intel_mocs_init_l3cc_table(dev_priv);
5350 /* Only when the HW is re-initialised, can we replay the requests */
5351 ret = __i915_gem_restart_engines(dev_priv);
5355 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5360 intel_uc_fini_hw(dev_priv);
5362 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5367 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
5369 struct i915_gem_context *ctx;
5370 struct intel_engine_cs *engine;
5371 enum intel_engine_id id;
5375 * As we reset the gpu during very early sanitisation, the current
5376 * register state on the GPU should reflect its defaults values.
5377 * We load a context onto the hw (with restore-inhibit), then switch
5378 * over to a second context to save that default register state. We
5379 * can then prime every new context with that state so they all start
5380 * from the same default HW values.
5383 ctx = i915_gem_context_create_kernel(i915, 0);
5385 return PTR_ERR(ctx);
5387 for_each_engine(engine, i915, id) {
5388 struct i915_request *rq;
5390 rq = i915_request_alloc(engine, ctx);
5397 if (engine->init_context)
5398 err = engine->init_context(rq);
5400 i915_request_add(rq);
5405 err = i915_gem_switch_to_kernel_context(i915);
5409 if (i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED, HZ / 5)) {
5410 i915_gem_set_wedged(i915);
5411 err = -EIO; /* Caller will declare us wedged */
5415 assert_kernel_context_is_current(i915);
5417 for_each_engine(engine, i915, id) {
5418 struct i915_vma *state;
5421 GEM_BUG_ON(to_intel_context(ctx, engine)->pin_count);
5423 state = to_intel_context(ctx, engine)->state;
5428 * As we will hold a reference to the logical state, it will
5429 * not be torn down with the context, and importantly the
5430 * object will hold onto its vma (making it possible for a
5431 * stray GTT write to corrupt our defaults). Unmap the vma
5432 * from the GTT to prevent such accidents and reclaim the
5435 err = i915_vma_unbind(state);
5439 err = i915_gem_object_set_to_cpu_domain(state->obj, false);
5443 engine->default_state = i915_gem_object_get(state->obj);
5445 /* Check we can acquire the image of the context state */
5446 vaddr = i915_gem_object_pin_map(engine->default_state,
5448 if (IS_ERR(vaddr)) {
5449 err = PTR_ERR(vaddr);
5453 i915_gem_object_unpin_map(engine->default_state);
5456 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
5457 unsigned int found = intel_engines_has_context_isolation(i915);
5460 * Make sure that classes with multiple engine instances all
5461 * share the same basic configuration.
5463 for_each_engine(engine, i915, id) {
5464 unsigned int bit = BIT(engine->uabi_class);
5465 unsigned int expected = engine->default_state ? bit : 0;
5467 if ((found & bit) != expected) {
5468 DRM_ERROR("mismatching default context state for class %d on engine %s\n",
5469 engine->uabi_class, engine->name);
5475 i915_gem_context_set_closed(ctx);
5476 i915_gem_context_put(ctx);
5481 * If we have to abandon now, we expect the engines to be idle
5482 * and ready to be torn-down. First try to flush any remaining
5483 * request, ensure we are pointing at the kernel context and
5486 if (WARN_ON(i915_gem_switch_to_kernel_context(i915)))
5489 if (WARN_ON(i915_gem_wait_for_idle(i915,
5491 MAX_SCHEDULE_TIMEOUT)))
5494 i915_gem_contexts_lost(i915);
5498 int i915_gem_init(struct drm_i915_private *dev_priv)
5502 /* We need to fallback to 4K pages if host doesn't support huge gtt. */
5503 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
5504 mkwrite_device_info(dev_priv)->page_sizes =
5505 I915_GTT_PAGE_SIZE_4K;
5507 dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
5509 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
5510 dev_priv->gt.resume = intel_lr_context_resume;
5511 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
5513 dev_priv->gt.resume = intel_legacy_submission_resume;
5514 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
5517 ret = i915_gem_init_userptr(dev_priv);
5521 ret = intel_uc_init_misc(dev_priv);
5525 ret = intel_wopcm_init(&dev_priv->wopcm);
5529 /* This is just a security blanket to placate dragons.
5530 * On some systems, we very sporadically observe that the first TLBs
5531 * used by the CS may be stale, despite us poking the TLB reset. If
5532 * we hold the forcewake during initialisation these problems
5533 * just magically go away.
5535 mutex_lock(&dev_priv->drm.struct_mutex);
5536 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5538 ret = i915_gem_init_ggtt(dev_priv);
5540 GEM_BUG_ON(ret == -EIO);
5544 ret = i915_gem_contexts_init(dev_priv);
5546 GEM_BUG_ON(ret == -EIO);
5550 ret = intel_engines_init(dev_priv);
5552 GEM_BUG_ON(ret == -EIO);
5556 intel_init_gt_powersave(dev_priv);
5558 ret = intel_uc_init(dev_priv);
5562 ret = i915_gem_init_hw(dev_priv);
5567 * Despite its name intel_init_clock_gating applies both display
5568 * clock gating workarounds; GT mmio workarounds and the occasional
5569 * GT power context workaround. Worse, sometimes it includes a context
5570 * register workaround which we need to apply before we record the
5571 * default HW state for all contexts.
5573 * FIXME: break up the workarounds and apply them at the right time!
5575 intel_init_clock_gating(dev_priv);
5577 ret = __intel_engines_record_defaults(dev_priv);
5581 if (i915_inject_load_failure()) {
5586 if (i915_inject_load_failure()) {
5591 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5592 mutex_unlock(&dev_priv->drm.struct_mutex);
5597 * Unwinding is complicated by that we want to handle -EIO to mean
5598 * disable GPU submission but keep KMS alive. We want to mark the
5599 * HW as irrevisibly wedged, but keep enough state around that the
5600 * driver doesn't explode during runtime.
5603 mutex_unlock(&dev_priv->drm.struct_mutex);
5605 WARN_ON(i915_gem_suspend(dev_priv));
5606 i915_gem_suspend_late(dev_priv);
5608 i915_gem_drain_workqueue(dev_priv);
5610 mutex_lock(&dev_priv->drm.struct_mutex);
5611 intel_uc_fini_hw(dev_priv);
5613 intel_uc_fini(dev_priv);
5616 intel_cleanup_gt_powersave(dev_priv);
5617 i915_gem_cleanup_engines(dev_priv);
5621 i915_gem_contexts_fini(dev_priv);
5624 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5625 mutex_unlock(&dev_priv->drm.struct_mutex);
5628 intel_uc_fini_misc(dev_priv);
5631 i915_gem_cleanup_userptr(dev_priv);
5634 mutex_lock(&dev_priv->drm.struct_mutex);
5637 * Allow engine initialisation to fail by marking the GPU as
5638 * wedged. But we only want to do this where the GPU is angry,
5639 * for all other failure, such as an allocation failure, bail.
5641 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
5642 i915_load_error(dev_priv,
5643 "Failed to initialize GPU, declaring it wedged!\n");
5644 i915_gem_set_wedged(dev_priv);
5647 /* Minimal basic recovery for KMS */
5648 ret = i915_ggtt_enable_hw(dev_priv);
5649 i915_gem_restore_gtt_mappings(dev_priv);
5650 i915_gem_restore_fences(dev_priv);
5651 intel_init_clock_gating(dev_priv);
5653 mutex_unlock(&dev_priv->drm.struct_mutex);
5656 i915_gem_drain_freed_objects(dev_priv);
5660 void i915_gem_fini(struct drm_i915_private *dev_priv)
5662 i915_gem_suspend_late(dev_priv);
5663 intel_disable_gt_powersave(dev_priv);
5665 /* Flush any outstanding unpin_work. */
5666 i915_gem_drain_workqueue(dev_priv);
5668 mutex_lock(&dev_priv->drm.struct_mutex);
5669 intel_uc_fini_hw(dev_priv);
5670 intel_uc_fini(dev_priv);
5671 i915_gem_cleanup_engines(dev_priv);
5672 i915_gem_contexts_fini(dev_priv);
5673 mutex_unlock(&dev_priv->drm.struct_mutex);
5675 intel_cleanup_gt_powersave(dev_priv);
5677 intel_uc_fini_misc(dev_priv);
5678 i915_gem_cleanup_userptr(dev_priv);
5680 i915_gem_drain_freed_objects(dev_priv);
5682 WARN_ON(!list_empty(&dev_priv->contexts.list));
5685 void i915_gem_init_mmio(struct drm_i915_private *i915)
5687 i915_gem_sanitize(i915);
5691 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
5693 struct intel_engine_cs *engine;
5694 enum intel_engine_id id;
5696 for_each_engine(engine, dev_priv, id)
5697 dev_priv->gt.cleanup_engine(engine);
5701 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
5705 if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
5706 !IS_CHERRYVIEW(dev_priv))
5707 dev_priv->num_fence_regs = 32;
5708 else if (INTEL_GEN(dev_priv) >= 4 ||
5709 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
5710 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
5711 dev_priv->num_fence_regs = 16;
5713 dev_priv->num_fence_regs = 8;
5715 if (intel_vgpu_active(dev_priv))
5716 dev_priv->num_fence_regs =
5717 I915_READ(vgtif_reg(avail_rs.fence_num));
5719 /* Initialize fence registers to zero */
5720 for (i = 0; i < dev_priv->num_fence_regs; i++) {
5721 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
5723 fence->i915 = dev_priv;
5725 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
5727 i915_gem_restore_fences(dev_priv);
5729 i915_gem_detect_bit_6_swizzle(dev_priv);
5732 static void i915_gem_init__mm(struct drm_i915_private *i915)
5734 spin_lock_init(&i915->mm.object_stat_lock);
5735 spin_lock_init(&i915->mm.obj_lock);
5736 spin_lock_init(&i915->mm.free_lock);
5738 init_llist_head(&i915->mm.free_list);
5740 INIT_LIST_HEAD(&i915->mm.unbound_list);
5741 INIT_LIST_HEAD(&i915->mm.bound_list);
5742 INIT_LIST_HEAD(&i915->mm.fence_list);
5743 INIT_LIST_HEAD(&i915->mm.userfault_list);
5745 INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
5748 int i915_gem_init_early(struct drm_i915_private *dev_priv)
5752 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
5753 if (!dev_priv->objects)
5756 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
5757 if (!dev_priv->vmas)
5760 dev_priv->luts = KMEM_CACHE(i915_lut_handle, 0);
5761 if (!dev_priv->luts)
5764 dev_priv->requests = KMEM_CACHE(i915_request,
5765 SLAB_HWCACHE_ALIGN |
5766 SLAB_RECLAIM_ACCOUNT |
5767 SLAB_TYPESAFE_BY_RCU);
5768 if (!dev_priv->requests)
5771 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
5772 SLAB_HWCACHE_ALIGN |
5773 SLAB_RECLAIM_ACCOUNT);
5774 if (!dev_priv->dependencies)
5777 dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN);
5778 if (!dev_priv->priorities)
5779 goto err_dependencies;
5781 INIT_LIST_HEAD(&dev_priv->gt.timelines);
5782 INIT_LIST_HEAD(&dev_priv->gt.active_rings);
5783 INIT_LIST_HEAD(&dev_priv->gt.closed_vma);
5785 i915_gem_init__mm(dev_priv);
5787 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
5788 i915_gem_retire_work_handler);
5789 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
5790 i915_gem_idle_work_handler);
5791 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
5792 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5794 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
5796 spin_lock_init(&dev_priv->fb_tracking.lock);
5798 err = i915_gemfs_init(dev_priv);
5800 DRM_NOTE("Unable to create a private tmpfs mount, hugepage support will be disabled(%d).\n", err);
5805 kmem_cache_destroy(dev_priv->dependencies);
5807 kmem_cache_destroy(dev_priv->requests);
5809 kmem_cache_destroy(dev_priv->luts);
5811 kmem_cache_destroy(dev_priv->vmas);
5813 kmem_cache_destroy(dev_priv->objects);
5818 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
5820 i915_gem_drain_freed_objects(dev_priv);
5821 GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));
5822 GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));
5823 WARN_ON(dev_priv->mm.object_count);
5824 WARN_ON(!list_empty(&dev_priv->gt.timelines));
5826 kmem_cache_destroy(dev_priv->priorities);
5827 kmem_cache_destroy(dev_priv->dependencies);
5828 kmem_cache_destroy(dev_priv->requests);
5829 kmem_cache_destroy(dev_priv->luts);
5830 kmem_cache_destroy(dev_priv->vmas);
5831 kmem_cache_destroy(dev_priv->objects);
5833 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
5836 i915_gemfs_fini(dev_priv);
5839 int i915_gem_freeze(struct drm_i915_private *dev_priv)
5841 /* Discard all purgeable objects, let userspace recover those as
5842 * required after resuming.
5844 i915_gem_shrink_all(dev_priv);
5849 int i915_gem_freeze_late(struct drm_i915_private *i915)
5851 struct drm_i915_gem_object *obj;
5852 struct list_head *phases[] = {
5853 &i915->mm.unbound_list,
5854 &i915->mm.bound_list,
5859 * Called just before we write the hibernation image.
5861 * We need to update the domain tracking to reflect that the CPU
5862 * will be accessing all the pages to create and restore from the
5863 * hibernation, and so upon restoration those pages will be in the
5866 * To make sure the hibernation image contains the latest state,
5867 * we update that state just before writing out the image.
5869 * To try and reduce the hibernation image, we manually shrink
5870 * the objects as well, see i915_gem_freeze()
5873 i915_gem_shrink(i915, -1UL, NULL, I915_SHRINK_UNBOUND);
5874 i915_gem_drain_freed_objects(i915);
5876 mutex_lock(&i915->drm.struct_mutex);
5877 for (phase = phases; *phase; phase++) {
5878 list_for_each_entry(obj, *phase, mm.link)
5879 WARN_ON(i915_gem_object_set_to_cpu_domain(obj, true));
5881 mutex_unlock(&i915->drm.struct_mutex);
5886 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5888 struct drm_i915_file_private *file_priv = file->driver_priv;
5889 struct i915_request *request;
5891 /* Clean up our request list when the client is going away, so that
5892 * later retire_requests won't dereference our soon-to-be-gone
5895 spin_lock(&file_priv->mm.lock);
5896 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
5897 request->file_priv = NULL;
5898 spin_unlock(&file_priv->mm.lock);
5901 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
5903 struct drm_i915_file_private *file_priv;
5908 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5912 file->driver_priv = file_priv;
5913 file_priv->dev_priv = i915;
5914 file_priv->file = file;
5916 spin_lock_init(&file_priv->mm.lock);
5917 INIT_LIST_HEAD(&file_priv->mm.request_list);
5919 file_priv->bsd_engine = -1;
5920 file_priv->hang_timestamp = jiffies;
5922 ret = i915_gem_context_open(i915, file);
5930 * i915_gem_track_fb - update frontbuffer tracking
5931 * @old: current GEM buffer for the frontbuffer slots
5932 * @new: new GEM buffer for the frontbuffer slots
5933 * @frontbuffer_bits: bitmask of frontbuffer slots
5935 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5936 * from @old and setting them in @new. Both @old and @new can be NULL.
5938 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5939 struct drm_i915_gem_object *new,
5940 unsigned frontbuffer_bits)
5942 /* Control of individual bits within the mask are guarded by
5943 * the owning plane->mutex, i.e. we can never see concurrent
5944 * manipulation of individual bits. But since the bitfield as a whole
5945 * is updated using RMW, we need to use atomics in order to update
5948 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
5949 sizeof(atomic_t) * BITS_PER_BYTE);
5952 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
5953 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
5957 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
5958 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
5962 /* Allocate a new GEM object and fill it with the supplied data */
5963 struct drm_i915_gem_object *
5964 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
5965 const void *data, size_t size)
5967 struct drm_i915_gem_object *obj;
5972 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
5976 GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
5978 file = obj->base.filp;
5981 unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
5983 void *pgdata, *vaddr;
5985 err = pagecache_write_begin(file, file->f_mapping,
5992 memcpy(vaddr, data, len);
5995 err = pagecache_write_end(file, file->f_mapping,
6009 i915_gem_object_put(obj);
6010 return ERR_PTR(err);
6013 struct scatterlist *
6014 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
6016 unsigned int *offset)
6018 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
6019 struct scatterlist *sg;
6020 unsigned int idx, count;
6023 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
6024 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
6026 /* As we iterate forward through the sg, we record each entry in a
6027 * radixtree for quick repeated (backwards) lookups. If we have seen
6028 * this index previously, we will have an entry for it.
6030 * Initial lookup is O(N), but this is amortized to O(1) for
6031 * sequential page access (where each new request is consecutive
6032 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
6033 * i.e. O(1) with a large constant!
6035 if (n < READ_ONCE(iter->sg_idx))
6038 mutex_lock(&iter->lock);
6040 /* We prefer to reuse the last sg so that repeated lookup of this
6041 * (or the subsequent) sg are fast - comparing against the last
6042 * sg is faster than going through the radixtree.
6047 count = __sg_page_count(sg);
6049 while (idx + count <= n) {
6050 unsigned long exception, i;
6053 /* If we cannot allocate and insert this entry, or the
6054 * individual pages from this range, cancel updating the
6055 * sg_idx so that on this lookup we are forced to linearly
6056 * scan onwards, but on future lookups we will try the
6057 * insertion again (in which case we need to be careful of
6058 * the error return reporting that we have already inserted
6061 ret = radix_tree_insert(&iter->radix, idx, sg);
6062 if (ret && ret != -EEXIST)
6066 RADIX_TREE_EXCEPTIONAL_ENTRY |
6067 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
6068 for (i = 1; i < count; i++) {
6069 ret = radix_tree_insert(&iter->radix, idx + i,
6071 if (ret && ret != -EEXIST)
6076 sg = ____sg_next(sg);
6077 count = __sg_page_count(sg);
6084 mutex_unlock(&iter->lock);
6086 if (unlikely(n < idx)) /* insertion completed by another thread */
6089 /* In case we failed to insert the entry into the radixtree, we need
6090 * to look beyond the current sg.
6092 while (idx + count <= n) {
6094 sg = ____sg_next(sg);
6095 count = __sg_page_count(sg);
6104 sg = radix_tree_lookup(&iter->radix, n);
6107 /* If this index is in the middle of multi-page sg entry,
6108 * the radixtree will contain an exceptional entry that points
6109 * to the start of that range. We will return the pointer to
6110 * the base page and the offset of this page within the
6114 if (unlikely(radix_tree_exception(sg))) {
6115 unsigned long base =
6116 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
6118 sg = radix_tree_lookup(&iter->radix, base);
6130 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
6132 struct scatterlist *sg;
6133 unsigned int offset;
6135 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
6137 sg = i915_gem_object_get_sg(obj, n, &offset);
6138 return nth_page(sg_page(sg), offset);
6141 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
6143 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
6148 page = i915_gem_object_get_page(obj, n);
6150 set_page_dirty(page);
6156 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
6159 struct scatterlist *sg;
6160 unsigned int offset;
6162 sg = i915_gem_object_get_sg(obj, n, &offset);
6163 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
6166 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
6168 struct sg_table *pages;
6171 if (align > obj->base.size)
6174 if (obj->ops == &i915_gem_phys_ops)
6177 if (obj->ops != &i915_gem_object_ops)
6180 err = i915_gem_object_unbind(obj);
6184 mutex_lock(&obj->mm.lock);
6186 if (obj->mm.madv != I915_MADV_WILLNEED) {
6191 if (obj->mm.quirked) {
6196 if (obj->mm.mapping) {
6201 pages = __i915_gem_object_unset_pages(obj);
6203 obj->ops = &i915_gem_phys_ops;
6205 err = ____i915_gem_object_get_pages(obj);
6209 /* Perma-pin (until release) the physical set of pages */
6210 __i915_gem_object_pin_pages(obj);
6212 if (!IS_ERR_OR_NULL(pages))
6213 i915_gem_object_ops.put_pages(obj, pages);
6214 mutex_unlock(&obj->mm.lock);
6218 obj->ops = &i915_gem_object_ops;
6219 if (!IS_ERR_OR_NULL(pages)) {
6220 unsigned int sg_page_sizes = i915_sg_page_sizes(pages->sgl);
6222 __i915_gem_object_set_pages(obj, pages, sg_page_sizes);
6225 mutex_unlock(&obj->mm.lock);
6229 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
6230 #include "selftests/scatterlist.c"
6231 #include "selftests/mock_gem_device.c"
6232 #include "selftests/huge_gem_object.c"
6233 #include "selftests/huge_pages.c"
6234 #include "selftests/i915_gem_object.c"
6235 #include "selftests/i915_gem_coherency.c"
6236 #include "selftests/i915_gem.c"