1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_connector.h>
58 #include <drm/i915_mei_hdcp_interface.h>
60 #include "i915_fixed.h"
61 #include "i915_params.h"
63 #include "i915_utils.h"
65 #include "intel_bios.h"
66 #include "intel_device_info.h"
67 #include "intel_display.h"
68 #include "intel_dpll_mgr.h"
69 #include "intel_frontbuffer.h"
70 #include "intel_lrc.h"
71 #include "intel_opregion.h"
72 #include "intel_ringbuffer.h"
74 #include "intel_uncore.h"
75 #include "intel_wopcm.h"
76 #include "intel_workarounds.h"
79 #include "i915_gem_context.h"
80 #include "i915_gem_fence_reg.h"
81 #include "i915_gem_object.h"
82 #include "i915_gem_gtt.h"
83 #include "i915_gpu_error.h"
84 #include "i915_request.h"
85 #include "i915_scheduler.h"
86 #include "i915_timeline.h"
89 #include "intel_gvt.h"
91 /* General customization:
94 #define DRIVER_NAME "i915"
95 #define DRIVER_DESC "Intel Graphics"
96 #define DRIVER_DATE "20190417"
97 #define DRIVER_TIMESTAMP 1555492067
99 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
100 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
101 * which may not necessarily be a user visible problem. This will either
102 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
103 * enable distros and users to tailor their preferred amount of i915 abrt
106 #define I915_STATE_WARN(condition, format...) ({ \
107 int __ret_warn_on = !!(condition); \
108 if (unlikely(__ret_warn_on)) \
109 if (!WARN(i915_modparams.verbose_state_checks, format)) \
111 unlikely(__ret_warn_on); \
114 #define I915_STATE_WARN_ON(x) \
115 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
117 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
119 bool __i915_inject_load_failure(const char *func, int line);
120 #define i915_inject_load_failure() \
121 __i915_inject_load_failure(__func__, __LINE__)
123 bool i915_error_injected(void);
127 #define i915_inject_load_failure() false
128 #define i915_error_injected() false
132 #define i915_load_error(i915, fmt, ...) \
133 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
136 typedef depot_stack_handle_t intel_wakeref_t;
140 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
153 #define for_each_hpd_pin(__pin) \
154 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
156 /* Threshold == 5 for long IRQs, 50 for short */
157 #define HPD_STORM_DEFAULT_THRESHOLD 50
159 struct i915_hotplug {
160 struct work_struct hotplug_work;
163 unsigned long last_jiffies;
168 HPD_MARK_DISABLED = 2
170 } stats[HPD_NUM_PINS];
172 struct delayed_work reenable_work;
176 struct work_struct dig_port_work;
178 struct work_struct poll_init_work;
181 unsigned int hpd_storm_threshold;
182 /* Whether or not to count short HPD IRQs in HPD storms */
183 u8 hpd_short_storm_enabled;
186 * if we get a HPD irq from DP and a HPD irq from non-DP
187 * the non-DP HPD could block the workqueue on a mode config
188 * mutex getting, that userspace may have taken. However
189 * userspace is waiting on the DP workqueue to run which is
190 * blocked behind the non-DP one.
192 struct workqueue_struct *dp_wq;
195 #define I915_GEM_GPU_DOMAINS \
196 (I915_GEM_DOMAIN_RENDER | \
197 I915_GEM_DOMAIN_SAMPLER | \
198 I915_GEM_DOMAIN_COMMAND | \
199 I915_GEM_DOMAIN_INSTRUCTION | \
200 I915_GEM_DOMAIN_VERTEX)
202 struct drm_i915_private;
203 struct i915_mm_struct;
204 struct i915_mmu_object;
206 struct drm_i915_file_private {
207 struct drm_i915_private *dev_priv;
208 struct drm_file *file;
212 struct list_head request_list;
213 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
214 * chosen to prevent the CPU getting more than a frame ahead of the GPU
215 * (when using lax throttling for the frontbuffer). We also use it to
216 * offer free GPU waitboosts for severely congested workloads.
218 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
221 struct idr context_idr;
222 struct mutex context_idr_lock; /* guards context_idr */
225 struct mutex vm_idr_lock; /* guards vm_idr */
227 unsigned int bsd_engine;
230 * Every context ban increments per client ban score. Also
231 * hangs in short succession increments ban score. If ban threshold
232 * is reached, client is considered banned and submitting more work
233 * will fail. This is a stop gap measure to limit the badly behaving
234 * clients access to gpu. Note that unbannable contexts never increment
235 * the client ban score.
237 #define I915_CLIENT_SCORE_HANG_FAST 1
238 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
239 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
240 #define I915_CLIENT_SCORE_BANNED 9
241 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
243 unsigned long hang_timestamp;
246 /* Interface history:
249 * 1.2: Add Power Management
250 * 1.3: Add vblank support
251 * 1.4: Fix cmdbuffer path, add heap destroy
252 * 1.5: Add vblank pipe configuration
253 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
254 * - Support vertical blank on secondary display pipe
256 #define DRIVER_MAJOR 1
257 #define DRIVER_MINOR 6
258 #define DRIVER_PATCHLEVEL 0
260 struct intel_overlay;
261 struct intel_overlay_error_state;
263 struct sdvo_device_mapping {
272 struct intel_connector;
273 struct intel_encoder;
274 struct intel_atomic_state;
275 struct intel_crtc_state;
276 struct intel_initial_plane_config;
280 struct intel_cdclk_state;
282 struct drm_i915_display_funcs {
283 void (*get_cdclk)(struct drm_i915_private *dev_priv,
284 struct intel_cdclk_state *cdclk_state);
285 void (*set_cdclk)(struct drm_i915_private *dev_priv,
286 const struct intel_cdclk_state *cdclk_state,
288 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
289 enum i9xx_plane_id i9xx_plane);
290 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
291 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
292 void (*initial_watermarks)(struct intel_atomic_state *state,
293 struct intel_crtc_state *cstate);
294 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
295 struct intel_crtc_state *cstate);
296 void (*optimize_watermarks)(struct intel_atomic_state *state,
297 struct intel_crtc_state *cstate);
298 int (*compute_global_watermarks)(struct intel_atomic_state *state);
299 void (*update_wm)(struct intel_crtc *crtc);
300 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
301 /* Returns the active state of the crtc, and if the crtc is active,
302 * fills out the pipe-config with the hw state. */
303 bool (*get_pipe_config)(struct intel_crtc *,
304 struct intel_crtc_state *);
305 void (*get_initial_plane_config)(struct intel_crtc *,
306 struct intel_initial_plane_config *);
307 int (*crtc_compute_clock)(struct intel_crtc *crtc,
308 struct intel_crtc_state *crtc_state);
309 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
310 struct drm_atomic_state *old_state);
311 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
312 struct drm_atomic_state *old_state);
313 void (*update_crtcs)(struct drm_atomic_state *state);
314 void (*audio_codec_enable)(struct intel_encoder *encoder,
315 const struct intel_crtc_state *crtc_state,
316 const struct drm_connector_state *conn_state);
317 void (*audio_codec_disable)(struct intel_encoder *encoder,
318 const struct intel_crtc_state *old_crtc_state,
319 const struct drm_connector_state *old_conn_state);
320 void (*fdi_link_train)(struct intel_crtc *crtc,
321 const struct intel_crtc_state *crtc_state);
322 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
323 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
324 /* clock updates for mode set */
326 /* render clock increase/decrease */
327 /* display clock increase/decrease */
328 /* pll clock increase/decrease */
330 int (*color_check)(struct intel_crtc_state *crtc_state);
332 * Program double buffered color management registers during
333 * vblank evasion. The registers should then latch during the
334 * next vblank start, alongside any other double buffered registers
335 * involved with the same commit.
337 void (*color_commit)(const struct intel_crtc_state *crtc_state);
339 * Load LUTs (and other single buffered color management
340 * registers). Will (hopefully) be called during the vblank
341 * following the latching of any double buffered registers
342 * involved with the same commit.
344 void (*load_luts)(const struct intel_crtc_state *crtc_state);
347 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
348 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
349 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
352 struct work_struct work;
354 u32 required_version;
355 u32 max_fw_size; /* bytes */
357 u32 dmc_fw_size; /* dwords */
360 i915_reg_t mmioaddr[8];
364 intel_wakeref_t wakeref;
367 enum i915_cache_level {
369 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
370 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
371 caches, eg sampler/render caches, and the
372 large Last-Level-Cache. LLC is coherent with
373 the CPU, but L3 is only visible to the GPU. */
374 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
377 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
380 /* This is always the inner lock when overlapping with struct_mutex and
381 * it's the outer lock when overlapping with stolen_lock. */
384 unsigned int possible_framebuffer_bits;
385 unsigned int busy_bits;
386 unsigned int visible_pipes_mask;
387 struct intel_crtc *crtc;
389 struct drm_mm_node compressed_fb;
390 struct drm_mm_node *compressed_llb;
398 bool underrun_detected;
399 struct work_struct underrun_work;
402 * Due to the atomic rules we can't access some structures without the
403 * appropriate locking, so we cache information here in order to avoid
406 struct intel_fbc_state_cache {
407 struct i915_vma *vma;
411 unsigned int mode_flags;
412 u32 hsw_bdw_pixel_rate;
416 unsigned int rotation;
421 * Display surface base address adjustement for
422 * pageflips. Note that on gen4+ this only adjusts up
423 * to a tile, offsets within a tile are handled in
424 * the hw itself (with the TILEOFF register).
431 u16 pixel_blend_mode;
435 const struct drm_format_info *format;
441 * This structure contains everything that's relevant to program the
442 * hardware registers. When we want to figure out if we need to disable
443 * and re-enable FBC for a new configuration we just check if there's
444 * something different in the struct. The genx_fbc_activate functions
445 * are supposed to read from it in order to program the registers.
447 struct intel_fbc_reg_params {
448 struct i915_vma *vma;
453 enum i9xx_plane_id i9xx_plane;
454 unsigned int fence_y_offset;
458 const struct drm_format_info *format;
463 unsigned int gen9_wa_cfb_stride;
466 const char *no_fbc_reason;
470 * HIGH_RR is the highest eDP panel refresh rate read from EDID
471 * LOW_RR is the lowest eDP panel refresh rate found from EDID
472 * parsing for same resolution.
474 enum drrs_refresh_rate_type {
477 DRRS_MAX_RR, /* RR count */
480 enum drrs_support_type {
481 DRRS_NOT_SUPPORTED = 0,
482 STATIC_DRRS_SUPPORT = 1,
483 SEAMLESS_DRRS_SUPPORT = 2
489 struct delayed_work work;
491 unsigned busy_frontbuffer_bits;
492 enum drrs_refresh_rate_type refresh_rate_type;
493 enum drrs_support_type type;
499 #define I915_PSR_DEBUG_MODE_MASK 0x0f
500 #define I915_PSR_DEBUG_DEFAULT 0x00
501 #define I915_PSR_DEBUG_DISABLE 0x01
502 #define I915_PSR_DEBUG_ENABLE 0x02
503 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
504 #define I915_PSR_DEBUG_IRQ 0x10
512 struct work_struct work;
513 unsigned busy_frontbuffer_bits;
514 bool sink_psr2_support;
516 bool colorimetry_support;
518 u8 sink_sync_latency;
519 ktime_t last_entry_attempt;
521 bool sink_not_reliable;
523 u16 su_x_granularity;
527 * Sorted by south display engine compatibility.
528 * If the new PCH comes with a south display engine that is not
529 * inherited from the latest item, please do not add it to the
530 * end. Instead, add it right after its "parent" PCH.
533 PCH_NOP = -1, /* PCH without south display */
534 PCH_NONE = 0, /* No PCH present */
535 PCH_IBX, /* Ibexpeak PCH */
536 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
537 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
538 PCH_SPT, /* Sunrisepoint PCH */
539 PCH_KBP, /* Kaby Lake PCH */
540 PCH_CNP, /* Cannon/Comet Lake PCH */
541 PCH_ICP, /* Ice Lake PCH */
544 enum intel_sbi_destination {
549 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
550 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
551 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
552 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
553 #define QUIRK_INCREASE_T12_DELAY (1<<6)
554 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
557 struct intel_fbc_work;
560 struct i2c_adapter adapter;
561 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
565 struct i2c_algo_bit_data bit_algo;
566 struct drm_i915_private *dev_priv;
569 struct i915_suspend_saved_registers {
572 u32 saveCACHE_MODE_0;
573 u32 saveMI_ARB_STATE;
577 u64 saveFENCE[I915_MAX_NUM_FENCES];
578 u32 savePCH_PORT_HOTPLUG;
582 struct vlv_s0ix_state {
589 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
590 u32 media_max_req_count;
591 u32 gfx_max_req_count;
623 /* Display 1 CZ domain */
628 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
630 /* GT SA CZ domain */
637 /* Display 2 CZ domain */
644 struct intel_rps_ei {
652 * work, interrupts_enabled and pm_iir are protected by
655 struct work_struct work;
656 bool interrupts_enabled;
659 /* PM interrupt bits that should never be masked */
662 /* Frequencies are stored in potentially platform dependent multiples.
663 * In other words, *_freq needs to be multiplied by X to be interesting.
664 * Soft limits are those which are used for the dynamic reclocking done
665 * by the driver (raise frequencies under heavy loads, and lower for
666 * lighter loads). Hard limits are those imposed by the hardware.
668 * A distinction is made for overclocking, which is never enabled by
669 * default, and is considered to be above the hard limit if it's
672 u8 cur_freq; /* Current frequency (cached, may not == HW) */
673 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
674 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
675 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
676 u8 min_freq; /* AKA RPn. Minimum frequency */
677 u8 boost_freq; /* Frequency to request when wait boosting */
678 u8 idle_freq; /* Frequency to request when we are idle */
679 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
680 u8 rp1_freq; /* "less than" RP0 power/freqency */
681 u8 rp0_freq; /* Non-overclocked max frequency. */
682 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
689 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
690 unsigned int interactive;
692 u8 up_threshold; /* Current %busy required to uplock */
693 u8 down_threshold; /* Current %busy required to downclock */
697 atomic_t num_waiters;
700 /* manual wa residency calculations */
701 struct intel_rps_ei ei;
706 u64 prev_hw_residency[4];
707 u64 cur_residency[4];
710 struct intel_llc_pstate {
714 struct intel_gen6_power_mgmt {
715 struct intel_rps rps;
716 struct intel_rc6 rc6;
717 struct intel_llc_pstate llc_pstate;
720 /* defined intel_pm.c */
721 extern spinlock_t mchdev_lock;
723 struct intel_ilk_power_mgmt {
731 unsigned long last_time1;
732 unsigned long chipset_power;
735 unsigned long gfx_power;
742 struct drm_i915_private;
743 struct i915_power_well;
745 struct i915_power_well_ops {
747 * Synchronize the well's hw state to match the current sw state, for
748 * example enable/disable it based on the current refcount. Called
749 * during driver init and resume time, possibly after first calling
750 * the enable/disable handlers.
752 void (*sync_hw)(struct drm_i915_private *dev_priv,
753 struct i915_power_well *power_well);
755 * Enable the well and resources that depend on it (for example
756 * interrupts located on the well). Called after the 0->1 refcount
759 void (*enable)(struct drm_i915_private *dev_priv,
760 struct i915_power_well *power_well);
762 * Disable the well and resources that depend on it. Called after
763 * the 1->0 refcount transition.
765 void (*disable)(struct drm_i915_private *dev_priv,
766 struct i915_power_well *power_well);
767 /* Returns the hw enabled state. */
768 bool (*is_enabled)(struct drm_i915_private *dev_priv,
769 struct i915_power_well *power_well);
772 struct i915_power_well_regs {
779 /* Power well structure for haswell */
780 struct i915_power_well_desc {
784 /* unique identifier for this power well */
785 enum i915_power_well_id id;
787 * Arbitraty data associated with this power well. Platform and power
793 * request/status flag index in the PUNIT power well
794 * control/status registers.
802 const struct i915_power_well_regs *regs;
804 * request/status flag index in the power well
805 * constrol/status registers.
808 /* Mask of pipes whose IRQ logic is backed by the pw */
810 /* The pw is backing the VGA functionality */
814 * The pw is for an ICL+ TypeC PHY port in
820 const struct i915_power_well_ops *ops;
823 struct i915_power_well {
824 const struct i915_power_well_desc *desc;
825 /* power well enable/disable usage count */
827 /* cached hw enabled state */
831 struct i915_power_domains {
833 * Power wells needed for initialization at driver init and suspend
834 * time are on. They are kept on until after the first modeset.
837 bool display_core_suspended;
838 int power_well_count;
840 intel_wakeref_t wakeref;
843 int domain_use_count[POWER_DOMAIN_NUM];
844 struct i915_power_well *power_wells;
847 #define MAX_L3_SLICES 2
848 struct intel_l3_parity {
849 u32 *remap_info[MAX_L3_SLICES];
850 struct work_struct error_work;
855 /** Memory allocator for GTT stolen memory */
856 struct drm_mm stolen;
857 /** Protects the usage of the GTT stolen memory allocator. This is
858 * always the inner lock when overlapping with struct_mutex. */
859 struct mutex stolen_lock;
861 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
864 /** List of all objects in gtt_space. Used to restore gtt
865 * mappings on resume */
866 struct list_head bound_list;
868 * List of objects which are not bound to the GTT (thus
869 * are idle and not used by the GPU). These objects may or may
870 * not actually have any pages attached.
872 struct list_head unbound_list;
874 /** List of all objects in gtt_space, currently mmaped by userspace.
875 * All objects within this list must also be on bound_list.
877 struct list_head userfault_list;
880 * List of objects which are pending destruction.
882 struct llist_head free_list;
883 struct work_struct free_work;
884 spinlock_t free_lock;
886 * Count of objects pending destructions. Used to skip needlessly
887 * waiting on an RCU barrier if no objects are waiting to be freed.
892 * Small stash of WC pages
894 struct pagestash wc_stash;
897 * tmpfs instance used for shmem backed objects
899 struct vfsmount *gemfs;
901 /** PPGTT used for aliasing the PPGTT with the GTT */
902 struct i915_hw_ppgtt *aliasing_ppgtt;
904 struct notifier_block oom_notifier;
905 struct notifier_block vmap_notifier;
906 struct shrinker shrinker;
908 /** LRU list of objects with fence regs on them. */
909 struct list_head fence_list;
912 * Workqueue to fault in userptr pages, flushed by the execbuf
913 * when required but otherwise left to userspace to try again
916 struct workqueue_struct *userptr_wq;
918 u64 unordered_timeline;
920 /* the indicator for dispatch video commands on two BSD rings */
921 atomic_t bsd_engine_dispatch_index;
923 /** Bit 6 swizzling required for X tiling */
925 /** Bit 6 swizzling required for Y tiling */
928 /* accounting, useful for userland debugging */
929 spinlock_t object_stat_lock;
934 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
936 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
937 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
939 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
940 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
942 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
944 struct ddi_vbt_port_info {
948 * This is an index in the HDMI/DVI DDI buffer translation table.
949 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
950 * populate this field.
952 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
960 u8 supports_typec_usb:1;
963 u8 alternate_aux_channel;
964 u8 alternate_ddc_pin;
968 int dp_max_link_rate; /* 0 for not limited by VBT */
971 enum psr_lines_to_wait {
972 PSR_0_LINES_TO_WAIT = 0,
978 struct intel_vbt_data {
979 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
980 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
983 unsigned int int_tv_support:1;
984 unsigned int lvds_dither:1;
985 unsigned int int_crt_support:1;
986 unsigned int lvds_use_ssc:1;
987 unsigned int int_lvds_support:1;
988 unsigned int display_clock_mode:1;
989 unsigned int fdi_rx_polarity_inverted:1;
990 unsigned int panel_type:4;
992 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
993 enum drm_panel_orientation orientation;
995 enum drrs_support_type drrs_type;
1005 struct edp_power_seq pps;
1011 bool require_aux_wakeup;
1013 enum psr_lines_to_wait lines_to_wait;
1014 int tp1_wakeup_time_us;
1015 int tp2_tp3_wakeup_time_us;
1016 int psr2_tp2_tp3_wakeup_time_us;
1022 bool active_low_pwm;
1023 u8 min_brightness; /* min_brightness/255 of max */
1024 u8 controller; /* brightness controller number */
1025 enum intel_backlight_type type;
1031 struct mipi_config *config;
1032 struct mipi_pps_data *pps;
1038 const u8 *sequence[MIPI_SEQ_MAX];
1039 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1040 enum drm_panel_orientation orientation;
1046 struct child_device_config *child_dev;
1048 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1049 struct sdvo_device_mapping sdvo_mappings[2];
1052 enum intel_ddb_partitioning {
1054 INTEL_DDB_PART_5_6, /* IVB+ */
1057 struct intel_wm_level {
1065 struct ilk_wm_values {
1071 enum intel_ddb_partitioning partitioning;
1074 struct g4x_pipe_wm {
1075 u16 plane[I915_MAX_PLANES];
1085 struct vlv_wm_ddl_values {
1086 u8 plane[I915_MAX_PLANES];
1089 struct vlv_wm_values {
1090 struct g4x_pipe_wm pipe[3];
1091 struct g4x_sr_wm sr;
1092 struct vlv_wm_ddl_values ddl[3];
1097 struct g4x_wm_values {
1098 struct g4x_pipe_wm pipe[2];
1099 struct g4x_sr_wm sr;
1100 struct g4x_sr_wm hpll;
1106 struct skl_ddb_entry {
1107 u16 start, end; /* in number of blocks, 'end' is exclusive */
1110 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1112 return entry->end - entry->start;
1115 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1116 const struct skl_ddb_entry *e2)
1118 if (e1->start == e2->start && e1->end == e2->end)
1124 struct skl_ddb_allocation {
1125 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1128 struct skl_ddb_values {
1129 unsigned dirty_pipes;
1130 struct skl_ddb_allocation ddb;
1133 struct skl_wm_level {
1141 /* Stores plane specific WM parameters */
1142 struct skl_wm_params {
1143 bool x_tiled, y_tiled;
1148 u32 plane_pixel_rate;
1149 u32 y_min_scanlines;
1150 u32 plane_bytes_per_line;
1151 uint_fixed_16_16_t plane_blocks_per_line;
1152 uint_fixed_16_16_t y_tile_minimum;
1154 u32 dbuf_block_size;
1158 * This struct helps tracking the state needed for runtime PM, which puts the
1159 * device in PCI D3 state. Notice that when this happens, nothing on the
1160 * graphics device works, even register access, so we don't get interrupts nor
1163 * Every piece of our code that needs to actually touch the hardware needs to
1164 * either call intel_runtime_pm_get or call intel_display_power_get with the
1165 * appropriate power domain.
1167 * Our driver uses the autosuspend delay feature, which means we'll only really
1168 * suspend if we stay with zero refcount for a certain amount of time. The
1169 * default value is currently very conservative (see intel_runtime_pm_enable), but
1170 * it can be changed with the standard runtime PM files from sysfs.
1172 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1173 * goes back to false exactly before we reenable the IRQs. We use this variable
1174 * to check if someone is trying to enable/disable IRQs while they're supposed
1175 * to be disabled. This shouldn't happen and we'll print some error messages in
1178 * For more, read the Documentation/power/runtime_pm.txt.
1180 struct i915_runtime_pm {
1181 atomic_t wakeref_count;
1185 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1187 * To aide detection of wakeref leaks and general misuse, we
1188 * track all wakeref holders. With manual markup (i.e. returning
1189 * a cookie to each rpm_get caller which they then supply to their
1190 * paired rpm_put) we can remove corresponding pairs of and keep
1191 * the array trimmed to active wakerefs.
1193 struct intel_runtime_pm_debug {
1196 depot_stack_handle_t last_acquire;
1197 depot_stack_handle_t last_release;
1199 depot_stack_handle_t *owners;
1200 unsigned long count;
1205 enum intel_pipe_crc_source {
1206 INTEL_PIPE_CRC_SOURCE_NONE,
1207 INTEL_PIPE_CRC_SOURCE_PLANE1,
1208 INTEL_PIPE_CRC_SOURCE_PLANE2,
1209 INTEL_PIPE_CRC_SOURCE_PLANE3,
1210 INTEL_PIPE_CRC_SOURCE_PLANE4,
1211 INTEL_PIPE_CRC_SOURCE_PLANE5,
1212 INTEL_PIPE_CRC_SOURCE_PLANE6,
1213 INTEL_PIPE_CRC_SOURCE_PLANE7,
1214 INTEL_PIPE_CRC_SOURCE_PIPE,
1215 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1216 INTEL_PIPE_CRC_SOURCE_TV,
1217 INTEL_PIPE_CRC_SOURCE_DP_B,
1218 INTEL_PIPE_CRC_SOURCE_DP_C,
1219 INTEL_PIPE_CRC_SOURCE_DP_D,
1220 INTEL_PIPE_CRC_SOURCE_AUTO,
1221 INTEL_PIPE_CRC_SOURCE_MAX,
1224 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1225 struct intel_pipe_crc {
1228 enum intel_pipe_crc_source source;
1231 struct i915_frontbuffer_tracking {
1235 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1242 struct i915_virtual_gpu {
1247 /* used in computing the new watermarks state */
1248 struct intel_wm_config {
1249 unsigned int num_pipes_active;
1250 bool sprites_enabled;
1251 bool sprites_scaled;
1254 struct i915_oa_format {
1259 struct i915_oa_reg {
1264 struct i915_oa_config {
1265 char uuid[UUID_STRING_LEN + 1];
1268 const struct i915_oa_reg *mux_regs;
1270 const struct i915_oa_reg *b_counter_regs;
1271 u32 b_counter_regs_len;
1272 const struct i915_oa_reg *flex_regs;
1275 struct attribute_group sysfs_metric;
1276 struct attribute *attrs[2];
1277 struct device_attribute sysfs_metric_id;
1282 struct i915_perf_stream;
1285 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1287 struct i915_perf_stream_ops {
1289 * @enable: Enables the collection of HW samples, either in response to
1290 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1291 * without `I915_PERF_FLAG_DISABLED`.
1293 void (*enable)(struct i915_perf_stream *stream);
1296 * @disable: Disables the collection of HW samples, either in response
1297 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1300 void (*disable)(struct i915_perf_stream *stream);
1303 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1304 * once there is something ready to read() for the stream
1306 void (*poll_wait)(struct i915_perf_stream *stream,
1311 * @wait_unlocked: For handling a blocking read, wait until there is
1312 * something to ready to read() for the stream. E.g. wait on the same
1313 * wait queue that would be passed to poll_wait().
1315 int (*wait_unlocked)(struct i915_perf_stream *stream);
1318 * @read: Copy buffered metrics as records to userspace
1319 * **buf**: the userspace, destination buffer
1320 * **count**: the number of bytes to copy, requested by userspace
1321 * **offset**: zero at the start of the read, updated as the read
1322 * proceeds, it represents how many bytes have been copied so far and
1323 * the buffer offset for copying the next record.
1325 * Copy as many buffered i915 perf samples and records for this stream
1326 * to userspace as will fit in the given buffer.
1328 * Only write complete records; returning -%ENOSPC if there isn't room
1329 * for a complete record.
1331 * Return any error condition that results in a short read such as
1332 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1333 * returning to userspace.
1335 int (*read)(struct i915_perf_stream *stream,
1341 * @destroy: Cleanup any stream specific resources.
1343 * The stream will always be disabled before this is called.
1345 void (*destroy)(struct i915_perf_stream *stream);
1349 * struct i915_perf_stream - state for a single open stream FD
1351 struct i915_perf_stream {
1353 * @dev_priv: i915 drm device
1355 struct drm_i915_private *dev_priv;
1358 * @link: Links the stream into ``&drm_i915_private->streams``
1360 struct list_head link;
1363 * @wakeref: As we keep the device awake while the perf stream is
1364 * active, we track our runtime pm reference for later release.
1366 intel_wakeref_t wakeref;
1369 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1370 * properties given when opening a stream, representing the contents
1371 * of a single sample as read() by userspace.
1376 * @sample_size: Considering the configured contents of a sample
1377 * combined with the required header size, this is the total size
1378 * of a single sample record.
1383 * @ctx: %NULL if measuring system-wide across all contexts or a
1384 * specific context that is being monitored.
1386 struct i915_gem_context *ctx;
1389 * @enabled: Whether the stream is currently enabled, considering
1390 * whether the stream was opened in a disabled state and based
1391 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1396 * @ops: The callbacks providing the implementation of this specific
1397 * type of configured stream.
1399 const struct i915_perf_stream_ops *ops;
1402 * @oa_config: The OA configuration used by the stream.
1404 struct i915_oa_config *oa_config;
1408 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1410 struct i915_oa_ops {
1412 * @is_valid_b_counter_reg: Validates register's address for
1413 * programming boolean counters for a particular platform.
1415 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1419 * @is_valid_mux_reg: Validates register's address for programming mux
1420 * for a particular platform.
1422 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1425 * @is_valid_flex_reg: Validates register's address for programming
1426 * flex EU filtering for a particular platform.
1428 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1431 * @enable_metric_set: Selects and applies any MUX configuration to set
1432 * up the Boolean and Custom (B/C) counters that are part of the
1433 * counter reports being sampled. May apply system constraints such as
1434 * disabling EU clock gating as required.
1436 int (*enable_metric_set)(struct i915_perf_stream *stream);
1439 * @disable_metric_set: Remove system constraints associated with using
1442 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1445 * @oa_enable: Enable periodic sampling
1447 void (*oa_enable)(struct i915_perf_stream *stream);
1450 * @oa_disable: Disable periodic sampling
1452 void (*oa_disable)(struct i915_perf_stream *stream);
1455 * @read: Copy data from the circular OA buffer into a given userspace
1458 int (*read)(struct i915_perf_stream *stream,
1464 * @oa_hw_tail_read: read the OA tail pointer register
1466 * In particular this enables us to share all the fiddly code for
1467 * handling the OA unit tail pointer race that affects multiple
1470 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1473 struct intel_cdclk_state {
1474 unsigned int cdclk, vco, ref, bypass;
1478 struct drm_i915_private {
1479 struct drm_device drm;
1481 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1482 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1483 struct intel_driver_caps caps;
1486 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1487 * end of stolen which we can optionally use to create GEM objects
1488 * backed by stolen memory. Note that stolen_usable_size tells us
1489 * exactly how much of this we are actually allowed to use, given that
1490 * some portion of it is in fact reserved for use by hardware functions.
1492 struct resource dsm;
1494 * Reseved portion of Data Stolen Memory
1496 struct resource dsm_reserved;
1499 * Stolen memory is segmented in hardware with different portions
1500 * offlimits to certain functions.
1502 * The drm_mm is initialised to the total accessible range, as found
1503 * from the PCI config. On Broadwell+, this is further restricted to
1504 * avoid the first page! The upper end of stolen memory is reserved for
1505 * hardware functions and similarly removed from the accessible range.
1507 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1509 struct intel_uncore uncore;
1511 struct i915_virtual_gpu vgpu;
1513 struct intel_gvt *gvt;
1515 struct intel_wopcm wopcm;
1517 struct intel_huc huc;
1518 struct intel_guc guc;
1520 struct intel_csr csr;
1522 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1524 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1525 * controller on different i2c buses. */
1526 struct mutex gmbus_mutex;
1529 * Base address of where the gmbus and gpio blocks are located (either
1530 * on PCH or on SoC for platforms without PCH).
1534 /* MMIO base address for MIPI regs */
1541 wait_queue_head_t gmbus_wait_queue;
1543 struct pci_dev *bridge_dev;
1544 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1545 /* Context used internally to idle the GPU and setup initial state */
1546 struct i915_gem_context *kernel_context;
1547 /* Context only to be used for injecting preemption commands */
1548 struct i915_gem_context *preempt_context;
1549 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1550 [MAX_ENGINE_INSTANCE + 1];
1552 struct resource mch_res;
1554 /* protects the irq masks */
1555 spinlock_t irq_lock;
1557 bool display_irqs_enabled;
1559 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1560 struct pm_qos_request pm_qos;
1562 /* Sideband mailbox protection */
1563 struct mutex sb_lock;
1565 /** Cached value of IMR to avoid reads in updating the bitfield */
1568 u32 de_irq_mask[I915_MAX_PIPES];
1575 u32 pipestat_irq_mask[I915_MAX_PIPES];
1577 struct i915_hotplug hotplug;
1578 struct intel_fbc fbc;
1579 struct i915_drrs drrs;
1580 struct intel_opregion opregion;
1581 struct intel_vbt_data vbt;
1583 bool preserve_bios_swizzle;
1586 struct intel_overlay *overlay;
1588 /* backlight registers and fields in struct intel_panel */
1589 struct mutex backlight_lock;
1592 bool no_aux_handshake;
1594 /* protects panel power sequencer state */
1595 struct mutex pps_mutex;
1597 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1598 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1600 unsigned int fsb_freq, mem_freq, is_ddr3;
1601 unsigned int skl_preferred_vco_freq;
1602 unsigned int max_cdclk_freq;
1604 unsigned int max_dotclk_freq;
1605 unsigned int rawclk_freq;
1606 unsigned int hpll_freq;
1607 unsigned int fdi_pll_freq;
1608 unsigned int czclk_freq;
1612 * The current logical cdclk state.
1613 * See intel_atomic_state.cdclk.logical
1615 * For reading holding any crtc lock is sufficient,
1616 * for writing must hold all of them.
1618 struct intel_cdclk_state logical;
1620 * The current actual cdclk state.
1621 * See intel_atomic_state.cdclk.actual
1623 struct intel_cdclk_state actual;
1624 /* The current hardware cdclk state */
1625 struct intel_cdclk_state hw;
1627 int force_min_cdclk;
1631 * wq - Driver workqueue for GEM.
1633 * NOTE: Work items scheduled here are not allowed to grab any modeset
1634 * locks, for otherwise the flushing done in the pageflip code will
1635 * result in deadlocks.
1637 struct workqueue_struct *wq;
1639 /* ordered wq for modesets */
1640 struct workqueue_struct *modeset_wq;
1642 /* Display functions */
1643 struct drm_i915_display_funcs display;
1645 /* PCH chipset type */
1646 enum intel_pch pch_type;
1647 unsigned short pch_id;
1649 unsigned long quirks;
1651 struct drm_atomic_state *modeset_restore_state;
1652 struct drm_modeset_acquire_ctx reset_ctx;
1654 struct i915_ggtt ggtt; /* VM representing the global address space */
1656 struct i915_gem_mm mm;
1657 DECLARE_HASHTABLE(mm_structs, 7);
1658 struct mutex mm_lock;
1660 struct intel_ppat ppat;
1662 /* Kernel Modesetting */
1664 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1665 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1667 #ifdef CONFIG_DEBUG_FS
1668 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1671 /* dpll and cdclk state is protected by connection_mutex */
1672 int num_shared_dpll;
1673 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1674 const struct intel_dpll_mgr *dpll_mgr;
1677 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1678 * Must be global rather than per dpll, because on some platforms
1679 * plls share registers.
1681 struct mutex dpll_lock;
1683 unsigned int active_crtcs;
1684 /* minimum acceptable cdclk for each pipe */
1685 int min_cdclk[I915_MAX_PIPES];
1686 /* minimum acceptable voltage level for each pipe */
1687 u8 min_voltage_level[I915_MAX_PIPES];
1689 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1691 struct i915_wa_list gt_wa_list;
1693 struct i915_frontbuffer_tracking fb_tracking;
1695 struct intel_atomic_helper {
1696 struct llist_head free_list;
1697 struct work_struct free_work;
1702 bool mchbar_need_disable;
1704 struct intel_l3_parity l3_parity;
1708 * Cannot be determined by PCIID. You must always read a register.
1713 * Protects RPS/RC6 register access and PCU communication.
1714 * Must be taken after struct_mutex if nested. Note that
1715 * this lock may be held for long periods of time when
1716 * talking to hw - so only take it when talking to hw!
1718 struct mutex pcu_lock;
1720 /* gen6+ GT PM state */
1721 struct intel_gen6_power_mgmt gt_pm;
1723 /* ilk-only ips/rps state. Everything in here is protected by the global
1724 * mchdev_lock in intel_pm.c */
1725 struct intel_ilk_power_mgmt ips;
1727 struct i915_power_domains power_domains;
1729 struct i915_psr psr;
1731 struct i915_gpu_error gpu_error;
1733 struct drm_i915_gem_object *vlv_pctx;
1735 /* list of fbdev register on this device */
1736 struct intel_fbdev *fbdev;
1737 struct work_struct fbdev_suspend_work;
1739 struct drm_property *broadcast_rgb_property;
1740 struct drm_property *force_audio_property;
1742 /* hda/i915 audio component */
1743 struct i915_audio_component *audio_component;
1744 bool audio_component_registered;
1746 * av_mutex - mutex for audio/video sync
1749 struct mutex av_mutex;
1750 int audio_power_refcount;
1754 struct list_head list;
1755 struct llist_head free_list;
1756 struct work_struct free_work;
1758 /* The hw wants to have a stable context identifier for the
1759 * lifetime of the context (for OA, PASID, faults, etc).
1760 * This is limited in execlists to 21 bits.
1763 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1764 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1765 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1766 struct list_head hw_id_list;
1771 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1772 u32 chv_phy_control;
1774 * Shadows for CHV DPLL_MD regs to keep the state
1775 * checker somewhat working in the presence hardware
1776 * crappiness (can't read out DPLL_MD for pipes B & C).
1778 u32 chv_dpll_md[I915_MAX_PIPES];
1782 bool power_domains_suspended;
1783 struct i915_suspend_saved_registers regfile;
1784 struct vlv_s0ix_state vlv_s0ix_state;
1787 I915_SAGV_UNKNOWN = 0,
1790 I915_SAGV_NOT_CONTROLLED
1795 * Raw watermark latency values:
1796 * in 0.1us units for WM0,
1797 * in 0.5us units for WM1+.
1806 * Raw watermark memory latency values
1807 * for SKL for all 8 levels
1812 /* current hardware state */
1814 struct ilk_wm_values hw;
1815 struct skl_ddb_values skl_hw;
1816 struct vlv_wm_values vlv;
1817 struct g4x_wm_values g4x;
1823 * Should be held around atomic WM register writing; also
1824 * protects * intel_crtc->wm.active and
1825 * cstate->wm.need_postvbl_update.
1827 struct mutex wm_mutex;
1830 * Set during HW readout of watermarks/DDB. Some platforms
1831 * need to know when we're still using BIOS-provided values
1832 * (which we don't fully trust).
1834 bool distrust_bios_wm;
1843 bool symmetric_memory;
1844 enum intel_dram_type {
1853 struct i915_runtime_pm runtime_pm;
1858 struct kobject *metrics_kobj;
1859 struct ctl_table_header *sysctl_header;
1862 * Lock associated with adding/modifying/removing OA configs
1863 * in dev_priv->perf.metrics_idr.
1865 struct mutex metrics_lock;
1868 * List of dynamic configurations, you need to hold
1869 * dev_priv->perf.metrics_lock to access it.
1871 struct idr metrics_idr;
1874 * Lock associated with anything below within this structure
1875 * except exclusive_stream.
1878 struct list_head streams;
1882 * The stream currently using the OA unit. If accessed
1883 * outside a syscall associated to its file
1884 * descriptor, you need to hold
1885 * dev_priv->drm.struct_mutex.
1887 struct i915_perf_stream *exclusive_stream;
1889 struct intel_context *pinned_ctx;
1890 u32 specific_ctx_id;
1891 u32 specific_ctx_id_mask;
1893 struct hrtimer poll_check_timer;
1894 wait_queue_head_t poll_wq;
1898 * For rate limiting any notifications of spurious
1899 * invalid OA reports
1901 struct ratelimit_state spurious_report_rs;
1904 int period_exponent;
1906 struct i915_oa_config test_config;
1909 struct i915_vma *vma;
1916 * Locks reads and writes to all head/tail state
1918 * Consider: the head and tail pointer state
1919 * needs to be read consistently from a hrtimer
1920 * callback (atomic context) and read() fop
1921 * (user context) with tail pointer updates
1922 * happening in atomic context and head updates
1923 * in user context and the (unlikely)
1924 * possibility of read() errors needing to
1925 * reset all head/tail state.
1927 * Note: Contention or performance aren't
1928 * currently a significant concern here
1929 * considering the relatively low frequency of
1930 * hrtimer callbacks (5ms period) and that
1931 * reads typically only happen in response to a
1932 * hrtimer event and likely complete before the
1935 * Note: This lock is not held *while* reading
1936 * and copying data to userspace so the value
1937 * of head observed in htrimer callbacks won't
1938 * represent any partial consumption of data.
1940 spinlock_t ptr_lock;
1943 * One 'aging' tail pointer and one 'aged'
1944 * tail pointer ready to used for reading.
1946 * Initial values of 0xffffffff are invalid
1947 * and imply that an update is required
1948 * (and should be ignored by an attempted
1956 * Index for the aged tail ready to read()
1959 unsigned int aged_tail_idx;
1962 * A monotonic timestamp for when the current
1963 * aging tail pointer was read; used to
1964 * determine when it is old enough to trust.
1966 u64 aging_timestamp;
1969 * Although we can always read back the head
1970 * pointer register, we prefer to avoid
1971 * trusting the HW state, just to avoid any
1972 * risk that some hardware condition could
1973 * somehow bump the head pointer unpredictably
1974 * and cause us to forward the wrong OA buffer
1975 * data to userspace.
1980 u32 gen7_latched_oastatus1;
1981 u32 ctx_oactxctrl_offset;
1982 u32 ctx_flexeu0_offset;
1985 * The RPT_ID/reason field for Gen8+ includes a bit
1986 * to determine if the CTX ID in the report is valid
1987 * but the specific bit differs between Gen 8 and 9
1989 u32 gen8_valid_ctx_bit;
1991 struct i915_oa_ops ops;
1992 const struct i915_oa_format *oa_formats;
1996 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1998 void (*cleanup_engine)(struct intel_engine_cs *engine);
2000 struct i915_gt_timelines {
2001 struct mutex mutex; /* protects list, tainted by GPU */
2002 struct list_head active_list;
2004 /* Pack multiple timelines' seqnos into the same page */
2005 spinlock_t hwsp_lock;
2006 struct list_head hwsp_free_list;
2009 intel_engine_mask_t active_engines;
2010 struct list_head active_rings;
2011 struct list_head closed_vma;
2012 u32 active_requests;
2015 * Is the GPU currently considered idle, or busy executing
2016 * userspace requests? Whilst idle, we allow runtime power
2017 * management to power down the hardware and display clocks.
2018 * In order to reduce the effect on performance, there
2019 * is a slight delay before we do so.
2021 intel_wakeref_t awake;
2024 * We leave the user IRQ off as much as possible,
2025 * but this means that requests will finish and never
2026 * be retired once the system goes idle. Set a timer to
2027 * fire periodically while the ring is running. When it
2028 * fires, go retire requests.
2030 struct delayed_work retire_work;
2033 * When we detect an idle GPU, we want to turn on
2034 * powersaving features. So once we see that there
2035 * are no more requests outstanding and no more
2036 * arrive within a small period of time, we fire
2037 * off the idle_work.
2039 struct delayed_work idle_work;
2041 ktime_t last_init_time;
2043 struct i915_vma *scratch;
2046 /* For i945gm vblank irq vs. C3 workaround */
2048 struct work_struct work;
2049 struct pm_qos_request pm_qos;
2050 u8 c3_disable_latency;
2054 /* perform PHY state sanity checks? */
2055 bool chv_phy_assert[2];
2059 /* Used to save the pipe-to-encoder mapping for audio */
2060 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2062 /* necessary resource sharing with HDMI LPE audio driver. */
2064 struct platform_device *platdev;
2068 struct i915_pmu pmu;
2070 struct i915_hdcp_comp_master *hdcp_master;
2071 bool hdcp_comp_added;
2073 /* Mutex to protect the above hdcp component related values. */
2074 struct mutex hdcp_comp_mutex;
2077 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2078 * will be rejected. Instead look for a better place.
2082 struct dram_dimm_info {
2083 u8 size, width, ranks;
2086 struct dram_channel_info {
2087 struct dram_dimm_info dimm_l, dimm_s;
2092 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2094 return container_of(dev, struct drm_i915_private, drm);
2097 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2099 return to_i915(dev_get_drvdata(kdev));
2102 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2104 return container_of(wopcm, struct drm_i915_private, wopcm);
2107 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2109 return container_of(guc, struct drm_i915_private, guc);
2112 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2114 return container_of(huc, struct drm_i915_private, huc);
2117 static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
2119 return container_of(uncore, struct drm_i915_private, uncore);
2122 /* Simple iterator over all initialised engines */
2123 #define for_each_engine(engine__, dev_priv__, id__) \
2125 (id__) < I915_NUM_ENGINES; \
2127 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2129 /* Iterator over subset of engines selected by mask */
2130 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2131 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
2133 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2136 enum hdmi_force_audio {
2137 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2138 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2139 HDMI_AUDIO_AUTO, /* trust EDID */
2140 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2143 #define I915_GTT_OFFSET_NONE ((u32)-1)
2146 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2147 * considered to be the frontbuffer for the given plane interface-wise. This
2148 * doesn't mean that the hw necessarily already scans it out, but that any
2149 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2151 * We have one bit per pipe and per scanout plane type.
2153 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2154 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2155 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2156 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2157 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2159 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2160 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2161 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2162 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2163 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2166 * Optimised SGL iterator for GEM objects
2168 static __always_inline struct sgt_iter {
2169 struct scatterlist *sgp;
2176 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2177 struct sgt_iter s = { .sgp = sgl };
2180 s.max = s.curr = s.sgp->offset;
2181 s.max += s.sgp->length;
2183 s.dma = sg_dma_address(s.sgp);
2185 s.pfn = page_to_pfn(sg_page(s.sgp));
2191 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2194 if (unlikely(sg_is_chain(sg)))
2195 sg = sg_chain_ptr(sg);
2200 * __sg_next - return the next scatterlist entry in a list
2201 * @sg: The current sg entry
2204 * If the entry is the last, return NULL; otherwise, step to the next
2205 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2206 * otherwise just return the pointer to the current element.
2208 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2210 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2214 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2215 * @__dmap: DMA address (output)
2216 * @__iter: 'struct sgt_iter' (iterator state, internal)
2217 * @__sgt: sg_table to iterate over (input)
2219 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2220 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2221 ((__dmap) = (__iter).dma + (__iter).curr); \
2222 (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \
2223 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2226 * for_each_sgt_page - iterate over the pages of the given sg_table
2227 * @__pp: page pointer (output)
2228 * @__iter: 'struct sgt_iter' (iterator state, internal)
2229 * @__sgt: sg_table to iterate over (input)
2231 #define for_each_sgt_page(__pp, __iter, __sgt) \
2232 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2233 ((__pp) = (__iter).pfn == 0 ? NULL : \
2234 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2235 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2236 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2238 bool i915_sg_trim(struct sg_table *orig_st);
2240 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2242 unsigned int page_sizes;
2246 GEM_BUG_ON(sg->offset);
2247 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2248 page_sizes |= sg->length;
2255 static inline unsigned int i915_sg_segment_size(void)
2257 unsigned int size = swiotlb_max_segment();
2260 return SCATTERLIST_MAX_SEGMENT;
2262 size = rounddown(size, PAGE_SIZE);
2263 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2264 if (size < PAGE_SIZE)
2270 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
2271 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2272 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2274 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
2275 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2277 #define REVID_FOREVER 0xff
2278 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2280 #define INTEL_GEN_MASK(s, e) ( \
2281 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2282 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2283 GENMASK((e) - 1, (s) - 1))
2285 /* Returns true if Gen is in inclusive range [Start, End] */
2286 #define IS_GEN_RANGE(dev_priv, s, e) \
2287 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2289 #define IS_GEN(dev_priv, n) \
2290 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2291 INTEL_INFO(dev_priv)->gen == (n))
2294 * Return true if revision is in range [since,until] inclusive.
2296 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2298 #define IS_REVID(p, since, until) \
2299 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2301 static __always_inline unsigned int
2302 __platform_mask_index(const struct intel_runtime_info *info,
2303 enum intel_platform p)
2305 const unsigned int pbits =
2306 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2308 /* Expand the platform_mask array if this fails. */
2309 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
2310 pbits * ARRAY_SIZE(info->platform_mask));
2315 static __always_inline unsigned int
2316 __platform_mask_bit(const struct intel_runtime_info *info,
2317 enum intel_platform p)
2319 const unsigned int pbits =
2320 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2322 return p % pbits + INTEL_SUBPLATFORM_BITS;
2326 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
2328 const unsigned int pi = __platform_mask_index(info, p);
2330 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
2333 static __always_inline bool
2334 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
2336 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2337 const unsigned int pi = __platform_mask_index(info, p);
2338 const unsigned int pb = __platform_mask_bit(info, p);
2340 BUILD_BUG_ON(!__builtin_constant_p(p));
2342 return info->platform_mask[pi] & BIT(pb);
2345 static __always_inline bool
2346 IS_SUBPLATFORM(const struct drm_i915_private *i915,
2347 enum intel_platform p, unsigned int s)
2349 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2350 const unsigned int pi = __platform_mask_index(info, p);
2351 const unsigned int pb = __platform_mask_bit(info, p);
2352 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
2353 const u32 mask = info->platform_mask[pi];
2355 BUILD_BUG_ON(!__builtin_constant_p(p));
2356 BUILD_BUG_ON(!__builtin_constant_p(s));
2357 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
2359 /* Shift and test on the MSB position so sign flag can be used. */
2360 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
2363 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
2365 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2366 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2367 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2368 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2369 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2370 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2371 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2372 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2373 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2374 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2375 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2376 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2377 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2378 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2379 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2380 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
2381 #define IS_IRONLAKE_M(dev_priv) \
2382 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
2383 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2384 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2385 INTEL_INFO(dev_priv)->gt == 1)
2386 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2387 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2388 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2389 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2390 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2391 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2392 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2393 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2394 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2395 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2396 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2397 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
2398 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2399 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2400 #define IS_BDW_ULT(dev_priv) \
2401 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
2402 #define IS_BDW_ULX(dev_priv) \
2403 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
2404 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2405 INTEL_INFO(dev_priv)->gt == 3)
2406 #define IS_HSW_ULT(dev_priv) \
2407 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
2408 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2409 INTEL_INFO(dev_priv)->gt == 3)
2410 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2411 INTEL_INFO(dev_priv)->gt == 1)
2412 /* ULX machines are also considered ULT. */
2413 #define IS_HSW_ULX(dev_priv) \
2414 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
2415 #define IS_SKL_ULT(dev_priv) \
2416 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
2417 #define IS_SKL_ULX(dev_priv) \
2418 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
2419 #define IS_KBL_ULT(dev_priv) \
2420 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
2421 #define IS_KBL_ULX(dev_priv) \
2422 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
2423 #define IS_AML_ULX(dev_priv) \
2424 (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
2425 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
2426 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2427 INTEL_INFO(dev_priv)->gt == 2)
2428 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2429 INTEL_INFO(dev_priv)->gt == 3)
2430 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2431 INTEL_INFO(dev_priv)->gt == 4)
2432 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2433 INTEL_INFO(dev_priv)->gt == 2)
2434 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2435 INTEL_INFO(dev_priv)->gt == 3)
2436 #define IS_CFL_ULT(dev_priv) \
2437 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2438 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2439 INTEL_INFO(dev_priv)->gt == 2)
2440 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2441 INTEL_INFO(dev_priv)->gt == 3)
2442 #define IS_CNL_WITH_PORT_F(dev_priv) \
2443 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2444 #define IS_ICL_WITH_PORT_F(dev_priv) \
2445 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2447 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2449 #define SKL_REVID_A0 0x0
2450 #define SKL_REVID_B0 0x1
2451 #define SKL_REVID_C0 0x2
2452 #define SKL_REVID_D0 0x3
2453 #define SKL_REVID_E0 0x4
2454 #define SKL_REVID_F0 0x5
2455 #define SKL_REVID_G0 0x6
2456 #define SKL_REVID_H0 0x7
2458 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2460 #define BXT_REVID_A0 0x0
2461 #define BXT_REVID_A1 0x1
2462 #define BXT_REVID_B0 0x3
2463 #define BXT_REVID_B_LAST 0x8
2464 #define BXT_REVID_C0 0x9
2466 #define IS_BXT_REVID(dev_priv, since, until) \
2467 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2469 #define KBL_REVID_A0 0x0
2470 #define KBL_REVID_B0 0x1
2471 #define KBL_REVID_C0 0x2
2472 #define KBL_REVID_D0 0x3
2473 #define KBL_REVID_E0 0x4
2475 #define IS_KBL_REVID(dev_priv, since, until) \
2476 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2478 #define GLK_REVID_A0 0x0
2479 #define GLK_REVID_A1 0x1
2481 #define IS_GLK_REVID(dev_priv, since, until) \
2482 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2484 #define CNL_REVID_A0 0x0
2485 #define CNL_REVID_B0 0x1
2486 #define CNL_REVID_C0 0x2
2488 #define IS_CNL_REVID(p, since, until) \
2489 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2491 #define ICL_REVID_A0 0x0
2492 #define ICL_REVID_A2 0x1
2493 #define ICL_REVID_B0 0x3
2494 #define ICL_REVID_B2 0x4
2495 #define ICL_REVID_C0 0x5
2497 #define IS_ICL_REVID(p, since, until) \
2498 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2500 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2501 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2502 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2504 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2506 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
2507 unsigned int first__ = (first); \
2508 unsigned int count__ = (count); \
2509 (INTEL_INFO(dev_priv)->engine_mask & \
2510 GENMASK(first__ + count__ - 1, first__)) >> first__; \
2512 #define VDBOX_MASK(dev_priv) \
2513 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2514 #define VEBOX_MASK(dev_priv) \
2515 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2517 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2518 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2519 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
2520 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2521 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2523 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2525 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2526 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2527 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2528 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2529 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2530 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2532 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2534 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2535 #define HAS_PPGTT(dev_priv) \
2536 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2537 #define HAS_FULL_PPGTT(dev_priv) \
2538 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2540 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2541 GEM_BUG_ON((sizes) == 0); \
2542 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2545 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2546 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2547 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2549 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2550 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2552 /* WaRsDisableCoarsePowerGating:skl,cnl */
2553 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2554 (IS_CANNONLAKE(dev_priv) || \
2555 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2557 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2558 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2559 IS_GEMINILAKE(dev_priv) || \
2560 IS_KABYLAKE(dev_priv))
2562 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2563 * rows, which changed the alignment requirements and fence programming.
2565 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2566 !(IS_I915G(dev_priv) || \
2567 IS_I915GM(dev_priv)))
2568 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2569 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2571 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2572 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2573 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2575 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2577 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2579 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2580 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2581 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2582 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2584 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2585 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2586 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2588 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2590 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2591 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2593 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2596 * For now, anything with a GuC requires uCode loading, and then supports
2597 * command submission once loaded. But these are logically independent
2598 * properties, so we have separate macros to test them.
2600 #define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
2601 #define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
2602 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2603 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2605 /* For now, anything with a GuC has also HuC */
2606 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2607 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2609 /* Having a GuC is not the same as using a GuC */
2610 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2611 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2612 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2614 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2616 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2617 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2618 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2619 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2620 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2621 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2622 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2623 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2624 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2625 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2626 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2627 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2628 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2629 #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
2630 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2631 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2632 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2633 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2635 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2636 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2637 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2638 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2639 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2640 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2641 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2642 #define HAS_PCH_LPT_LP(dev_priv) \
2643 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2644 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2645 #define HAS_PCH_LPT_H(dev_priv) \
2646 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2647 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2648 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2649 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2650 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2651 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2653 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2655 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2657 /* DPF == dynamic parity feature */
2658 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2659 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2660 2 : HAS_L3_DPF(dev_priv))
2662 #define GT_FREQUENCY_MULTIPLIER 50
2663 #define GEN9_FREQ_SCALER 3
2665 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2667 #include "i915_trace.h"
2669 static inline bool intel_vtd_active(void)
2671 #ifdef CONFIG_INTEL_IOMMU
2672 if (intel_iommu_gfx_mapped)
2678 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2680 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2684 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2686 return IS_BROXTON(dev_priv) && intel_vtd_active();
2691 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2692 const char *fmt, ...);
2694 #define i915_report_error(dev_priv, fmt, ...) \
2695 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2697 #ifdef CONFIG_COMPAT
2698 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2701 #define i915_compat_ioctl NULL
2703 extern const struct dev_pm_ops i915_pm_ops;
2705 extern int i915_driver_load(struct pci_dev *pdev,
2706 const struct pci_device_id *ent);
2707 extern void i915_driver_unload(struct drm_device *dev);
2709 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2710 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2711 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2712 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2713 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2714 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2715 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2717 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2718 int intel_engines_init(struct drm_i915_private *dev_priv);
2720 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2722 /* intel_hotplug.c */
2723 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2724 u32 pin_mask, u32 long_mask);
2725 void intel_hpd_init(struct drm_i915_private *dev_priv);
2726 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2727 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2728 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2730 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2731 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2734 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2736 unsigned long delay;
2738 if (unlikely(!i915_modparams.enable_hangcheck))
2741 /* Don't continually defer the hangcheck so that it is always run at
2742 * least once after work has been scheduled on any ring. Otherwise,
2743 * we will ignore a hung ring if a second ring is kept busy.
2746 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2747 queue_delayed_work(system_long_wq,
2748 &dev_priv->gpu_error.hangcheck_work, delay);
2751 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2752 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2753 int intel_irq_install(struct drm_i915_private *dev_priv);
2754 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2756 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2758 return dev_priv->gvt;
2761 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2763 return dev_priv->vgpu.active;
2766 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2769 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2773 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2776 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2777 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2778 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2781 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2783 u32 enabled_irq_mask);
2785 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
2787 ilk_update_display_irq(dev_priv, bits, bits);
2790 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
2792 ilk_update_display_irq(dev_priv, bits, 0);
2794 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2797 u32 enabled_irq_mask);
2798 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2799 enum pipe pipe, u32 bits)
2801 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2803 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2804 enum pipe pipe, u32 bits)
2806 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2808 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2810 u32 enabled_irq_mask);
2812 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
2814 ibx_display_interrupt_update(dev_priv, bits, bits);
2817 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
2819 ibx_display_interrupt_update(dev_priv, bits, 0);
2823 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2824 struct drm_file *file_priv);
2825 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2826 struct drm_file *file_priv);
2827 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2828 struct drm_file *file_priv);
2829 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2830 struct drm_file *file_priv);
2831 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2832 struct drm_file *file_priv);
2833 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2834 struct drm_file *file_priv);
2835 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2836 struct drm_file *file_priv);
2837 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2838 struct drm_file *file_priv);
2839 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2840 struct drm_file *file_priv);
2841 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2842 struct drm_file *file_priv);
2843 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2844 struct drm_file *file);
2845 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2846 struct drm_file *file);
2847 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2848 struct drm_file *file_priv);
2849 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2850 struct drm_file *file_priv);
2851 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2852 struct drm_file *file_priv);
2853 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2854 struct drm_file *file_priv);
2855 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2856 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2857 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2858 struct drm_file *file);
2859 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2860 struct drm_file *file_priv);
2861 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv);
2863 void i915_gem_sanitize(struct drm_i915_private *i915);
2864 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2865 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2866 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2867 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2868 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2870 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2871 const struct drm_i915_gem_object_ops *ops);
2872 struct drm_i915_gem_object *
2873 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2874 struct drm_i915_gem_object *
2875 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2876 const void *data, size_t size);
2877 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2878 void i915_gem_free_object(struct drm_gem_object *obj);
2880 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2882 if (!atomic_read(&i915->mm.free_count))
2885 /* A single pass should suffice to release all the freed objects (along
2886 * most call paths) , but be a little more paranoid in that freeing
2887 * the objects does take a little amount of time, during which the rcu
2888 * callbacks could have added new objects into the freed list, and
2889 * armed the work again.
2893 } while (flush_work(&i915->mm.free_work));
2896 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2899 * Similar to objects above (see i915_gem_drain_freed-objects), in
2900 * general we have workers that are armed by RCU and then rearm
2901 * themselves in their callbacks. To be paranoid, we need to
2902 * drain the workqueue a second time after waiting for the RCU
2903 * grace period so that we catch work queued via RCU from the first
2904 * pass. As neither drain_workqueue() nor flush_workqueue() report
2905 * a result, we make an assumption that we only don't require more
2906 * than 2 passes to catch all recursive RCU delayed work.
2912 i915_gem_drain_freed_objects(i915);
2913 drain_workqueue(i915->wq);
2917 struct i915_vma * __must_check
2918 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2919 const struct i915_ggtt_view *view,
2924 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2925 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2927 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2929 static inline int __sg_page_count(const struct scatterlist *sg)
2931 return sg->length >> PAGE_SHIFT;
2934 struct scatterlist *
2935 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2936 unsigned int n, unsigned int *offset);
2939 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2943 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2947 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2950 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2951 struct sg_table *pages,
2952 unsigned int sg_page_sizes);
2953 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2955 static inline int __must_check
2956 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2958 might_lock(&obj->mm.lock);
2960 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2963 return __i915_gem_object_get_pages(obj);
2967 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2969 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2973 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2975 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2977 atomic_inc(&obj->mm.pages_pin_count);
2981 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
2983 return atomic_read(&obj->mm.pages_pin_count);
2987 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2989 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2990 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
2992 atomic_dec(&obj->mm.pages_pin_count);
2996 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2998 __i915_gem_object_unpin_pages(obj);
3001 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock/struct_mutex */
3003 I915_MM_SHRINKER /* called "recursively" from direct-reclaim-esque */
3006 int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3007 enum i915_mm_subclass subclass);
3008 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3010 enum i915_map_type {
3013 #define I915_MAP_OVERRIDE BIT(31)
3014 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3015 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3018 static inline enum i915_map_type
3019 i915_coherent_map_type(struct drm_i915_private *i915)
3021 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
3025 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3026 * @obj: the object to map into kernel address space
3027 * @type: the type of mapping, used to select pgprot_t
3029 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3030 * pages and then returns a contiguous mapping of the backing storage into
3031 * the kernel address space. Based on the @type of mapping, the PTE will be
3032 * set to either WriteBack or WriteCombine (via pgprot_t).
3034 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3035 * mapping is no longer required.
3037 * Returns the pointer through which to access the mapped object, or an
3038 * ERR_PTR() on error.
3040 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3041 enum i915_map_type type);
3043 void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
3044 unsigned long offset,
3045 unsigned long size);
3046 static inline void i915_gem_object_flush_map(struct drm_i915_gem_object *obj)
3048 __i915_gem_object_flush_map(obj, 0, obj->base.size);
3052 * i915_gem_object_unpin_map - releases an earlier mapping
3053 * @obj: the object to unmap
3055 * After pinning the object and mapping its pages, once you are finished
3056 * with your access, call i915_gem_object_unpin_map() to release the pin
3057 * upon the mapping. Once the pin count reaches zero, that mapping may be
3060 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3062 i915_gem_object_unpin_pages(obj);
3065 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3066 unsigned int *needs_clflush);
3067 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3068 unsigned int *needs_clflush);
3069 #define CLFLUSH_BEFORE BIT(0)
3070 #define CLFLUSH_AFTER BIT(1)
3071 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3074 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3076 i915_gem_object_unpin_pages(obj);
3079 static inline int __must_check
3080 i915_mutex_lock_interruptible(struct drm_device *dev)
3082 return mutex_lock_interruptible(&dev->struct_mutex);
3085 int i915_gem_dumb_create(struct drm_file *file_priv,
3086 struct drm_device *dev,
3087 struct drm_mode_create_dumb *args);
3088 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3089 u32 handle, u64 *offset);
3090 int i915_gem_mmap_gtt_version(void);
3092 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3093 struct drm_i915_gem_object *new,
3094 unsigned frontbuffer_bits);
3096 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3098 static inline bool __i915_wedged(struct i915_gpu_error *error)
3100 return unlikely(test_bit(I915_WEDGED, &error->flags));
3103 static inline bool i915_reset_failed(struct drm_i915_private *i915)
3105 return __i915_wedged(&i915->gpu_error);
3108 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3110 return READ_ONCE(error->reset_count);
3113 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3114 struct intel_engine_cs *engine)
3116 return READ_ONCE(error->reset_engine_count[engine->id]);
3119 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3120 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3122 void i915_gem_init_mmio(struct drm_i915_private *i915);
3123 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3124 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3125 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3126 void i915_gem_fini(struct drm_i915_private *dev_priv);
3127 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3128 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3129 unsigned int flags, long timeout);
3130 void i915_gem_suspend(struct drm_i915_private *dev_priv);
3131 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3132 void i915_gem_resume(struct drm_i915_private *dev_priv);
3133 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3134 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3137 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3139 const struct i915_sched_attr *attr);
3140 #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
3143 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3145 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3147 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3148 struct i915_vma * __must_check
3149 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3151 const struct i915_ggtt_view *view,
3152 unsigned int flags);
3153 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3154 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3156 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3157 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3159 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3160 enum i915_cache_level cache_level);
3162 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3163 struct dma_buf *dma_buf);
3165 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3166 struct drm_gem_object *gem_obj, int flags);
3168 static inline struct i915_hw_ppgtt *
3169 i915_vm_to_ppgtt(struct i915_address_space *vm)
3171 return container_of(vm, struct i915_hw_ppgtt, vm);
3174 /* i915_gem_fence_reg.c */
3175 struct drm_i915_fence_reg *
3176 i915_reserve_fence(struct drm_i915_private *dev_priv);
3177 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3179 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3181 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3182 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3183 struct sg_table *pages);
3184 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3185 struct sg_table *pages);
3187 static inline struct i915_gem_context *
3188 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3190 return idr_find(&file_priv->context_idr, id);
3193 static inline struct i915_gem_context *
3194 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3196 struct i915_gem_context *ctx;
3199 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3200 if (ctx && !kref_get_unless_zero(&ctx->ref))
3207 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3208 struct drm_file *file);
3209 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3210 struct drm_file *file);
3211 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3212 struct drm_file *file);
3213 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3214 struct intel_context *ce,
3217 /* i915_gem_evict.c */
3218 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3219 u64 min_size, u64 alignment,
3220 unsigned cache_level,
3223 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3224 struct drm_mm_node *node,
3225 unsigned int flags);
3226 int i915_gem_evict_vm(struct i915_address_space *vm);
3228 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3230 /* belongs in i915_gem_gtt.h */
3231 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3234 if (INTEL_GEN(dev_priv) < 6)
3235 intel_gtt_chipset_flush();
3238 /* i915_gem_stolen.c */
3239 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3240 struct drm_mm_node *node, u64 size,
3241 unsigned alignment);
3242 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3243 struct drm_mm_node *node, u64 size,
3244 unsigned alignment, u64 start,
3246 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3247 struct drm_mm_node *node);
3248 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3249 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
3250 struct drm_i915_gem_object *
3251 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3252 resource_size_t size);
3253 struct drm_i915_gem_object *
3254 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3255 resource_size_t stolen_offset,
3256 resource_size_t gtt_offset,
3257 resource_size_t size);
3259 /* i915_gem_internal.c */
3260 struct drm_i915_gem_object *
3261 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3264 /* i915_gem_shrinker.c */
3265 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3266 unsigned long target,
3267 unsigned long *nr_scanned,
3269 #define I915_SHRINK_PURGEABLE 0x1
3270 #define I915_SHRINK_UNBOUND 0x2
3271 #define I915_SHRINK_BOUND 0x4
3272 #define I915_SHRINK_ACTIVE 0x8
3273 #define I915_SHRINK_VMAPS 0x10
3274 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3275 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3276 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3277 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
3278 struct mutex *mutex);
3280 /* i915_gem_tiling.c */
3281 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3283 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3285 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3286 i915_gem_object_is_tiled(obj);
3289 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3290 unsigned int tiling, unsigned int stride);
3291 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3292 unsigned int tiling, unsigned int stride);
3294 /* i915_debugfs.c */
3295 #ifdef CONFIG_DEBUG_FS
3296 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3297 int i915_debugfs_connector_add(struct drm_connector *connector);
3298 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3300 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3301 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3303 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3306 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3308 /* i915_cmd_parser.c */
3309 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3310 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3311 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3312 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3313 struct drm_i915_gem_object *batch_obj,
3314 struct drm_i915_gem_object *shadow_batch_obj,
3315 u32 batch_start_offset,
3320 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3321 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3322 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3323 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3325 /* i915_suspend.c */
3326 extern int i915_save_state(struct drm_i915_private *dev_priv);
3327 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3330 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3331 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3333 /* intel_lpe_audio.c */
3334 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3335 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3336 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3337 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3338 enum pipe pipe, enum port port,
3339 const void *eld, int ls_clock, bool dp_output);
3342 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3343 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3344 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3346 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3348 extern struct i2c_adapter *
3349 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3350 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3351 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3352 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3354 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3356 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3359 void intel_bios_init(struct drm_i915_private *dev_priv);
3360 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3361 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3362 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3363 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3364 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3365 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3366 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3367 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3368 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3370 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3372 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
3376 extern void intel_register_dsm_handler(void);
3377 extern void intel_unregister_dsm_handler(void);
3379 static inline void intel_register_dsm_handler(void) { return; }
3380 static inline void intel_unregister_dsm_handler(void) { return; }
3381 #endif /* CONFIG_ACPI */
3383 /* intel_device_info.c */
3384 static inline struct intel_device_info *
3385 mkwrite_device_info(struct drm_i915_private *dev_priv)
3387 return (struct intel_device_info *)INTEL_INFO(dev_priv);
3390 static inline struct intel_sseu
3391 intel_device_default_sseu(struct drm_i915_private *i915)
3393 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
3394 struct intel_sseu value = {
3395 .slice_mask = sseu->slice_mask,
3396 .subslice_mask = sseu->subslice_mask[0],
3397 .min_eus_per_subslice = sseu->max_eus_per_subslice,
3398 .max_eus_per_subslice = sseu->max_eus_per_subslice,
3405 extern void intel_modeset_init_hw(struct drm_device *dev);
3406 extern int intel_modeset_init(struct drm_device *dev);
3407 extern void intel_modeset_cleanup(struct drm_device *dev);
3408 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3410 extern void intel_display_resume(struct drm_device *dev);
3411 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3412 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3413 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3414 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3415 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3416 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3418 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3420 void intel_dsc_enable(struct intel_encoder *encoder,
3421 const struct intel_crtc_state *crtc_state);
3422 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
3424 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3425 struct drm_file *file);
3428 extern struct intel_overlay_error_state *
3429 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3430 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3431 struct intel_overlay_error_state *error);
3433 extern struct intel_display_error_state *
3434 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3435 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3436 struct intel_display_error_state *error);
3438 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3439 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3440 u32 val, int fast_timeout_us,
3441 int slow_timeout_ms);
3442 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3443 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3445 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3446 u32 reply_mask, u32 reply, int timeout_base_ms);
3448 /* intel_sideband.c */
3449 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3450 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3451 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3452 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3453 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3454 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3455 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3456 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3457 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3458 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3459 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3460 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3461 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3462 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3463 enum intel_sbi_destination destination);
3464 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3465 enum intel_sbi_destination destination);
3466 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3467 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3469 /* intel_dpio_phy.c */
3470 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3471 enum dpio_phy *phy, enum dpio_channel *ch);
3472 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3473 enum port port, u32 margin, u32 scale,
3474 u32 enable, u32 deemphasis);
3475 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3476 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3477 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3479 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3481 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
3482 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3483 u8 lane_lat_optim_mask);
3484 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3486 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3487 u32 deemph_reg_value, u32 margin_reg_value,
3488 bool uniq_trans_scale);
3489 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3490 const struct intel_crtc_state *crtc_state,
3492 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3493 const struct intel_crtc_state *crtc_state);
3494 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3495 const struct intel_crtc_state *crtc_state);
3496 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3497 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3498 const struct intel_crtc_state *old_crtc_state);
3500 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3501 u32 demph_reg_value, u32 preemph_reg_value,
3502 u32 uniqtranscale_reg_value, u32 tx3_demph);
3503 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3504 const struct intel_crtc_state *crtc_state);
3505 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3506 const struct intel_crtc_state *crtc_state);
3507 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3508 const struct intel_crtc_state *old_crtc_state);
3510 /* intel_combo_phy.c */
3511 void icl_combo_phys_init(struct drm_i915_private *dev_priv);
3512 void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);
3513 void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
3514 void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
3516 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3517 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3518 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3519 const i915_reg_t reg);
3521 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3523 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3524 const i915_reg_t reg)
3526 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3529 #define __I915_REG_OP(op__, dev_priv__, ...) \
3530 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
3532 #define I915_READ8(reg__) __I915_REG_OP(read8, dev_priv, (reg__))
3533 #define I915_WRITE8(reg__, val__) __I915_REG_OP(write8, dev_priv, (reg__), (val__))
3535 #define I915_READ16(reg__) __I915_REG_OP(read16, dev_priv, (reg__))
3536 #define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))
3537 #define I915_READ16_NOTRACE(reg__) __I915_REG_OP(read16_notrace, dev_priv, (reg__))
3538 #define I915_WRITE16_NOTRACE(reg__, val__) __I915_REG_OP(write16_notrace, dev_priv, (reg__), (val__))
3540 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
3541 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
3542 #define I915_READ_NOTRACE(reg__) __I915_REG_OP(read_notrace, dev_priv, (reg__))
3543 #define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
3545 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3546 * will be implemented using 2 32-bit writes in an arbitrary order with
3547 * an arbitrary delay between them. This can cause the hardware to
3548 * act upon the intermediate value, possibly leading to corruption and
3549 * machine death. For this reason we do not support I915_WRITE64, or
3550 * dev_priv->uncore.funcs.mmio_writeq.
3552 * When reading a 64-bit value as two 32-bit values, the delay may cause
3553 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3554 * occasionally a 64-bit register does not actualy support a full readq
3555 * and must be read using two 32-bit reads.
3557 * You have been warned.
3559 #define I915_READ64(reg__) __I915_REG_OP(read64, dev_priv, (reg__))
3560 #define I915_READ64_2x32(lower_reg__, upper_reg__) \
3561 __I915_REG_OP(read64_2x32, dev_priv, (lower_reg__), (upper_reg__))
3563 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
3564 #define POSTING_READ16(reg__) __I915_REG_OP(posting_read16, dev_priv, (reg__))
3566 /* These are untraced mmio-accessors that are only valid to be used inside
3567 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3570 * Think twice, and think again, before using these.
3572 * As an example, these accessors can possibly be used between:
3574 * spin_lock_irq(&dev_priv->uncore.lock);
3575 * intel_uncore_forcewake_get__locked();
3579 * intel_uncore_forcewake_put__locked();
3580 * spin_unlock_irq(&dev_priv->uncore.lock);
3583 * Note: some registers may not need forcewake held, so
3584 * intel_uncore_forcewake_{get,put} can be omitted, see
3585 * intel_uncore_forcewake_for_reg().
3587 * Certain architectures will die if the same cacheline is concurrently accessed
3588 * by different clients (e.g. on Ivybridge). Access to registers should
3589 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3590 * a more localised lock guarding all access to that bank of registers.
3592 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
3593 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
3594 #define I915_WRITE64_FW(reg__, val__) __I915_REG_OP(write64_fw, dev_priv, (reg__), (val__))
3595 #define POSTING_READ_FW(reg__) __I915_REG_OP(posting_read_fw, dev_priv, (reg__))
3597 /* "Broadcast RGB" property */
3598 #define INTEL_BROADCAST_RGB_AUTO 0
3599 #define INTEL_BROADCAST_RGB_FULL 1
3600 #define INTEL_BROADCAST_RGB_LIMITED 2
3602 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3604 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3605 return VLV_VGACNTRL;
3606 else if (INTEL_GEN(dev_priv) >= 5)
3607 return CPU_VGACNTRL;
3612 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3614 unsigned long j = msecs_to_jiffies(m);
3616 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3619 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3621 /* nsecs_to_jiffies64() does not guard against overflow */
3622 if (NSEC_PER_SEC % HZ &&
3623 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3624 return MAX_JIFFY_OFFSET;
3626 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3630 * If you need to wait X milliseconds between events A and B, but event B
3631 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3632 * when event A happened, then just before event B you call this function and
3633 * pass the timestamp as the first argument, and X as the second argument.
3636 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3638 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3641 * Don't re-read the value of "jiffies" every time since it may change
3642 * behind our back and break the math.
3644 tmp_jiffies = jiffies;
3645 target_jiffies = timestamp_jiffies +
3646 msecs_to_jiffies_timeout(to_wait_ms);
3648 if (time_after(target_jiffies, tmp_jiffies)) {
3649 remaining_jiffies = target_jiffies - tmp_jiffies;
3650 while (remaining_jiffies)
3652 schedule_timeout_uninterruptible(remaining_jiffies);
3656 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3657 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3659 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3660 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3661 * perform the operation. To check beforehand, pass in the parameters to
3662 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3663 * you only need to pass in the minor offsets, page-aligned pointers are
3666 * For just checking for SSE4.1, in the foreknowledge that the future use
3667 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3669 #define i915_can_memcpy_from_wc(dst, src, len) \
3670 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3672 #define i915_has_memcpy_from_wc() \
3673 i915_memcpy_from_wc(NULL, NULL, 0)
3676 int remap_io_mapping(struct vm_area_struct *vma,
3677 unsigned long addr, unsigned long pfn, unsigned long size,
3678 struct io_mapping *iomap);
3680 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3682 if (INTEL_GEN(i915) >= 10)
3683 return CNL_HWS_CSB_WRITE_INDEX;
3685 return I915_HWS_CSB_WRITE_INDEX;
3688 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
3690 return i915_ggtt_offset(i915->gt.scratch);