1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_atomic.h>
58 #include <drm/drm_connector.h>
59 #include <drm/i915_mei_hdcp_interface.h>
61 #include "i915_fixed.h"
62 #include "i915_params.h"
64 #include "i915_utils.h"
66 #include "gt/intel_lrc.h"
67 #include "gt/intel_engine.h"
68 #include "gt/intel_workarounds.h"
70 #include "intel_bios.h"
71 #include "intel_device_info.h"
72 #include "intel_display.h"
73 #include "intel_dpll_mgr.h"
74 #include "intel_frontbuffer.h"
75 #include "intel_opregion.h"
76 #include "intel_runtime_pm.h"
78 #include "intel_uncore.h"
79 #include "intel_wakeref.h"
80 #include "intel_wopcm.h"
83 #include "i915_gem_context.h"
84 #include "i915_gem_fence_reg.h"
85 #include "i915_gem_object.h"
86 #include "i915_gem_gtt.h"
87 #include "i915_gpu_error.h"
88 #include "i915_request.h"
89 #include "i915_scheduler.h"
90 #include "i915_timeline.h"
93 #include "intel_gvt.h"
95 /* General customization:
98 #define DRIVER_NAME "i915"
99 #define DRIVER_DESC "Intel Graphics"
100 #define DRIVER_DATE "20190524"
101 #define DRIVER_TIMESTAMP 1558719322
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105 * which may not necessarily be a user visible problem. This will either
106 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107 * enable distros and users to tailor their preferred amount of i915 abrt
110 #define I915_STATE_WARN(condition, format...) ({ \
111 int __ret_warn_on = !!(condition); \
112 if (unlikely(__ret_warn_on)) \
113 if (!WARN(i915_modparams.verbose_state_checks, format)) \
115 unlikely(__ret_warn_on); \
118 #define I915_STATE_WARN_ON(x) \
119 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
121 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
123 bool __i915_inject_load_failure(const char *func, int line);
124 #define i915_inject_load_failure() \
125 __i915_inject_load_failure(__func__, __LINE__)
127 bool i915_error_injected(void);
131 #define i915_inject_load_failure() false
132 #define i915_error_injected() false
136 #define i915_load_error(i915, fmt, ...) \
137 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
142 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
155 #define for_each_hpd_pin(__pin) \
156 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
158 /* Threshold == 5 for long IRQs, 50 for short */
159 #define HPD_STORM_DEFAULT_THRESHOLD 50
161 struct i915_hotplug {
162 struct work_struct hotplug_work;
165 unsigned long last_jiffies;
170 HPD_MARK_DISABLED = 2
172 } stats[HPD_NUM_PINS];
174 struct delayed_work reenable_work;
178 struct work_struct dig_port_work;
180 struct work_struct poll_init_work;
183 unsigned int hpd_storm_threshold;
184 /* Whether or not to count short HPD IRQs in HPD storms */
185 u8 hpd_short_storm_enabled;
188 * if we get a HPD irq from DP and a HPD irq from non-DP
189 * the non-DP HPD could block the workqueue on a mode config
190 * mutex getting, that userspace may have taken. However
191 * userspace is waiting on the DP workqueue to run which is
192 * blocked behind the non-DP one.
194 struct workqueue_struct *dp_wq;
197 #define I915_GEM_GPU_DOMAINS \
198 (I915_GEM_DOMAIN_RENDER | \
199 I915_GEM_DOMAIN_SAMPLER | \
200 I915_GEM_DOMAIN_COMMAND | \
201 I915_GEM_DOMAIN_INSTRUCTION | \
202 I915_GEM_DOMAIN_VERTEX)
204 struct drm_i915_private;
205 struct i915_mm_struct;
206 struct i915_mmu_object;
208 struct drm_i915_file_private {
209 struct drm_i915_private *dev_priv;
210 struct drm_file *file;
214 struct list_head request_list;
215 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
216 * chosen to prevent the CPU getting more than a frame ahead of the GPU
217 * (when using lax throttling for the frontbuffer). We also use it to
218 * offer free GPU waitboosts for severely congested workloads.
220 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
223 struct idr context_idr;
224 struct mutex context_idr_lock; /* guards context_idr */
227 struct mutex vm_idr_lock; /* guards vm_idr */
229 unsigned int bsd_engine;
232 * Every context ban increments per client ban score. Also
233 * hangs in short succession increments ban score. If ban threshold
234 * is reached, client is considered banned and submitting more work
235 * will fail. This is a stop gap measure to limit the badly behaving
236 * clients access to gpu. Note that unbannable contexts never increment
237 * the client ban score.
239 #define I915_CLIENT_SCORE_HANG_FAST 1
240 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
241 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
242 #define I915_CLIENT_SCORE_BANNED 9
243 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
245 unsigned long hang_timestamp;
248 /* Interface history:
251 * 1.2: Add Power Management
252 * 1.3: Add vblank support
253 * 1.4: Fix cmdbuffer path, add heap destroy
254 * 1.5: Add vblank pipe configuration
255 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
256 * - Support vertical blank on secondary display pipe
258 #define DRIVER_MAJOR 1
259 #define DRIVER_MINOR 6
260 #define DRIVER_PATCHLEVEL 0
262 struct intel_overlay;
263 struct intel_overlay_error_state;
265 struct sdvo_device_mapping {
274 struct intel_connector;
275 struct intel_encoder;
276 struct intel_atomic_state;
277 struct intel_crtc_state;
278 struct intel_initial_plane_config;
282 struct intel_cdclk_state;
284 struct drm_i915_display_funcs {
285 void (*get_cdclk)(struct drm_i915_private *dev_priv,
286 struct intel_cdclk_state *cdclk_state);
287 void (*set_cdclk)(struct drm_i915_private *dev_priv,
288 const struct intel_cdclk_state *cdclk_state,
290 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
291 enum i9xx_plane_id i9xx_plane);
292 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
293 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
294 void (*initial_watermarks)(struct intel_atomic_state *state,
295 struct intel_crtc_state *cstate);
296 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
297 struct intel_crtc_state *cstate);
298 void (*optimize_watermarks)(struct intel_atomic_state *state,
299 struct intel_crtc_state *cstate);
300 int (*compute_global_watermarks)(struct intel_atomic_state *state);
301 void (*update_wm)(struct intel_crtc *crtc);
302 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
303 /* Returns the active state of the crtc, and if the crtc is active,
304 * fills out the pipe-config with the hw state. */
305 bool (*get_pipe_config)(struct intel_crtc *,
306 struct intel_crtc_state *);
307 void (*get_initial_plane_config)(struct intel_crtc *,
308 struct intel_initial_plane_config *);
309 int (*crtc_compute_clock)(struct intel_crtc *crtc,
310 struct intel_crtc_state *crtc_state);
311 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
312 struct drm_atomic_state *old_state);
313 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
314 struct drm_atomic_state *old_state);
315 void (*update_crtcs)(struct drm_atomic_state *state);
316 void (*audio_codec_enable)(struct intel_encoder *encoder,
317 const struct intel_crtc_state *crtc_state,
318 const struct drm_connector_state *conn_state);
319 void (*audio_codec_disable)(struct intel_encoder *encoder,
320 const struct intel_crtc_state *old_crtc_state,
321 const struct drm_connector_state *old_conn_state);
322 void (*fdi_link_train)(struct intel_crtc *crtc,
323 const struct intel_crtc_state *crtc_state);
324 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
325 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
326 /* clock updates for mode set */
328 /* render clock increase/decrease */
329 /* display clock increase/decrease */
330 /* pll clock increase/decrease */
332 int (*color_check)(struct intel_crtc_state *crtc_state);
334 * Program double buffered color management registers during
335 * vblank evasion. The registers should then latch during the
336 * next vblank start, alongside any other double buffered registers
337 * involved with the same commit.
339 void (*color_commit)(const struct intel_crtc_state *crtc_state);
341 * Load LUTs (and other single buffered color management
342 * registers). Will (hopefully) be called during the vblank
343 * following the latching of any double buffered registers
344 * involved with the same commit.
346 void (*load_luts)(const struct intel_crtc_state *crtc_state);
350 struct work_struct work;
352 u32 required_version;
353 u32 max_fw_size; /* bytes */
355 u32 dmc_fw_size; /* dwords */
358 i915_reg_t mmioaddr[8];
362 intel_wakeref_t wakeref;
365 enum i915_cache_level {
367 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
368 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
369 caches, eg sampler/render caches, and the
370 large Last-Level-Cache. LLC is coherent with
371 the CPU, but L3 is only visible to the GPU. */
372 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
375 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
378 /* This is always the inner lock when overlapping with struct_mutex and
379 * it's the outer lock when overlapping with stolen_lock. */
382 unsigned int possible_framebuffer_bits;
383 unsigned int busy_bits;
384 unsigned int visible_pipes_mask;
385 struct intel_crtc *crtc;
387 struct drm_mm_node compressed_fb;
388 struct drm_mm_node *compressed_llb;
396 bool underrun_detected;
397 struct work_struct underrun_work;
400 * Due to the atomic rules we can't access some structures without the
401 * appropriate locking, so we cache information here in order to avoid
404 struct intel_fbc_state_cache {
405 struct i915_vma *vma;
409 unsigned int mode_flags;
410 u32 hsw_bdw_pixel_rate;
414 unsigned int rotation;
419 * Display surface base address adjustement for
420 * pageflips. Note that on gen4+ this only adjusts up
421 * to a tile, offsets within a tile are handled in
422 * the hw itself (with the TILEOFF register).
429 u16 pixel_blend_mode;
433 const struct drm_format_info *format;
439 * This structure contains everything that's relevant to program the
440 * hardware registers. When we want to figure out if we need to disable
441 * and re-enable FBC for a new configuration we just check if there's
442 * something different in the struct. The genx_fbc_activate functions
443 * are supposed to read from it in order to program the registers.
445 struct intel_fbc_reg_params {
446 struct i915_vma *vma;
451 enum i9xx_plane_id i9xx_plane;
452 unsigned int fence_y_offset;
456 const struct drm_format_info *format;
461 unsigned int gen9_wa_cfb_stride;
464 const char *no_fbc_reason;
468 * HIGH_RR is the highest eDP panel refresh rate read from EDID
469 * LOW_RR is the lowest eDP panel refresh rate found from EDID
470 * parsing for same resolution.
472 enum drrs_refresh_rate_type {
475 DRRS_MAX_RR, /* RR count */
478 enum drrs_support_type {
479 DRRS_NOT_SUPPORTED = 0,
480 STATIC_DRRS_SUPPORT = 1,
481 SEAMLESS_DRRS_SUPPORT = 2
487 struct delayed_work work;
489 unsigned busy_frontbuffer_bits;
490 enum drrs_refresh_rate_type refresh_rate_type;
491 enum drrs_support_type type;
497 #define I915_PSR_DEBUG_MODE_MASK 0x0f
498 #define I915_PSR_DEBUG_DEFAULT 0x00
499 #define I915_PSR_DEBUG_DISABLE 0x01
500 #define I915_PSR_DEBUG_ENABLE 0x02
501 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
502 #define I915_PSR_DEBUG_IRQ 0x10
510 struct work_struct work;
511 unsigned busy_frontbuffer_bits;
512 bool sink_psr2_support;
514 bool colorimetry_support;
516 u8 sink_sync_latency;
517 ktime_t last_entry_attempt;
519 bool sink_not_reliable;
521 u16 su_x_granularity;
525 * Sorted by south display engine compatibility.
526 * If the new PCH comes with a south display engine that is not
527 * inherited from the latest item, please do not add it to the
528 * end. Instead, add it right after its "parent" PCH.
531 PCH_NOP = -1, /* PCH without south display */
532 PCH_NONE = 0, /* No PCH present */
533 PCH_IBX, /* Ibexpeak PCH */
534 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
535 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
536 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
537 PCH_CNP, /* Cannon/Comet Lake PCH */
538 PCH_ICP, /* Ice Lake PCH */
541 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
542 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
543 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
544 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
545 #define QUIRK_INCREASE_T12_DELAY (1<<6)
546 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
549 struct intel_fbc_work;
552 struct i2c_adapter adapter;
553 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
557 struct i2c_algo_bit_data bit_algo;
558 struct drm_i915_private *dev_priv;
561 struct i915_suspend_saved_registers {
564 u32 saveCACHE_MODE_0;
565 u32 saveMI_ARB_STATE;
569 u64 saveFENCE[I915_MAX_NUM_FENCES];
570 u32 savePCH_PORT_HOTPLUG;
574 struct vlv_s0ix_state {
581 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
582 u32 media_max_req_count;
583 u32 gfx_max_req_count;
615 /* Display 1 CZ domain */
620 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
622 /* GT SA CZ domain */
629 /* Display 2 CZ domain */
636 struct intel_rps_ei {
643 struct mutex lock; /* protects enabling and the worker */
646 * work, interrupts_enabled and pm_iir are protected by
649 struct work_struct work;
650 bool interrupts_enabled;
653 /* PM interrupt bits that should never be masked */
656 /* Frequencies are stored in potentially platform dependent multiples.
657 * In other words, *_freq needs to be multiplied by X to be interesting.
658 * Soft limits are those which are used for the dynamic reclocking done
659 * by the driver (raise frequencies under heavy loads, and lower for
660 * lighter loads). Hard limits are those imposed by the hardware.
662 * A distinction is made for overclocking, which is never enabled by
663 * default, and is considered to be above the hard limit if it's
666 u8 cur_freq; /* Current frequency (cached, may not == HW) */
667 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
668 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
669 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
670 u8 min_freq; /* AKA RPn. Minimum frequency */
671 u8 boost_freq; /* Frequency to request when wait boosting */
672 u8 idle_freq; /* Frequency to request when we are idle */
673 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
674 u8 rp1_freq; /* "less than" RP0 power/freqency */
675 u8 rp0_freq; /* Non-overclocked max frequency. */
676 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
683 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
684 unsigned int interactive;
686 u8 up_threshold; /* Current %busy required to uplock */
687 u8 down_threshold; /* Current %busy required to downclock */
691 atomic_t num_waiters;
694 /* manual wa residency calculations */
695 struct intel_rps_ei ei;
700 u64 prev_hw_residency[4];
701 u64 cur_residency[4];
704 struct intel_llc_pstate {
708 struct intel_gen6_power_mgmt {
709 struct intel_rps rps;
710 struct intel_rc6 rc6;
711 struct intel_llc_pstate llc_pstate;
714 /* defined intel_pm.c */
715 extern spinlock_t mchdev_lock;
717 struct intel_ilk_power_mgmt {
725 unsigned long last_time1;
726 unsigned long chipset_power;
729 unsigned long gfx_power;
736 struct drm_i915_private;
737 struct i915_power_well;
739 struct i915_power_well_ops {
741 * Synchronize the well's hw state to match the current sw state, for
742 * example enable/disable it based on the current refcount. Called
743 * during driver init and resume time, possibly after first calling
744 * the enable/disable handlers.
746 void (*sync_hw)(struct drm_i915_private *dev_priv,
747 struct i915_power_well *power_well);
749 * Enable the well and resources that depend on it (for example
750 * interrupts located on the well). Called after the 0->1 refcount
753 void (*enable)(struct drm_i915_private *dev_priv,
754 struct i915_power_well *power_well);
756 * Disable the well and resources that depend on it. Called after
757 * the 1->0 refcount transition.
759 void (*disable)(struct drm_i915_private *dev_priv,
760 struct i915_power_well *power_well);
761 /* Returns the hw enabled state. */
762 bool (*is_enabled)(struct drm_i915_private *dev_priv,
763 struct i915_power_well *power_well);
766 struct i915_power_well_regs {
773 /* Power well structure for haswell */
774 struct i915_power_well_desc {
778 /* unique identifier for this power well */
779 enum i915_power_well_id id;
781 * Arbitraty data associated with this power well. Platform and power
787 * request/status flag index in the PUNIT power well
788 * control/status registers.
796 const struct i915_power_well_regs *regs;
798 * request/status flag index in the power well
799 * constrol/status registers.
802 /* Mask of pipes whose IRQ logic is backed by the pw */
804 /* The pw is backing the VGA functionality */
808 * The pw is for an ICL+ TypeC PHY port in
814 const struct i915_power_well_ops *ops;
817 struct i915_power_well {
818 const struct i915_power_well_desc *desc;
819 /* power well enable/disable usage count */
821 /* cached hw enabled state */
825 struct i915_power_domains {
827 * Power wells needed for initialization at driver init and suspend
828 * time are on. They are kept on until after the first modeset.
831 bool display_core_suspended;
832 int power_well_count;
834 intel_wakeref_t wakeref;
837 int domain_use_count[POWER_DOMAIN_NUM];
839 struct delayed_work async_put_work;
840 intel_wakeref_t async_put_wakeref;
841 u64 async_put_domains[2];
843 struct i915_power_well *power_wells;
846 #define MAX_L3_SLICES 2
847 struct intel_l3_parity {
848 u32 *remap_info[MAX_L3_SLICES];
849 struct work_struct error_work;
854 /** Memory allocator for GTT stolen memory */
855 struct drm_mm stolen;
856 /** Protects the usage of the GTT stolen memory allocator. This is
857 * always the inner lock when overlapping with struct_mutex. */
858 struct mutex stolen_lock;
860 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
863 /** List of all objects in gtt_space. Used to restore gtt
864 * mappings on resume */
865 struct list_head bound_list;
867 * List of objects which are not bound to the GTT (thus
868 * are idle and not used by the GPU). These objects may or may
869 * not actually have any pages attached.
871 struct list_head unbound_list;
873 /** List of all objects in gtt_space, currently mmaped by userspace.
874 * All objects within this list must also be on bound_list.
876 struct list_head userfault_list;
878 /* Manual runtime pm autosuspend delay for user GGTT mmaps */
879 struct intel_wakeref_auto userfault_wakeref;
882 * List of objects which are pending destruction.
884 struct llist_head free_list;
885 struct work_struct free_work;
886 spinlock_t free_lock;
888 * Count of objects pending destructions. Used to skip needlessly
889 * waiting on an RCU barrier if no objects are waiting to be freed.
894 * Small stash of WC pages
896 struct pagestash wc_stash;
899 * tmpfs instance used for shmem backed objects
901 struct vfsmount *gemfs;
903 /** PPGTT used for aliasing the PPGTT with the GTT */
904 struct i915_hw_ppgtt *aliasing_ppgtt;
906 struct notifier_block oom_notifier;
907 struct notifier_block vmap_notifier;
908 struct shrinker shrinker;
910 /** LRU list of objects with fence regs on them. */
911 struct list_head fence_list;
914 * Workqueue to fault in userptr pages, flushed by the execbuf
915 * when required but otherwise left to userspace to try again
918 struct workqueue_struct *userptr_wq;
920 u64 unordered_timeline;
922 /* the indicator for dispatch video commands on two BSD rings */
923 atomic_t bsd_engine_dispatch_index;
925 /** Bit 6 swizzling required for X tiling */
927 /** Bit 6 swizzling required for Y tiling */
930 /* accounting, useful for userland debugging */
931 spinlock_t object_stat_lock;
936 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
938 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
939 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
941 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
942 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
944 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
946 struct ddi_vbt_port_info {
950 * This is an index in the HDMI/DVI DDI buffer translation table.
951 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
952 * populate this field.
954 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
962 u8 supports_typec_usb:1;
965 u8 alternate_aux_channel;
966 u8 alternate_ddc_pin;
970 int dp_max_link_rate; /* 0 for not limited by VBT */
973 enum psr_lines_to_wait {
974 PSR_0_LINES_TO_WAIT = 0,
980 struct intel_vbt_data {
981 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
982 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
985 unsigned int int_tv_support:1;
986 unsigned int lvds_dither:1;
987 unsigned int int_crt_support:1;
988 unsigned int lvds_use_ssc:1;
989 unsigned int int_lvds_support:1;
990 unsigned int display_clock_mode:1;
991 unsigned int fdi_rx_polarity_inverted:1;
992 unsigned int panel_type:4;
994 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
995 enum drm_panel_orientation orientation;
997 enum drrs_support_type drrs_type;
1007 struct edp_power_seq pps;
1013 bool require_aux_wakeup;
1015 enum psr_lines_to_wait lines_to_wait;
1016 int tp1_wakeup_time_us;
1017 int tp2_tp3_wakeup_time_us;
1018 int psr2_tp2_tp3_wakeup_time_us;
1024 bool active_low_pwm;
1025 u8 min_brightness; /* min_brightness/255 of max */
1026 u8 controller; /* brightness controller number */
1027 enum intel_backlight_type type;
1033 struct mipi_config *config;
1034 struct mipi_pps_data *pps;
1040 const u8 *sequence[MIPI_SEQ_MAX];
1041 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1042 enum drm_panel_orientation orientation;
1048 struct child_device_config *child_dev;
1050 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1051 struct sdvo_device_mapping sdvo_mappings[2];
1054 enum intel_ddb_partitioning {
1056 INTEL_DDB_PART_5_6, /* IVB+ */
1059 struct intel_wm_level {
1067 struct ilk_wm_values {
1073 enum intel_ddb_partitioning partitioning;
1076 struct g4x_pipe_wm {
1077 u16 plane[I915_MAX_PLANES];
1087 struct vlv_wm_ddl_values {
1088 u8 plane[I915_MAX_PLANES];
1091 struct vlv_wm_values {
1092 struct g4x_pipe_wm pipe[3];
1093 struct g4x_sr_wm sr;
1094 struct vlv_wm_ddl_values ddl[3];
1099 struct g4x_wm_values {
1100 struct g4x_pipe_wm pipe[2];
1101 struct g4x_sr_wm sr;
1102 struct g4x_sr_wm hpll;
1108 struct skl_ddb_entry {
1109 u16 start, end; /* in number of blocks, 'end' is exclusive */
1112 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1114 return entry->end - entry->start;
1117 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1118 const struct skl_ddb_entry *e2)
1120 if (e1->start == e2->start && e1->end == e2->end)
1126 struct skl_ddb_allocation {
1127 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1130 struct skl_ddb_values {
1131 unsigned dirty_pipes;
1132 struct skl_ddb_allocation ddb;
1135 struct skl_wm_level {
1143 /* Stores plane specific WM parameters */
1144 struct skl_wm_params {
1145 bool x_tiled, y_tiled;
1150 u32 plane_pixel_rate;
1151 u32 y_min_scanlines;
1152 u32 plane_bytes_per_line;
1153 uint_fixed_16_16_t plane_blocks_per_line;
1154 uint_fixed_16_16_t y_tile_minimum;
1156 u32 dbuf_block_size;
1160 * This struct helps tracking the state needed for runtime PM, which puts the
1161 * device in PCI D3 state. Notice that when this happens, nothing on the
1162 * graphics device works, even register access, so we don't get interrupts nor
1165 * Every piece of our code that needs to actually touch the hardware needs to
1166 * either call intel_runtime_pm_get or call intel_display_power_get with the
1167 * appropriate power domain.
1169 * Our driver uses the autosuspend delay feature, which means we'll only really
1170 * suspend if we stay with zero refcount for a certain amount of time. The
1171 * default value is currently very conservative (see intel_runtime_pm_enable), but
1172 * it can be changed with the standard runtime PM files from sysfs.
1174 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1175 * goes back to false exactly before we reenable the IRQs. We use this variable
1176 * to check if someone is trying to enable/disable IRQs while they're supposed
1177 * to be disabled. This shouldn't happen and we'll print some error messages in
1180 * For more, read the Documentation/power/runtime_pm.txt.
1182 struct i915_runtime_pm {
1183 atomic_t wakeref_count;
1187 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1189 * To aide detection of wakeref leaks and general misuse, we
1190 * track all wakeref holders. With manual markup (i.e. returning
1191 * a cookie to each rpm_get caller which they then supply to their
1192 * paired rpm_put) we can remove corresponding pairs of and keep
1193 * the array trimmed to active wakerefs.
1195 struct intel_runtime_pm_debug {
1198 depot_stack_handle_t last_acquire;
1199 depot_stack_handle_t last_release;
1201 depot_stack_handle_t *owners;
1202 unsigned long count;
1207 enum intel_pipe_crc_source {
1208 INTEL_PIPE_CRC_SOURCE_NONE,
1209 INTEL_PIPE_CRC_SOURCE_PLANE1,
1210 INTEL_PIPE_CRC_SOURCE_PLANE2,
1211 INTEL_PIPE_CRC_SOURCE_PLANE3,
1212 INTEL_PIPE_CRC_SOURCE_PLANE4,
1213 INTEL_PIPE_CRC_SOURCE_PLANE5,
1214 INTEL_PIPE_CRC_SOURCE_PLANE6,
1215 INTEL_PIPE_CRC_SOURCE_PLANE7,
1216 INTEL_PIPE_CRC_SOURCE_PIPE,
1217 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1218 INTEL_PIPE_CRC_SOURCE_TV,
1219 INTEL_PIPE_CRC_SOURCE_DP_B,
1220 INTEL_PIPE_CRC_SOURCE_DP_C,
1221 INTEL_PIPE_CRC_SOURCE_DP_D,
1222 INTEL_PIPE_CRC_SOURCE_AUTO,
1223 INTEL_PIPE_CRC_SOURCE_MAX,
1226 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1227 struct intel_pipe_crc {
1230 enum intel_pipe_crc_source source;
1233 struct i915_frontbuffer_tracking {
1237 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1244 struct i915_virtual_gpu {
1249 /* used in computing the new watermarks state */
1250 struct intel_wm_config {
1251 unsigned int num_pipes_active;
1252 bool sprites_enabled;
1253 bool sprites_scaled;
1256 struct i915_oa_format {
1261 struct i915_oa_reg {
1266 struct i915_oa_config {
1267 char uuid[UUID_STRING_LEN + 1];
1270 const struct i915_oa_reg *mux_regs;
1272 const struct i915_oa_reg *b_counter_regs;
1273 u32 b_counter_regs_len;
1274 const struct i915_oa_reg *flex_regs;
1277 struct attribute_group sysfs_metric;
1278 struct attribute *attrs[2];
1279 struct device_attribute sysfs_metric_id;
1284 struct i915_perf_stream;
1287 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1289 struct i915_perf_stream_ops {
1291 * @enable: Enables the collection of HW samples, either in response to
1292 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1293 * without `I915_PERF_FLAG_DISABLED`.
1295 void (*enable)(struct i915_perf_stream *stream);
1298 * @disable: Disables the collection of HW samples, either in response
1299 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1302 void (*disable)(struct i915_perf_stream *stream);
1305 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1306 * once there is something ready to read() for the stream
1308 void (*poll_wait)(struct i915_perf_stream *stream,
1313 * @wait_unlocked: For handling a blocking read, wait until there is
1314 * something to ready to read() for the stream. E.g. wait on the same
1315 * wait queue that would be passed to poll_wait().
1317 int (*wait_unlocked)(struct i915_perf_stream *stream);
1320 * @read: Copy buffered metrics as records to userspace
1321 * **buf**: the userspace, destination buffer
1322 * **count**: the number of bytes to copy, requested by userspace
1323 * **offset**: zero at the start of the read, updated as the read
1324 * proceeds, it represents how many bytes have been copied so far and
1325 * the buffer offset for copying the next record.
1327 * Copy as many buffered i915 perf samples and records for this stream
1328 * to userspace as will fit in the given buffer.
1330 * Only write complete records; returning -%ENOSPC if there isn't room
1331 * for a complete record.
1333 * Return any error condition that results in a short read such as
1334 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1335 * returning to userspace.
1337 int (*read)(struct i915_perf_stream *stream,
1343 * @destroy: Cleanup any stream specific resources.
1345 * The stream will always be disabled before this is called.
1347 void (*destroy)(struct i915_perf_stream *stream);
1351 * struct i915_perf_stream - state for a single open stream FD
1353 struct i915_perf_stream {
1355 * @dev_priv: i915 drm device
1357 struct drm_i915_private *dev_priv;
1360 * @link: Links the stream into ``&drm_i915_private->streams``
1362 struct list_head link;
1365 * @wakeref: As we keep the device awake while the perf stream is
1366 * active, we track our runtime pm reference for later release.
1368 intel_wakeref_t wakeref;
1371 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1372 * properties given when opening a stream, representing the contents
1373 * of a single sample as read() by userspace.
1378 * @sample_size: Considering the configured contents of a sample
1379 * combined with the required header size, this is the total size
1380 * of a single sample record.
1385 * @ctx: %NULL if measuring system-wide across all contexts or a
1386 * specific context that is being monitored.
1388 struct i915_gem_context *ctx;
1391 * @enabled: Whether the stream is currently enabled, considering
1392 * whether the stream was opened in a disabled state and based
1393 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1398 * @ops: The callbacks providing the implementation of this specific
1399 * type of configured stream.
1401 const struct i915_perf_stream_ops *ops;
1404 * @oa_config: The OA configuration used by the stream.
1406 struct i915_oa_config *oa_config;
1410 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1412 struct i915_oa_ops {
1414 * @is_valid_b_counter_reg: Validates register's address for
1415 * programming boolean counters for a particular platform.
1417 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1421 * @is_valid_mux_reg: Validates register's address for programming mux
1422 * for a particular platform.
1424 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1427 * @is_valid_flex_reg: Validates register's address for programming
1428 * flex EU filtering for a particular platform.
1430 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1433 * @enable_metric_set: Selects and applies any MUX configuration to set
1434 * up the Boolean and Custom (B/C) counters that are part of the
1435 * counter reports being sampled. May apply system constraints such as
1436 * disabling EU clock gating as required.
1438 int (*enable_metric_set)(struct i915_perf_stream *stream);
1441 * @disable_metric_set: Remove system constraints associated with using
1444 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1447 * @oa_enable: Enable periodic sampling
1449 void (*oa_enable)(struct i915_perf_stream *stream);
1452 * @oa_disable: Disable periodic sampling
1454 void (*oa_disable)(struct i915_perf_stream *stream);
1457 * @read: Copy data from the circular OA buffer into a given userspace
1460 int (*read)(struct i915_perf_stream *stream,
1466 * @oa_hw_tail_read: read the OA tail pointer register
1468 * In particular this enables us to share all the fiddly code for
1469 * handling the OA unit tail pointer race that affects multiple
1472 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1475 struct intel_cdclk_state {
1476 unsigned int cdclk, vco, ref, bypass;
1480 struct drm_i915_private {
1481 struct drm_device drm;
1483 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1484 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1485 struct intel_driver_caps caps;
1488 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1489 * end of stolen which we can optionally use to create GEM objects
1490 * backed by stolen memory. Note that stolen_usable_size tells us
1491 * exactly how much of this we are actually allowed to use, given that
1492 * some portion of it is in fact reserved for use by hardware functions.
1494 struct resource dsm;
1496 * Reseved portion of Data Stolen Memory
1498 struct resource dsm_reserved;
1501 * Stolen memory is segmented in hardware with different portions
1502 * offlimits to certain functions.
1504 * The drm_mm is initialised to the total accessible range, as found
1505 * from the PCI config. On Broadwell+, this is further restricted to
1506 * avoid the first page! The upper end of stolen memory is reserved for
1507 * hardware functions and similarly removed from the accessible range.
1509 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1511 struct intel_uncore uncore;
1513 struct i915_virtual_gpu vgpu;
1515 struct intel_gvt *gvt;
1517 struct intel_wopcm wopcm;
1519 struct intel_huc huc;
1520 struct intel_guc guc;
1522 struct intel_csr csr;
1524 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1526 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1527 * controller on different i2c buses. */
1528 struct mutex gmbus_mutex;
1531 * Base address of where the gmbus and gpio blocks are located (either
1532 * on PCH or on SoC for platforms without PCH).
1536 /* MMIO base address for MIPI regs */
1543 wait_queue_head_t gmbus_wait_queue;
1545 struct pci_dev *bridge_dev;
1546 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1547 /* Context used internally to idle the GPU and setup initial state */
1548 struct i915_gem_context *kernel_context;
1549 /* Context only to be used for injecting preemption commands */
1550 struct i915_gem_context *preempt_context;
1551 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1552 [MAX_ENGINE_INSTANCE + 1];
1554 struct resource mch_res;
1556 /* protects the irq masks */
1557 spinlock_t irq_lock;
1559 bool display_irqs_enabled;
1561 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1562 struct pm_qos_request pm_qos;
1564 /* Sideband mailbox protection */
1565 struct mutex sb_lock;
1566 struct pm_qos_request sb_qos;
1568 /** Cached value of IMR to avoid reads in updating the bitfield */
1571 u32 de_irq_mask[I915_MAX_PIPES];
1578 u32 pipestat_irq_mask[I915_MAX_PIPES];
1580 struct i915_hotplug hotplug;
1581 struct intel_fbc fbc;
1582 struct i915_drrs drrs;
1583 struct intel_opregion opregion;
1584 struct intel_vbt_data vbt;
1586 bool preserve_bios_swizzle;
1589 struct intel_overlay *overlay;
1591 /* backlight registers and fields in struct intel_panel */
1592 struct mutex backlight_lock;
1595 bool no_aux_handshake;
1597 /* protects panel power sequencer state */
1598 struct mutex pps_mutex;
1600 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1601 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1603 unsigned int fsb_freq, mem_freq, is_ddr3;
1604 unsigned int skl_preferred_vco_freq;
1605 unsigned int max_cdclk_freq;
1607 unsigned int max_dotclk_freq;
1608 unsigned int rawclk_freq;
1609 unsigned int hpll_freq;
1610 unsigned int fdi_pll_freq;
1611 unsigned int czclk_freq;
1615 * The current logical cdclk state.
1616 * See intel_atomic_state.cdclk.logical
1618 * For reading holding any crtc lock is sufficient,
1619 * for writing must hold all of them.
1621 struct intel_cdclk_state logical;
1623 * The current actual cdclk state.
1624 * See intel_atomic_state.cdclk.actual
1626 struct intel_cdclk_state actual;
1627 /* The current hardware cdclk state */
1628 struct intel_cdclk_state hw;
1630 int force_min_cdclk;
1634 * wq - Driver workqueue for GEM.
1636 * NOTE: Work items scheduled here are not allowed to grab any modeset
1637 * locks, for otherwise the flushing done in the pageflip code will
1638 * result in deadlocks.
1640 struct workqueue_struct *wq;
1642 /* ordered wq for modesets */
1643 struct workqueue_struct *modeset_wq;
1645 /* Display functions */
1646 struct drm_i915_display_funcs display;
1648 /* PCH chipset type */
1649 enum intel_pch pch_type;
1650 unsigned short pch_id;
1652 unsigned long quirks;
1654 struct drm_atomic_state *modeset_restore_state;
1655 struct drm_modeset_acquire_ctx reset_ctx;
1657 struct i915_ggtt ggtt; /* VM representing the global address space */
1659 struct i915_gem_mm mm;
1660 DECLARE_HASHTABLE(mm_structs, 7);
1661 struct mutex mm_lock;
1663 struct intel_ppat ppat;
1665 /* Kernel Modesetting */
1667 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1668 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1670 #ifdef CONFIG_DEBUG_FS
1671 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1674 /* dpll and cdclk state is protected by connection_mutex */
1675 int num_shared_dpll;
1676 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1677 const struct intel_dpll_mgr *dpll_mgr;
1680 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1681 * Must be global rather than per dpll, because on some platforms
1682 * plls share registers.
1684 struct mutex dpll_lock;
1686 unsigned int active_crtcs;
1687 /* minimum acceptable cdclk for each pipe */
1688 int min_cdclk[I915_MAX_PIPES];
1689 /* minimum acceptable voltage level for each pipe */
1690 u8 min_voltage_level[I915_MAX_PIPES];
1692 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1694 struct i915_wa_list gt_wa_list;
1696 struct i915_frontbuffer_tracking fb_tracking;
1698 struct intel_atomic_helper {
1699 struct llist_head free_list;
1700 struct work_struct free_work;
1705 bool mchbar_need_disable;
1707 struct intel_l3_parity l3_parity;
1711 * Cannot be determined by PCIID. You must always read a register.
1715 /* gen6+ GT PM state */
1716 struct intel_gen6_power_mgmt gt_pm;
1718 /* ilk-only ips/rps state. Everything in here is protected by the global
1719 * mchdev_lock in intel_pm.c */
1720 struct intel_ilk_power_mgmt ips;
1722 struct i915_power_domains power_domains;
1724 struct i915_psr psr;
1726 struct i915_gpu_error gpu_error;
1728 struct drm_i915_gem_object *vlv_pctx;
1730 /* list of fbdev register on this device */
1731 struct intel_fbdev *fbdev;
1732 struct work_struct fbdev_suspend_work;
1734 struct drm_property *broadcast_rgb_property;
1735 struct drm_property *force_audio_property;
1737 /* hda/i915 audio component */
1738 struct i915_audio_component *audio_component;
1739 bool audio_component_registered;
1741 * av_mutex - mutex for audio/video sync
1744 struct mutex av_mutex;
1745 int audio_power_refcount;
1749 struct list_head list;
1750 struct llist_head free_list;
1751 struct work_struct free_work;
1753 /* The hw wants to have a stable context identifier for the
1754 * lifetime of the context (for OA, PASID, faults, etc).
1755 * This is limited in execlists to 21 bits.
1758 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1759 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1760 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1761 struct list_head hw_id_list;
1766 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1767 u32 chv_phy_control;
1769 * Shadows for CHV DPLL_MD regs to keep the state
1770 * checker somewhat working in the presence hardware
1771 * crappiness (can't read out DPLL_MD for pipes B & C).
1773 u32 chv_dpll_md[I915_MAX_PIPES];
1777 bool power_domains_suspended;
1778 struct i915_suspend_saved_registers regfile;
1779 struct vlv_s0ix_state vlv_s0ix_state;
1782 I915_SAGV_UNKNOWN = 0,
1785 I915_SAGV_NOT_CONTROLLED
1790 * Raw watermark latency values:
1791 * in 0.1us units for WM0,
1792 * in 0.5us units for WM1+.
1801 * Raw watermark memory latency values
1802 * for SKL for all 8 levels
1807 /* current hardware state */
1809 struct ilk_wm_values hw;
1810 struct skl_ddb_values skl_hw;
1811 struct vlv_wm_values vlv;
1812 struct g4x_wm_values g4x;
1818 * Should be held around atomic WM register writing; also
1819 * protects * intel_crtc->wm.active and
1820 * cstate->wm.need_postvbl_update.
1822 struct mutex wm_mutex;
1825 * Set during HW readout of watermarks/DDB. Some platforms
1826 * need to know when we're still using BIOS-provided values
1827 * (which we don't fully trust).
1829 bool distrust_bios_wm;
1838 bool symmetric_memory;
1839 enum intel_dram_type {
1848 struct intel_bw_info {
1853 struct drm_private_obj bw_obj;
1855 struct i915_runtime_pm runtime_pm;
1860 struct kobject *metrics_kobj;
1861 struct ctl_table_header *sysctl_header;
1864 * Lock associated with adding/modifying/removing OA configs
1865 * in dev_priv->perf.metrics_idr.
1867 struct mutex metrics_lock;
1870 * List of dynamic configurations, you need to hold
1871 * dev_priv->perf.metrics_lock to access it.
1873 struct idr metrics_idr;
1876 * Lock associated with anything below within this structure
1877 * except exclusive_stream.
1880 struct list_head streams;
1884 * The stream currently using the OA unit. If accessed
1885 * outside a syscall associated to its file
1886 * descriptor, you need to hold
1887 * dev_priv->drm.struct_mutex.
1889 struct i915_perf_stream *exclusive_stream;
1891 struct intel_context *pinned_ctx;
1892 u32 specific_ctx_id;
1893 u32 specific_ctx_id_mask;
1895 struct hrtimer poll_check_timer;
1896 wait_queue_head_t poll_wq;
1900 * For rate limiting any notifications of spurious
1901 * invalid OA reports
1903 struct ratelimit_state spurious_report_rs;
1906 int period_exponent;
1908 struct i915_oa_config test_config;
1911 struct i915_vma *vma;
1918 * Locks reads and writes to all head/tail state
1920 * Consider: the head and tail pointer state
1921 * needs to be read consistently from a hrtimer
1922 * callback (atomic context) and read() fop
1923 * (user context) with tail pointer updates
1924 * happening in atomic context and head updates
1925 * in user context and the (unlikely)
1926 * possibility of read() errors needing to
1927 * reset all head/tail state.
1929 * Note: Contention or performance aren't
1930 * currently a significant concern here
1931 * considering the relatively low frequency of
1932 * hrtimer callbacks (5ms period) and that
1933 * reads typically only happen in response to a
1934 * hrtimer event and likely complete before the
1937 * Note: This lock is not held *while* reading
1938 * and copying data to userspace so the value
1939 * of head observed in htrimer callbacks won't
1940 * represent any partial consumption of data.
1942 spinlock_t ptr_lock;
1945 * One 'aging' tail pointer and one 'aged'
1946 * tail pointer ready to used for reading.
1948 * Initial values of 0xffffffff are invalid
1949 * and imply that an update is required
1950 * (and should be ignored by an attempted
1958 * Index for the aged tail ready to read()
1961 unsigned int aged_tail_idx;
1964 * A monotonic timestamp for when the current
1965 * aging tail pointer was read; used to
1966 * determine when it is old enough to trust.
1968 u64 aging_timestamp;
1971 * Although we can always read back the head
1972 * pointer register, we prefer to avoid
1973 * trusting the HW state, just to avoid any
1974 * risk that some hardware condition could
1975 * somehow bump the head pointer unpredictably
1976 * and cause us to forward the wrong OA buffer
1977 * data to userspace.
1982 u32 gen7_latched_oastatus1;
1983 u32 ctx_oactxctrl_offset;
1984 u32 ctx_flexeu0_offset;
1987 * The RPT_ID/reason field for Gen8+ includes a bit
1988 * to determine if the CTX ID in the report is valid
1989 * but the specific bit differs between Gen 8 and 9
1991 u32 gen8_valid_ctx_bit;
1993 struct i915_oa_ops ops;
1994 const struct i915_oa_format *oa_formats;
1998 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2000 struct i915_gt_timelines {
2001 struct mutex mutex; /* protects list, tainted by GPU */
2002 struct list_head active_list;
2004 /* Pack multiple timelines' seqnos into the same page */
2005 spinlock_t hwsp_lock;
2006 struct list_head hwsp_free_list;
2009 struct list_head active_rings;
2010 struct list_head closed_vma;
2012 struct intel_wakeref wakeref;
2015 * Is the GPU currently considered idle, or busy executing
2016 * userspace requests? Whilst idle, we allow runtime power
2017 * management to power down the hardware and display clocks.
2018 * In order to reduce the effect on performance, there
2019 * is a slight delay before we do so.
2021 intel_wakeref_t awake;
2023 struct blocking_notifier_head pm_notifications;
2025 ktime_t last_init_time;
2027 struct i915_vma *scratch;
2031 struct notifier_block pm_notifier;
2034 * We leave the user IRQ off as much as possible,
2035 * but this means that requests will finish and never
2036 * be retired once the system goes idle. Set a timer to
2037 * fire periodically while the ring is running. When it
2038 * fires, go retire requests.
2040 struct delayed_work retire_work;
2043 * When we detect an idle GPU, we want to turn on
2044 * powersaving features. So once we see that there
2045 * are no more requests outstanding and no more
2046 * arrive within a small period of time, we fire
2047 * off the idle_work.
2049 struct work_struct idle_work;
2052 /* For i945gm vblank irq vs. C3 workaround */
2054 struct work_struct work;
2055 struct pm_qos_request pm_qos;
2056 u8 c3_disable_latency;
2060 /* perform PHY state sanity checks? */
2061 bool chv_phy_assert[2];
2065 /* Used to save the pipe-to-encoder mapping for audio */
2066 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2068 /* necessary resource sharing with HDMI LPE audio driver. */
2070 struct platform_device *platdev;
2074 struct i915_pmu pmu;
2076 struct i915_hdcp_comp_master *hdcp_master;
2077 bool hdcp_comp_added;
2079 /* Mutex to protect the above hdcp component related values. */
2080 struct mutex hdcp_comp_mutex;
2083 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2084 * will be rejected. Instead look for a better place.
2088 struct dram_dimm_info {
2089 u8 size, width, ranks;
2092 struct dram_channel_info {
2093 struct dram_dimm_info dimm_l, dimm_s;
2098 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2100 return container_of(dev, struct drm_i915_private, drm);
2103 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2105 return to_i915(dev_get_drvdata(kdev));
2108 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2110 return container_of(wopcm, struct drm_i915_private, wopcm);
2113 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2115 return container_of(guc, struct drm_i915_private, guc);
2118 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2120 return container_of(huc, struct drm_i915_private, huc);
2123 static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
2125 return container_of(uncore, struct drm_i915_private, uncore);
2128 /* Simple iterator over all initialised engines */
2129 #define for_each_engine(engine__, dev_priv__, id__) \
2131 (id__) < I915_NUM_ENGINES; \
2133 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2135 /* Iterator over subset of engines selected by mask */
2136 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2137 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
2139 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2142 enum hdmi_force_audio {
2143 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2144 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2145 HDMI_AUDIO_AUTO, /* trust EDID */
2146 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2149 #define I915_GTT_OFFSET_NONE ((u32)-1)
2152 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2153 * considered to be the frontbuffer for the given plane interface-wise. This
2154 * doesn't mean that the hw necessarily already scans it out, but that any
2155 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2157 * We have one bit per pipe and per scanout plane type.
2159 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2160 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2161 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2162 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2163 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2165 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2166 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2167 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2168 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2169 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2172 * Optimised SGL iterator for GEM objects
2174 static __always_inline struct sgt_iter {
2175 struct scatterlist *sgp;
2182 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2183 struct sgt_iter s = { .sgp = sgl };
2186 s.max = s.curr = s.sgp->offset;
2187 s.max += s.sgp->length;
2189 s.dma = sg_dma_address(s.sgp);
2191 s.pfn = page_to_pfn(sg_page(s.sgp));
2197 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2200 if (unlikely(sg_is_chain(sg)))
2201 sg = sg_chain_ptr(sg);
2206 * __sg_next - return the next scatterlist entry in a list
2207 * @sg: The current sg entry
2210 * If the entry is the last, return NULL; otherwise, step to the next
2211 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2212 * otherwise just return the pointer to the current element.
2214 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2216 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2220 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2221 * @__dmap: DMA address (output)
2222 * @__iter: 'struct sgt_iter' (iterator state, internal)
2223 * @__sgt: sg_table to iterate over (input)
2225 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2226 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2227 ((__dmap) = (__iter).dma + (__iter).curr); \
2228 (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \
2229 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2232 * for_each_sgt_page - iterate over the pages of the given sg_table
2233 * @__pp: page pointer (output)
2234 * @__iter: 'struct sgt_iter' (iterator state, internal)
2235 * @__sgt: sg_table to iterate over (input)
2237 #define for_each_sgt_page(__pp, __iter, __sgt) \
2238 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2239 ((__pp) = (__iter).pfn == 0 ? NULL : \
2240 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2241 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2242 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2244 bool i915_sg_trim(struct sg_table *orig_st);
2246 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2248 unsigned int page_sizes;
2252 GEM_BUG_ON(sg->offset);
2253 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2254 page_sizes |= sg->length;
2261 static inline unsigned int i915_sg_segment_size(void)
2263 unsigned int size = swiotlb_max_segment();
2266 return SCATTERLIST_MAX_SEGMENT;
2268 size = rounddown(size, PAGE_SIZE);
2269 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2270 if (size < PAGE_SIZE)
2276 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
2277 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2278 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2280 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
2281 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2283 #define REVID_FOREVER 0xff
2284 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2286 #define INTEL_GEN_MASK(s, e) ( \
2287 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2288 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2289 GENMASK((e) - 1, (s) - 1))
2291 /* Returns true if Gen is in inclusive range [Start, End] */
2292 #define IS_GEN_RANGE(dev_priv, s, e) \
2293 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2295 #define IS_GEN(dev_priv, n) \
2296 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2297 INTEL_INFO(dev_priv)->gen == (n))
2300 * Return true if revision is in range [since,until] inclusive.
2302 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2304 #define IS_REVID(p, since, until) \
2305 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2307 static __always_inline unsigned int
2308 __platform_mask_index(const struct intel_runtime_info *info,
2309 enum intel_platform p)
2311 const unsigned int pbits =
2312 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2314 /* Expand the platform_mask array if this fails. */
2315 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
2316 pbits * ARRAY_SIZE(info->platform_mask));
2321 static __always_inline unsigned int
2322 __platform_mask_bit(const struct intel_runtime_info *info,
2323 enum intel_platform p)
2325 const unsigned int pbits =
2326 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2328 return p % pbits + INTEL_SUBPLATFORM_BITS;
2332 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
2334 const unsigned int pi = __platform_mask_index(info, p);
2336 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
2339 static __always_inline bool
2340 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
2342 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2343 const unsigned int pi = __platform_mask_index(info, p);
2344 const unsigned int pb = __platform_mask_bit(info, p);
2346 BUILD_BUG_ON(!__builtin_constant_p(p));
2348 return info->platform_mask[pi] & BIT(pb);
2351 static __always_inline bool
2352 IS_SUBPLATFORM(const struct drm_i915_private *i915,
2353 enum intel_platform p, unsigned int s)
2355 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2356 const unsigned int pi = __platform_mask_index(info, p);
2357 const unsigned int pb = __platform_mask_bit(info, p);
2358 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
2359 const u32 mask = info->platform_mask[pi];
2361 BUILD_BUG_ON(!__builtin_constant_p(p));
2362 BUILD_BUG_ON(!__builtin_constant_p(s));
2363 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
2365 /* Shift and test on the MSB position so sign flag can be used. */
2366 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
2369 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
2371 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2372 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2373 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2374 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2375 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2376 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2377 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2378 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2379 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2380 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2381 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2382 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2383 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2384 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2385 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2386 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
2387 #define IS_IRONLAKE_M(dev_priv) \
2388 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
2389 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2390 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2391 INTEL_INFO(dev_priv)->gt == 1)
2392 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2393 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2394 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2395 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2396 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2397 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2398 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2399 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2400 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2401 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2402 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2403 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
2404 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2405 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2406 #define IS_BDW_ULT(dev_priv) \
2407 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
2408 #define IS_BDW_ULX(dev_priv) \
2409 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
2410 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2411 INTEL_INFO(dev_priv)->gt == 3)
2412 #define IS_HSW_ULT(dev_priv) \
2413 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
2414 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2415 INTEL_INFO(dev_priv)->gt == 3)
2416 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2417 INTEL_INFO(dev_priv)->gt == 1)
2418 /* ULX machines are also considered ULT. */
2419 #define IS_HSW_ULX(dev_priv) \
2420 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
2421 #define IS_SKL_ULT(dev_priv) \
2422 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
2423 #define IS_SKL_ULX(dev_priv) \
2424 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
2425 #define IS_KBL_ULT(dev_priv) \
2426 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
2427 #define IS_KBL_ULX(dev_priv) \
2428 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
2429 #define IS_AML_ULX(dev_priv) \
2430 (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
2431 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
2432 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2433 INTEL_INFO(dev_priv)->gt == 2)
2434 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2435 INTEL_INFO(dev_priv)->gt == 3)
2436 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2437 INTEL_INFO(dev_priv)->gt == 4)
2438 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2439 INTEL_INFO(dev_priv)->gt == 2)
2440 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2441 INTEL_INFO(dev_priv)->gt == 3)
2442 #define IS_CFL_ULT(dev_priv) \
2443 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2444 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2445 INTEL_INFO(dev_priv)->gt == 2)
2446 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2447 INTEL_INFO(dev_priv)->gt == 3)
2448 #define IS_CNL_WITH_PORT_F(dev_priv) \
2449 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2450 #define IS_ICL_WITH_PORT_F(dev_priv) \
2451 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2453 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2455 #define SKL_REVID_A0 0x0
2456 #define SKL_REVID_B0 0x1
2457 #define SKL_REVID_C0 0x2
2458 #define SKL_REVID_D0 0x3
2459 #define SKL_REVID_E0 0x4
2460 #define SKL_REVID_F0 0x5
2461 #define SKL_REVID_G0 0x6
2462 #define SKL_REVID_H0 0x7
2464 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2466 #define BXT_REVID_A0 0x0
2467 #define BXT_REVID_A1 0x1
2468 #define BXT_REVID_B0 0x3
2469 #define BXT_REVID_B_LAST 0x8
2470 #define BXT_REVID_C0 0x9
2472 #define IS_BXT_REVID(dev_priv, since, until) \
2473 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2475 #define KBL_REVID_A0 0x0
2476 #define KBL_REVID_B0 0x1
2477 #define KBL_REVID_C0 0x2
2478 #define KBL_REVID_D0 0x3
2479 #define KBL_REVID_E0 0x4
2481 #define IS_KBL_REVID(dev_priv, since, until) \
2482 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2484 #define GLK_REVID_A0 0x0
2485 #define GLK_REVID_A1 0x1
2487 #define IS_GLK_REVID(dev_priv, since, until) \
2488 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2490 #define CNL_REVID_A0 0x0
2491 #define CNL_REVID_B0 0x1
2492 #define CNL_REVID_C0 0x2
2494 #define IS_CNL_REVID(p, since, until) \
2495 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2497 #define ICL_REVID_A0 0x0
2498 #define ICL_REVID_A2 0x1
2499 #define ICL_REVID_B0 0x3
2500 #define ICL_REVID_B2 0x4
2501 #define ICL_REVID_C0 0x5
2503 #define IS_ICL_REVID(p, since, until) \
2504 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2506 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2507 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2508 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2510 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2512 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
2513 unsigned int first__ = (first); \
2514 unsigned int count__ = (count); \
2515 (INTEL_INFO(dev_priv)->engine_mask & \
2516 GENMASK(first__ + count__ - 1, first__)) >> first__; \
2518 #define VDBOX_MASK(dev_priv) \
2519 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2520 #define VEBOX_MASK(dev_priv) \
2521 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2523 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2524 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2525 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
2526 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2527 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2529 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2531 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2532 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2533 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2534 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2535 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2536 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2538 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2540 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2541 #define HAS_PPGTT(dev_priv) \
2542 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2543 #define HAS_FULL_PPGTT(dev_priv) \
2544 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2546 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2547 GEM_BUG_ON((sizes) == 0); \
2548 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2551 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2552 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2553 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2555 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2556 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2558 /* WaRsDisableCoarsePowerGating:skl,cnl */
2559 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2560 (IS_CANNONLAKE(dev_priv) || \
2561 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2563 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2564 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2565 IS_GEMINILAKE(dev_priv) || \
2566 IS_KABYLAKE(dev_priv))
2568 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2569 * rows, which changed the alignment requirements and fence programming.
2571 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2572 !(IS_I915G(dev_priv) || \
2573 IS_I915GM(dev_priv)))
2574 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2575 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2577 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2578 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2579 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2581 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2583 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2585 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2586 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2587 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2588 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2590 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2591 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2592 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2594 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
2596 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2598 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2599 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2601 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2604 * For now, anything with a GuC requires uCode loading, and then supports
2605 * command submission once loaded. But these are logically independent
2606 * properties, so we have separate macros to test them.
2608 #define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
2609 #define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
2610 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2611 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2613 /* For now, anything with a GuC has also HuC */
2614 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2615 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2617 /* Having a GuC is not the same as using a GuC */
2618 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2619 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2620 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2622 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2624 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2625 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2626 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2627 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2628 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2629 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2630 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2631 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2632 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2633 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2634 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2635 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2636 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2637 #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
2638 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2639 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2640 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2641 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2643 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2644 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2645 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2646 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2647 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2648 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2649 #define HAS_PCH_LPT_LP(dev_priv) \
2650 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2651 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2652 #define HAS_PCH_LPT_H(dev_priv) \
2653 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2654 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2655 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2656 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2657 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2658 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2660 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2662 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2664 /* DPF == dynamic parity feature */
2665 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2666 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2667 2 : HAS_L3_DPF(dev_priv))
2669 #define GT_FREQUENCY_MULTIPLIER 50
2670 #define GEN9_FREQ_SCALER 3
2672 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2674 #include "i915_trace.h"
2676 static inline bool intel_vtd_active(void)
2678 #ifdef CONFIG_INTEL_IOMMU
2679 if (intel_iommu_gfx_mapped)
2685 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2687 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2691 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2693 return IS_BROXTON(dev_priv) && intel_vtd_active();
2698 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2699 const char *fmt, ...);
2701 #define i915_report_error(dev_priv, fmt, ...) \
2702 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2704 #ifdef CONFIG_COMPAT
2705 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2708 #define i915_compat_ioctl NULL
2710 extern const struct dev_pm_ops i915_pm_ops;
2712 extern int i915_driver_load(struct pci_dev *pdev,
2713 const struct pci_device_id *ent);
2714 extern void i915_driver_unload(struct drm_device *dev);
2716 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2717 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2718 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2719 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2720 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2721 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2722 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2724 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2726 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2728 unsigned long delay;
2730 if (unlikely(!i915_modparams.enable_hangcheck))
2733 /* Don't continually defer the hangcheck so that it is always run at
2734 * least once after work has been scheduled on any ring. Otherwise,
2735 * we will ignore a hung ring if a second ring is kept busy.
2738 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2739 queue_delayed_work(system_long_wq,
2740 &dev_priv->gpu_error.hangcheck_work, delay);
2743 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2745 return dev_priv->gvt;
2748 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2750 return dev_priv->vgpu.active;
2754 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2755 struct drm_file *file_priv);
2756 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2757 struct drm_file *file_priv);
2758 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2759 struct drm_file *file_priv);
2760 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2761 struct drm_file *file_priv);
2762 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2763 struct drm_file *file_priv);
2764 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2765 struct drm_file *file_priv);
2766 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2767 struct drm_file *file_priv);
2768 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2769 struct drm_file *file_priv);
2770 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2771 struct drm_file *file_priv);
2772 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2773 struct drm_file *file_priv);
2774 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2775 struct drm_file *file);
2776 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2777 struct drm_file *file);
2778 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2779 struct drm_file *file_priv);
2780 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2781 struct drm_file *file_priv);
2782 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2783 struct drm_file *file_priv);
2784 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2785 struct drm_file *file_priv);
2786 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2787 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2788 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2789 struct drm_file *file);
2790 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2791 struct drm_file *file_priv);
2792 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2793 struct drm_file *file_priv);
2794 void i915_gem_sanitize(struct drm_i915_private *i915);
2795 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2796 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2797 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2798 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2799 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2801 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2802 const struct drm_i915_gem_object_ops *ops);
2803 struct drm_i915_gem_object *
2804 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2805 struct drm_i915_gem_object *
2806 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2807 const void *data, size_t size);
2808 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2809 void i915_gem_free_object(struct drm_gem_object *obj);
2811 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2813 if (!atomic_read(&i915->mm.free_count))
2816 /* A single pass should suffice to release all the freed objects (along
2817 * most call paths) , but be a little more paranoid in that freeing
2818 * the objects does take a little amount of time, during which the rcu
2819 * callbacks could have added new objects into the freed list, and
2820 * armed the work again.
2824 } while (flush_work(&i915->mm.free_work));
2827 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2830 * Similar to objects above (see i915_gem_drain_freed-objects), in
2831 * general we have workers that are armed by RCU and then rearm
2832 * themselves in their callbacks. To be paranoid, we need to
2833 * drain the workqueue a second time after waiting for the RCU
2834 * grace period so that we catch work queued via RCU from the first
2835 * pass. As neither drain_workqueue() nor flush_workqueue() report
2836 * a result, we make an assumption that we only don't require more
2837 * than 3 passes to catch all _recursive_ RCU delayed work.
2843 i915_gem_drain_freed_objects(i915);
2845 drain_workqueue(i915->wq);
2848 struct i915_vma * __must_check
2849 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2850 const struct i915_ggtt_view *view,
2855 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2856 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2858 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2860 static inline int __sg_page_count(const struct scatterlist *sg)
2862 return sg->length >> PAGE_SHIFT;
2865 struct scatterlist *
2866 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2867 unsigned int n, unsigned int *offset);
2870 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2874 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2878 i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
2882 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2885 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2886 struct sg_table *pages,
2887 unsigned int sg_page_sizes);
2888 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2890 static inline int __must_check
2891 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2893 might_lock(&obj->mm.lock);
2895 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2898 return __i915_gem_object_get_pages(obj);
2902 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2904 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2908 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2910 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2912 atomic_inc(&obj->mm.pages_pin_count);
2916 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
2918 return atomic_read(&obj->mm.pages_pin_count);
2922 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2924 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2925 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
2927 atomic_dec(&obj->mm.pages_pin_count);
2931 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2933 __i915_gem_object_unpin_pages(obj);
2936 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock/struct_mutex */
2938 I915_MM_SHRINKER /* called "recursively" from direct-reclaim-esque */
2941 int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2942 enum i915_mm_subclass subclass);
2943 void __i915_gem_object_truncate(struct drm_i915_gem_object *obj);
2945 enum i915_map_type {
2948 #define I915_MAP_OVERRIDE BIT(31)
2949 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
2950 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
2953 static inline enum i915_map_type
2954 i915_coherent_map_type(struct drm_i915_private *i915)
2956 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2960 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
2961 * @obj: the object to map into kernel address space
2962 * @type: the type of mapping, used to select pgprot_t
2964 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
2965 * pages and then returns a contiguous mapping of the backing storage into
2966 * the kernel address space. Based on the @type of mapping, the PTE will be
2967 * set to either WriteBack or WriteCombine (via pgprot_t).
2969 * The caller is responsible for calling i915_gem_object_unpin_map() when the
2970 * mapping is no longer required.
2972 * Returns the pointer through which to access the mapped object, or an
2973 * ERR_PTR() on error.
2975 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2976 enum i915_map_type type);
2978 void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
2979 unsigned long offset,
2980 unsigned long size);
2981 static inline void i915_gem_object_flush_map(struct drm_i915_gem_object *obj)
2983 __i915_gem_object_flush_map(obj, 0, obj->base.size);
2987 * i915_gem_object_unpin_map - releases an earlier mapping
2988 * @obj: the object to unmap
2990 * After pinning the object and mapping its pages, once you are finished
2991 * with your access, call i915_gem_object_unpin_map() to release the pin
2992 * upon the mapping. Once the pin count reaches zero, that mapping may be
2995 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
2997 i915_gem_object_unpin_pages(obj);
3000 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3001 unsigned int *needs_clflush);
3002 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3003 unsigned int *needs_clflush);
3004 #define CLFLUSH_BEFORE BIT(0)
3005 #define CLFLUSH_AFTER BIT(1)
3006 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3009 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3011 i915_gem_object_unpin_pages(obj);
3014 static inline int __must_check
3015 i915_mutex_lock_interruptible(struct drm_device *dev)
3017 return mutex_lock_interruptible(&dev->struct_mutex);
3020 int i915_gem_dumb_create(struct drm_file *file_priv,
3021 struct drm_device *dev,
3022 struct drm_mode_create_dumb *args);
3023 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3024 u32 handle, u64 *offset);
3025 int i915_gem_mmap_gtt_version(void);
3027 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3028 struct drm_i915_gem_object *new,
3029 unsigned frontbuffer_bits);
3031 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3033 static inline bool __i915_wedged(struct i915_gpu_error *error)
3035 return unlikely(test_bit(I915_WEDGED, &error->flags));
3038 static inline bool i915_reset_failed(struct drm_i915_private *i915)
3040 return __i915_wedged(&i915->gpu_error);
3043 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3045 return READ_ONCE(error->reset_count);
3048 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3049 struct intel_engine_cs *engine)
3051 return READ_ONCE(error->reset_engine_count[engine->id]);
3054 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3055 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3057 void i915_gem_init_mmio(struct drm_i915_private *i915);
3058 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3059 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3060 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3061 void i915_gem_fini(struct drm_i915_private *dev_priv);
3062 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3063 unsigned int flags, long timeout);
3064 void i915_gem_suspend(struct drm_i915_private *dev_priv);
3065 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3066 void i915_gem_resume(struct drm_i915_private *dev_priv);
3067 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3068 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3071 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3073 const struct i915_sched_attr *attr);
3074 #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
3077 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3079 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3081 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3082 struct i915_vma * __must_check
3083 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3085 const struct i915_ggtt_view *view,
3086 unsigned int flags);
3087 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3088 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3090 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3091 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3093 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3094 enum i915_cache_level cache_level);
3096 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3097 struct dma_buf *dma_buf);
3099 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3100 struct drm_gem_object *gem_obj, int flags);
3102 static inline struct i915_hw_ppgtt *
3103 i915_vm_to_ppgtt(struct i915_address_space *vm)
3105 return container_of(vm, struct i915_hw_ppgtt, vm);
3108 /* i915_gem_fence_reg.c */
3109 struct drm_i915_fence_reg *
3110 i915_reserve_fence(struct drm_i915_private *dev_priv);
3111 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3113 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3115 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3116 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3117 struct sg_table *pages);
3118 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3119 struct sg_table *pages);
3121 static inline struct i915_gem_context *
3122 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3124 return idr_find(&file_priv->context_idr, id);
3127 static inline struct i915_gem_context *
3128 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3130 struct i915_gem_context *ctx;
3133 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3134 if (ctx && !kref_get_unless_zero(&ctx->ref))
3141 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3142 struct drm_file *file);
3143 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3144 struct drm_file *file);
3145 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3146 struct drm_file *file);
3147 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3148 struct intel_context *ce,
3151 /* i915_gem_evict.c */
3152 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3153 u64 min_size, u64 alignment,
3154 unsigned cache_level,
3157 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3158 struct drm_mm_node *node,
3159 unsigned int flags);
3160 int i915_gem_evict_vm(struct i915_address_space *vm);
3162 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3164 /* belongs in i915_gem_gtt.h */
3165 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3168 if (INTEL_GEN(dev_priv) < 6)
3169 intel_gtt_chipset_flush();
3172 /* i915_gem_stolen.c */
3173 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3174 struct drm_mm_node *node, u64 size,
3175 unsigned alignment);
3176 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3177 struct drm_mm_node *node, u64 size,
3178 unsigned alignment, u64 start,
3180 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3181 struct drm_mm_node *node);
3182 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3183 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
3184 struct drm_i915_gem_object *
3185 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3186 resource_size_t size);
3187 struct drm_i915_gem_object *
3188 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3189 resource_size_t stolen_offset,
3190 resource_size_t gtt_offset,
3191 resource_size_t size);
3193 /* i915_gem_internal.c */
3194 struct drm_i915_gem_object *
3195 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3198 /* i915_gem_shrinker.c */
3199 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3200 unsigned long target,
3201 unsigned long *nr_scanned,
3203 #define I915_SHRINK_PURGEABLE BIT(0)
3204 #define I915_SHRINK_UNBOUND BIT(1)
3205 #define I915_SHRINK_BOUND BIT(2)
3206 #define I915_SHRINK_ACTIVE BIT(3)
3207 #define I915_SHRINK_VMAPS BIT(4)
3208 #define I915_SHRINK_WRITEBACK BIT(5)
3209 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3210 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3211 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3212 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
3213 struct mutex *mutex);
3215 /* i915_gem_tiling.c */
3216 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3218 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3220 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3221 i915_gem_object_is_tiled(obj);
3224 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3225 unsigned int tiling, unsigned int stride);
3226 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3227 unsigned int tiling, unsigned int stride);
3229 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3231 /* i915_cmd_parser.c */
3232 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3233 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3234 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3235 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3236 struct drm_i915_gem_object *batch_obj,
3237 struct drm_i915_gem_object *shadow_batch_obj,
3238 u32 batch_start_offset,
3243 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3244 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3245 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3246 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3248 /* i915_suspend.c */
3249 extern int i915_save_state(struct drm_i915_private *dev_priv);
3250 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3253 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3254 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3256 /* intel_device_info.c */
3257 static inline struct intel_device_info *
3258 mkwrite_device_info(struct drm_i915_private *dev_priv)
3260 return (struct intel_device_info *)INTEL_INFO(dev_priv);
3264 extern void intel_modeset_init_hw(struct drm_device *dev);
3265 extern int intel_modeset_init(struct drm_device *dev);
3266 extern void intel_modeset_cleanup(struct drm_device *dev);
3267 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3269 extern void intel_display_resume(struct drm_device *dev);
3270 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3271 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3272 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3273 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3274 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3275 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3277 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3280 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3281 struct drm_file *file);
3283 extern struct intel_display_error_state *
3284 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3285 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3286 struct intel_display_error_state *error);
3288 #define __I915_REG_OP(op__, dev_priv__, ...) \
3289 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
3291 #define I915_READ8(reg__) __I915_REG_OP(read8, dev_priv, (reg__))
3292 #define I915_WRITE8(reg__, val__) __I915_REG_OP(write8, dev_priv, (reg__), (val__))
3294 #define I915_READ16(reg__) __I915_REG_OP(read16, dev_priv, (reg__))
3295 #define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))
3296 #define I915_READ16_NOTRACE(reg__) __I915_REG_OP(read16_notrace, dev_priv, (reg__))
3297 #define I915_WRITE16_NOTRACE(reg__, val__) __I915_REG_OP(write16_notrace, dev_priv, (reg__), (val__))
3299 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
3300 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
3301 #define I915_READ_NOTRACE(reg__) __I915_REG_OP(read_notrace, dev_priv, (reg__))
3302 #define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
3304 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3305 * will be implemented using 2 32-bit writes in an arbitrary order with
3306 * an arbitrary delay between them. This can cause the hardware to
3307 * act upon the intermediate value, possibly leading to corruption and
3308 * machine death. For this reason we do not support I915_WRITE64, or
3309 * dev_priv->uncore.funcs.mmio_writeq.
3311 * When reading a 64-bit value as two 32-bit values, the delay may cause
3312 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3313 * occasionally a 64-bit register does not actualy support a full readq
3314 * and must be read using two 32-bit reads.
3316 * You have been warned.
3318 #define I915_READ64(reg__) __I915_REG_OP(read64, dev_priv, (reg__))
3319 #define I915_READ64_2x32(lower_reg__, upper_reg__) \
3320 __I915_REG_OP(read64_2x32, dev_priv, (lower_reg__), (upper_reg__))
3322 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
3323 #define POSTING_READ16(reg__) __I915_REG_OP(posting_read16, dev_priv, (reg__))
3325 /* These are untraced mmio-accessors that are only valid to be used inside
3326 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3329 * Think twice, and think again, before using these.
3331 * As an example, these accessors can possibly be used between:
3333 * spin_lock_irq(&dev_priv->uncore.lock);
3334 * intel_uncore_forcewake_get__locked();
3338 * intel_uncore_forcewake_put__locked();
3339 * spin_unlock_irq(&dev_priv->uncore.lock);
3342 * Note: some registers may not need forcewake held, so
3343 * intel_uncore_forcewake_{get,put} can be omitted, see
3344 * intel_uncore_forcewake_for_reg().
3346 * Certain architectures will die if the same cacheline is concurrently accessed
3347 * by different clients (e.g. on Ivybridge). Access to registers should
3348 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3349 * a more localised lock guarding all access to that bank of registers.
3351 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
3352 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
3353 #define I915_WRITE64_FW(reg__, val__) __I915_REG_OP(write64_fw, dev_priv, (reg__), (val__))
3354 #define POSTING_READ_FW(reg__) __I915_REG_OP(posting_read_fw, dev_priv, (reg__))
3356 /* "Broadcast RGB" property */
3357 #define INTEL_BROADCAST_RGB_AUTO 0
3358 #define INTEL_BROADCAST_RGB_FULL 1
3359 #define INTEL_BROADCAST_RGB_LIMITED 2
3361 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3362 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3364 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3365 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3366 * perform the operation. To check beforehand, pass in the parameters to
3367 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3368 * you only need to pass in the minor offsets, page-aligned pointers are
3371 * For just checking for SSE4.1, in the foreknowledge that the future use
3372 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3374 #define i915_can_memcpy_from_wc(dst, src, len) \
3375 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3377 #define i915_has_memcpy_from_wc() \
3378 i915_memcpy_from_wc(NULL, NULL, 0)
3381 int remap_io_mapping(struct vm_area_struct *vma,
3382 unsigned long addr, unsigned long pfn, unsigned long size,
3383 struct io_mapping *iomap);
3385 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3387 if (INTEL_GEN(i915) >= 10)
3388 return CNL_HWS_CSB_WRITE_INDEX;
3390 return I915_HWS_CSB_WRITE_INDEX;
3393 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
3395 return i915_ggtt_offset(i915->gt.scratch);
3398 static inline void add_taint_for_CI(unsigned int taint)
3401 * The system is "ok", just about surviving for the user, but
3402 * CI results are now unreliable as the HW is very suspect.
3403 * CI checks the taint state after every test and will reboot
3404 * the machine if the kernel is tainted.
3406 add_taint(taint, LOCKDEP_STILL_OK);